Large
(e.g. 128 x 128)
Crosspoint Switch
SD/HD
Adaptive Equalizer DS10CP152
2 x 2 LVDS
Crosspoint Switch
SD/HD
Reclocker +
Cable Driver
INPUT CARD OUTPUT CARD
CROSSPOINT
CARD
BACKPLANES
SD/HD
Reclocker +
Cable Driver
SD/HD
Reclocker +
Cable Driver
SD/HD
Reclocker +
Cable Driver
DS10CP152
2 x 2 LVDS
Crosspoint Switch
DS10CP152
2 x 2 LVDS
Crosspoint Switch
DS10CP152
2 x 2 LVDS
Crosspoint Switch
SD/HD
Adaptive Equalizer
SD/HD
Adaptive Equalizer
SD/HD
Adaptive Equalizer
DS10CP152
www.ti.com
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
DS10CP152 1.5 Gbps 2X2 LVDS Crosspoint Switch
Check for Samples: DS10CP152
1FEATURES DESCRIPTION
The DS10CP152 is a 1.5 Gbps 2x2 LVDS crosspoint
2• DC - 1.5 Gbps Low Jitter, Low Skew, Low switch optimized for high-speed signal routing and
Power Operation switching over lossy FR-4 printed circuit board
• Pin Configurable, Fully Differential, Non- backplanes and balanced cables. Fully differential
Blocking Architecture signal paths ensure exceptional signal integrity and
noise immunity. The non-blocking architecture allows
• Wide Input Common Mode Voltage Range connections of any input to any output or outputs.
Allows DC-Coupled Interface to LVDS, CML
and LVPECL Drivers Wide input common mode range allows the switch to
• On-chip 100ΩInput and Output Termination accept signals with LVDS, CML and LVPECL levels;
the output levels are LVDS. A very small package
Minimizes Insertion and Return Losses, footprint requires a minimal space on the board while
Reduces Component Count and Minimizes the flow-through pinout allows easy board layout.
Board Space Each differential input and output is internally
• 7 kV ESD on LVDS I/O Pins Protects Adjoining terminated with a 100Ωresistor to lower device return
Components losses, reduce component count and further minimize
• Small SOIC-16 Space Saving Package board space.
APPLICATIONS
• High-Speed Channel Select Applications
• Clock and Data Buffering and Muxing
• SD/HD SDI Routers
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
2 x 2
IN0+
IN0-
IN1+
IN1-
EN0
OUT0+
EN1
OUT0-
OUT1+
OUT1-
SEL1 SEL0
DS10CP152
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
Connection Diagram
DS10CP152 Pin Diagram
See Package Number D (R-PDSO-G16)
PIN DESCRIPTIONS
Pin
Pin Name I/O, Type Pin Description
Number
IN0+, IN0- , 3, 4, I, LVDS Inverting and non-inverting high speed LVDS input pins.
IN1+, IN1- 6, 7
OUT0+, OUT0-, 14, 13, O, LVDS Inverting and non-inverting high speed LVDS output pins.
OUT1+, OUT1- 11, 10
SEL1, SEL0 1, 2 I, LVCMOS Switch configuration pins.
EN0, EN1 16, 15 I, LVCMOS Output enable pins.
NC 8, 9 NC "NO CONNECT" pins.
VDD 5 Power Power supply pin.
GND 12 Power Ground pin.
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Product Folder Links: DS10CP152
DS10CP152
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VCC + 0.3V)
LVDS Input Voltage −0.3V to +4V
Differential Input Voltage |VID| 1V
LVDS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage 0V to 1V
LVDS Output Short Circuit Current Duration 5 ms
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
D Package 1.72W
Derate D Package 13.75 mW/°C above +25°C
Package Thermal Resistance
θJA +72.7°C/W
θJC +41.2°C/W
ESD Susceptibility
HBM (3) ≥7 kV
MM (4) ≥250V
CDM (5) ≥1250V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input Voltage (VID) 0 1 V
Operating Free Air Temperature (TA)−40 +25 +85 °C
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DS10CP152
DS10CP152
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
www.ti.com
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VDD V
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN = 3.6V 40 175 250 μA
VCC = 3.6V
IIL Low Level Input Current VIN = GND ±1 ±10 μA
VCC = 3.6V
VCL Input Clamp Voltage ICL =−18 mA, VCC = 0V −0.9 −1.5 V
LVDS INPUT DC SPECIFICATIONS
VID Input Differential Voltage 0 1 V
VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV
VTL Differential Input Low Threshold −100 0 mV
VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC - V
0.05
VIN = 3.6V or 0V ±1 ±10 μA
IIN Input Current VCC = 3.6V or 0V
CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF
RIN Input Termination Resistor Between IN+ and IN- 100 Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD Differential Output Voltage 250 350 450 mV
RL= 100Ω
ΔVOD Change in Magnitude of VOD for Complimentary -35 35 mV
Output States
VOS Offset Voltage 1.05 1.2 1.375 V
RL= 100Ω
ΔVOS Change in Magnitude of VOS for Complimentary -35 35 mV
Output States
IOS Output Short Circuit Current (4) OUT to GND -23 -55 mA
OUT to VCC 8 55 mA
COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF
ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω
SUPPLY CURRENT
ICC Supply Current EN0 = EN1 = H 58 70 mA
ICCZ Outputs Powered Down Supply Current EN0 = EN1 = L 25 30 mA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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Product Folder Links: DS10CP152
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SNLS261E –OCTOBER 2007–REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS
tPLHD Differential Propagation Delay Low to 440 650 ps
High (3) RL= 100Ω
tPHLD Differential Propagation Delay High to 400 650 ps
Low (3)
tSKD1 Pulse Skew |tPLHD −tPHLD| 40 120 ps
(3) (4)
tSKD2 Channel to Channel Skew 25 60 ps
(3)(5)
tSKD3 Part to Part Skew 45 190 ps
(3)(6)
tLHT Rise Time (3) 170 350 ps
RL= 100Ω
tHLT Fall Time (3) 170 350 ps
tON Output Enable Time 5 20 μs
tOFF Output Disable Time 3 12 ns
tSEL Select Time 3 12 ns
JITTER PERFORMANCE (3)
tRJ1 VID = 350 mV 135 MHz 0.5 1.2 ps
VCM = 1.2V
tRJ2 311 MHz 0.5 1.2 ps
Clock (RZ)
Random Jitter (RMS Value) (7)
tRJ3 503 MHz 0.5 1.2 ps
tRJ4 750 MHz 0.5 1.2 ps
tDJ1 VID = 350 mV 270 Mbps 9 38 ps
VCM = 1.2V
tDJ2 622 Mbps 7 36 ps
Deterministic Jitter (Peak-to-Peak Clock (RZ)
Value )(8)
tDJ3 1.06 Gbps 7 34 ps
tDJ4 1.5 Gbps 9 35 ps
tTJ1 VID = 350 mV 270 Mbps 0.01 0.03 UIP-P
VCM = 1.2V
tTJ2 622 Mbps 0.01 0.04 UIP-P
PRBS-23 (NRZ)
Total Jitter (Peak to Peak Value) (9)
tTJ3 1.06 Gbps 0.01 0.05 UIP-P
tTJ4 1.5 Gbps 0.01 0.07 UIP-P
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Typical values represent most likely parametric norms for VCC = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(3) Specification is ensured by characterization and is not tested in production.
(4) tSKD1, |tPLHD −tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(5) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(6) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(7) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(8) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(9) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS10CP152
RL
OUT+
OUT-
IN+
IN-
Signal Generator R D
R D RL
VOL
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
VOH
DS10CP152
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
www.ti.com
DC Test Circuits
Figure 1.
AC Test Circuits and Timing Diagrams
Figure 2.
Figure 3.
Figure 4.
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Product Folder Links: DS10CP152
OUT+
OUT-
50:50:
VCC
CML3.3V or CML2.5V
Driver
100: Differential T-Line
DS10CP152
Receiver
IN+
IN-
100:
OUT+
OUT-
DS10CP152
Receiver
IN+
IN-
100: Differential T-Line
100:
LVDS
Driver
DS10CP152
www.ti.com
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The DS10CP152 is a 1.5 Gbps 2x2 LVDS digital crosspoint switch optimized for high-speed signal routing and
switching over lossy FR-4 printed circuit board backplanes and balanced cables.
Table 1. Switch Configuration Truth Table
SEL1 SEL0 OUT1 OUT0
0 0 IN0 IN0
0 1 IN0 IN1
1 0 IN1 IN0
1 1 IN1 IN1
Table 2. Output Enable Truth Table
EN1 EN0 OUT1 OUT0
0 0 Disabled Disabled
0 1 Disabled Enabled
1 0 Enabled Disabled
1 1 Enabled Enabled
Input Interfacing
The DS10CP152 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS10CP152 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS10CP152 inputs are internally terminated with a 100Ωresistor.
Figure 5. Typical LVDS Driver DC-Coupled Interface to an DS10CP152 Input
Figure 6. Typical CML Driver DC-Coupled Interface to an DS10CP152 Input
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DS10CP152
OUT+
OUT-
CML or
LVPECL or
LVDS
IN+
IN-
100:
100: Differential T-Line Differential
Receiver
DS10CP152
Driver
100:
OUT+
OUT-
150-250:
100: Differential T-Line LVDS
Receiver
IN+
IN-
100:
LVPECL
Driver
150-250:
DS10CP152
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
www.ti.com
Figure 7. Typical LVPECL Driver DC-Coupled Interface to an DS10CP152 Input
Output Interfacing
The DS10CP152 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accommodate LVDS compliant signals, it is recommended to check
respective receiver's data sheet prior to implementing the suggested interface implementation.
Figure 8. Typical DS10CP152 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
8Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS10CP152
DS10CP152
www.ti.com
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
Typical Performance Characteristics
Figure 9. A 270 Mbps NRZ PRBS-7 After 2" Figure 10. A 622 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline Differential FR-4 Stripline
V:100 mV / DIV, H:500 ps / DIV V:100 mV / DIV, H:200 ps / DIV
Figure 11. A 1.06 Gbps NRZ PRBS-7 After 2" Figure 12. A 1.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV V:100 mV / DIV, H:100 ps / DIV
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: DS10CP152
DS10CP152
SNLS261E –OCTOBER 2007–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 9
10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS10CP152
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS10CP152TMAX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS10CP152TMAX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2013
Pack Materials-Page 2
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