Rev 1; 11/03 10-Tap Silicon Delay Line The DS1110 delay line is an improved replacement for the DS1010. It has ten equally spaced taps providing delays from 5ns to 500ns. The devices are offered in a standard 16-pin SO or 14-pin TSSOP. The DS1110 series delay lines provide a nominal accuracy of 5% or 2ns, whichever is greater, at 5V and +25C. The DS1110 reproduces the input logic state at the tap 10 output after a fixed delay as specified by the dash number extension of the part number. The DS1110 is designed to produce both leading- and trailing-edge delays with equal precision. Each tap is capable of driving up to ten 74LS type loads. Dallas Semiconductor can customize standard products to meet special needs. Applications Features All-Silicon, 5V, 10-Tap Delay Line Improved, Drop-In Replacement for the DS1010 10 Taps Equally Spaced Delays are Stable and Precise Leading- and Trailing-Edge Accuracy Delay Tolerance 5% or 2ns, whichever is Greater, at 5V and +25C Economical Auto-Insertable, Low Profile Low-Power CMOS TTL/CMOS Compatible Vapor Phase, IR, and Wave Solderable Communications Equipment Fast-Turn Prototypes Medical Devices Automated Test Equipment Delays Specified Over Commercial and Industrial Temperature Ranges PC Peripheral Devices Custom Delays Available Standard 16-Pin SO or 14-Pin TSSOP Pin Configurations TOP VIEW IN 1 N.C. 2 TAP2 3 Ordering Information PART TEMP RANGE PIN-PACKAGE DS1110E-XXX -40C to +85C 14 TSSOP DS1110S-XXX -40C to +85C 16 SO 14 VCC 13 TAP1 DS1110E 12 TAP3 TAP4 4 11 TAP5 TAP6 5 10 TAP7 TAP8 6 9 TAP9 GND 7 8 TAP10 Selector Guide appears at end of data sheet. TSSOP Pin Configurations continued at end of data sheet. _____________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 DS1110 General Description DS1110 10-Tap Silicon Delay Line ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...................See IPC/JEDEC J-STD-020A Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 5%, TA = -40C to +85C.) MIN TYP MAX UNITS Supply Voltage PARAMETER SYMBOL VCC (Note 1) 4.75 5.0 5.25 V High-Level Input Voltage VIH (Note 1) 2.4 VCC + 0.3 V Low-Level Input Voltage VIL (Note 1) -0.3 +0.8 V 0V VI VCC -1.0 Input Leakage Current II CONDITIONS Active Current ICC VCC = max, period = min (Note 2) High-Level Output Current IOH VCC = min, VOH = 2.3V Low-Level Output Current IOL VCC = min, VOL = 0.5V 40 +1.0 A 150 mA -1.0 mA 12 mA AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 5%, TA = -40C to +85C.) PARAMETER SYMBOL Input Pulse Width tWI Input-to-Tap Delay (Delays 40ns) tPLH tPHL Input-to-Tap Delay (Delays > 40ns) tPLH tPHL Power-Up Time Input Period 2 CONDITIONS (Note 6) MIN TYP +25C, 5.0V (Notes 3, 5, 6, 7, 9) -2 Table 1 +2 0C to +70C (Notes 4-7) -3 Table 1 +3 -40C to +85C (Notes 4-7) -4 Table 1 +4 +25C, 5.0V (Notes 3, 5, 6, 7, 9) -5 Table 1 +5 0C to +70C (Notes 4-7) -8 Table 1 +8 -40C to +85C (Notes 4-7) -13 Table 1 +13 200 (Note 8) ______________________________________________________________________ UNITS ns tPU Period MAX 10% of tap 10 2 (tWI) or 20, whichever is greater ns % ms ns 10-Tap Silicon Delay Line DS1110 CAPACITANCE (TA = +25C.) PARAMETER Input Capacitance Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: CONDITIONS SYMBOL MIN TYP MAX UNITS 5 10 pF CIN All voltages are referenced to ground. Measured with outputs open. Initial tolerances are with respect to the nominal value at +25C and VCC = 5.0V for both leading and trailing edges. Temperature and voltage tolerances are with respect to the actual delay measured over stated temperature range and a 4.75V to 5.25V range. Intermediate delay values are available on a custom basis. See Test Conditions section. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other taps also slow down; tap 3 can never be faster than tap 2. Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.) For Tap 1 delays greater than 20ns, the tolerance is 3ns or 5%, whichever is greater. Typical Operating Characteristics (VCC = 5.0V, TA = +25C, unless otherwise noted.) DS1110-50 ACTIVE CURRENT vs. INPUT FREQUENCY DS1110-500 ACTIVE CURRENT vs. INPUT FREQUENCY 180 160 ACTIVE CURRENT (mA) 30 25 20 15 10 140 120 100 80 60 40 15pF LOAD/TAP VCC = 5.25V 5 DS1110 toc02 35 15pF LOAD/TAP VCC = 5.25V 20 0 0 0.1 0.1 10 1.0 1.0 100 10 FREQUENCY (MHz) FREQUENCY (MHz) DS1110-500 TAP 10 DELAY vs. TEMPERATURE DS1110-50 TAP 10 DELAY vs. TEMPERATURE 54 DS1110 toc03 575 550 DS1110 toc04 ACTIVE CURRENT (mA) 200 DS1110 toc01 40 53 52 DELAY (ns) DELAY (ns) 525 500 51 50 49 475 48 450 47 500kHz INPUT 46 425 -40 -15 10 35 TEMPERATURE (C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) _____________________________________________________________________ 3 Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25C, unless otherwise noted.) DS1110-500 DELAY vs. TAP DS1110-50 DELAY vs. TAP 400 FALLING EDGE 45 40 350 35 300 DELAY (ns) RISING EDGE 250 200 150 30 RISING EDGE 25 20 15 100 10 500kHz INPUT 50 5 0 0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 TAP TAP DS1110-500 TAP 10 DELAY vs. VOLTAGE DS1110-50 TAP 10 DELAY vs. VOLTAGE 55 DS1110 toc07 540 9 10 DS1110 toc08 DELAY (ns) DS1110 toc06 FALLING EDGE 450 50 DS1110 toc05 500 53 520 FALLING EDGE DELAY (ns) DELAY (ns) DS1110 10-Tap Silicon Delay Line 500 51 FALLING EDGE 49 RISING EDGE RISING EDGE 480 47 500kHz INPUT 460 4.750 4.875 5.000 5.125 45 4.750 5.250 4.875 5.000 5.125 5.250 VOLTAGE (V) VOLTAGE (V) Pin Description PIN NAME 4 FUNCTION TSSOP SO 1 1 IN 2 2, 3, 15 N.C. No Connection 7 8 GND Ground 13, 3, 12, 4, 11, 5, 10, 6, 9, 8 14, 4, 13, 5, 12, 6, 11, 7, 10, 9 Tap 1-Tap 10 14 16 VCC Input Tap Output Number 5.0V ______________________________________________________________________ 10-Tap Silicon Delay Line Table 1. Part Number by Delay (tPHL, tPLH) The DS1110 delay line is an improved replacement for the DS1010. It has ten equally spaced taps providing delays from 5ns to 500ns. The devices are offered in a standard 16-pin SO or 14-pin TSSOP. The DS1110 series delay lines provide a nominal accuracy of 5% or 2ns, whichever is greater, at 5V and +25C. The DS1110 reproduces the input logic state at the tap 10 output after a fixed delay as specified by the dash number extension of the part number. The DS1110 is designed to produce both leading- and trailing-edge delays with equal precision. Each tap is capable of driving up to ten 74LS type loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests call 972-371-4348. PART TOTAL DELAY* (ns) DELAY/TAP (ns) DS1110-50 50 5 DS1110-60 60 6 DS1110-75 75 7.5 DS1110-80 80 8 DS1110-100 100 10 DS1110-125 125 12.5 DS1110-150 150 15 DS1110-175 175 17.5 DS1110-200 200 20 DS1110-250 250 25 DS1110-300 300 30 DS1110-350 350 35 DS1110-400 400 40 DS1110-450 450 45 DS1110-500 500 50 *Custom delays are available. TAP1 TAP2 TAP9 TAP10 IN 10% 10% 10% 10% Figure 1. Logic Diagram PERIOD tFALL tRISE VIH 2.2V 2.2V 1.5V 1.5V 1.5V 0.8V 0.8V IN VIL tWI tWI tPLH tPLH 1.5V 1.5V OUT Figure 2. Timing Diagram: Silicon Delay Line _____________________________________________________________________ 5 DS1110 Detailed Description DS1110 10-Tap Silicon Delay Line Terminology Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t WI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. Test Setup Description Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1110. A precision pulse generator under software control produces the input waveform. Time delays are measured by a time interval counter (20ps resolution) connected PULSE GENERATOR START Z0 = 50 TIME INTERVAL COUNTER STOP VHF SWITCH CONTROL UNIT DEVICE UNDER TEST Figure 3. Test Circuit 6 ______________________________________________________________________ 10-Tap Silicon Delay Line Output Each output is loaded with the equivalent of one 74FO4 input gate. Delay is measured at the 1.5V level on the rising and falling edge. Chip Information TRANSISTOR COUNT: 6813 DS1110 between the input and each tap. Each tap is selected and connected to the counter by a VHF switch-control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE-488 bus. Table 2. Test Conditions INPUT CONDITION Ambient Temperature +25C 3C Supply Voltage (VCC) 5.0V 0.1V High = 3.0V 0.1V Input Pulse Low = 0.0V 0.1V Source Impedance 50 max Rise and Fall Time 3ns max Pulse Width 500ns (1s for -500ns) Period 1s (2s for -500ns) Note: The above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. Selector Guide TEMP RANGE PINPACKAGE TOTAL DELAY (ns)* DS1110E-50 -40C to +85C 14 TSSOP 50 DS1110E-60 -40C to +85C 14 TSSOP 60 DS1110E-75 -40C to +85C 14 TSSOP DS1110E-80 -40C to +85C 14 TSSOP DS1110E-100 -40C to +85C DS1110E-125 DS1110E-150 TOTAL DELAY (ns)* TEMP RANGE PINPACKAGE DS1110S-50 -40C to +85C 16 SO 50 DS1110S-60 -40C to +85C 16 SO 60 75 DS1110S-75 -40C to +85C 16 SO 75 80 DS1110S-80 -40C to +85C 16 SO 80 14 TSSOP 100 DS1110S-100 -40C to +85C 16 SO 100 -40C to +85C 14 TSSOP 125 DS1110S-125 -40C to +85C 16 SO 125 -40C to +85C 14 TSSOP 150 DS1110S-150 -40C to +85C 16 SO 150 DS1110E-175 -40C to +85C 14 TSSOP 175 DS1110S-175 -40C to +85C 16 SO 175 DS1110E-200 -40C to +85C 14 TSSOP 200 DS1110S-200 -40C to +85C 16 SO 200 DS1110E-250 -40C to +85C 14 TSSOP 250 DS1110S-250 -40C to +85C 16 SO 250 DS1110E-300 -40C to +85C 14 TSSOP 300 DS1110S-300 -40C to +85C 16 SO 300 DS1110E-350 -40C to +85C 14 TSSOP 350 DS1110S-350 -40C to +85C 16 SO 350 DS1110E-400 -40C to +85C 14 TSSOP 400 DS1110S-400 -40C to +85C 16 SO 400 DS1110E-450 -40C to +85C 14 TSSOP 450 DS1110S-450 -40C to +85C 16 SO 450 DS1110E-500 -40C to +85C 14 TSSOP 500 DS1110S-500 -40C to +85C 16 SO 500 PART PART *Custom delays are available. _____________________________________________________________________ 7 DS1110 10-Tap Silicon Delay Line Pin Configurations (continued) Package Information For the latest package outline information, go to www.maxim-ic. com/packages. TOP VIEW IN1 1 16 VCC N.C. 2 15 N.C. N.C. 3 TAP2 4 14 TAP1 DS1110S 13 TAP3 TAP4 5 12 TAP5 TAP6 6 11 TAP7 TAP8 7 10 TAP9 GND 8 9 TAP10 SO (300mil) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.