W29N01HZ/W
Release Date: November, 9th, 2016
1 Revision A
W29N01HZ/W
1G-BIT 1.8V
NAND FLASH MEMORY
W29N01HZ/W
Release Date: November, 9th, 2016
2 Revision A
Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................... 6
2. FEATURES ....................................................................................................................................... 6
3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7
3.1 Pin assignment 48 pin TSOP1 (x8) ...................................................................................... 7
3.2 Pin assignment 48 ball VFBGA (x8) ..................................................................................... 8
3.3 Pin assignment 63 ball VFBGA ............................................................................................ 9
3.4 Pin Descriptions .................................................................................................................. 10
4. PIN DESCRITPIONS ...................................................................................................................... 11
4.1 Chip Enable (#CE) .............................................................................................................. 11
4.2 Write Enable (#WE) ............................................................................................................ 11
4.3 Read Enable (#RE) ............................................................................................................ 11
4.4 Address Latch Enable (ALE) .............................................................................................. 11
4.5 Command Latch Enable (CLE) .......................................................................................... 11
4.6 Write Protect (#WP) ............................................................................................................ 11
4.7 Ready/Busy (RY/#BY) ........................................................................................................ 11
4.8 Input and Output (I/Ox) ....................................................................................................... 11
5. BLOCK DIAGRAM .......................................................................................................................... 12
6. MEMORY ARRAY ORGANIZATION .............................................................................................. 13
6.1 Array Organization (x8) ...................................................................................................... 13
6.2 Array Organization (x16) .................................................................................................... 14
7. MODE SELECTION TABLE ........................................................................................................... 15
8. COMMAND TABLE......................................................................................................................... 16
9. DEVICE OPERATIONS .................................................................................................................. 17
9.1 READ operation .................................................................................................................. 17
9.1.1 PAGE READ (00h-30h)......................................................................................................... 17
9.1.2 RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 18
9.1.3 READ ID (90h) ...................................................................................................................... 18
9.1.4 READ PARAMETER PAGE (ECh) ....................................................................................... 19
9.1.5 READ STATUS (70h)............................................................................................................ 21
9.2 PROGRAM operation ......................................................................................................... 23
9.2.1 PAGE PROGRAM (80h-10h) ................................................................................................ 23
9.2.2 SERIAL DATA INPUT (80h) .................................................................................................. 23
9.2.3 RANDOM DATA INPUT (85h) .............................................................................................. 24
9.3 COPY BACK operation....................................................................................................... 25
9.3.1 READ for COPY BACK (00h-35h) ........................................................................................ 25
9.3.2 PROGRAM for COPY BACK (85h-10h) ................................................................................ 25
9.4 BLOCK ERASE operation .................................................................................................. 27
9.4.1 BLOCK ERASE (60h-D0h) .................................................................................................... 27
9.5 RESET operation ................................................................................................................ 28
9.5.1 RESET (FFh) ........................................................................................................................ 28
9.6 WRITE PROTECT .............................................................................................................. 29
10. ELECTRICAL CHARACTERISTICS............................................................................................... 31
10.1 Absolute Maximum Ratings (1.8V) ..................................................................................... 31
W29N01HZ/W
Release Date: November, 9th, 2016
3 Revision A
10.2 Operating Ranges (1.8V) ................................................................................................... 31
10.3 Device power-up timing ...................................................................................................... 32
10.4 DC Electrical Characteristics .............................................................................................. 33
10.5 AC Measurement Conditions ............................................................................................. 34
10.6 AC timing characteristics for Command, Address and Data Input (1.8V) .......................... 35
10.7 AC timing characteristics for Operation (1.8V) ................................................................... 36
10.8 Program and Erase Characteristics ................................................................................... 37
11. TIMING DIAGRAMS ....................................................................................................................... 38
12. INVALID BLOCK MANAGEMENT .................................................................................................. 47
12.1 Invalid blocks ...................................................................................................................... 47
12.2 Initial invalid blocks ............................................................................................................. 47
12.3 Error in operation ................................................................................................................ 48
12.4 Addressing in program operation ....................................................................................... 49
13. PACKAGE DIMENSIONS ............................................................................................................... 50
13.1 TSOP 48-pin 12x20 ............................................................................................................ 50
13.2 Fine-Pitch Ball Grid Array 48-ball ....................................................................................... 51
13.3 Fine-Pitch Ball Grid Array 63-ball ....................................................................................... 52
14. ORDERING INFORMATION .......................................................................................................... 53
15. VALID PART NUMBERS ................................................................................................................ 54
16. REVISION HISTORY ...................................................................................................................... 55
W29N01HZ/W
Release Date: November, 9th, 2016
4 Revision A
List of Tables
Table 3.1 Pin Descriptions .......................................................................................................................... 10
Table 6.1 Addressing .................................................................................................................................. 13
Table 6.2 Addressing .................................................................................................................................. 14
Table 7.1 Mode Selection ........................................................................................................................... 15
Table 8.1 Command Table.......................................................................................................................... 16
Table 9.1 Device ID and configuration codes for Address 00h................................................................... 19
Table 9.2 ONFI identifying codes for Address 20h ..................................................................................... 19
Table 9.3 Parameter Page Output Value .................................................................................................... 21
Table 9.4 Status Register Bit Definition ...................................................................................................... 22
Table 10.1 Absolute Maximum Ratings ...................................................................................................... 31
Table 10.2 Operating Ranges ..................................................................................................................... 31
Table 10.3 DC Electrical Characteristics .................................................................................................... 33
Table 10.4 AC Measurement Conditions .................................................................................................... 34
Table 10.5 AC timing characteristics for Command, Address and Data Input ........................................... 35
Table 10.6 AC timing characteristics for Operation .................................................................................... 36
Table 10.7 Program and Erase Characteristics .......................................................................................... 37
Table 12.1 Valid Block Number .................................................................................................................. 47
Table 12.2 Block failure ............................................................................................................................... 48
Table 15.1 Part Numbers for Industrial Temperature ................................................................................. 54
Table 16.1 History Table ............................................................................................................................. 55
List of Figures
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S) ...................................................................... 7
Figure 3-2 Pin Assignment 48-ball VFBGA (Package Code D) .................................................................... 8
Figure 3-3 Pin Assignment 63-ball VFBGA (Package Code B) .................................................................... 9
Figure 5-1 NAND Flash Memory Block Diagram ........................................................................................ 12
Figure 6-1 Array Organization ..................................................................................................................... 13
Figure 6-2 Array Organization ..................................................................................................................... 14
Figure 9-1 Page Read Operations .............................................................................................................. 17
Figure 9-2 Random Data Output ................................................................................................................. 18
Figure 9-3 Read ID ...................................................................................................................................... 18
Figure 9-4 Read Parameter Page ............................................................................................................... 19
Figure 9-5 Read Status Operation .............................................................................................................. 22
Figure 9-6 Page Program ............................................................................................................................ 23
Figure 9-7 Random Data Input ................................................................................................................... 24
Figure 9-8 Copy Back Program Operation .................................................................................................. 26
Figure 9-9 Copy Back Operation with Random Data Input ......................................................................... 26
Figure 9-10 Block Erase Operation ............................................................................................................. 27
Figure 9-11 Reset Operation....................................................................................................................... 28
Figure 9-12 Erase Enable ........................................................................................................................... 29
Figure 9-13 Erase Disable .......................................................................................................................... 29
W29N01HZ/W
Release Date: November, 9th, 2016
5 Revision A
Figure 9-14 Program Enable ....................................................................................................................... 29
Figure 9-15 Program Disable ...................................................................................................................... 30
Figure 9-16 Program for Copy Back Enable ............................................................................................... 30
Figure 9-17 Program for Copy Back Disable .............................................................................................. 30
Figure 10-1 Power ON/OFF sequence ....................................................................................................... 32
Figure 11-1 Command Latch Cycle ............................................................................................................ 38
Figure 11-2 Address Latch Cycle ................................................................................................................ 38
Figure 11-3 Data Latch Cycle ..................................................................................................................... 39
Figure 11-4 Serial Access Cycle after Read ............................................................................................... 39
Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 40
Figure 11-6 Read Status Operation ............................................................................................................ 40
Figure 11-7 Page Read Operation .............................................................................................................. 41
Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 41
Figure 11-9 Random Data Output Operation .............................................................................................. 42
Figure 11-10 Read ID .................................................................................................................................. 43
Figure 11-11 Page Program........................................................................................................................ 43
Figure 11-12 #CE Don't Care Page Program Operation ............................................................................ 44
Figure 11-13 Page Program with Random Data Input ................................................................................ 44
Figure 11-14 Copy Back ............................................................................................................................. 45
Figure 11-15 Block Erase ............................................................................................................................ 45
Figure 11-16 Reset ..................................................................................................................................... 46
Figure 12-1 flow chart of create initial invalid block table ........................................................................... 48
Figure 12-2 Bad block Replacement ........................................................................................................... 49
Figure 13-1 TSOP 48-pin 12x20mm ........................................................................................................... 50
Figure 13-2 Fine-Pitch Ball Grid Array 48-Ball ............................................................................................ 51
Figure 13-3 Fine-Pitch Ball Grid Array 63-Ball (9x11mm) .......................................................................... 52
Figure 14-1 Ordering Part Number Description .......................................................................................... 53
W29N01HZ/W
Release Date: November, 9th, 2016
6 Revision A
1. GENERAL DESCRIPTION
The W29N01HZ/W (1G-bit) NAND Flash memory provides a storage solution for embedded systems with
limited space, pins and power. It is ideal for code shadowing to RAM, solid state applications and storing
media data such as, voice, video, text and photos. The device operates on a single 1.7V to 1.95V power
supply with active current consumption as low as 13mA at 1.8V and 10uA for CMOS standby current.
The memory array totals 138,412,032 bytes, and organized into 1,024 erasable blocks of 135,168 bytes
(135,168 words). Each block consists of 64 programmable pages of 2,112-bytes (1056 words) each. Each
page consists of 2,048-bytes (1024 words) for the main data storage area and 64-bytes (32words) for the
spare data area (The spare area is typically used for error management functions).
The W29N01HZ/W supports the standard NAND flash memory interface using the multiplexed 8-bit (16-bit)
bus to transfer data, addresses, and command instructions. The five control signals, CLE, ALE, #CE, #RE
and #WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write
Protect) and the RY/#BY (Ready/Busy) for monitoring the device status.
2. FEATURES
Basic Features
– Density : 1Gbit (Single chip solution)
– Vcc : 1.7V to 1.95V
– Bus width : x8 x16(1)
– Operating temperature
Industrial: -40°C to 85°C
Single-Level Cell (SLC) technology.
Organization
– Density: 1G-bit/128M-byte
– Page size
2,112 bytes (2048 + 64 bytes)
1,056 words (1024 + 32 words)
– Block size
64 pages (128K + 4K bytes)
64 pages (64K + 2K words)
Highest Performance
– Read performance (Max.)
Random read: 25us
Sequential read cycle: 25ns
– Write Erase performance
Page program time: 250us(typ.)
Block erase time: 2ms(typ.)
– Endurance 100,000 Erase/Program
Cycles(2)
– 10-years data retention
Command set
– Standard NAND command set
– Additional command support
Copy Back
Lowest power consumption
– Read: 13 mA(typ.)
– Program/Erase:10mA(typ)
– CMOS standby: 10uA(typ.)
Space Efficient Packaging
– 48-ball VFBGA
– 63-ball VFBGA
– Contact Winbond for stacked
packages/KGD
Note:
1. X16 device is for 1.8V MCP only
2. Endurance specification is based on 1bit/528 byte ECC (Error Correcting Code).
W29N01HZ/W
Release Date: November, 9th, 2016
7 Revision A
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W29N01HZ/W is offered in a 48-pin TSOP1 packeage (Code S), 48-ball (Code D) and 63-ball (Code
B) VFBGA package as shown in Figure 3-1 to 3-3, respectively. Package diagrams and dimensions
are illustrated in Section: Package Dimensions.
3.1 Pin assignment 48 pin TSOP1 (x8)
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S)
3
4
1
2
Top View
7
8
5
6
11
12
9
10
15
16
13
14
19
20
17
18
23
24
21
22
46
45
48
47
42
41
44
43
38
37
40
39
34
33
36
35
30
29
32
31
26
25
28
27
48-pin TSOP1
Standard package
12mm x 20mm
N.C
N.C
N.C
N.C
IO5
IO4
IO7
IO6
N.C
Vcc
N.C
N.C
N.C
N.C
Vss
N.C
IO1
IO0
IO3
IO2
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
RY/#BY
#RE
N.C
N.C
N.C
Vcc
#CE
N.C
N.C
CLE
Vss
N.C
#WP
DNU
ALE
#WE
N.C
N.C
N.C
N.C
X8X8
W29N01HZ/W
Release Date: November, 9th, 2016
8 Revision A
3.2 Pin assignment 48 ball VFBGA (x8)
Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D)
3 41 2 5 6
A
B
E
F
C
D
G
H
RY/#BY
#RE N.CN.C
#CE
N.CCLE
Vss
N.C
#WP ALE #WE
N.CN.C N.C N.CN.C N.C
N.CN.C N.C N.C N.C
N.CN.C N.C
N.C N.C N.CN.C
N.C N.C IO5
IO4
IO7
IO6
N.C
N.C
IO1
IO0
IO3IO2 Vss
Vcc
Vcc
Vss
DNU N.C
Top View, ball down
W29N01HZ/W
Release Date: November, 9th, 2016
9 Revision A
3.3 Pin assignment 63 ball VFBGA
3 41 2 7 85 6
A
B
910
E
F
C
D
J
K
G
H
L
M
N.CN.C
N.C
RY/#BY
#RE N.CN.C
#CE
N.CCLE
Vss
N.C
#WP ALE #WE
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.CN.C N.C N.CN.C N.C
N.CN.C N.C N.C N.C
N.CN.C N.C
N.C N.C N.CN.C
N.C N.C IO5
IO4
IO7
IO6
N.C
N.C
IO1
IO0
IO3IO2 Vss
Vcc
Vcc
Vss
DNU N.C
Top View, ball down
Figure 3-3 Pin Assignment 63-ball VFBGA (Package Code B)
W29N01HZ/W
Release Date: November, 9th, 2016
10 Revision A
3.4 Pin Descriptions
PIN NAME
I/O
FUNCTION
#WP
I
Write Protect
ALE
I
Address Latch Enable
#CE
I
Chip Enable
#WE
I
Write Enable
RY/#BY
O
Ready/Busy
#RE
I
Read Enable
CLE
I
Command Latch Enable
I/O[0-7]
I/O[0-15]
I/O
Data Input/Output (x8,x16)
Vcc
Supply
Power supply
Vss
Supply
Ground
DNU
-
Do Not Use: This pins are unconnected pins.
N.C
-
No Connect
Table 3.1 Pin Descriptions
Note:
1. Connect all Vcc and Vss pins to power supply or ground. Do not leave Vcc or Vss disconnected.
W29N01HZ/W
Release Date: November, 9th, 2016
11 Revision A
4. PIN DESCRITPIONS
4.1 Chip Enable (#CE)
#CE pin enables and disables device operation. When #CE is high the device is disabled and the I/O
pins are set to high impedance and enters into standby mode if not busy. When #CE is set low the
device will be enabled, power consumption will increase to active levels and the device is ready for
Read and Write operations.
4.2 Write Enable (#WE)
#WE pin enables the device to control write operations to input pins of the device. Such as, command
instructions, addresses and data that are latched on the rising edge of #WE.
4.3 Read Enable (#RE)
#RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on the
I/O bus after the tREA period from the falling edge of #RE. Column addresses are incremented for
each #RE pulse.
4.4 Address Latch Enable (ALE)
ALE pin controls address input to the address register of the device. When ALE is active high,
addresses are latched via the I/O pins on the rising edge of #WE.
4.5 Command Latch Enable (CLE)
CLE pin controls command input to the command register of the device. When CLE is active high,
commands are latched into the command register via I/O pins on the rising edge of #WE.
4.6 Write Protect (#WP)
#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is active
low, all program/erase operations are disabled.
4.7 Ready/Busy (RY/#BY)
RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is
processing either a program, erase or read operations. When it returns to high, those operations have
completed. RY/#BY pin is an open drain.
4.8 Input and Output (I/Ox)
I/Ox bi-directional pins are used for the following; command, address and data operations.
W29N01HZ/W
Release Date: November, 9th, 2016
12 Revision A
5. BLOCK DIAGRAM
Figure 5-1 NAND Flash Memory Block Diagram
Figure 5-1 NAND Flash Memory Block Diagram
Memory array
Data register
IO control
unit
Status
register
Address
latch
Command
latch
Logic
Control
Control
unit
Column decode unit
Row decode unit
High
Voltage
Generator
RY/#BY
RY/#BY
#CE
CLE
#WE
#RE
#WP
ALE
IO0 to IO7
IO8 to IO15
(x16 only)
W29N01HZ/W
Release Date: November, 9th, 2016
13 Revision A
6. MEMORY ARRAY ORGANIZATION
6.1 Array Organization (x8)
Figure 6-1 Array Organization
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd cycle
L
L
L
L
A11
A10
A9
A8
3rd cycle
A19
A18
A17
A16
A15
A14
A13
A12
4th cycle
A27
A26
A25
A24
A23
A22
A21
A20
Table 6.1 Addressing
Notes:
1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.
2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A27 during the 3rd and 4th cycles
are row addresses.
3. The device ignores any additional address inputs that exceed the device’s requirement.
2048
1 block
64
2112 bytes
Data register
Total
1024 blocks
1 page = 2048+64 bytes
1 block = 64 pages
= (128K+4K) bytes
1 device =1024 blocks
= (128M + 4M) bytes
IO0 ~ IO7
W29N01HZ/W
Release Date: November, 9th, 2016
14 Revision A
6.2 Array Organization (x16)
Figure 6-2 Array Organization
I/O8~15
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st cycle
L
A7
A6
A5
A4
A3
A2
A1
A0
2nd cycle
L
L
L
L
L
L
A10
A9
A8
3rd cycle
L
A18
A17
A16
A15
A14
A13
A12
A11
4th cycle
L
A26
A25
A24
A23
A22
A21
A20
A19
Table 6.2 Addressing
Notes:
* “L” must to be held Low during the address cycle is inputted
* A0 to A10 of 1st and 2nd cycle are column address, A11 to A26 of 3rd and 4th cycle are row address
* The device ignores any additional address input than the device is required
1024
1 block
32
1056 words
Data register
Total
1024 blocks
1 page = 1024+32 words
1 block = 64 pages
= (64K+2K) words
1 device =1024 blocks
= (64M + 2M) words
IO0 ~ IO15
W29N01HZ/W
Release Date: November, 9th, 2016
15 Revision A
7. MODE SELECTION TABLE
MODE
CLE
ALE
#CE
#WE
#RE
#WP
Read
mode
Command input
H
L
L
H
X
Address input
L
H
L
H
X
Program
Erase
mode
Command input
H
L
L
H
H
Address input
L
H
L
H
H
Data input
L
L
L
H
H
Sequential Read and Data output
L
L
L
H
X
During read (busy)
X
X
X
X
H
X
During program (busy)
X
X
X
X
X
H
During erase (busy)
X
X
X
X
X
H
Write protect
X
X
X
X
X
L
Standby
X
X
H
X
X
0V/Vcc
Table 7.1 Mode Selection
Notes:
1. “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.
2. #WP should be biased to CMOS HIGH or LOW for standby.
W29N01HZ/W
Release Date: November, 9th, 2016
16 Revision A
8. COMMAND TABLE
COMMAND
1ST
CYCLE
2ND
CYCLE
3rd
CYCLE
4th
CYCLE
Acceptable
during
busy
PAGE READ
00h
30h
READ for COPY BACK
00h
35h
READ ID
90h
READ STATUS
70h
Yes
RESET
FFh
Yes
PAGE PROGRAM
80h
10h
PROGRAM for COPY BACK
85h
10h
BLOCK ERASE
60h
D0h
RANDOM DATA INPUT*1
85h
RANDOM DATA OUTPUT*1
05h
E0h
READ PARAMETER PAGE
ECh
Table 8.1 Command Table
Notes:
1. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.
2. Any command that are not in the above table are considered as undefined and are prohibited as inputs.
W29N01HZ/W
Release Date: November, 9th, 2016
17 Revision A
9. DEVICE OPERATIONS
9.1 READ operation
9.1.1 PAGE READ (00h-30h)
When the device powers on, 00h command is latched to command register. Therefore, system only
issues four address cycles and 30h command for initial read from the device. This operation can also
be entered by writing 00h command to the command register, and then write four address cycles,
followed by writing 30h command. After writing 30h command, the data is transferred from NAND
array to Data Register during tR. Data transfer progress can be done by monitoring the status of the
RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is an alternate
method by using the READ STATUS (70h) command. If the READ STATUS command is issued
during read operation, the Read (00h) command must be re-issued to read out the data from Data
Register. When the data transfer is complete, RY/#BY signal goes HIGH, and the data can be read
from Data Register by toggling #RE. Read is sequential from initial column address to the end of the
page. (See Figure 9-1)
Figure 9-1 Page Read Operations
Address (4cycles) 30h Data Output (Serial Access)
Don’t care
l/Ox
#RE
RY/#BY
ALE
#WE
#CE
CLE
00h
tR
W29N01HZ/W
Release Date: November, 9th, 2016
18 Revision A
9.1.2 RANDOM DATA OUTPUT (05h-E0h)
The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data
from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is
available after the PAGE READ (00h-30h) sequence by writing the 05h command following by the
two cycle column address and then the E0h command. Toggling #RE will output data sequentially.
The RANDOM DATA OUTPUT command can be issued multiple times, but limited to the current
loaded page.
Figure 9-2 Random Data Output
9.1.3 READ ID (90h)
READ ID command is comprised of two modes determined by the input address, device (00h) or
ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command
Register followed by a 00h address cycle, then toggle #RE for 5 single byte cycles, W29N01HZ/W.
The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific Information
(see Table 9.1). If the READ ID command is followed by 20h address, the output code includes 4
single byte cycles of ONFI identifying information (See Table 9.2). The device remains in the READ
ID Mode until the next valid command is issued.
I/Ox
#WE
#RE
CLE
#CE
ALE
tAR
90h
(or 20h)
Address, 1 cycle
00h Byte 1
Byte 0
tREA
Byte 2 Byte 4
Byte 3
tWHR
Figure 9-3 Read ID
#RE
RY/#BY
I/Ox 05h E0h
Address(2cycles)
30h
Address(4cycles)
tR
Data out Data out
00h
W29N01HZ/W
Release Date: November, 9th, 2016
19 Revision A
# of
Byte/Cycles
1st
Byte/Cycle
2nd
Byte/Cycle
3rd
Byte/Cycle
4th
Byte/Cycle
5th
Byte/Cycle
W29N01HZ
EFh
A1h
00h
95h
00h
W29N01HW
EFh
B1h
00h
D5h
00h
Description
MFR ID
Device ID
Cache
Programming
Non-supported
Page Size:2KB
Spare Area Size:64b
BLK Size w/o
Spare:128KB
Organized:x8 or x16
Serial Access:25ns
x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.
Table 9.1 Device ID and configuration codes for Address 00h
# of Byte/Cycles
1st
Byte/Cycle
2nd
Byte/Cycle
3rd
Byte/Cycle
4th
Byte/Cycle
Code
4Fh
4Eh
46h
49h
Table 9.2 ONFI identifying codes for Address 20h
9.1.4 READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE can read out the device’s parameter data structure, such as,
manufacturer information, device organization, timing parameters, key features, and other pertinent
device parameters. The data structure is stored with at least three copies in the device’s parameter
page. Figure 9-4 shows the READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT (05h-
E0h) command is supported during data output.
I/Ox
CLE
#WE
ALE
#RE
RY/#BY
ECh P000h
tR
・・・ P1022 P1023
P1
Figure 9-4 Read Parameter Page
W29N01HZ/W
Release Date: November, 9th, 2016
20 Revision A
Byte
Description
Value
0-3
Parameter page signature
4Fh, 4Eh, 46h, 49h
4-5
Revision number
02h, 00h
6-7
Features
supported
W29N01HZ
10h, 00h
W29N01HW
11h, 00h
8-9
Optional commands supported
10h, 00h
10-31
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
32-43
Device manufacturer
57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,
20h
44-63
Device model
W29N01HZ
57h, 32h, 39h, 4Eh, 30h, 31h, 48h, 5Ah, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h
W29N01HW
57h, 32h, 39h, 4Eh, 30h, 31h, 48h, 57h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h
64
Manufacturer ID
EFh
65-66
Date code
00h, 00h
67-79
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
80-83
# of data bytes per page
00h, 08h, 00h, 00h
84-85
# of spare bytes per page
40h, 00h
86-89
# of data bytes per partial page
00h, 02h, 00h, 00h
90-91
# of spare bytes per partial page
10h, 00h
92-95
# of pages per block
40h, 00h, 00h, 00h
96-99
# of blocks per unit
00h, 04h, 00h, 00h
100
# of logical units
01h
101
# of address cycles
22h
102
# of bits per cell
01h
103-104
Bad blocks maximum per unit
14h, 00h
105-106
Block endurance
01h, 05h
107
Guaranteed valid blocks at beginning of
target
01h
108-109
Block endurance for guaranteed valid
blocks
00h, 00h
110
# of programs per page
04h
111
Partial programming attributes
00h
112
# of ECC bits
01h
W29N01HZ/W
Release Date: November, 9th, 2016
21 Revision A
Byte
Description
Value
113
# of interleaved address bits
00h
114
Interleaved operation attributes
00h
115-127
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
128
I/O pin capacitance
0Ah
129-130
Timing mode
support
W29N01HZ
07h, 00h
W29N01HW
07h, 00h
131-132
Program cache timing
00h, 00h
133-134
Maximum page program time
BCh, 02h
135-136
Maximum block erase time
10h, 27h
137-138
Maximum random read time
19h, 00h
139-140
W29N01HZ
50h, 00h
W29N01HW
50h, 00h
141-163
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h
164-165
Vendor specific revision #
01h,00h
166-253
Vendor specific
00h
254-255
Integrity CRC
Set at shipment
256-511
Value of bytes 0-255
512-767
Value of bytes 0-255
>767
Additional redundant parameter pages
x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.
Table 9.3 Parameter Page Output Value
9.1.5 READ STATUS (70h)
The W29N01HZ/W has an 8-bit Status Register which can be read during device operation. Refer to
Table 9.4 for specific Status Register definitions. After writing 70h command to the Command
Register, read cycles will only read from the Status Register. The status can be read from I/O[7:0]
outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status Register
read. The Command Register remains in status read mode until another command is issued. To
change to normal read mode, issue the PAGE READ (00h) command. After the PAGE READ
command is issued, data output starts from the initial column address.
W29N01HZ/W
Release Date: November, 9th, 2016
22 Revision A
#CE
CLE
#WE
#RE
tCLR
I/Ox 70h Status Output
tREA
Figure 9-5 Read Status Operation
SR bit
Page Read
Page Program
Block Erase
Definition
I/O 0
Not Use
Pass/Fail
Pass/Fail
0=Successful Program/Erase
1=Error in Program/Erase
I/O 1
Not Use
Not Use
Not Use
0
I/O 2
Not Use
Not Use
Not Use
0
I/O 3
Not Use
Not Use
Not Use
0
I/O 4
Not Use
Not Use
Not Use
0
I/O 5
Ready/Busy
Ready/Busy
Ready/Busy
Ready = 1
Busy = 0
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Ready = 1
Busy = 0
I/O 7
Write Protect
Write Protect
Write Protect
Unprotected = 1
Protected = 0
Table 9.4 Status Register Bit Definition
W29N01HZ/W
Release Date: November, 9th, 2016
23 Revision A
9.2 PROGRAM operation
9.2.1 PAGE PROGRAM (80h-10h)
The W29N01HZ/W Page Program command will program pages sequentially within a block, from the
lower order page address to higher order page address. Programming pages out of sequence is
prohibited. The W29N01HZ/W supports partial-page programming operations up to 4 times before an
erase is required if partitioning a page. Note; programming a single bit more than once without first
erasing it is not supported.
9.2.2 SERIAL DATA INPUT (80h)
Page Program operation starts with the execution of the Serial Data Input command (80h) to the
Command Register, following next by inputting four address cycles and then the data is loaded. Serial
data is loaded to Data register with each #WE cycle. The Program command (10h) is written to the
Command Register after the serial data input is finished. At this time the internal write state controller
automatically executes the algorithms for program and verifies operations. Once the programming
starts, determining the completion of the program process can be done by monitoring the RY/#BY
output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will stay LOW during
the internal array programming operation during the period of (tPROG). During page program
operation, only two commands are available, READ STATUS (70h) and RESET (FFh). When the
device status goes to the ready state, Status Register Bit 0 (I/O0) indicates whether the program
operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-6). The Command Register remains in
read status mode until the next command is issued.
Figure 9-6 Page Program
tPROG
Address (4cycles)
RY/#BY
I/Ox Din80h 10h 70h Status
I/O0 =0 pass
I/O0 =1 fail
W29N01HZ/W
Release Date: November, 9th, 2016
24 Revision A
9.2.3 RANDOM DATA INPUT (85h)
After the Page Program (80h) execution of the initial data has been loaded into the Data register, if
the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command
can perform this function to a new column address prior to the Program (10h) command. The
RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-7).
Figure 9-7 Random Data Input
RY/#BY
I/Ox
CLE
#WE
ALE
#RE
#CE
Din 70h Status
Address (4cycles)
80h 10h
Address
(2 cycles)
85h Din
tPROG
Don’t care
W29N01HZ/W
Release Date: November, 9th, 2016
25 Revision A
9.3 COPY BACK operation
Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h)
command first, then the PROGRAM for COPY BACK (85h-10h) command.
9.3.1 READ for COPY BACK (00h-35h)
The READ for COPY BACK command is used together with the PROGRAM for COPY BACK (85h-
10h) command. To start execution, READ for COPY BACK (00h) command is written to the Command
Register, followed by the four cycles of the source page address. To start the transfer of the selected
page data from the memory array to the Data register, write the 35h command to the Command
Register.
After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH
marking the completion of the operation, the transferred data from the source page into the Data
register may be read out by toggling #RE. Data is output sequentially from the column address that
was originally specified with the READ for COPY BACK command. RANDOM DATA OUTPUT (05h-
E0h) commands can be issued multiple times without any limitation after READ for COPY BACK
command has been executed (see Figures 9-8 and 9-9).
At this point the device is in ready state to accept the PROGRAM for COPY BACK command.
9.3.2 PROGRAM for COPY BACK (85h-10h)
After the READ for COPY BACK command operation has been completed and RY/#BY goes HIGH,
the PROGRAM for COPY BACK command can be written to the Command Register. The command
results in the transfer of data to the Data Register, then internal operations start programming of the
new destination page. The sequence would be, write 85h to the Command Register, followed by the
four cycle destination page address to the NAND array. Next write the 10h command to the Command
Register; this will signal the internal controller to automatically start to program the data to new
destination page. During this programming time, RY/#BY will LOW. The READ STATUS command
can be used instead of the RY/#BY signal to determine when the program is complete. When Status
Register Bit 6 (I/O6) equals to “1”, Status Register Bit 0 (I/O0) will indicate if the operation was
successful or not.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for COPY BACK
command for modifying the original data. Once the data is copied into the Data register using the
READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h)
command, along with the address of the data to be changed. The data to be changed is placed on
the external data pins. This operation copies the data into the Data register. Once the 10h command
is written to the Command Register, the original data and the modified data are transferred to the
Data Register, and programming of the new page commences. The RANDOM DATA INPUT
command can be issued numerous times without limitation, as necessary before starting the
programming sequence with 10h command.
Since COPY BACK operations do not use external memory and the data of source page might include
a bit errors, a competent ECC scheme should be developed to check the data before programming
data to a new destination page.
W29N01HZ/W
Release Date: November, 9th, 2016
26 Revision A
Optional
Data output
No limitation
RY / # BY
I/ Ox
tR tPROG
CLE
#WE
ALE
#RE
#CE
Data Output
00h Address (4cycles) 35h 05h Address
(2cycles) E0h 85h Address(4cycles) 10h 70h Status
Output
Don’t care
Optional No limitation
RY/#BY
I/Ox
tR
CLE
#WE
ALE
#RE
#CE
00h35h85h10h
tPROG
70h
DataOutput 85h
Don’t care
Address(4Cycles) Data Input Data Input
Figure 9-9 Copy Back Operation with Random Data Input
Figure 9-8 Copy Back Program Operation
W29N01HZ/W
Release Date: November, 9th, 2016
27 Revision A
9.4 BLOCK ERASE operation
9.4.1 BLOCK ERASE (60h-D0h)
Erase operations happen at the architectural block unit. This W29N01HZ/W has 1024 erase blocks.
Each block is organized into 64 pages (x8:2112 bytes/page, x16:1056 words/page), 132K bytes
(x8:128K + 4K bytes, x16:64 K+ 2Kwords)/block. The BLOCK ERASE command operates on a block
by block basis.
Erase Setup command (60h) is written to the Command Register. Next, the two cycle block address
is written to the device. The page address bits are loaded during row address cycle, but are ignored.
The Erase Confirm command (D0h) is written to the Command Register at the rising edge of #WE,
RY/#BY goes LOW and the internal controller automatically handles the block erase sequence of
operation. RY/#BY goes LOW during Block Erase internal operations for a period of tBERS,
The READ STATUS (70h) command can be used for confirm block erase status. When Status
Register Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0) will
indicate a pass/fail condition (see Figure 9-10).
Figure 9-10 Block Erase Operation
CLE
#WE
ALE
RY/#BY
#CE
#RE
I/Ox
tBERS
I/ O 0 =0 pass
I/ O 0 =1 fail
Address Input (2cycles)
60hD0h Status Output
70h
Don’t care
W29N01HZ/W
Release Date: November, 9th, 2016
28 Revision A
9.5 RESET operation
9.5.1 RESET (FFh)
READ, PROGRAM, and ERASE commands can be aborted by the RESET (FFh) command during
the time the W29N01HZ/W is in the busy state. The Reset operation puts the device into known status.
The data that is processed in either the programming or erasing operations are no longer valid. This
means the data can be partially programmed or erased and therefore data is invalid. The Command
Register is cleared and is ready to accept next command. The Data Register contents are marked
invalid.
The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is written
when #WP is LOW. After RESET command is written to the command register, RY/#BY goes LOW
for a period of tRST (see Figure 9-11).
CLE
#WE
RY/#BY
#CE
I/Ox
RESET
command
tRST
tWB
FFh
Figure 9-11 Reset Operation
W29N01HZ/W
Release Date: November, 9th, 2016
29 Revision A
9.6 WRITE PROTECT
#WP pin can enable or disable program and erase commands preventing or allowing program and
erase operations. Figure 9-12 to 9-17 shows the enabling or disabling timing with #WP setup time
(tWW) that is from rising or falling edge of #WP to latch the first commands. After first command is
latched, #WP pin must not toggle until the command operation is complete and the device is in the
ready state. (Status Register Bit5 (I/O5) equal 1)
I /Ox
#WE
#WP
tWW
RY/#BY
60h D0h
Figure 9-12 Erase Enable
I/Ox
#WE
#WP
tWW
RY/#BY
60h D0h
Figure 9-13 Erase Disable
I/Ox
#WE
#WP
tWW
RY/#BY
10h10h
80h
Figure 9-14 Program Enable
W29N01HZ/W
Release Date: November, 9th, 2016
30 Revision A
I/Ox
# WE
#WP
80 h
tWW
RY/#BY
10h
Figure 9-15 Program Disable
I/Ox
#WE
#WP
85h
tWW
RY/#BY
10h
Figure 9-16 Program for Copy Back Enable
I/Ox
#WE
# WP
85h
tWW
RY/#BY
10h
Figure 9-17 Program for Copy Back Disable
W29N01HZ/W
Release Date: November, 9th, 2016
31 Revision A
10. ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings (1.8V)
PARAMETERS
SYMBOL
CONDITIONS
RANGE
UNIT
Supply Voltage
VCC
–0.6 to +2.4
V
Voltage Applied to Any Pin
VIN
Relative to Ground
–0.6 to +2.4
V
Storage Temperature
TSTG
–65 to +150
°C
Short circuit output current, I/Os
5
mA
Table 10.1 Absolute Maximum Ratings
Notes:
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for
periods <30ns.
2. Maximum DC voltage on input/output pins is Vcc+0.3V which, during transitions, may overshoot to Vcc+2.0V
for periods <20ns.
3. This device has been designed and tested for the specified operation ranges. Proper operation outside of
these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
10.2 Operating Ranges (1.8V)
PARAMETER
SYMBOL
CONDITIONS
SPEC
UNIT
MIN
MAX
Supply Voltage
VCC
1.7
1.95
V
Ambient Temperature,
Operating
TA
Industrial
-40
+85
°C
Table 10.2 Operating Ranges
W29N01HZ/W
Release Date: November, 9th, 2016
32 Revision A
10.3 Device power-up timing
The device is designed to avoid unexpected program/erase operations during power transitions.
When the device is powered on, an internal voltage detector disables all functions whenever Vcc is
below about 2V at 3V device, 1.1V at 1.8V device.. Write Protect (#WP) pin provides hardware
protection and is recommended to be kept at VIL during power up and power down. A recovery time
of minimum 1ms is required before internal circuit gets ready for any command sequences (See
Figure 10-1).
Figure 10-1 Power ON/OFF sequence
5 ms (Max)
Vcc
RY/#BY
1ms
(Min)
Undefined
#WP
#WE
W29N01HZ/W
Release Date: November, 9th, 2016
33 Revision A
10.4 DC Electrical Characteristics
PARAMETER
SYMBOL
CONDITIONS
SPEC
UNIT
MIN
TYP
MAX
Sequential Read current
Icc1
tRC= tRC MIN
#CE=VIL
IOUT=0mA
-
13
25
mA
Program current
Icc2
-
-
10
25
mA
Erase current
Icc3
-
-
10
25
mA
Standby current (TTL)
ISB1
#CE=VIH
#WP=0V/Vcc
-
-
1
mA
Standby current (CMOS)
ISB2
#CE=Vcc – 0.2V
#WP=0V/Vcc
-
10
50
µA
Input leakage current
ILI
VIN= 0 V to Vcc
-
-
±10
µA
Output leakage current
ILO
VOUT=0V to Vcc
-
-
±10
µA
Input high voltage
VIH
I/O15~0, #CE,#WE,#RE,
#WP,CLE,ALE
0.8 x Vcc
-
Vcc + 0.3
V
Input low voltage
VIL
-
-0.3
-
0.2 x Vcc
V
Output high voltage(1)
VOH
IOH=-100µA
Vcc -0.1
-
-
V
Output low voltage(1)
VOL
IOL=+100µA
-
-
0.1
V
Output low current
IOL(RY/#BY)
VOL=0.2V
3
4
mA
Table 10.3 DC Electrical Characteristics
Note:
1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
W29N01HZ/W
Release Date: November, 9th, 2016
34 Revision A
10.6 AC Measurement Conditions
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
Input Capacitance(1), (2)
CIN
-
10
pF
Input/Output Capacitance(1), (2)
CIO
-
10
pF
Input Rise and Fall Times
TR/TF
-
2.5
ns
Input Pulse Voltages
-
0 to VCC
V
Input/Output timing Voltage
-
Vcc/2
V
Output load (1)
CL
1TTL GATE and CL=30pF
-
Table 10.4 AC Measurement Conditions
Notes:
1. Verified on device characterization , not 100% tested
2. Test conditions TA=25’C, f=1MHz, VIN=0V
W29N01HZ/W
Release Date: November, 9th, 2016
35 Revision A
10.7 AC timing characteristics for Command, Address and Data Input (1.8V)
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
ALE to Data Loading Time(1)
tADL
70
-
ns
ALE Hold Time
tALH
5
-
ns
ALE setup Time
tALS
10
-
ns
#CE Hold Time
tCH
5
-
ns
CLE Hold Time
tCLH
5
-
ns
CLE setup Time
tCLS
10
-
ns
#CE setup Time
tCS
20
-
ns
Data Hold Time
tDH
5
-
ns
Data setup Time
tDS
10
-
ns
Write Cycle Time
tWC
25
-
ns
#WE High Hold Time
tWH
10
-
ns
#WE Pulse Width
tWP
12
-
ns
#WP setup Time
tWW
100
-
ns
Table 10.5 AC timing characteristics for Command, Address and Data Input
Note:
1. tADL is the time from the #WE rising edge of final address cycle to the #WE rising edge of first data cycle.
W29N01HZ/W
Release Date: November, 9th, 2016
36 Revision A
10.8 AC timing characteristics for Operation (1.8V)
PARAMETER
SYMBOL
SPEC
UNIT
MIN
MAX
ALE to #RE Delay
tAR
10
-
ns
#CE Access Time
tCEA
-
25
ns
#CE HIGH to Output High-Z(1)
tCHZ
-
50
ns
CLE to #RE Delay
tCLR
10
-
ns
#CE HIGH to Output Hold
tCOH
15
-
ns
Output High-Z to #RE LOW
tIR
0
-
ns
Data Transfer from Cell to Data Register
tR
-
25
µs
READ Cycle Time
tRC
25
-
ns
#RE Access Time
tREA
-
22
ns
#RE HIGH Hold Time
tREH
10
-
ns
#RE HIGH to Output Hold
tRHOH
15
-
ns
#RE HIGH to #WE LOW
tRHW
100
-
ns
#RE HIGH to Output High-Z(1)
tRHZ
-
100
ns
#RE LOW to output hold
tRLOH
3
-
ns
#RE Pulse Width
tRP
12
-
ns
Ready to #RE LOW
tRR
20
-
ns
Reset Time (READ/PROGRAM/ERASE)(2)
tRST
-
5/10/500
µs
#WE HIGH to Busy(3)
tWB
-
100
ns
#WE HIGH to #RE LOW
tWHR
80
-
ns
Table 10.6 AC timing characteristics for Operation
Notes:
1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not
100 % tested
2. The RESET (FFh) command is issued while the device is idle, the device goes busy for a maximum of 5us.
3. Do not issue new command during tWB, even if RY/#BY is ready.
W29N01HZ/W
Release Date: November, 9th, 2016
37 Revision A
10.9 Program and Erase Characteristics
PARAMETER
SYMBOL
SPEC
UNIT
TYP
MAX
Number of partial page programs
NoP
-
4
cycles
Page Program time
tPROG
250
700
µs
Block Erase Time
tBERS
2
10
ms
Table 10.7 Program and Erase Characteristics
W29N01HZ/W
Release Date: November, 9th, 2016
38 Revision A
11. TIMING DIAGRAMS
Figure 11-1 Command Latch Cycle
Figure 11-2 Address Latch Cycle
tCS
Command
tWP
tCLHtCLS
tCH
tALS tALH
tDS tDH
Don’t care
CLE
#WE
ALE
I/Ox
#CE
tCS
Address
tWP
tWC
tALS tALH
tDS tDH
tCLS
tWH
Don’t care Undefined
CLE
#CE
I/Ox
#WE
ALE
W29N01HZ/W
Release Date: November, 9th, 2016
39 Revision A
Note: 1. Din Final = 2,111(x8)
Figure 11-3 Data Latch Cycle
Figure 11-4 Serial Access Cycle after Read
Din 0
tWP
tCLH
tALS
tDS tDH
tWP tWP
Din 1
tDS tDH
tWH
Din Final1
tDS tDH
tCH
tWC
Don’t care
CLE
#CE
I/Ox
#WE
ALE
tCHZ
tCEA
tRP
tRHZ
Dout Dout
tREA
tREH
tREA
Dout
tREA
tRHOH
tCOH
tRHZ
tRR tRC
Don’t care
#CE
I/Ox
#RE
RY/#BY
W29N01HZ/W
Release Date: November, 9th, 2016
40 Revision A
Figure 11-5 Serial Access Cycle after Read (EDO)
Figure 11-6 Read Status Operation
tCHZ
tCEA
tRP
Dout
tREA
tREH
tREA
tCOH
tRHZ
tRR
tRC
Dout
tRHOH
tRLOH
Don’t care
I/Ox
RY/#BY
#RE
#CE
Dout
#CE
#RE
#WE
tWP tCH
tRHZ
tCHZ
CLE
I/Ox
tCOH
Status
output
tRHOH
tRP
tCEA
tCS
tCLR
tCLS tCLH
70h
tDS tDH tIR tREA
tWHR
Don’t care
W29N01HZ/W
Release Date: November, 9th, 2016
41 Revision A
Busy
Dout
n+1
Dout
n
Dout
m
00h 30h
tAR
tWB
tCLR
tRC
tRR
tWC
tRP
tRHZ
tR
I/Ox
#WE
ALE
#RE
RY/#BY
CLE
#CE
Don’t care
Address(4Cycles)
Figure 11-7 Page Read Operation
CLE
#WE
ALE
#CE
#RE
I/Ox
Out
tCEA
tREA
tCOH
tCHZ
#CE
#RE
I/Ox
tR
00h Address (4 cycles) 30h Data output
Don’t care
RY/#BY
Figure 11-8 #CE Don't Care Read Operation
W29N01HZ/W
Release Date: November, 9th, 2016
42 Revision A
tRC
tRR
Column address n
tREA
Column address m
tCLR
tAR
tWB
tWC
tWHR
00h30h05h E0h
Busy
tR
#WE
ALE
#RE
RY/#BY
CLE
#CE
I/Ox
Don’t care
tRHW
Figure 11-9 Random Data Output Operation
W29N01HZ/W
Release Date: November, 9th, 2016
43 Revision A
Note: 1. See Table 9.1 for actual value.
Figure 11-10 Read ID
I/Ox
#WE
ALE
#RE
RY/#BY
CLE
#CE
Din
m
Din
n
80h Col
add 1 Col
add 2
tWC
Row
add 1 Row
add 2 Status
SERIAL DATA
INPUT command
70h
tPROGtWB
tADL
10h
1 up to m Byte
serial input
PROGRAM
command
READ STATUS
command
x8 device:m = 2112 bytes
tWHR
Don’t care
Figure 11-11 Page Program
I/Ox
#WE
#RE
CLE
#CE
ALE
tAR
90h
(or 20h)
Address, 1 cycle
00h Byte 1
Byte 0
tREA
Byte 2 Byte 4
Byte 3
tWHR
W29N01HZ/W
Release Date: November, 9th, 2016
44 Revision A
I/Ox
CLE
#WE
ALE
#CE
80h Address(4 cycles) Data input Data input 10h
#WE
#CE
tCS tCH
tWP
Don’t care
Figure 11-12 #CE Don't Care Page Program Operation
I/Ox
CLE
#WE
ALE
#RE
#CE
80h Col
add 2
Col
add 1
ｔWC
Din
ｎ
Din
N+1
Serial Data
Input Command
85h Status
70h
10h
Din
N+1
Serial INPUT
Command
Program
Command
tADL
tWB
tPROG
Random Data Input
Command
RY/#BY
Column address Serial INPUT
Row
add2
tADL
Col
add1 Col
add2 Din
ｎ
Don’t care
Row
add1
Figure 11-13 Page Program with Random Data Input
W29N01HZ/W
Release Date: November, 9th, 2016
45 Revision A
Figure 11-14 Copy Back
#RE
RY/#BY
CLE
#CE
#WE
ALE
Busy
60h D0h
tBERS
tWC
Status
70h
BLOCK ERASE SETUP
command
ERASE
command READ STATUS
command
tWB
I/Ox
Don’t care
Address(2cycles)
Figure 11-15 Block Erase
00h
ｔWC
Serial data INPUT
Command
tADL
Program
Command
tWB
tPROG
I/Ox
CLE
#WE
ALE
#RE
#CE
RY/#BY
tWB
tR
Busy
Col
add 1 Col
add 2 Row
add1 Row
add2 35h85hCol
add 1 Col
add 2 Row
add1 Row
add2 Din
1Din
n10h Status
70h
Don’t care
W29N01HZ/W
Release Date: November, 9th, 2016
46 Revision A
Figure 11-16 Reset
I/Ox
#WE
RY/#BY
CLE
#CE
FFh
tRST
RESET
command
tWB
W29N01HZ/W
Release Date: November, 9th, 2016
47 Revision A
12. INVALID BLOCK MANAGEMENT
12.1 Invalid blocks
The W29N01HZ/W may have initial invalid blocks when it ships from factory. Also, additional invalid
blocks may develop during the use of the device. Nvb represents the minimum number of valid blocks
in the total number of available blocks (See Table 12.1). An invalid block is defined as blocks that
contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid block at the time
of shipment.
Parameter
Symbol
Min
Max
Unit
Valid block number
Nvb
1004
1024
blocks
Table 12.1 Valid Block Number
12.2 Initial invalid blocks
Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from
factory.
Although the device contains initial invalid blocks, a valid block of the device is of the same quality
and reliability as all valid blocks in the device with reference to AC and DC specifications. The
W29N01HZ/W has internal circuits to isolate each block from other blocks and therefore, the invalid
blocks will not affect the performance of the entire device.
Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All initial
invalid blocks are marked with non-FFh at the first byte of spare area on the 1st or 2nd page. The initial
invalid block information cannot be recovered if inadvertently erased. Therefore, software should be
created to initially check for invalid blocks by reading the marked locations before performing any
program or erase operation, and create a table of initial invalid blocks as following flow chart
W29N01HZ/W
Release Date: November, 9th, 2016
48 Revision A
Figure 12-1 flow chart of create initial invalid block table
12.3 Error in operation
Additional invalid blocks may develop in the device during its life cycle. Following the procedures
herein is required to guarantee reliable data in the device.
After each program and erase operation, check the status read to determine if the operation failed. In
case of failure, a block replacement should be done with a bad-block management algorithm. The
system has to use a minimum 1-bit ECC per 528 bytes of data to ensure data recovery.
Operation
Detection and recommended procedure
Erase
Status read after erase Block Replacement
Program
Status read after program Block Replacement
Read
Verify ECC ECC correction
Table 12.2 Block failure
W29N01HZ/W
Release Date: November, 9th, 2016
49 Revision A
Figure 12-2 Bad block Replacement
Note:
1. An error happens in the nth page of block A during program or erase operation.
2. Copy the data in block A to the same location of block B which is valid block.
3. Copy the nth page data of block A in the buffer memory to the nth page of block B
4. Creating or updating bad block table for preventing further program or erase to block A
.
12.4 Addressing in program operation
The pages within the block have to be programmed sequentially from LSB (least significant bit) page
to the MSB (most significant bit) within the block. The LSB is defined as the start page to program,
does not need to be page 0 in the block. Random page programming is prohibited.
W29N01HZ/W
Release Date: November, 9th, 2016
50 Revision A
13. PACKAGE DIMENSIONS
13.1 TSOP 48-pin 12x20
Figure 13-1 TSOP 48-pin 12x20mm
e
1
48
b
E
D
Y
A1
A
A2
L1
L
c
H
D
0.020
0.004
0.007
0.037
0.002
MIN.
0.60
Y
L
L1
c
0.50
0.10
0.70
0.21
MILLIMETER
A
A2
b
A1
0.95
0.17
0.05
Symbol
MIN.
1.20
0.27
1.05
1.00
0.22
MAX.
NOM.
0.028
0.008
0.024
0.011
0.041
0.047
0.009
0.039
NOM.
INCH
MAX.
E
H
D
0
5
0
5
e
D
18.3
18.4
18.5
19.8
20.0
20.2
11.9
12.0
12.1
0.720
0.724
0.728
0.780
0.787
0.795
0.468
0.472
0.476
0.10
0.80
0.031
0.004
0.020
0.50
W29N01HZ/W
Release Date: November, 9th, 2016
51 Revision A
13.2 Fine-Pitch Ball Grid Array 48-ball
Figure 13-2 Fine-Pitch Ball Grid Array 48-Ball
W29N01HZ/W
Release Date: November, 9th, 2016
52 Revision A
13.3 Fine-Pitch Ball Grid Array 63-ball
Figure 13-3 Fine-Pitch Ball Grid Array 63-Ball (9x11mm)
W29N01HZ/W
Release Date: November, 9th, 2016
53 Revision A
14. ORDERING INFORMATION
Figure 14-1 Ordering Part Number Description
Winbond Standard Product
W: Winbond
Product Family
ONFI compatible NAND Flash memory
Density
01: 1 Gbit
Product Version
H
Supply Voltage and Bus Width
Z: 1.7~1.95V and X8 device
W: 1.7~1.95V and X16 device
Packages
D: VFBGA-48
B: VFBGA-63 (9*11)
Temparature Ranges
I: -40 to 85'C
Option Information
N: General product
Reserved
A: 1bit-ECC
W
29N
01
H
Z
I
N
A
D
S: TSOP-48
W29N01HZ/W
Release Date: November, 9th, 2016
54 Revision A
15. VALID PART NUMBERS
The following table provides the valid part numbers for the W29N01HZ/W NAND Flash Memory.
Please contact Winbond for specific availability by density and package type. Winbond NAND Flash
memories use a 12-digit Product Number for ordering.
Part Numbers for Industrial Temperature:
PACKAGE
TYPE
DENSITY
VCC
BUS
PRODUCT NUMBER
TOP SIDE MARKING
S
TSOP-48
1G-bit
1.8V
X8
W29N01HZSINA
W29N01HZSINA
D
VFBGA-48
1G-bit
1.8V
X8
W29N01HZDINA
W29N01HZDINA
B
VFBGA-63
1G-bit
1.8V
X8
W29N01HZBINA
W29N01HZBINA
Table 15.1 Part Numbers for Industrial Temperature
W29N01HZ/W
Release Date: November, 9th, 2016
55 Revision A
16. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
0.1
10/01/15
New Create
0.2
02/01/16
19, 32
Update Parameter Page Output Value
Update Icc1,Icc2,Icc3 maximum value
0.3
03/28/16
7, 50, 53, 54
Add TSOP-48 package
A
11/09/16
Remove “Preliminary”
Table 16.1 History Table
Trademarks
Winbond is trademark of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane
or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Furthermore, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to
a situation where in personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own
risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
