CS1601H-FSZ - Cirrus Logic, Inc.

Cirrus Logic, Inc.

http://www.cirrus.com

CS1601

CS1601H

Digital PFC Controller for Electronic Ballasts

Features

Low PFC System Cost

Best-in-class THD

Digital EMI Noise Shaping Reduces Conducted EMI

Adaptive Switching Frequency Control Minimizes Boost

Inductor Size

High Efficiency Due to Zero-current Switching

Integrated Feedback Compensation Simplifies System

Design

Comprehensive Safety Features

• Undervoltage Lockout (UVLO)

• Output Overvoltage Protection

• Cycle-by-cycle Current Limiting

• Input Voltage Brownout Protection

• Open/Short Loop Protection for IAC & IFB Pins

• Thermal Shutdown

Pin Placement Similar to Traditional Boundary Mode (CRM)

Controllers

Applications

LED Power Supply/Driver

Fluorescent Ballasts

HID Ballasts

Overview

The CS1601 and CS1601H are digital power factor correction

(PFC) controllers designed to deliver the lowest PFC system

cost in electronic ballast applications. The controller operates

in a variable frequency discontinuous conduction mode (VF-

DCM) with zero-current switching optimized to deliver best-in-

class THD and minimize the size and cost of magnetic

components. The CS1601 operates at switching frequencies of

up to 70kHz, and the CS1601H operates at frequencies of up

to 100kHz.

The VF-DCM control algorithm varies both duty cycle and

frequency. This spreads the EMI frequency spectrum, thus

reducing conducted EMI filtering requirements. In addition, the

maximum switching frequency is reached at the peak of the AC

input, which allows the use of a smaller, more cost-effective

boost inductor.

The feedback loop is closed through an integrated

compensation network within the controller, eliminating the

need for additional external components. Protection features

such as overvoltage, overcurrent, open and short-circuit

protection, overtemperature, and brownout protect the system

during abnormal transient conditions.

Ordering Information

See page 16.

R2 R3

R4 R7

C1 C2 Regulated

DC Output

Mains

BR 1

BR1

BR 1

BR1

CS1601

CS1601H

GDZCD

IFB

GND

CSIAC

VDD

STBY

rect

link

FEB’12

DS931F3

CS1601

2DS931F3

1. INTRODUCTION

Figure 1. CS1601 Block Diagram

The CS1601 digital power factor correction (PFC) control IC is

designed to deliver the lowest system cost by reducing the

total number of system components and optimizing the EMI

noise signature, which reduces the conducted EMI filter

requirements. The CS1601 digital algorithm determines the

behavior of the boost converter during startup, normal

operation, and under fault conditions (overvoltage,

overcurrent, and overtemperature).

Figure 1 illustrates a high-level block diagram of the CS1601.

The PFC processor logic regulates the power transfer by

using an adaptive digital algorithm to optimize the PFC active-

switch (MOSFET) drive signal duty cycle and switching

frequency. The adaptive controller uses independent analog-

to-digital converter (ADC) channels when sensing the

feedback and feedforward analog signals required to

implement the digital PFC control algorithm.

The AC mains rectified voltage (on pin IAC) and PFC output

link voltage (on pin IFB) are transformed by the PFC

processor logic and used to generate the optimum PFC

active-switch drive signal (GD) by calculating the optimal

switching frequency and tON time on a cycle-by-cycle basis.

An auxiliary winding is typically added to the PFC boost

inductor to provide zero-current detection (ZCD) information.

The ZCD acts as a demagnetization sensor used to monitor

the PFC active-switching behavior and efficiency. The

auxiliary voltage is normalized using an external attenuator

and is connected to the ZCD pin, providing the CS1601 a

mechanism to detect the valley/zero crossings. The ZCD

comparator looks for the zero crossing on the auxiliary winding

and switches when the auxiliary voltage is below zero.

Switching in the valley of the oscillation minimizes the

switching losses and reduces EMI noise.

The PFC controller uses a current sensor for overcurrent

protection. The boost inductor peak current is measured

across an external resistor in the switching circuit on a cycle-

by-cycle basis. An overcurrent fault is generated when the

sense voltage applied to the CS pin exceeds a predefined

reference voltage.

The CS1601 includes a supervisor and protection circuit to

manage startup, shutdown, and fault conditions. The

protection circuit is designed to prevent output overvoltage as

a result of load and AC mains transients. The PFC power

converter main rectified voltage (Vrect) and output link voltage

(Vlink) are monitored for overvoltage faults that would lead to

shutdown of the PFC controller. The PFC overvoltage

protection is designed for auto-recovery; operation resumes

once the fault clears.

POR +

DD ( on)

DD ( off)

Voltage

Regulator 8

VDD

ZCD

Z CD(t h )

Zero-Crossing

Detect

GND

IFB

IAC

LEB

15 k

24k

15 k

24k

ADC

ZCB

600

Threshold

CS Clamp

CS ( clamp )

CS (th)

STBY

600 k

ref

CS1601

DS931F3 3

2. PIN DESCRIPTION

CSPFC Current Sense

IFBLink Voltage Sense

ZCD PFC Zero-current Detect

GND Ground

GD P FC Ga te D riv e r

VDD IC Supply Voltage

STBYStandby

IA CRectifier Voltage Sense

8-lead SOIC

Figure 2. CS1601 Pin Assignments

Pin Name Pin # I/O Description

IFB 1IN

Link Voltage Sense — A current proportional to the output link voltage of the PFC is

input here. The current is measured with an ADC.

STBY 2IN

Standby — A voltage below 0.8V puts the IC into a non-operating, low-power state.

The input has an internal 600k pull-up resistor to the VDD pin.

IAC 3IN

Rectifier Voltage Sense — A current proportional to the rectified line voltage is input

here. The current is measured with an ADC.

CS 4IN

PFC Current Sense — The current flowing in the PFC MOSFET is sensed through a

resistor. The resulting voltage is applied to this pin and digitized for use by the PFC

computational logic to limit the maximum current through the power FET.

ZCD 5IN

PFC Zero-current Detect — Boost Inductor demagnetization sensing input for zero-

current detection (ZCD) information. The pin is externally connected to the PFC boost

inductor auxiliary winding through an external resistor divider.

GND 6PWR

Ground — Common reference. Current return for both the input signal portion of the IC

and the gate driver.

GD 7OUT

PFC Gate Driver — The totem pole stage is able to drive the power MOSFET with a

peak current of 0.5A source and 1.0A sink.

VDD 8PWR

IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the

gate driver. A storage capacitor is connected on this pin to serve as a reservoir for oper-

ating current for the device, including the gate drive current to the power transistor. This

pin is clamped to a maximum voltage (Vz) by an internal zener function.

CS1601

4DS931F3

3. CHARACTERISTICS AND SPECIFICATIONS

3.1 Electrical Characteristics

Typical characteristics conditions:

TA=25°C, V

DD = 13V, GND = 0V

All voltages are measured with respect to GND.

Unless otherwise specified, all currents are positive when

flowing into the IC.

Minimum/Maximum characteristics conditions:

TJ= -40° to +125 °C, VDD = 10V to 15V, GND = 0V

Parameter Condition Symbol Min Typ Max Unit

VDD Supply Voltage

Operating Range After Turn-on VDD 7.9 - 17.0 V

Turn-on Threshold Voltage VDD Increasing VDD(on) 9.8 10.2 10.5 V

Turn-off Threshold Voltage (UVLO) VDD Decreasing VDD(off) 7.9 8.1 8.3 V

UVLO Hysteresis VHys -2.1-V

Zener Voltage IDD =20mA V

Z17.0 17.9 19.0 V

VDD Supply Current

Startup Supply Current VDD =V

DD(on) IST -6895A

Operating Supply Current4

CS1601

CS1601H

CL= 1nF, fsw = 70kHz

CL=1nF, fsw=100kHz

IDD -

1.5

1.75

2.1

2.25

Standby Supply Current STBY < 0.8V ISB -80125A

Reference

Reference Current Iref - 129 - A

PFC Gate Drive

Output Source Resistance IGD = 100mA, VDD =13V R

OH -9-

Output Sink Resistance IGD = -200mA, VDD =13V R

OL -6-

Rise Time4 CL=1nF,V

DD =13V t

r-3250ns

Fall Time 4CL=1nF,V

DD =13V t

f-1527ns

Output Voltage Low State IGD = -200mA, VDD =13V Vol - 0.9 1.3 V

Output Voltage High State IGD = 100mA, VDD =13V Voh 11.3 11.8 - V

Zero-current Detection (ZCD)

ZCD Threshold VZCD(th) -50-mV

ZCD Blanking tZCB - 200 - ns

ZCD Sink Current1IZCD -2 - - mA

Upper Voltage Clamp IZCD =1mA V

CLP -V

DD -V

Overvoltage Protection (OVP)

IFB Current at Startup Mode IIFB(startup) -116-A

IFB Current at Normal Mode IIFB(norm) - 129 - A

OVP Threshold Iref =129AI

OVP - 139 - A

OVP Hysteresis Iref =129AI

OVP(Hy) -2-A

CS1601

DS931F3 5

Notes: 1. External circuitry should be designed to ensure the ZCD sink current pulled from the internal clamp diode when it

is forward biased does not exceed specification.

2. Specifications guaranteed by design and are characterized and correlated using statistical process methods.

3. STBY is designed to be driven by an open collector. The input is internally pulled up with a 600 k resistor.

4. For test purposes, load capacitance (CL) is 1nF and is connected as shown in the following diagram.

Overcurrent Protection (OCP)

Current Sense Reference Clamp VCS(clamp) -1.0-V

Threshold on Current Sense VCS(th) -0.5-V

Leading Edge Blanking tLEB - 300 - ns

Delay to Output tCS - 60 350 ns

Brownout Protection (BP)

Input Brownout Protection Threshold Gate Drive Turns Off IBP(lower) -31.6-A

Input Brownout Recovery Threshold Gate Drive Turns On IBP(upper) -39.6-A

Thermal Protection2

Thermal Shutdown Threshold TSD 134 147 159 °C

Thermal Shutdown Hysteresis TSD(Hy) -9-°C

STBY Input 3

Logic Threshold Low - - 0.8 V

Logic Threshold High VDD-0.8 - - V

Parameter Condition Symbol Min Typ Max Unit

GD OUT

GND

VDD

Buffer

1nF

+15V

-15V

CS1601

6DS931F3

3.2 Absolute Maximum Ratings

Characteristics conditions:

All voltages are measured with respect to GND.

Notes: 5. Long-term operation at the maximum junction temperature will result in reduced product life. Derate internal power

dissipation at the rate of 50mW/ °C for variation over temperature.

WARNING:

Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Pin Symbol Parameter Value Unit

DD IC Supply Voltage 19 V

1,2,3,4,5 - Analog Input Maximum Voltage -0.5 to (VDD+0.5) V

1,2,3,4,5 - Analog Input Maximum Current 50 mA

GD Gate Drive Output Voltage -0.3 to (VDD+0.3) V

GD Gate Drive Output Current -1.0 / +0.5 A

-P

DTotal Power Dissipation @ TA=50°C 600 mW

-JA Junction-to-Ambient Thermal Impedance 107 °C/W

-T

AOperating Ambient Temperature Range -40 to +125 °C

-T

JJunction Temperature Operating Range5-40 to +125 °C

-T

Stg Storage Temperature Range -65 to +150 °C

All Pins ESD Electrostatic Discharge Capability Human Body Model

Charged Device Model

2000

500

CS1601

DS931F3 7

4. TYPICAL ELECTRICAL PERFORMANCE

-3.0%

-2.5%

-2.0%

-1.5%

-1.0%

-0.5%

0.0%

0.5%

-50 0 50 100 150

ref

Drift

Temperature (

Figure 3. Supply Current vs. Supply Voltage Figure 4. Supply Current (ISB, IST, IDD) vs. Temp

Figure 5. UVLO Hysteresis vs. Temp Figure 6. Turn-on & Turn-off Threshold vs. Temp

Figure 7. Reference Current (Iref) Drift vs. Temp

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 2 4 6 8 1012141618

(V)

Rising

Falling

SW(max)

= 70kHz

SW(max)

= 100kHz

(mA)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 0 50 100 150

Supply Current (mA)

Temperature (

Start-up

SW(max)

= 70kHz

SW(max)

= 100kHz

Operating

-40 0 40 80 120

Temperature (OC)

UVLO Hysteresis

Temperature (OC)

7.5

8.5

9.5

10.5

-60 -10 40 90 140

VDD (V)

Temperature (OC)

Turn On

Turn Off

CS1601

8DS931F3

-60 -40 -20 0 40 100 120 140

Gate Resistor (R

, R

) Temp (oC)

Zout (Ohm)

Source

Sink

= 13 V

source

= 100 mA

sink

= 200 mA

20 60 80

Figure 8. Gate Resistance (ROH, ROL) vs. Temp

Figure 10. OVP vs. Temp

96%

98%

100%

102%

104%

106%

-50 0 50 100 150

link

(Normalized at 25

Temperature (

OVP

Normal

17.5

18.5

-50 0 50 100 150

VZ(V)

Temperature (oC)

= 20 mA

Figure 9. VDD Zener Voltage vs. Temp

CS1601

DS931F3 9

5. GENERAL DESCRIPTION

The CS1601 offers numerous features, options, and

functional capabilities to the electronic product lighting

designer. This digital power factor correction (PFC) control IC

is designed to replace legacy analog PFC controllers with

minimal design effort.

5.1 PFC Operation

One key feature of the CS1601 is its operating frequency

profile. Figure 10 illustrates how the frequency varies over a

half cycle of the line voltage in steady-state operation. When

power is first applied to the CS1601, it examines the line

voltage and adapts its operating frequency to the line voltage,

as shown in Figure 10. The operating frequency is varied from

the peak to the trough of the AC input. During startup, the

control algorithm generates maximum power while operating

in critical conduction mode (CRM), providing an approximate

square-wave current envelope within every half-line cycle.

Figure 10. Switching Frequency vs. Phase Angle

Figure 11 illustrates how the operating frequency of the

CS1601 (as a percentage of maximum frequency) changes

with output power and the peak of the line voltage.

Figure 11. CS1601 Max Switching Freq vs. Output Power

Figure 12 illustrates how the operating frequency of CS1601H

changes with output power and the peak of the line voltage.

Figure 12. CS1601H Max Switching Freq vs.Output Power

When PO falls below 5%, the CS1601 changes to Burst Mode.

(Refer to 5.3 Burst Mode on page 10 for more information.)

The CS1601 is designed to function as a DCM controller.

However, during peak periods, the controller may interchange

control methods and operate in a quasi-critical-conduction

mode (quasi-CRM) at low line. For example, at 108VAC main

input under full load, the PFC controller will function as a

quasi-CRM controller at the peak of the AC line cycle, as

shown in Figure 13.

Figure 13. DCM and Quasi-CRM Operation with CS1601

The zero-current detection (ZCD) of the boost inductor is

achieved using an auxiliary winding. When the stored energy

of the inductor is fully released to the output, the voltage on the

ZCD pin decreases, triggering a new switching cycle. This

quasi-resonant switching allows the active switch to be turned

on with near-zero inductor current, resulting in a nearly

lossless switch event. This minimizes turn-on losses and EMI

noise created by the switching cycle. PFC control is achieved

during light load by using on-time modulation.

100

120

0 45 90 135 180

Rectified Line Voltage Phase (Deg.)

% of Max

Switching Freq. (% of Max.)

Line Voltage (% of Max.)

% P

O max

SW max

(kHz)

Bu rst Mode

60 80 100

Vin >156 VAC (Input Voltage 108 – 305 VAC, V

link

= 460 V )

Vin <182 VAC (Input Voltage 108 –305 VAC , V

link

= 460 V)

Vin <158 VAC (Input Vol tage 90 –264 VAC , V

link

= 400 V)

Vin >136 VAC (Input Voltage 90 – 264 VAC , V

link

= 400 V)

% P

O max

SW ma x

(kHz)

100

Burst Mode

Vin > 156 VAC (Input Voltage 108 – 305 VAC , V

link

= 460 V)

Vin < 182 VAC (Input Vol tage 108 – 305 VAC, V

link

= 460 V)

Vin < 158 VAC (Input Vol tage 90 – 264 VAC, V

link

= 400 V )

Vin >136 VAC ( Input Voltage 90 – 264 VAC , V

link

= 400 V)

20 40

560 80 100

DCM Quasi CRM DCM Quasi CRM DCM

ILB

t [ms]

IAC

Inductor Current

CS1601

10 DS931F3

5.2 Startup vs. Normal Operation Mode

The CS1601 has two discrete operation modes: startup and

normal. Startup mode will be activated when Vlink is less than

90% of nominal value, VO(startup), and remains active until Vlink

reaches 100% of nominal value, as shown in Figure 14.

Startup mode is activated during initial system power-up. Any

Vlink drop to less than VO(startup), such as a load change, can

cause the system to enter startup mode until Vlink is brought

back into regulation.

Figure 14. Startup and Normal Modes

Startup mode is defined as a surge of current delivering

maximum power to the output regardless of the load. During

every active switch cycle, the 'ON' time is calculated to drive a

constant peak current over the entire line cycle. However, the

'OFF' time is calculated based on the DCM/CCM boundary

equation.

5.3 Burst Mode

Burst mode is used to improve system efficiency when the

system output power (Po) is <5% of nominal. Burst mode is

implemented by intermittently disabling the PFC over a full

half-line period under light-load conditions, as shown in

Figure 15.

Figure 15. Burst Mode

5.4 Output Power and PFC Boost Inductor

In normal operating mode, the nominal output power is

estimated by the following equation:

where:

Porated output power of the system

efficiency of the boost converter (estimated as 100%

by the PFC algorithm)

Vin(min) minimum RMS line voltage measured after the

rectifier and EMI filter. Vin(min) is equal to 90Vrms or

108Vrms depending on the AC Line Voltage

operating range.

Vlink nominal PFC output voltage; Vlink = 400V when

Vin(min) =90VrmsorV

link = 460V when

Vin(min) = 108Vrms

fmax maximum switching frequency; for the CS1601

fmax = 70kHz and the CS1601H fmax = 100kHz

LBboost inductor specified by rated power requirement

 margin factor to guarantee rated output power (Po)

against boost inductor tolerances.

Equation 1 is provided for explanation purposes only. Using

substituted required design values for Vlink and fmax gives the

following equation:

Changing the value for the Vlink voltage is not recommended.

Solving Equation 2 for the PFC boost inductor LB gives the

following equation:

If a value of the boost inductor other than that obtained from

Equation 3 above is used, the total output power capability

and the minimum input voltage threshold will differ according

to Equation 2. Note that if the input voltage drops below

108Vrms and the inductance value is <LB, the link voltage

Vlink will drop below 460V and fall out of regulation.

Figure 16. Relative Effects of Varying Boost Inductance

t [ms]

Vlink

[V]

100%

90%

Startup Mode

Normal

Mode

Startup Mode

Normal

Mode

Vin

[V]

t [ms]

FET

Vgs

Burst Mode

Active

Vin

[W]

t [ms]

PFC

Disable

Burst Threshold

o Vin min

2

Vlink Vin min 2–

max LBVlink



---------------------------------------------------------

=[Eq.1]

o 108V2

460V 108V 2–

270kHz L

B460V

-------------------------------------------------------------

=[Eq.2]

LB 108V2

460V 108V 2–

270kHzP

o460V

-------------------------------------------------------------

=[Eq.3]

AC(rms)

108 305

o(m ax)

L > L



L = L

L < L



CS1601

DS931F3 11

5.5 PFC Output Capacitor

The value of the PFC output capacitor needs to be selected

based upon voltage ripple and hold-up requirements. To

ensure system stability with the digital controller, the

recommended value of the capacitor is within the range of

0.25F/watt to 0.5F/watt with a Vlink voltage of 460V.

5.6 Output IFB Sense and Input IAC Sense

A current proportional to the PFC output voltage, Vlink, is

supplied to the IC on pin IFB and is used as a feedback control

signal. This current is compared against an internal fixed-

value reference current.

The ADC is used to measure the magnitude of the IIFB current

through resistor RIFB. The magnitude of the IIFB current is then

compared to an internal reference current of (Iref) 129A.

Figure 17. IFB Input Pin Model

Resistor RIFB sets the feedback current and is calculated as

follows:

By using digital loop compensation, the voltage feedback

signal does not require an external compensation network.

A current proportional to the AC input voltage is supplied to the

IC on pin IAC and is used by the PFC control algorithm.

Figure 18. IAC Input Pin Model

Resistor RIAC sets the IAC current and is derived as follows:

For optimal performance, resistors RIAC and RIFB should use

1% tolerance or better resistors for best Vlink voltage accuracy.

5.7 Valley Switching

The zero-current detection (ZCD) pin is monitored for

demagnetization in the auxiliary winding of the boost inductor

(LB). The ZCD circuit is designed to detect the VAux

valley/zero crossings by sensing the voltage transformed onto

the auxiliary winding of LB.

Figure 19. ZCD Input Pin Model

The objective of zero-voltage switching is to initiate each

MOSFET switching cycle when its drain-source voltage is at

the lowest possible voltage potential, thus reducing switching

losses. The CS1601 uses an auxiliary winding on the PFC

boost inductor to implement zero-voltage switching.

Figure 20. Zero-voltage Switch

During each switching cycle, when the boost diode current

reaches zero, the boost MOSFET drain-source voltage begins

oscillating at the resonant frequency of the boost inductor and

MOSFET parasitic output capacitance. The ZCD_below_zero

signal transitions from high to low just prior to a local minimum

of the MOSFET drain-source voltage oscillation. The zero-

crossing detect circuit ensures that a ZCD_below_zero pulse

will only be generated when the comparator output is

continuously high for a nominal time period (tZCB) of 200ns.

Therefore, any negative edges on the comparator's output

due to spurious glitches will not cause a pulse to be

generated.

Due to the CS1601's variable-frequency control, the MOSFET

switching cycle will not always be initiated at the first resonant

valley. The external circuitry should be designed so that the

current (IZCD) at the ZCD pin is approximately ±1.0mA. The

IFB

VDD

15 k

Vlink

CS1601

24 k ADC

RIFB

IFB

RIFB

Vlink VDD

–

Iref

----------------------------- 460V VDD

–

129A

-------------------------------== [Eq.4]

IAC

IA C

VDD

15 k

rect

CS1601

24 k ADC

RIAC RIFB

=[Eq.5]

Au x

link

ZCD

CS1601

ZCD_below_z ero

FE T Drain

N:1

Aux

Demag

Comparator

th( Z CD)

ZCD

Zero Crossing

Detection

GD ‘ON’

ZCD_below _zero

CS1601

12 DS931F3

table below depicts approximate values for R3 and R4 for a

range of boost-to-auxiliary inductor turns ratio, N.

Table 1. Aux Inductor Turns Ratio vs. R3 and R4

Resistors R3 and R4 were calculated using Vlink = 460V and

Cp=10pF.

Equation 6 is used to calculate the cut-off frequency defined

by the RC circuit at the ZCD pin.

where:

fc The cut-off frequency, fc, needs to be 10x the ringing

frequency.

Cp Capacitance at the ZCD pin

5.8 Brownout Protection

The CS1601 brownout detection circuit monitors the peak of

the Vrect input voltage and disables the PWM switching when

it drops below a predetermined threshold. Hysteresis and

minimum detection time are provided to avoid brownout

detection during short input transients. When brownout is

detected, the CS1601 enters standby mode. On recovery from

brownout, it re-enters normal operating mode.

Current IAC is proportional to the AC input voltage Vrect,where

Vrect =R

IACxIAC and RIAC =R1+R2 (see Figure 18 on

page 11). The digitized current applied to the IAC pin is

monitored by the brownout protection algorithm. When Vrect

drops below the brownout detection threshold, the CS1601

triggers a timer. The IC asserts the brownout protection and

stops the gate-drive switching only if the timer exceeds 56ms.

This is the equivalent of 7 rectified line cycles at 60Hz.

During the brownout state, the device continues monitoring

the input line voltage. The device exits the brownout state

when IAC exceeds the brownout upper threshold for at least

56ms. Typical values for the lower (IBP(lower)) and upper

(IBP(upper)) brownout thresholds are 31.6A and 39.6A,

respectively.

The overpower protection may activate prior to brownout

protection, depending on the load.

Figure 21. Brownout Sequence

The maximum response time of the brownout protection

feature occurs at light-load conditions. It is calculated by

Equation 7.

where:

VBP(th) Brownout threshold voltage, VBP(th) = IBP(lower) xRIAC

5.9 Overvoltage Protection

The overvoltage protection (OVP) will trigger immediately and

stop the gate drive when the current into the IFB pin (IOVP)

exceeds 105% of the reference current (Iref) value. The IC

resumes gate drive switching when the measured current at IFB

drops below IOVP –I

OVP(Hy). Equation 8 is used to calculate the

OVP threshold (VOVP).

5.10 Overcurrent Protection

To limit boost inductor current through the FET and to prevent

boost inductor saturation conditions, the CS1601 incorporates

a cycle-by-cycle peak inductor current limit circuit using an

external shunt resistor to ‘sense’ the FET source current

accurately. The overcurrent protection (OCP) circuit is

designed to monitor the current when the active switch is

turned on. The OCP circuit is enabled after the leading-edge

blanking time (tLEB). The shunt voltage is compared to a

reference voltage, Vcs(th), to determine whether an

overcurrent condition exists. The OCP circuit triggers

immediately, allowing the OCP algorithm to turn off the gate

driver.

The overcurrent protection circuit is also designed to monitor

for a catastrophic overcurrent occurrence by sensing sudden

and abnormal operating currents. A second OCP threshold,

Vcs(clamp), determines whether a severe overcurrent condition

exists. This immediately turns off the gate drive, and the

system enters a restart mode. The CS1601 inhibits all

switching operations for approximately 1.6ms and then

attempts to restart normal operation.

N~R3~R4

946k1.75k

10 42k1.75k

11 37.5 k1.75k

12 35.5k1.75k

13 32k1.75k

14 29.5k1.75k

15 27.5k1.75k

fc12R3 R4



Cp

=[Eq.6]

56 ms

Start

Timer

Enter Standby Exit Standby

Upper

Lower

Brownout

Thresholds

Start Timer

TBrownout

TBrownout 8ms 8ms

------------ 128 V VBP th

–56 ms++=[Eq.7]

8=8

---128 94.8–56++117ms=

VOVP RIFB IOVP

VDD

+= [Eq.8]

CS1601

DS931F3 13

5.11 Overpower Protection

The CS1601 incorporates an internal overpower protection

(OPP) algorithm that provides protection from overload

conditions. This algorithm uses the condition that output

power is a function of the boost inductor (see section 5.4

Output Power and PFC Boost Inductor on page 10).

Under moderate overload, Vlink may droop up to 10% while

maintaining rated power and PFC. Further increasing the load

current causes Vlink to drop below the startup threshold

(~360V). Below this threshold, the circuit switches the

operating mode to startup with more power available to raise

Vlink. As Vlink reaches its nominal value, startup mode is

canceled and power is now limited to the rated value. If the

overload is still present, this cycle will repeat.

If a sustained overload, or a repeated cycle of overload

events, is detected for greater than 112 ms, the CS1601 shuts

down for 2.5 seconds and then attempts to restart.

5.12 Open/Short Loop Protection

If the PFC output sense resistor, RIFB, fails (open or short to

GND), the measured output voltage decreases at a slew rate of

about 2 V/s, which is determined by the ADC sampling rate.

The IC stops the gate drive when the measured output voltage is

lower than the measured line voltage. The IC resumes gate drive

switching when the current into the IFB pin becomes larger than

or equal to the current into the IAC pin, and Vlink is greater than

the peak of the line voltage (Vrect(pk)). The maximum response

time of open/short loop protection for RIFB is about 150s.

If the PFC input sense resistor RIAC fails (open or short to GND),

the current reference signal supplied to the IC on pin IAC falls to

zero.

5.13 Internal Overtemperature Protection

An internal thermal sensor triggers a shutdown when the

temperature exceeds 135°C (nominal) on the silicon. The

sensor sends a signal to the core that supplies current to all

internal digital logic, cutting off power from them. Once the

temperature of the IC has dropped by 9°C (nominal), the

sensor resets, allowing power to the logic.

5.14 Standby (STBY) Function

The standby (STBY) pin provides a means by which an

external signal can cause the CS1601 to enter a non-

operating, low-power state. The STBY input is intended to be

driven by an open-collector/open-drain device. Internal to the

pin, there is a pull-up resistor connected to the VDD pin, as

shown in Figure 22. Since the pull-up resistor has a high

impedance, a filter capacitor (up to 1000pF) may be required

on this pin.

Figure 22. STBY Pin Connection

When the STBY pin is not used, it is recommended that the pin

be tied to VDD (pulled high).

<1 nF

600 k

See Text

VDD

STBY

GND

CS1601

14 DS931F3

5.15 Summary of Equations

Eq. # Equation Variables/Recommended Values

Output Power (page 10)

PoRated output power of the system.

Efficiency of the boost converter (estimated as

100% by the PFC algorithm).

Vin(min) Minimum RMS line voltage is 90Vrms,

measured after the rectifier and EMI filter.

Vlink Nominal PFC output voltage must be 400V.

fmax Maximum switching frequency is 70kHz.

LBBoost inductor specified by rated power

requirement.

Margin factor to guarantee rated output power

(Po) against boost inductor tolerances.

RIAC Value of the IAC pin sense resistor(s).

RIFB Value of the IFB pin sense resistor(s).

Iref Value of the fixed, internal reference current.

fc The cut-off frequency, fc, needs to be 10x the

ringing frequency or fc = 10MHz.

Cp Capacitance at the ZCD pin. Cp<10pF.

VBP(th) Brownout threshold voltage. VBP(th) = 94.8V.

Cout Value of the output capacitor in mF.

fline(min) Minimum line frequency.

VDD IC Supply Voltage.

VOVP OVP threshold.

IOVP Current into the IFB pin.

Output Power with recommended values (page 10)

Boost Inductor (page 10)

Output IFB Sense Resistor (page 11)

Input IAC Sense Resistor (page 11)

Auxiliary Winding Cut-off Frequency (page 12)

Maximum Response Time for Brownout: (page 12)

Overvoltage Protection (page 12)

Boost Inductor Peak Current

Boost Inductor RMS Current

Vlink Voltage Ripple

o Vin min

2

Vlink Vin min 2–

max LBVlink



---------------------------------------------------------

=

o 90Vrms2

400V 90Vrms 2–

270kHz L

B400V

-------------------------------------------------------------

=

LB 90Vrms2

400V 90Vrms 2–

270kHzP

o400V

-------------------------------------------------------------

=

RIFB

Vlink VDD

–

Iref

----------------------------- 400V VDD

–

129A

-------------------------------

RIAC RIFB

fc12R3 R4



Cp

=

TBrownout 8ms 8ms

------------ 128 V VBP th

–56 ms++=

VOVP RIFB IOVP

VDD

ILB pk



Vin min 2

--------------------------------------------

ILB rms

Vin min



------------------------------

Vlink rip

2fline min

Vlink

Cout



------------------------------------------------------------------------

CS1601

DS931F3 15

6. PACKAGE DRAWING

MILLIMETERS INCHES

Dimension MIN NOM MAX MIN NOM MAX

A - - - - 1.75 - - - - 0.069

A1 0.10 - - 0.25 0.004 - - 0.010

b 0.31 - - 0.51 0.012 - - 0.020

c 0.10 - - 0.25 0.004 - - 0.010

D 4.90 BSC 0.193 BSC

E 6.00 BSC 0.236 BSC

E1 3.90 BSC 0.154 BSC

e 1.27 BSC 0.050 BSC

L 0.40 - - 1.27 0.016 - - 0.050

Θ0° - - 8° 0° - - 8°

aaa 0.10 0.004

bbb 0.25 0.010

ddd 0.25 0.010

Notes:

1. Controlling dimensions are in millimeters

2. Dimensions and Tolerances per ASME Y14.5M

3. This drawing conforms to JEDEC outline MS-012, variation AA for standard SOIC-8 narrow body

4. Recommended reflow profile is per JEDEC/IPC J-STD-020

SOIC-8 NARROW (150 MIL BODY) PACKAGE DRAWING

CS1601

16 DS931F3

7. ORDERING INFORMATION

8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

9. REVISION HISTORY

Part # Temperature Range Package Description

CS1601-FSZ -40°C to +125°C 8-lead SOIC, Lead (Pb) Free

CS1601H-FSZ -40°C to +125°C 8-lead SOIC, Lead (Pb) Free

Model Number Peak Reflow Temp MSL Ratinga

a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Max Floor Lifeb

b. Stored at 30°C, 60% relative humidity.

CS1601-FSZ 260°C 2 365 Days

CS1601H-FSZ 260°C 2 365 Days

Revision Date Changes

PP5 MAY 2011 Updated Typical Electrical Performance section.

PP6 JUN 2011 Updated Characteristics and Specifications section.

F1 SEP 2011 Finalized. Updated Characteristics and Specifications section.

F2 JAN 2012 Edited for content and clarity. Corrected typographical errors.

F3 FEB 2012 Revised MSL rating.

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find one nearest you go to http://www.cirrus.com

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