1. General description
The 74HC573; 74HCT573 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type
inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all latches.
When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are
transparent, i.e. a latch output will change state each time its corresponding D input
changes.
When LE is LOW the latches store the information that was present at the D-inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
The 74HC573; 74HCT573 is functionally identical to:
74HC563; 74HCT563, but inverted outputs
74HC373; 74HCT373, but different pin arrangement
2. Features
Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
Functionally identical to 74HC563; 74HCT563 and 74HC373; 74HCT373
Complies with JEDEC standard no. 7A
ESD protection:
HBM EIA/JESD22-A114-C exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from 40 °Cto+85°C and from 40 °C to +125 °C
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Rev. 03 — 17 January 2006 Product data sheet
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 2 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
3. Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL×VCC2×fo) = sum of outputs.
4. Ordering information
Table 1: Quick reference data
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
= 6 ns
Symbol Parameter Conditions Min Typ Max Unit
74HC573
tPHL,
tPLH
propagation delay VCC = 5 V; CL= 15 pF
Dn to Qn - 14 - ns
LE to Qn - 15 - ns
Ciinput capacitance - 3.5 - pF
CPD power dissipation
capacitance per latch;
VI= GND to VCC
[1] -26-pF
74HCT573
tPHL,
tPLH
propagation delay VCC = 5 V; CL= 15 pF
Dn to Qn - 17 - ns
LE to Qn - 15 - ns
Ciinput capacitance - 3.5 - pF
CPD power dissipation
capacitance per latch;
VI= GND to (VCC 1.5 V) [1] -26-pF
Table 2: Ordering information
Type number Package
Temperature range Name Description Version
74HC573
74HC573N 40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC573D 40 °C to +125 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74HC573DB 40 °C to +125 °C SSOP20 plastic small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HC573PW 40 °C to +125 °C TSSOP20 plastic small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HC573BQ 40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
20 terminals; body 2.5 ×4.5 × 0.85 mm
SOT764-1
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 3 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
5. Functional diagram
74HCT573
74HCT573N 40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT573D 40 °C to +125 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm SOT163-1
74HCT573DB 40 °C to +125 °C SSOP20 plastic small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HCT573PW 40 °C to +125 °C TSSOP20 plastic small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HCT573BQ 40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
20 terminals; body 2.5 ×4.5 × 0.85 mm
SOT764-1
Table 2: Ordering information
…continued
Type number Package
Temperature range Name Description Version
Fig 1. Functional diagram
mna809
3-STATE
OUTPUTS
LATCH
1 to 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
9
11
1
8
7
6
5
4
3
2
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 4 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
mna807
D0
D1
D2
D3
D4
D5
D6
D7 LE
OE Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
11
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
mna808
12
13
14
15
16
17
18
11 C1
1EN1
1D 19
9
8
7
6
5
4
3
2
Fig 4. Logic diagram
001aae075
Q4
D4
DQ
Q3
D3
DQ
Q2
D2
DQ
Q1
D1
D
LE
Q
Q0
D0
D
LATCH
1LATCH
2LATCH
3LATCH
4LATCH
5
Q
LE
OE
LE LE LE LE
Q5
D5
DQ
LATCH
6
LE
Q6
D6
DQ
LATCH
7
LE
Q7
D7
DQ
LATCH
8
LE
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 5 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input
Fig 5. Pin configuration DIP20, SO20,
SSOP20 and TSSOP20 Fig 6. Pin configuration DHVQFN20
001aae076
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
OE VCC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
GND LE
74HC573
74HCT573
001aae077
74HC573
74HCT573
Transparent top view
Q7
D6
D7
Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0
GND(1)
Q0
GND
LE
OE
VCC
912
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
Table 3: Pin description
Symbol Pin Description
OE 1 3-state output enable input (active LOW)
D0 2 data input 0
D1 3 data input 1
D2 4 data input 2
D3 5 data input 3
D4 6 data input 4
D5 7 data input 5
D6 8 data input 6
D7 9 data input 7
GND 10 ground (0 V)
LE 11 latch enable input (active HIGH)
Q7 12 3-state latch output 7
Q6 13 3-state latch output 6
Q5 14 3-state latch output 5
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 6 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
7. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
8. Limiting values
Q4 15 3-state latch output 4
Q3 16 3-state latch output 3
Q2 17 3-state latch output 2
Q1 18 3-state latch output 1
Q0 19 3-state latch output 0
VCC 20 supply voltage
Table 3: Pin description
…continued
Symbol Pin Description
Table 4: Function table[1]
Operating mode Control Input Internal
latches Output
OE LE Dn Qn
Enable and read register
(transparent mode) LHLLL
HHH
Latch and read register L L l L L
hHH
Latch register and disable outputs H L l L Z
hHZ
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - ±20 mA
IOK output clamping current VO<0.5 V or VO>V
CC + 0.5 V - ±20 mA
IOoutput current VO = 0.5 V to (VCC + 0.5 V) - ±35 mA
ICC quiescent supply current - 70 mA
IGND ground current - 70 mA
Tstg storage temperature 65 +150 °C
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 7 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO20 package: Ptot derates linearly with 8 mW/K above 70 °C.
[3] For SSOP20 and TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 °C
[4] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 °C.
9. Recommended operating conditions
Ptot total power dissipation
DIP20 package [1] - 750 mW
SO20 package [2] - 500 mW
SSOP20 package [3] - 500 mW
TSSOP20 package [3] - 500 mW
DHVQFN20 package [4] - 500 mW
Table 5: Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
Table 6: Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
74HC573
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 °C
tr, tfinput rise and fall time VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
74HCT573
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 °C
tr, tfinput rise and fall time VCC = 4.5 V - 6.0 500 ns
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 8 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
10. Static characteristics
Table 7: Static characteristics 74HC573
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
VIH HIGH-state input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-state input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-state output voltage VI = VIH or VIL ---
IO=20 µA; VCC = 2.0 V 1.9 2.0 - V
IO=20 µA; VCC = 4.5 V 4.4 4.5 - V
IO=20 µA; VCC = 6.0 V 5.9 6.0 - V
IO=6.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO=7.8 mA; VCC = 6 V 5.48 5.81 - V
VOL LOW-state output voltage VI = VIH or VIL
IO=20µA; VCC = 2.0 V - 0 0.1 V
IO=20µA; VCC = 4.5 V - 0 0.1 V
IO=20µA; VCC = 6.0 V - 0 0.1 V
IO= 6.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO= 7.8 mA; VCC = 6 V - 0.16 0.26 V
ILI input leakage current VI=V
CC or GND; VCC = 6 V - - ±0.1 µA
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND - - ±0.5 µA
ICC quiescent supply current VI=V
CC or GND; IO = 0 A;
VCC = 6.0 V - - 8.0 µA
Ciinput capacitance - 3.5 - pF
Tamb =40 °C to +85 °C
VIH HIGH-state input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-state input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-state output voltage VI = VIH or VIL
IO=20 µA; VCC = 2.0 V 1.9 - - V
IO=20 µA; VCC = 4.5 V 4.4 - - V
IO=20 µA; VCC = 6.0 V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.84 - - V
IO = 7.8 mA; VCC = 6.0 V 5.34 - - V
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 9 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
VOL LOW-state output voltage VI = VIH or VIL
IO=20µA; VCC = 2.0 V - - 0.1 V
IO=20µA; VCC = 4.5 V - - 0.1 V
IO=20µA; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.33 V
IO = 7.8 mA; VCC = 6 V - - 0.33 V
ILI input leakage current VI=V
CC or GND; VCC = 6 V - - ±1.0 µA
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND - - ±5.0 µA
ICC quiescent supply current VI=V
CC or GND; IO = 0 A;
VCC = 6.0 V --80µA
Tamb =40 °C to +125 °C
VIH HIGH-state input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-state input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-state output voltage VI = VIH or VIL
IO=20 µA; VCC = 2.0 V 1.9 - - V
IO=20 µA; VCC = 4.5 V 4.4 - - V
IO=20 µA; VCC = 6.0 V 5.9 - - V
IO = 6.0 mA; VCC = 4.5 V 3.7 - - V
IO = 7.8 mA; VCC = 6.0 V 5.2 - - V
VOL LOW-state output voltage VI = VIH or VIL
IO=20µA; VCC = 2.0 V - - 0.1 V
IO=20µA; VCC = 4.5 V - - 0.1 V
IO=20µA; VCC = 6.0 V - - 0.1 V
IO = 6.0 mA; VCC = 4.5 V - - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - - 0.4 V
ILI input leakage current VI=V
CC or GND; VCC = 6.0 V - - ±1.0 µA
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND - - ±10.0 µA
ICC quiescent supply current VI=V
CC or GND; IO = 0 A;
VCC = 6.0 V - - 160 µA
Table 7: Static characteristics 74HC573
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 8: Static characteristics 74HCT573
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 10 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
VOH HIGH-state output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=20 µA 4.4 4.5 - V
IO=6.0 mA 3.98 4.32 - V
VOL LOW-state output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=20µA - 0 0.1 V
IO= 6.0 mA - 0.16 0.26 V
ILI input leakage current VI=V
CC or GND; VCC = 5.5 V - - ±0.1 µA
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND per input pin;
other inputs at GND or VCC; IO= 0 A; VCC = 5.5 V --±0.5 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 A; VCC = 5.5 V - - 8.0 µA
ICC additional quiescent
supply current per input pin; VI=V
CC 2.1 V; other inputs at
VCC or GND; IO= 0 A; VCC = 4.5 V to 5.5 V
Dn - 35 126 µA
LE - 65 234 µA
OE - 125 450 µA
Ciinput capacitance - 3.5 - pF
Tamb =40 °C to +85 °C
VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-state output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=20 µA 4.4 - - V
IO=6.0 mA 3.84 - - V
VOL LOW-state output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=20µA - - 0.1 V
IO= 6.0 mA - - 0.33 V
ILI input leakage current VI=V
CC or GND; VCC = 5.5 V - - ±1.0 µA
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND per input pin;
other inputs at GND or VCC; IO= 0 A; VCC = 5.5 V ±5.0 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 A; VCC = 5.5 V - - 80 µA
ICC additional quiescent
supply current per input pin; VI=V
CC 2.1 V; other inputs at
VCC or GND; IO= 0 A; VCC = 4.5 V to 5.5 V
Dn - - 158 µA
LE - - 293 µA
OE - - 563 µA
Table 8: Static characteristics 74HCT573
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 11 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
11. Dynamic characteristics
Tamb =40 °C to +125 °C
VIH HIGH-state input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-state input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-state output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=20 µA 4.4 - - V
IO=6.0 mA 3.7 - - V
VOL LOW-state output voltage VI=V
IH or VIL; VCC = 4.5 V
IO=20µA - - 0.1 V
IO= 6.0 mA - - 0.4 V
ILI input leakage current VI=V
CC or GND; VCC = 5.5 V - - ±1.0 µA
IOZ OFF-state output current VI = VIH or VIL; VO=V
CC or GND per input pin;
other inputs at GND or VCC; IO= 0 A; VCC = 5.5 V --±10.0 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 A; VCC = 5.5 V - - 160 µA
ICC additional quiescent
supply current per input pin; VI=V
CC 2.1 V; other inputs at
VCC or GND; IO= 0 A; VCC = 4.5 V to 5.5 V
Dn - - 172 µA
LE - - 319 µA
OE - - 613 µA
Table 8: Static characteristics 74HCT573
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 9: Dynamic characteristics 74HC573
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
tPHL,
tPLH
propagation delay Dn to Qn see Figure 7
VCC = 2.0 V - 47 150 ns
VCC = 4.5 V - 17 30 ns
VCC =5V; C
L= 15 pF - 14 - ns
VCC = 6.0 V - 14 26 ns
tPHL,
tPLH
propagation delay LE to Qn see Figure 8
VCC = 2.0 V - 50 150 ns
VCC = 4.5 V - 18 30 ns
VCC =5V; C
L= 15 pF - 15 - ns
VCC = 6.0 V - 14 26 ns
tPZH,
tPZL
3-state output enable time OE to Qn see Figure 9
VCC = 2.0 V - 44 140 ns
VCC = 4.5 V - 16 28 ns
VCC = 6.0 V - 13 24 ns
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 12 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
tPHZ,
tPLZ
3-state output disable time OE to Qn see Figure 9
VCC = 2.0 V - 55 150 ns
VCC = 4.5 V - 20 30 ns
VCC = 6.0 V - 16 26 ns
tTHL,
tTLH
output transition time see Figure 7
VCC = 2.0 V - 14 60 ns
VCC = 4.5 V - 5 12 ns
VCC = 6.0 V - 4 10 ns
tWpulse width LE HIGH see Figure 8
VCC = 2.0 V 80 14 - ns
VCC = 4.5 V 16 5 - ns
VCC = 6.0 V 14 4 - ns
tsu set-up time Dn to LE see Figure 10
VCC = 2.0 V 50 11 - ns
VCC = 4.5 V 10 4 - ns
VCC = 6.0 V 9 3 - ns
thhold time Dn to LE see Figure 10
VCC = 2.0 V 5 3 - ns
VCC = 4.5 V 5 1 - ns
VCC = 6.0 V 5 1 - ns
CPD power dissipation capacitance per latch; VI= GND to VCC [1] -26-pF
Tamb =40 to +85 °C
tPHL,
tPLH
propagation delay Dn to Qn see Figure 7
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
tPHL,
tPLH
propagation delay LE to Qn see Figure 8
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
tPZH,
tPZL
3-state output enable time OE to Qn see Figure 9
VCC = 2.0 V - - 175 ns
VCC = 4.5 V - - 35 ns
VCC = 6.0 V - - 30 ns
tPHZ,
tPLZ
3-state output disable time OE to Qn see Figure 9
VCC = 2.0 V - - 190 ns
VCC = 4.5 V - - 38 ns
VCC = 6.0 V - - 33 ns
Table 9: Dynamic characteristics 74HC573
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 13 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
tTHL,
tTLH
output transition time see Figure 7
VCC = 2.0 V - - 75 ns
VCC = 4.5 V - - 15 ns
VCC = 6.0 V - - 13 ns
tWpulse width LE HIGH see Figure 8
VCC = 2.0 V 100 - - ns
VCC = 4.5 V 20 - - ns
VCC = 6.0 V 17 - - ns
tsu set-up time Dn to LE see Figure 10
VCC = 2.0 V 65 - - ns
VCC = 4.5 V 13 - - ns
VCC = 6.0 V 11 - - ns
thhold time Dn to LE see Figure 10
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Tamb =40 to +125 °C
tPHL,
tPLH
propagation delay Dn to Qn see Figure 7
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
tPHL,
tPLH
propagation delay LE to Qn see Figure 8
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
tPZH,
tPZL
3-state output enable time OE to Qn see Figure 9
VCC = 2.0 V - - 210 ns
VCC = 4.5 V - - 42 ns
VCC = 6.0 V - - 36 ns
tPHZ,
tPLZ
3-state output disable time OE to Qn see Figure 9
VCC = 2.0 V - - 225 ns
VCC = 4.5 V - - 45 ns
VCC = 6.0 V - - 38 ns
tTHL,
tTLH
output transition time see Figure 7
VCC = 2.0 V - - 90 ns
VCC = 4.5 V - - 18 ns
VCC = 6.0 V - - 15 ns
Table 9: Dynamic characteristics 74HC573
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 14 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL×VCC2×fo) = sum of outputs.
tWpulse width LE HIGH see Figure 8
VCC = 2.0 V 120 - - ns
VCC = 4.5 V 24 - - ns
VCC = 6.0 V 20 - - ns
tsu set-up time Dn to LE see Figure 10
VCC = 2.0 V 75 - - ns
VCC = 4.5 V 15 - - ns
VCC = 6.0 V 13 - - ns
thhold time Dn to LE see Figure 10
VCC = 2.0 V 5 - - ns
VCC = 4.5 V 5 - - ns
VCC = 6.0 V 5 - - ns
Table 9: Dynamic characteristics 74HC573
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions Min Typ Max Unit
Table 10: Dynamic characteristics 74HCT573
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions Min Typ Max Unit
Tamb =25°C
tPHL,
tPLH
propagation delay Dn to Qn see Figure 7
VCC = 4.5 V - 20 35 ns
VCC =5V; C
L= 15 pF - 17 - ns
tPHL,
tPLH
propagation delay LE to Qn see Figure 8
VCC = 4.5 V - 18 35 ns
VCC =5V; C
L= 15 pF - 15 - ns
tPZH,
tPZL
3-state output enable time OE to Qn VCC = 4.5 V; see Figure 9 - 1730ns
tPHZ,
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 9 - 1830ns
tTHL,
tTLH
output transition time VCC = 4.5 V; see Figure 7 - 5 12 ns
tWpulse width LE HIGH VCC = 4.5 V; see Figure 8 16 5 - ns
tsu set-up time Dn to LE VCC = 4.5 V; see Figure 10 13 7 - ns
thhold time Dn to LE VCC = 4.5 V; see Figure 10 94- ns
CPD power dissipation capacitance per latch;
VI= GND to (VCC 1.5 V) [1] -26-pF
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 15 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi×N+(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL×VCC2×fo) = sum of outputs.
Tamb =40 to +85 °C
tPHL,
tPLH
propagation delay Dn to Qn VCC = 4.5 V; see Figure 7 --44ns
tPHL,
tPLH
propagation delay LE to Qn VCC = 4.5 V; see Figure 8 --44ns
tPZH,
tPZL
3-state output enable time OE to Qn VCC = 4.5 V; see Figure 9 --38ns
tPHZ,
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 9 --38ns
tTHL,
tTLH
output transition time VCC = 4.5 V; see Figure 7 --15ns
tWpulse width LE HIGH VCC = 4.5 V; see Figure 8 20--ns
tsu set-up time Dn to LE VCC = 4.5 V; see Figure 10 16--ns
thhold time Dn to LE VCC = 4.5 V; see Figure 10 11--ns
Tamb =40 to +125 °C
tPHL,
tPLH
propagation delay Dn to Qn VCC = 4.5 V; see Figure 7 --53ns
tPHL,
tPLH
propagation delay LE to Qn VCC = 4.5 V; see Figure 8 --53ns
tPZH,
tPZL
3-state output enable time OE to Qn VCC = 4.5 V; see Figure 9 --45ns
tPHZ,
tPLZ
3-state output disable time OE to Qn VCC = 4.5 V; see Figure 9 --45ns
tTHL,
tTLH
output transition time VCC = 4.5 V; see Figure 7 --18ns
tWpulse width LE HIGH VCC = 4.5 V; see Figure 8 24--ns
tsu set-up time Dn to LE VCC = 4.5 V; see Figure 10 20--ns
thhold time Dn to LE VCC = 4.5 V; see Figure 10 14--ns
Table 10: Dynamic characteristics 74HCT573
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 16 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
12. Waveforms
Measurement points are given in Table 11.
Fig 7. Propagation delay data input (Dn) to output (Qn) and output transition time
Measurement points are given in Table 11.
Fig 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to
output (Qn) and output transition time
001aae082
Dn input
Qn output
VM
tPLH tPHL
tTHL
tTLH
VM
90 %
10 %
VM
VM
tPLH
tPHL
tW
LE input
Qn output
001aae083
tTLH
tTHL
90 %
10 %
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 17 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Measurement points are given in Table 11.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 9. 3-state enable and disable times
Measurement points are given in Table 11.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 10. Set-up and hold times for data input (Dn) to latch input (LE)
Table 11: Measurement points
Type Input Output
VMVM
74HC573 0.5VCC 0.5VCC
74HCT573 1.3 V 1.3 V
001aae307
tPLZ
tPHZ
outputs
disabled outputs
enabled
90%
10%
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
001aae084
VM
LE input
Dn input VM
th
tsu
th
tsu
74HC_HCT573_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 17 January 2006 18 of 26
Philips Semiconductors 74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Test data is given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 11. Load circuitry for measuring switching times
Table 12: Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC573 VCC 6 ns 15 pF, 50 pF 1 kopen GND VCC
74HCT573 3 V 6 ns 15 pF, 50 pF 1 kopen GND VCC
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
PULSE
GENERATOR