ADMV4420-EVALZ User Guide UG-1404 One Technology Way * P.O. Box 9106 * Norwood, MA 02062-9106, U.S.A. * Tel: 781.329.4700 * Fax: 781.461.3113 * www.analog.com Evaluating the ADMV4420, K Band Downconverter with Integrated Fractional-N PLL and VCO FEATURES EVALUATION BOARD PHOTOGRAPH Full feature evaluation board for the ADMV4420 On-board SDP-S connector for SPI control 5 V operation ACE software interface for SPI control EVALUATION KIT CONTENTS ADMV4420-EVALZ 17099-001 EQUIPMENT NEEDED 5 V dc power supply SDP-S controller board USB cable RF signal generator Spectrum analyzer 50 SMA female to 75 Type F male adapter Figure 1. DOCUMENTS NEEDED ADMV4420 data sheet ADMV4420-EVALZ user guide SOFTWARE NEEDED Analysis, Control, Evaluation (ACE) software GENERAL DESCRIPTION The ADMV4420 is a highly integrated, double balanced, active mixer with integrated fractional-N synthesizer, ideally suited for next generation K band satellite communications. The radio frequency (RF) front end consists of an integrated RF balun and a low noise amplifier (LNA) for optimum 7 dB, single sideband noise figure while minimizing external components. Additionally, the high dynamic range intermediate frequency (IF) output amplifier provides a nominal conversion gain of 36 dB. An integrated, low phase noise, fractional-N phase-locked loop (PLL) with a multicore voltage controlled oscillator (VCO) and an internal x2 multiplier generates the necessary on-chip local oscillator (LO) signal for the double balanced mixer, eliminating the need for external frequency synthesis. The multicore VCO PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 20 uses an internal autocalibration routine that allows the PLL to select the necessary settings and lock in approximately 400 s. The reference input to the PLL employs a differentially excited 50 MHz crystal oscillator on the evaluation board. Alternatively, the reference input can be driven by an external single-ended reference source. The phase frequency detector (PFD) comparison frequency of the PLL operates up to 50 MHz. The ADMV4420 is fabricated on a silicon germanium (SiGe), bipolar complementary metal-oxide semiconductor (BiCMOS) process and is available in a 32-lead, RoHS compliant, 5 mm x 5 mm LFCSP with an exposed pad. The device is specified over the -40C to +85C temperature range on a 5 V power supply. ADMV4420-EVALZ User Guide UG-1404 TABLE OF CONTENTS Features .............................................................................................. 1 Evaluation Kit Contents ................................................................... 1 Installing the ACE Software and ADMV4420 Plug-Ins and Drivers ............................................................................................5 Equipment Needed ........................................................................... 1 Initial Setup ....................................................................................5 Documents Needed .......................................................................... 1 ADMV4420 Block Diagram and Functions ...................................7 Software Needed ............................................................................... 1 VCO Band and Core Readback Sequence .............................. 14 Evaluation Board Photograph ......................................................... 1 Frequency Update Sequence ..................................................... 14 General Description ......................................................................... 1 Results .............................................................................................. 15 Revision History ............................................................................... 2 Evaluation Board Schematics and Artwork ................................ 17 Evaluation Board Hardware ............................................................ 3 Ordering Information .................................................................... 19 Evaluation Board Software Quick Start Procedures .................... 5 Bill of Materials ........................................................................... 19 REVISION HISTORY 10/2018--Revision 0: Initial Version Rev. 0 | Page 2 of 20 UG-1404 ADMV4420-EVALZ User Guide EVALUATION BOARD HARDWARE The ADMV4420-EVALZ comes with an ADMV4420 chip. Figure 4 shows the location of this chip on the evaluation board and the block diagram of the ADMV4420. 17099-002 When evaluating the device, connect the RF input to an RF signal generator. The ADMV4420-EVALZ runs on a 5 V dc supply. Figure 2 shows the top side of the ADMV4420-EVALZ and is intended for evaluation purposes only. Connect the 5 V dc to the VPOS1 test point and ground to the GND2 test point on the ADMV4420-EVALZ. Connect a 50 SMA female to a 75 Type F male adapter to J4 (IF output). Connect the output of the adapter to a spectrum analyzer. The ADMV4420-EVALZ has 50 MHz crystal on board. Optionally, the user can connect a reference signal from a low phase signal generator to the J2 SMA connector. If the user wants to use an external reference, depopulate Y1, C5, and C6 and then install a 0.01 F capacitor at C21, a 1 nF capacitor at C6, and 50 at R21. See Figure 5 for ADMV4420-EVALZ lab connections. Figure 3 shows the block diagram of the ADMV4420 lab bench setup. Figure 2. Top View of the ADMV4420-EVALZ USB SDP-S CONNECTOR RF INPUT AND OPTIONAL EXTERNAL REFERENCE FREQUENCY AT 50MHz, 0dBm ADMV4420 IF OUTPUT EVALUATION BOARD 75 TYPE F MALE TO 50 SMA FEMALE ADAPTER SPECTRUM ANALYZER Figure 3. Block Diagram of the ADMV4420-EVALZ Lab Bench Setup Rev. 0 | Page 3 of 20 17099-003 5V DC POWER SUPPLY 29 28 SDI 30 CS VPOS4_IF 31 SCLK IFOUT 32 PLL LOOP FILTER VTUNE GND UG-1404 DECL5_RF ADMV4420-EVALZ User Guide 27 26 25 GND 1 SPI/ LOGIC ADMV4420 24 SDO GND 2 23 GND GND 3 16.75GHz TO 21.15GHz RFIN 4 CALIBRATION SWITCH 22 CPOUT x2 GND 5 21 VPOS3_CP VCO GND 6 INTEGER REG MODULUS FRACTION REG 20 ENBL1 VCO THIRD-ORDER FRACTIONAL INTERPOLATOR 19 ENBL0 N-COUNTER 8.375GHz TO 10.575GHz 18 GND CHARGE PUMP PHASE/ FREQUENCY DETECTOR 12 13 14 15 16 17099-004 11 x1 OR x2 GND 10 /1 REFERENCE REFERENCE REFERENCE DIVIDE BY 2 DIVIDER DOUBLER MUXOUT 1.8V SDM LDO REF/XTAL1 VPOS1_VCO 9 /1 OR /2 3.3V PLL LDO XTAL2/NC 3.3V VCO LDO VPOS2_PLL 8 DECL4_SDM 7 DECL2_VCO2 DECL3_PLL DECL1_VCO1 17 GND BLEED CURRENT Figure 4. Evaluation Board Configuration SPECTRUM ANALYZER IF OUTPUT 50 SMA FEMALE TO 75 TYPE F MALE ADAPTER RF FREQUENCY GENERATOR COMPUTER USB TO MICRO USB CABLE SDP-S CONNECTOR RFIN DC POWER SUPPLY ADMV4420 SDP-S BOARD EVALUATION BOARD 17099-005 GND 5V DC Figure 5. ADMV4420-EVALZ Lab Connections Rev. 0 | Page 4 of 20 UG-1404 ADMV4420-EVALZ User Guide EVALUATION BOARD SOFTWARE QUICK START PROCEDURES INSTALLING THE ACE SOFTWARE AND ADMV4420 PLUG-INS AND DRIVERS After the installations finish, the ADMV4420-EVALZ plug-in appears when the ACE software opens (see Figure 8). The ADMV4420-EVALZ software uses the Analog Devices, Inc., Analysis, Control, Evaluation (ACE) software. For instructions on how to install and use the ACE software, go to www.analog.com/ACE. 17099-008 If the ACE software has already been installed on the PC, ensure that it is the latest version as listed on www.analog.com/ACE. When installing the ACE software, ensure that during installation that the SDP Drivers, LRF Drivers, and .Net 40 Client driver installations are checked as well (see Figure 6). Figure 8. ADMV4420-EVALZ Plug-In Window after the ACE Software Opens INITIAL SETUP 17099-006 To set up the ADMV4420-EVALZ, take the following steps: 1. Figure 6. Drivers That Must be Installed Along with ACE After the ACE software is installed, download the Board.ADMV4420.acezip file from the ADMV4420 product page. 2. After the download is finished, double click on the Board.ADMV4420.acezip file and the ADMV4420 is then installed on ACE. 3. 17099-007 Alternatively, on the main ACE window, click on Tools > Manage Plug-ins > Available Plug-ins and then search for Board.ADMV4420. Highlight the search result and click on the Install Selected button (see Figure 7). Figure 7. Installing the ADMV4420 Plug-In from ACE Rev. 0 | Page 5 of 20 Connect a USB cable to the PC and then to the USB connector of the system development platform (SDP-S) controller board. Connect the SDP-S board to the ADMV4420-EVALZ through the on-board SDP-S connector on the ADMV4420-EVALZ. Power up the ADMV4420-EVALZ with a 5 V dc supply. When the USB cable is connected to the PC, the green LED lights up. The PC recognizes the ADMV4420EVALZ/SDP-S connector. Open the ACE software. The ADMV4420-EVALZ appears in the Attached Hardware section (see Figure 9). Doubleclick on the evaluation board plug-in. If the device is turned off and turned back on, or if the USB cable is unplugged and plugged back in again, while the ACE software is open, the user may lose contact with the ADMV4420-EVALZ. If this happens, click System, the USB symbol on the ADMV4420 subsystem, and Acquire to talk to the ADMV4420-EVALZ again. In some cases, this may not work, and the ACE session must be closed by clicking on File < Close Session. ADMV4420-EVALZ User Guide UG-1404 5. 17099-009 6. On the left side of the screen, go to the INITIAL CONFIGURATION menu and enter the Initial Settings. If nothing is entered, the default settings that appear on the menu are applied to the device and are used for calculations. After entering the Initial Settings, click Apply at the bottom of the menu. The initial settings must be applied to use the main block diagram. Use the ADMV4420 page with the block diagram in the ACE software to interact with the ADMV4420 device (see Figure 11). Figure 9. Attached Hardware Section When the ADMV4420-EVALZ Connects 17099-011 The ADMV4420 Block Diagram then opens with the INITIAL CONFIGURATION Initial Settings menu (see Figure 10). Figure 11. ADMV4420 Block Diagram in the ACE Software 17099-010 4. Figure 10. ADMV4420-EVALZ with INITIAL CONFIGURATION Rev. 0 | Page 6 of 20 UG-1404 ADMV4420-EVALZ User Guide ADMV4420 BLOCK DIAGRAM AND FUNCTIONS The ADMV4420 ACE plug-in is conveniently organized to appear similar to the block diagram shown in the ADMV4420 data sheet. In this way, it is easy to correlate the functions on the ADMV4420-EVALZ with the descriptions in the ADMV4420 data sheet. A full description of the settings of each block and its corresponding registers is given in the ADMV4420 data sheet. Some of the blocks and their functions are described as they pertain to the ADMV4420-EVALZ. The block diagrams with labels are shown in Figure 13 through Figure 16. Table 1 describes the functionality of all the blocks. Due to ongoing improvements and enhancements to the software, some of the screen images in this user guide may not be the latest versions found in the software. INITIAL 1 INITIAL 2 INITIAL 3 INITIAL 4 INITIAL 5 INITIAL 6 INITIAL 7 INITIAL 8 INITIAL 9 INITIAL 10 INITIAL 11 INITIAL 12 17099-012 INITIAL 11 Figure 12. ADMV4420 INITIAL CONFIGURATION Menu with Labels Rev. 0 | Page 7 of 20 ADMV4420-EVALZ User Guide B E D C G N2 N1 I N3 J N4 R F L1 L2 L3 S1 S2 K S3 N6 L4 QA N5 N7 O H5 H4 H3 H6 QB T1 T2 T3 H2 H1 17099-013 W Figure 13. ADMV4420 Main Block Diagram with Labels M1 M2 M3 M4 M5 M6 17099-014 A UG-1404 Figure 14. ADMV4420 Block Diagram Labels for VCO Locked Frequency vs. Requested Frequency Difference Rev. 0 | Page 8 of 20 UG-1404 ADMV4420-EVALZ User Guide 17099-015 QA1 QA2 QA3 Figure 15. ADMV4420 Block Diagram Labels for Charge Pump 17099-016 QB1 QB2 QB3 Figure 16. ADMV4420 Block Diagram Labels for Charge Pump Bleed Current Table 1. ADMV4420 Block Diagram Label Functions (See Figure 12 and Figure 13 Unless Indicated Otherwise) Label Initial Configuration Labels Initial 1 Initial 2 Initial 3 Initial 4 Initial 5 Function See Figure 12. Click on Restore Software Defaults to restore the software default values for the initial block labels. Enter the Reference Frequency here. This value updates the Reference (Label H1) after the Apply button (Label Initial 12) is clicked. Enter the LO Frequency here. This value updates the LO Frequency (Label I) after the Apply button (Label Initial 12) is clicked. Enter the RF Frequency here. This value updates the RFIN (Label F) frequency after the Apply button (Label Initial 12) is clicked. Enter the Step Size here. This value updates the VCO Step Size (Label K) after the Apply button (Label Initial 12) is clicked. Rev. 0 | Page 9 of 20 ADMV4420-EVALZ User Guide Label Initial 6 Initial 7 Initial 8 Initial 9 Initial 10 Initial 11 Initial 12 A B C D E F G UG-1404 Function Enter or scroll to the Charge Pump Current here. This value updates the Charge Pump Current (Label QA2), seen in Figure 15, after the Apply button (Label Initial 12) is clicked. Enter the Bleed Current here. This value updates the Bleed Current (Label QB2), as seen in Figure 16, after the Apply button (Label Initial 12) is clicked. Click on the Reference Doubler dropdown menu and select whether the doubler is enabled or disabled here. This value updates the Reference Doubler (Label H3) after the Apply button (Label Initial 12) is clicked. Enter the Reference Divider value here. This value updates the Reference Divider (Label H5) after the Apply button (Label Initial 12) is clicked. Click on the Reference Divider dropdown menu and select whether the reference divide by 2 is enabled or disabled. This value updates the Reference Divide-by-2 (Label H4) after the Apply button (Label Initial 12) is clicked. Click on the Summary button to get a list of all the values in the INITIAL CONFIGURATION labels. Click on the Apply button to input all the initial configuration values to the main block diagram. The main block diagram does not function until the Apply button is clicked. To apply all of the register values to the device, click Apply Changes (Label A). If auto apply is highlighted in the ADMV4420 Board tab, the Apply Changes feature (Label A) and the Read All feature (Label B) continuously run every few seconds, and the Apply Changes (Label A) and Read All (Label B) buttons do not have to be clicked to apply or read back the block diagram settings. To read back all of the serial port interface (SPI) registers of the device, click Read All (Label B). If auto apply is highlighted in the ADMV4420 Board tab, the Apply Changes feature (Label A) and the Read All feature (Label B) continuously run every few seconds, and the Apply Changes (Label A) and Read All (Label B) buttons do not have to be clicked to apply or read back the block diagram settings. Click Reset Chip (Label C) to enable the soft reset bit field in the ADI_SPI_CONFIG_1 register (Register 0x000). Click Diff (Label D) to show registers that are different on the device. Click Software Defaults (Label E) to load the software defaults on to the device, and then click Apply Changes (Label A). Enter the RFIN (Label F) frequency here. The absolute difference between the RFIN (Label F) frequency and the LO Frequency (Label I) is displayed here in the IFOUT frequency label. The IF frequency equation is as follows: IF Frequency = |RF Input Frequency - LO Frequency| H1 to H6 H1 H2 H3 H4 H5 H6 Input reference block. Enter the reference frequency in the Reference text box and then click Apply Changes (Label A). Click on the reference type dropdown box to choose the reference type and then click Apply Changes (Label A). The reference type updates the reference register, Register 0x20E, Bit 1, which corresponds to the REF_IN_MODE bit. When REF_IN_MODE is 0, the on-board crystal oscillator is chosen. When REF_IN_MODE is 1, the external reference single-ended mode is chosen. For single-ended operation, populate C21 with R1 and C6 and remove C5 and Y1. See the Bill of Materials section for more information. Click on the Reference Doubler box and a dropdown menu appears with choices whether to enable the reference doubler or disable the reference doubler. Then, click Apply Changes (Label A). The Reference Doubler updates the reference register, Register 0x20E, Bit 2, which corresponds to the EN_REF_X2 bit. When the reference doubler is enabled, EN_REF_X2 is 1 and vice versa. Click on the Reference Divide-by-2 box and a dropdown menu appears with choices whether to enable the reference divide by 2 or disable the reference divide by 2. Then, click Apply Changes (Label A). The reference divide by 2 updates the reference register, Register 0x20E, Bit 0, which corresponds to the RDIV2_SEL bit. When the reference divide by 2 is enabled, RDIV2_SEL is 1 and vice versa. Click on the Reference Divider box and enter the reference divider value, then click Apply Changes (Label A). The reference divider updates the R_DIV_L register (Bits[7:0]) and the R_DIV_H register (Bits[1:0]), which correspond to the R_DIV bits. The R_DIV bits are 10 bits wide, and the reference divider ranges from 1 to 1023. The PFD Frequency is displayed here. The PFD frequency is calculated based on the following formula: PFD Frequency Reference Frequency x = I Reference Doubler ( Reference Divide by 2 x Reference Divider ) Enter the LO Frequency on this label and then click Apply Changes (Label A). The LO frequency is twice the VCO Frequency (Label J) based on the following equation: LO Frequency = VCO Frequency x 2 Rev. 0 | Page 10 of 20 UG-1404 Label J ADMV4420-EVALZ User Guide Function Enter the VCO Frequency on this label and then click Apply Changes (Label A). The VCO frequency is half the LO Frequency (Label I), as seen in the following equation: VCO = Frequency LO Frequency x 1 2 The VCO frequency is also related to the PFD Frequency (Label H6) and the N Counter (Label L4) by the following equation: VCO Frequency = PFD Frequency x N Counter Enter the VCO Step Size on this label and then click Apply Changes (Label A). The step size determines the nearest resolution to which the VCO Frequency (Label J), and therefore the LO Frequency (Label I), locks to. The step size is related to the PFD Frequency (Label H6), MOD (Label L3) and the greatest common denominator (GCD) function by the following equation: K MOD = L1 to L4 L1 L2 L3 L4 PFD Frequency GCD ( PFD Frequency , Step Size ) INT, FRAC, MOD, and N counter labels. Enter the INT value on this label and then click Apply Changes (Label A). The INT value updates the 16-bit INT bit field, which is on Register INT_L, Bits[7:0] (Register 0x200) and Register INT_H, Bits[15:8] (Register 0x201). The INT value is automatically updated when the VCO Frequency (Label J), LO Frequency (Label I), or N Counter (Label L4) is changed. Enter the FRAC value on this label and then click Apply Changes (Label A). The FRAC value updates the 24-bit FRAC bit field, which is on Register FRAC_L, Bits[7:0] (Register 0x202), Register FRAC_M, Bits[15:8] (Register 0x203), and Register FRAC_H, Bits[23:16] (Register 0x204). The FRAC value is automatically updated when the VCO Frequency (Label J), LO Frequency (Label I), VCO Step Size (Label K), or N Counter (Label L4) is changed. Enter the MOD value on this label and then click Apply Changes (Label A). The MOD value updates the 24-bit MOD bit field, which is on Register MOD_L, Bits[7:0] (Register 0x208), Register MOD_M, Bits[15:8] (Register 0x209), and Register MOD_H, Bits[23:16] (Register 0x20A). The MOD value is automatically updated when the VCO Step Size (Label K) is changed. Enter the N Counter value on this label and then click Apply Changes (Label A). The N counter value updates the INT (Label L3), FRAC (Label L2), MOD (Label L3), LO Frequency (Label I), and VCO Frequency (Label J). The N counter is related to the VCO Frequency (Label J) and PFD Frequency (Label H6) by the following equation: N Counter = VCO Frequency PFD Frequency The N counter is related to the INT (Label L1), FRAC (Label L2), and MOD (Label L3) by the following equation: N Counter = INT + FRAC MOD The INT (Label L1) value is calculated from the N counter value using the following equation: INT = FLOOR(N Counter) The FRAC (Label L2) value is calculated from the N counter, INT (Label L1), and MOD (Label L3) value using the following equation: FRAC = |N Counter - INT| x MOD M1 to M6 M1 M2 The MOD (Label L3) value is calculated using the equation in Label K. VCO frequency different block. The VCO frequency different block appears on the right of the main block diagram if the requested VCO Frequency (Label J) is different from the actual VCO frequency on the device. This usually happens when the VCO Step Size (Label K) value is not small enough to lock to the desired VCO Frequency (Label J). See Figure 14. VCO Frequency Different indicator. When the VCO Frequency Different indicator is on, the requested VCO Frequency (Label J) is different from the actual VCO frequency on the device. The Difference in Locked vs. Requested VCO Frequency shows the difference between the requested VCO Frequency (Label J) and the actual VCO frequency on the device. The Difference in Locked vs. Requested VCO Frequency is calculated using the following equation: FRAC (Label L2) = | INT (Label L1) + x PFD Frequency (Label H 6) - ( N Counter (Label L 4) x PFD Frequency (Label H 6) ) | MOD (Label L3) Rev. 0 | Page 11 of 20 ADMV4420-EVALZ User Guide Label M3 UG-1404 Function The Difference in Locked vs. Requested LO Frequency shows the difference between the requested LO Frequency (Label J) and the actual LO frequency on the device. The Difference in Locked vs. Requested LO Frequency is calculated using the following equation: Difference in Locked vs. Requested LO Frequency = 2 x Difference in Locked vs. Requested VCO Frequency (Label M2) M4 The Locked LO Frequency label shows the actual LO frequency on the device. The Locked LO Frequency is calculated using the following equation: Locked LO Frequency = 2 x Locked VCO Frequency (Label M5) M5 M6 N1 to N7 N1 N2 N3 N4 N5 N6 N7 O QA, QA1 to QA3, QB, and QB1 to QB3 QA QA1 QA2 QA3 QB QB1 QB2 QB3 R The Locked VCO Frequency label shows the actual VCO frequency on the device. The Locked VCO Frequency is calculated using the following equation: FRAC (Label L2) Locked VCO Frequency =| INT (Label L1) + x PFD Frequency (Label H 6) | MOD (Label L3) The Actual IF Frequency out label shows the actual IF frequency on the device as opposed to the IF Frequency (Label G) based on the requested RFIN (Label F) frequency and LO Frequency (Label I). The actual IF frequency out is calculated using the following equation: Actual IF Frequency Out = |RF Frequency (Label F) - Locked VCO Frequency (Label M5)| Enable blocks. Click LNA Enable Block and click Apply Changes (Label A) to set the EN_LNA bit (Bit 0) in the enables register (Register 0x0103). Click Mixer Enable Block and click Apply Changes (Label A) to set the EN_MIXER bit (Bit 1) in the enables register (Register 0x0103). Click IF AMP Enable Block and click Apply Changes (Label A) to set the EN_IFAMP bit (Bit 2) in enables register (Register 0x0103). Click LO Enable Block and click Apply Changes (Label A) to set the EN_LO bit (Bit 5) in enables register (Register 0x0103). Click PLL Enable Block and click Apply Changes (Label A) to set the EN_PLL bit (Bit 6) in the enables register (Register 0x0103). Click VCO Enable Block and click Apply Changes (Label A) to set the EN_VCO bit (Bit 3) in the enables register (Register 0x0103). Click on the Power Up Circuit dropdown menu and click Apply Changes (Label A) to set or unset N1 to N6 altogether. Click on the Reset button to reset the circuit. This button does a similar function to the Reset Chip (Label C) button. Charge pump and charge pump bleed blocks. See Figure 15 and Figure 16. Click on the Charge Pump block to configure the charge pump current and charge pump mode on the device. The Charge Pump block diagram appears as shown in Figure 15. Click on the Charge Pump Mode dropdown menu and choose which mode the charge pump operates and click Apply Changes (Label A). If open loop operation is required, choose Charge Pump Hi-z Operation. For general use, keep the charge pump mode on normal use. The charge pump mode sets the CP_STATE bits (Bits[1:0]) in the CP_STATE register (Register 0x22C). Use the scroll button or type in the required Charge Pump Current in microamps. The charge pump current sets the CP_CURRENT bits (Bits[3:0]) in the CP_CURRENT register (Register 0x22E). The charge pump current varies from 312.5 A to 5000 A in steps of 312.5 A. Click on the Charge Pump Block Diagram Close button to exit the charge pump block. Click on the Charge Pump Bleed block to configure the charge pump bleed current and charge pump bleed mode on the device. The Charge Pump Bleed block diagram appears as shown in Figure 16. Click on the Charge Pump Bleed Mode dropdown menu and choose which mode the charge pump bleed operates and click Apply Changes (Label A). The charge pump bleed mode sets the EN_BLEED bit (Bit 0) in the CP_BLEED_EN register (Register 0x22D). Use the scroll button or type in the required Charge Pump Bleed Current in microamps. The charge pump bleed current sets the BICP bits (Bits[7:0]) in the CP_BLEED register (Register 0x22F). The charge pump bleed current varies from 0 A to 956.25 A in steps of 3.75 A. Click on the Charge Pump Bleed Block Diagram Close button to exit the charge pump bleed block. Click Enable Autocal block and click Apply Changes (Label A) to set the EN_AUTOCAL bit (Bit 1) in the AUTOCAL register (Register 0x226). Rev. 0 | Page 12 of 20 UG-1404 S2 S3 T1 to T3 T1 T2 T3 W Function Read VCO band and core sequence and label. The VCO BAND Readback label displays the VCO band when the Read Band and Core (Label S3) button is pressed. This label only updates when S3 is pressed. The VCO CORE Readback label displays the VCO core when the Read Band and Core (Label S3) button is pressed. This label only updates when S3 is pressed. Click the Read Band and Core button to update S1 and S2. The VCO Band and Core Readback Sequence section describes how the values for S1 and S2 are obtained. MUXOUT and lock detect settings. Click on the Lock Detect Bias dropdown menu to select the lock detect bias setting and then click Apply Changes (Label A).The lock detect bias sets the LD_BIAS bits (Bits[7:6]) in the LOCK_DETECT register (Register 0x214). Click on the Lock Detect Count dropdown menu to select the lock detect count setting and then click Apply Changes (Label A).The lock detect count sets the LD_COUNT bits (Bits[5:3]) in the LOCK_DETECT register (Register 0x214). Click on the Muxout Select dropdown menu to select the MUXOUT pin setting and then click Apply Changes (Label A). The MUXOUT pin sets the PLL_MUX_SEL bits (Bits[7:0]) in the PLL_MUX_SEL register (Register 0x213). The Muxout Select dropdown menu controls the functionality of the MUXOUT pin on the ADMV4420. When the MUXOUT pin is set to digital lock detect and the PLL is locked, or if the MUXOUT pin is set to logic high, the LED DS1 turns on. Click Proceed to Memory Map (Label W) to open the ADMV4420 memory map (see Figure 17). 17099-017 Label S1 to S3 S1 ADMV4420-EVALZ User Guide Figure 17. ADMV4420 Memory Map in the ACE Software Rev. 0 | Page 13 of 20 ADMV4420-EVALZ User Guide UG-1404 VCO BAND AND CORE READBACK SEQUENCE FREQUENCY UPDATE SEQUENCE The read band and core run the following sequence to obtain the values for the VCO core and VCO band: When the VCO frequency or charge pump must be updated, the INT register, MOD register, and FRAC register must be updated in a specific sequence. The ADMV4420 software automatically follows this sequence when the VCO frequency must be updated. When the charge pump must be updated, the CP_CURRENT register is updated before this sequence. The sequence that the ADMV4420 software uses is as follows: 1. 2. 3. 4. 5. 6. Write 0x04 to VCO_READBACK_SEL bits (Bits[2:0]) in the VCO_READBACK_SEL register (Register 0x21F). Read back Register VCO_DATA_READBACK1 (Register 0x211). The first two bits (Bits[1:0]) equal the VCO core. Write 0x01 to VCO_READBACK_SEL bits (Bits[2:0]) in the VCO_READBACK_SEL register (Register 0x21F). Read back Register VCO_DATA_READBACK1 (Register 0x211). The readback value equals the VCO band. 1. 2. 3. 4. 5. 6. 7. 8. 9. Rev. 0 | Page 14 of 20 Write to FRAC_H register (Register 0x204) Write to FRAC_M register (Register 0x203) Write to FRAC_L register (Register 0x202) Write to MOD_H register (Register 0x20A) Write to MOD_M register (Register 0x209) Write to MOD_L register (Register 0x208) Write to INT_H register (Register 0x201) Write to INT_L register (Register 0x200) Wait 16 SPI clock cycles UG-1404 ADMV4420-EVALZ User Guide RESULTS When testing the ADMV4420-EVALZ, the following are the expected results for an 18 GHz RF signal at -40 dBm, using the on-board crystal oscillator. oscillator. Figure 19 shows the corresponding results on a spectrum analyzer when the RF signal is -40 dBm. Board traces are not de-embedded. 17099-018 Figure 18 shows the ACE block diagram settings for a 17 GHz LO with an 18 GHz RF signal, and 50 MHz on-board crystal 17099-019 Figure 18. Block Diagram Settings for18 GHz RF Signal, 17 GHz LO with 50 MHz On-Board Crystal Oscillator Figure 19. ADMV4420 Results with a 17 GHz LO, 18 GHz RF Signal at -40 dBm, and 50 MHz On-Board Crystal Oscillator Rev. 0 | Page 15 of 20 ADMV4420-EVALZ User Guide UG-1404 spectrum analyzer when the RF signal is -40 dBm. Board traces are not de-embedded. 17099-020 Figure 20 shows the ACE block diagram settings for a 20.2 GHz LO with an 18 GHz RF signal, and 50 MHz on-board crystal oscillator. Figure 21 shows the corresponding results on a 17099-021 Figure 20. Block Diagram Settings for18 GHz RF Signal, 20.2 GHz LO with 50 MHz On-Board Crystal Oscillator Figure 21. ADMV4420 Results with a 20.2 GHz LO, 18 GHz RF Signal at -40 dBm, and 50 MHz On-Board Crystal Oscillator Rev. 0 | Page 16 of 20 Figure 22. ADMV4420-EVALZ Schematic Rev. 0 | Page 17 of 20 1 VCC5P0 1 ENBL0 1 ENBL1 C33 10F VPOS2 51nH L1 AGND U1 C19 100pF C27 0.1F AGND C15 100pF AGND AGND AGND GND 24 50MHz XTAL1 XTAL2 VCC5P0 1 3 C6 20pF C21 DNI 0.01F AGND GND1 GND2 GND3 C1 10F C5 20pF AGND C29 100pF AGND C30 10pF AGND AGND C8 0.1F C18 10pF C DS1 A R19 1k AGND 1 AGND AGND C26 220pF R4 680 C25 6800pF C22 0.1F VPOS3 1 2 3 6 7 A0 A1 A2 SCL WP DEFAULT CONFIG; USE CASE 2 C5 = 20pF C6 = 20pF CASE 2: USING CRYSTAL POPULATE C5 AND C6 DNI C21 U2 R28 DNI 0 SDA_SDP AGND C11 0.1F ENBL0 VCC5P0 AGND VSS 4 TWI_A0 GPIO6_SDP SDA 5 8 VCC 3P3V TWI_A0 C35 10F R16 0 VCC5P0 CASE 1: USING SMA POPULATE C21 AND C6 = 1nF. DNI C5 AND Y1 R27 100k R26 DNI AGND R25 100k C28 DNI VTUNE AGND R11 0 R5 1.5k VCC5P0 AGND C23 100pF AGND C34 10F R14 0 C24 470pF 5 4 3 2 R1 49.9 AGND AGND C12 0.1F VPOS4 24 GND SDO 23 GND GND 22 GND CPOUT 21 RFIN VPOS3_CP 20 GND ENBL1 19 ADMV4420 GND ENBL0 18 DECL1_VCO1 GND 17 DECL2_VCO2 GND C4 10F C16 10pF 1 2 3 4 5 6 7 8 AGND C7 0.1F R29 1k AGND AGND C20 100pF AGND C9 4.7F C13 0.1F R13 0 C32 10F C2 10pF AGND VPOS1 AGND C14 10F VCC5P0 R15 0 AGND AGND 234 J1 AGND AGND AGND AGND C10 10pF C3 10F AGND 0.01F J4 C17 9 AGND 2 3 4 5 1 32 31 30 29 28 27 26 25 PAD DECL5_RF GND IFOUT VPOS4_IF VTUNE CS SCLK SDI VPOS1_VCO DECL3_PLL DECL4_SDM VPOS2_PLL XTAL2/NC REF/XTAL1 MUXOUT GND 10 11 12 13 14 15 16 CPOUT AGND 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 J3 AGND C37 DNI SDO AGND C38 DNI SCLK 3P3V C36 DNI CS C39 DNI SDI AGND AGND ENBL1 SCL_SDP SDA_SDP GPIO7_SDP AGND 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 J3 17099-022 UG-1404 ADMV4420-EVALZ User Guide EVALUATION BOARD SCHEMATICS AND ARTWORK UG-1404 Figure 23. ADMV4420-EVALZ Top 17099-024 17099-023 ADMV4420-EVALZ User Guide Figure 24. ADMV4420-EVALZ Bottom Rev. 0 | Page 18 of 20 UG-1404 ADMV4420-EVALZ User Guide ORDERING INFORMATION BILL OF MATERIALS Table 2. Configuration Options Components C1 to C4, C7 to C16, C18 to C20, C22, C23, C27, C29, C30, C32, C34, C35, R29 Description Power supply decoupling and low dropout (LDO) decoupling capacitors. R29 resistor is needed to aid in discharging the decoupling capacitor, C4, and Capacitor C18. Test loops for SPI, enable pins, and MUXOUT. Default Conditions C1, C3, C14, C32, C35 = 10 F (Size 0603), C34, C4 = 10 F (Size 0402), C7, C8, C11 to C13, C22, C27 = 0.1 F (Size 0402), C15, C19, C20, C23, C29 = 100 pF (Size 0402), C2, C10, C16, C18, C30 = 10 pF (Size 0402), C9 = 4.7 F (Size 0402), R29 = 1 k (Size 0402) CNLOOPTP C17 = 0.01 F (Size 0402), L1 = 51 nH (Size 0402), J4 = 75 connector (531-40039, AMPHENOL531-40039) DS1 C24, R4, R5, C25, C26, R11 IF output interface. The open collector IF output interface is biased through pullup Choke Inductor L1. The C17 capacitor is an ac-coupling capacitor. LED indicator for lock detect. Loop filter components. VPOS1 to VPOS4, VCC5P0 GND1 to GND3 J1 VPOS test loops. Test loops for ground. RFIN connector. J2, R1, C21, C5, C6, Y1 Reference Circuits. Case 1 using SMA: populate C21, R1, and C6. Do not install (DNI) C5 and Y1. Case 2 using crystal: populate C5 and C6. DNI C21. Use Case 2 for default condition. R13 to R16 U2, R25, R27, C11 Shorts. 32-bit electronically erasable programmable read-only memory (EEPROM) circuits. Mounting holes for heatsinks. Device under test (DUT). SDP-S connector. CS, SDI, SDO, SCLK, ENBL0, ENBL1, MUXOUT C17, L1, J4 MTG1 to MTG4 ADMV4420 J3 Rev. 0 | Page 19 of 20 SML-210MTT86 C24 = 470 pF (Size 0402), R4 = 680 (Size 0402), C25 = 6800 pF (Size 0402), R5 = 1.5 k (Size 0402), R11 = 0 (Size 0402), C26 = 220 pF (Size 0402) CNLOOPTP CNLOOPTP Southwest Microwave 2.92 mm connector, 1092-04A-5/SRI K connector 25-146-1000-92 R1 = 49.9 (Size 0402), J2 = JOHNSON142-0701-851 Case 1: C5 = DNI, C6 = 1 nF (Size 0402), Y1 = DNI, C21 = 0.01 F (Size0402) Case 2: C5 = 20 pF (Size 0402), C6 = 20 pF (Size 0402), Y1 = 50 MHz crystal (NX3225SA 12 pF, YSML126W98H28), C21 = DNI 0 (Size 0402) R25, R27 = 100 k (Size 0402), U2 = 24LC32A-I/MS, C11 = 0.1 F Keystone Electronics CORP-5002 Not applicable FX8-120S-SV(21), HRSFX8-120S-SV ADMV4420-EVALZ User Guide UG-1404 NOTES ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the "Evaluation Board"), you are agreeing to be bound by the terms and conditions set forth below ("Agreement") unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you ("Customer") and Analog Devices, Inc. ("ADI"), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. 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