FS612510-02 - AMI Semiconductor, Inc.

American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

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1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC

1.0 Features

• Generates one bank of ten clock outputs (1Y0 to

1Y9) from one reference clock input (CLK)

• Designed to meet the PLL Component Specifications

as noted in the PC133 SDRAM Registered DIMM

Design Specification

• External feedback input (FBIN) to synchronize all

clock outputs to the reference input

• Operating freque ncy 25MHz to 140MH z

• Tight tracking skew (spread-spectrum tolerant)

• On-chip 25Ω series damping resistors for driving

point-to-point loads

• Output enable (G) enables or disables low all clock

outputs

• Available with an auto power-down option that turns

off the PLL and forces all outputs low when the refer-

ence clock stops (FS612510-02)

• Packaged in a 24-pin TSSOP

Figure 1: Block Diagram

FS612510

1Y0

1Y1

1Y2

1Y3

1Y4

1Y5

1Y6

1Y7

1Y8

PLL

FBIN

CLK

FBOUT

AVDD

1Y9

VDD

GND

AGND

2.0 Description

The FS612 510 is a low sk ew, low jitter CMOS zero-dela y

phase-lock loop (PLL) clock buffer IC designed for high-

speed motherboard applications, such as those using

133MH z SDRAM.

Ten buffered clock outputs are derived from an onboard

open-loop PLL. The PLL aligns the frequency and phase

of all output clocks to the reference input clock CLK, in-

cluding an FBOUT clock that feeds bac k to FBIN to c lose

the loop. Mult iple power and ground supplies help re duce

the effects of noise on device performance.

All ten outputs 1Y0 to 1Y9 are enabled and disabled low

by the ac ti ve-h igh G signal. T he PLL can be bypassed for

test purposes by pulling AVDD to ground.

Figure 2: Pin Configuration

AGND

VDD

1Y0 AVDD

CLK

GND

1Y3

1Y4

VDD

FBOUT

1Y6

GND

1Y7

GND

1Y8

1Y5

VDD

FBIN

FS612510

1Y1

1Y2

VDD

1Y9

Table 1: Function Table

INPUT OUTPUT

PLL AVDD G CLK 1Y0-1Y9 FBOUT

HLL L L

HLH L H

HHL L L

Zero-Delay

HHH H H

LLL L L

LLH L H

LHL L L

PLL Bypass

LHH H H

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1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC

Table 2: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN TYPE NAME DESCRIPTION

3 DO 1Y0 Clock output

4 DO 1Y1 Clock output

5 DO 1Y2 Clock output

8 DO 1Y3 Clock output

9 DO 1Y4 Clock output

15 DO 1Y5 Clock output

16 DO 1Y6 Clock output

17 DO 1Y7 Clock output

20 DO 1Y8 Clock output

21 DO 1Y9 Clock output

Enabled by G

23 P AVDD Power Supply / Test mode enable. This pin provides t he power supply to the internal P LL. When the

pin is pulled low, the PLL is bypassed and the output clocks directly follow the input clock

1 P AGND PLL supply ground

24 DI CLK Reference clock input (Note: -02 version has a pull-down on this pin)

13 DI FBIN Feedback clock input; must be connected to FBOUT to complete the loop

12 DO FBOUT Feedback output clock

11 DI G Output enable stops all cl ocks (1Y0 – 1Y9) in a low state when this pin is low

6, 7, 18, 19 P GND Ground for all clock outputs

2, 10, 14, 22 P VDD Power supply for all clock outputs

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1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC

3.0 Device Operation

The FS612510 is a zero-delay buffer intended f or use on

buffered PC133 SDRAM DIMMs.

The FS612510 precisely aligns the frequency and phase

of the ou tput cloc ks to the inpu t CLK by use of an on-chi p

phase-lock loop (PLL). The PLL generates up to 10 low-

skew, low-jitter copies of the CLK, with the outputs ad-

justed for 50% duty cycle.

The FBOUT clock must be hardwired to the FBIN pin to

complete the loop. The PLL actively adjusts the output

clocks so that there is no phase error between the refer-

ence clock (CLK) and the feedback clock (FBIN).

Since the device uses a PLL to lock the output clocks to

the input c lock, there is a power-up stabilization t ime that

is required for the PLL to achieve phase lock.

Note that all inputs and outputs use LVCMOS signal lev-

els.

3.1 PLL Bypass

When the AVDD pin is pulled low, the reference clock

signal b ypasses the PLL and is m uxed direct ly through to

the outputs . The PLL is power ed d own, an d d ev ice acts a

fanout buffer.

Note that if AVDD is re-established, the PLL requires a

power-up and stabilization time to lock to the input clock.

3.2 Output Enable/Disable

All ten outputs are e nabled or d isabled as a group b y the

G enable signal.

A logic-high on G input enables all the clock outputs to

swing in phase with the r eference c lock . A logic-lo w on G

forces all of the clock outputs to a logic-low state.

The function table Table 1 shows the effect of the G en-

able signal on the clock outputs.

3.3 Power-Down

The FS612510-02 version provides an auto power-down

feature that shuts off the PLL, drives all outputs low, and

places the device into a low current state if the reference

clock stops. The power-down circuit is level sensitive,

and detects either a DC high or low on the CLK input.

4.0 Tracking Skew

PLL-bas ed buff er ICs may be required t o f ollo w a spread-

spectrum modulated reference clock for frequencies

greater than 66MHz. Spread spectrum modulation limits

peak EMI em iss ions by inten tiona lly intro duci ng jitt er onto

a clock signal, eff ectivel y spre ading the pe ak ener gy over

a range of frequencies.

A downstream PLL, contained in a clock buffer IC such

as this one, must carefully track the modulated input ref-

erence clock. A measure of how closely the downstream

PLL follows the modulated clock is called the tracking

skew. To ensure a tight tracking skew, the loop band-

width of a downstream PLL is increased and the loop

phase angle is reduced over that of typical PLL-based

clock generators.

The type of modulation profile used impacts tracking

skew. The maximum frequency change occurs at the

profile lim its where the modulation changes the slew rate

polarity. To track the sudden reversal in clock frequency,

the downstream PLL must have a large loop bandwidth.

The ability of the downstream PLL to catch up to the

modulatin g clock is determined by the loop transfer func-

tion phase angle.

The spread-spectrum reference clock should be either a

triangle-wave or a non-linear (Lexmark) modulation pro-

file, with a modulation frequency of 50kHz or less.

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1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC1:10 Zero-Delay Clock Buffer IC

1:10 Zero-Delay Clock Buffer IC

5.0 Electrical Specifications

Table 3: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER SYMBOL MIN. MAX. UNITS

Supply Voltage, dc, Clock Buffers (VSS = ground) AVDD VSS - 0 .5 7 V

Supply Voltage, dc, Core VDD VSS - 0.5 7 V

Input Voltage, dc VIVSS - 0.5 V DD+0.5 V

Output Voltage, dc VOVSS - 0.5 V DD+0.5 V

Input Clamp Current, dc (V I < 0 or VI > VDD)I

IK -50 50 mA

Output Clamp Current, dc (VI < 0 or VI > VDD)I

OK -50 50 mA

Storage Temperature Range (non-condensing) TS-65 150 °C

Ambient Temperature Range, Under Bias TA-55 125 °C

Junction Temperature TJ125 °C

Lead Temperature (soldering, 10s) 260 °C

Static Disc harge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage res ulti ng in a loss of functional ity or performance may occur if this device is subjected to a high-energy

electrost a tic discharge.

Table 4: Operating Conditions

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Supply Voltage, Core and Outputs VDD 3.3V ± 10% 3.0 3.3 3.6 V

Ambient Operating Temperature Range TA070°C

Output Load Capacit ance CL15 pF

Input Frequency fCLK CLK 50 140 MHz

Input Duty Cycle CLK 40 60 %

Input Rise/Fall Time CLK 3 ns

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Table 5: DC Electrical Specifications

Unless otherwise stated, all power supplies = 3.3V%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal charac-

terization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

Supply Current, Dynamic fCLK = 133.33MHz; VDD = 3.3V 135 mA

Supply Current, Static IDDL Outputs l ow; VDD = 3.3V 3 mA

Output Enable Input (G)

High-Level Input V olt age VIH 2.0 VDD+0.3 V

Low-Level Input V oltage VIL VSS-0.3 0.8 V

Input Leakage Current II-5 5 µA

Clock Inputs (CLK, FBIN)

High-Level Input V olt age VIH 2.0 VDD+0.3 V

Low-Level Input V oltage VIL VSS-0.3 0.8 V

-01 version -5 5

Input Leakage Current II-02 version has a pul l -down on CLK 28 µA

Input Loading Capacitance * CL(in) As seen by an external clock driver 4 pF

Clock Outputs (1Y0:9, FBOUT)

VDD = 2.9V, VO = 2.0V -18 -12

High-Level Output Sourc e Current IOH VDD = 3.7V, VO = 2.0V -35 -12 mA

VDD = 2.9V, VO = 0.8V 12 16

Low-Level Output Sink Current IOL VDD = 3.7V, VO = 0.8V 12 17 mA

Output Impedance zO33 Ω

Tristate Output Current IOZ -10 10 µA

Short Circuit S ource Current * IOSH VO = 0V; shorted for 30s, max. -60 mA

Short Circuit S i nk Current * IOSL VO = 3.3V; shorted for 30s, max. 90 mA

Table 6: Clock Output Drive (1Y0:4, 2Y0:3, FBOUT)

Voltage Low Drive Current (mA) High Drive Current (mA)

0.1 V -47 -59 2 2

0.2 V -45 -58 4 4

0.4 V -43 -56 8 9

0.6 V -40 -55 12 13

0.8 V -38 -52 16 17

1.0 V -35 -50 20 21

1.2 V -32 -47 24 25

1.4 V -29 -45 27 29

1.6 V -26 -41 31 33

1.8 V -22 -38 34 36

2.0 V -18 -35 38 40

2.2 V -15 -31 41 43

2.4 V -10 -28 43 46

2.6 V -6 -24 45 49

2.8 V -2 -20 48 51

3.0 V 0 -15 49 53

3.3 V -9 56

-60

-45

-30

-15

00.511.522.533.5

Output Voltage (V)

Output Current (mA)

30Ω

50Ω

90Ω

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3.6 V -2 59

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Table 7: AC Timing Specifications

Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and

are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.

PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS

Overall

Skew, Output to Output * tsk(o) Measured on the rising edge at 1.65V; CL = 15pF 150 ps

Skew, Tracking * Measured using a –0.5% 31.5kHz spread

spectrum reference clock at 133.33MHz 150 ps

Static Phase Error * From rising edge on CLK to rising edge on FBIN -120 ps

Clock Stabilization Time * Tim e required for the PLL to achieve phase lock 3 ms

Loop Bandwidth * For calculation of Track i ng Skew 1.2 MHz

Phase Angle * For calculation of Tracki ng Skew -0.031 °

Clock Outputs (1Y0:9, FBOUT)

Duty Cycle * dtRatio of high pulse width to one clock period,

measured at 1.65V 45 55 %

Jitter, Cycle-Cycle * tj(CC) Adjacent cycles at 1.65V -75 +75 ps

Jitter, Period (peak-peak) * tj(∆P) From rising edge to next rising edge at 1.65V

Rise Time * trVO = 0.4V to 2.0V; CL = 15pF 1.2 ns

Fall Time * tfVO = 2.0V to 0.4V ; CL = 15pF 1.4 ns

Enable Delay * tDLH via G 1 10 ns

Disable Del ay * tDHL via G 1 10 ns

Figure 3: Clock Skew Measurement

clock skew (t

sk(o)

)

Any

output

Any

output

50% V

Figure 4: Phase Error Measurement

phase error

CLK

FBIN

50% V

Figure 5: Timing Measurement Points

0.4V

2.4V

3.3V

50% V

Figure 6: Output Enable Measurement

DLZ

10%

90%

DHZ

50% 50%

50%

DZL

DHZ

Output

Enable

Output

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6.0 Package Information

Table 8: 24-pin TSSOP Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

MIN. MAX. MIN. MAX.

A - 0.047 - 1.20

A10.002 0.006 0.05 0.15

A20.0315 0.0413 0.80 1.05

b 0.0075 0.0118 0.19 0.30

C 0.0035 0.0079 0.09 0.20

D 0.303 0.311 7.70 7.90

E10.169 0.177 4.30 4.50

E 0.252 6.40 BSC

e 0.0256 0. 65 BSC

L 0.0177 0.0295 0.45 0.75

S 0.0079 - 0.20 -

θ10°8°0°8°

θ212 REF 12 REF

θ312 REF 12 REF

AMERICAN MICROSYSTEMS, INC.

SEATI NG PLA NEBASE PLANE

A c

Table 9: 24-pin TSSOP Package Characteristics

PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS

Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 84 ° C/W

Lead Inductanc e, Self L11 Longest lead 1.7 nH

L12 Longest lead to any 1st adjacent lead 0.6

Lead Inductanc e, Mutual L13 Longest lead to any 2nd adjacent lead 0.24 nH

Lead Capacitance, Bulk C11 Longest lead to VSS 0.3 pF

C12 Longest lead to any 1st adjacent lead 0.1

Lead Capacitance, Mutual C13 Longest lead to any 2nd adjacent lead 0.007 pF

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7.0 Ordering Information

Table 10: Device Ordering Codes

DEVICE

NUMBER ORDERING CODE PACKAGE TYPE OPERATING

TEMPERATURE RANGE SHIPPING

CONFIGURATION

FS612510-01 12055-102 24-pin TSSOP

(Thin Shrink Small Outline Package) 0°C to 70°C (Commercial) Tape and Reel

FS612510-02 12055-103 24-pin TSSOP

(Thin Shrink Small Outline Package) 0°C to 70°C (Commercial) Tape and Reel

Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI

makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom

of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-

serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are

intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-

ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not rec om-

mended without additional processing by AMI for such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,

WWW Address: http://www.amis.com E-mail: tgp@amis.com