FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC 1.0 Features 2.0 * Generates one bank of ten clock outputs (1Y0 to 1Y9) from one reference clock input (CLK) * Designed to meet the PLL Component Specifications as noted in the PC133 SDRAM Registered DIMM Design Specification * External feedback input (FBIN) to synchronize all clock outputs to the reference input * Operating frequency 25MHz to 140MHz * Tight tracking skew (spread-spectrum tolerant) * On-chip 25 series damping resistors for driving point-to-point loads * Output enable (G) enables or disables low all clock outputs * Available with an auto power-down option that turns off the PLL and forces all outputs low when the reference clock stops (FS612510-02) * Packaged in a 24-pin TSSOP Description The FS612510 is a low skew, low jitter CMOS zero-delay phase-lock loop (PLL) clock buffer IC designed for highspeed motherboard applications, such as those using 133MHz SDRAM. Ten buffered clock outputs are derived from an onboard open-loop PLL. The PLL aligns the frequency and phase of all output clocks to the reference input clock CLK, including an FBOUT clock that feeds back to FBIN to close the loop. Multiple power and ground supplies help reduce the effects of noise on device performance. All ten outputs 1Y0 to 1Y9 are enabled and disabled low by the active-high G signal. The PLL can be bypassed for test purposes by pulling AVDD to ground. Figure 2: Pin Configuration G AVDD 1Y0 3 22 VDD 1Y1 4 21 1Y9 20 1Y8 19 GND 18 GND 5 6 1Y0 GND 7 1Y3 8 17 1Y7 1Y4 9 16 1Y6 VDD 10 15 1Y5 G 11 14 VDD FBOUT 12 13 FBIN 1Y4 CLK 1Y5 Table 1: Function Table AGND 1Y6 PLL 1Y9 FBOUT GND PLL Bypass 1Y8 Zero-Delay 1Y7 FS612510 VDD 1Y2 1Y3 PLL CLK 23 GND 1Y2 FBIN 24 2 VDD 1Y1 AVDD 1 FS612510 Figure 1: Block Diagram AGND INPUT OUTPUT AVDD G CLK 1Y0-1Y9 FBOUT H L L L L H L H L H H H L L L H H H H H L L L L L L L H L H L H L L L L H H H H American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ISO9001 QS9000 FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME 3 DO 1Y0 Clock output 4 DO 1Y1 Clock output 5 DO 1Y2 Clock output 8 DO 1Y3 Clock output 9 DO 1Y4 Clock output 15 DO 1Y5 Clock output 16 DO 1Y6 Clock output 17 DO 1Y7 Clock output 20 DO 1Y8 Clock output 21 DO 1Y9 23 DESCRIPTION Enabled by G Clock output P AVDD Power Supply / Test mode enable. This pin provides the power supply to the internal PLL. When the pin is pulled low, the PLL is bypassed and the output clocks directly follow the input clock PLL supply ground 1 P AGND 24 DI CLK Reference clock input (Note: -02 version has a pull-down on this pin) 13 DI FBIN Feedback clock input; must be connected to FBOUT to complete the loop 12 DO FBOUT 11 DI G 6, 7, 18, 19 P GND Ground for all clock outputs 2, 10, 14, 22 P VDD Power supply for all clock outputs ISO9001 QS9000 Feedback output clock Output enable stops all clocks (1Y0 - 1Y9) in a low state when this pin is low 2 FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC 3.3 3.0 Device Operation The FS612510-02 version provides an auto power-down feature that shuts off the PLL, drives all outputs low, and places the device into a low current state if the reference clock stops. The power-down circuit is level sensitive, and detects either a DC high or low on the CLK input. The FS612510 is a zero-delay buffer intended for use on buffered PC133 SDRAM DIMMs. The FS612510 precisely aligns the frequency and phase of the output clocks to the input CLK by use of an on-chip phase-lock loop (PLL). The PLL generates up to 10 lowskew, low-jitter copies of the CLK, with the outputs adjusted for 50% duty cycle. The FBOUT clock must be hardwired to the FBIN pin to complete the loop. The PLL actively adjusts the output clocks so that there is no phase error between the reference clock (CLK) and the feedback clock (FBIN). Since the device uses a PLL to lock the output clocks to the input clock, there is a power-up stabilization time that is required for the PLL to achieve phase lock. Note that all inputs and outputs use LVCMOS signal levels. 3.1 4.0 A downstream PLL, contained in a clock buffer IC such as this one, must carefully track the modulated input reference clock. A measure of how closely the downstream PLL follows the modulated clock is called the tracking skew. To ensure a tight tracking skew, the loop bandwidth of a downstream PLL is increased and the loop phase angle is reduced over that of typical PLL-based clock generators. PLL Bypass The type of modulation profile used impacts tracking skew. The maximum frequency change occurs at the profile limits where the modulation changes the slew rate polarity. To track the sudden reversal in clock frequency, the downstream PLL must have a large loop bandwidth. The ability of the downstream PLL to catch up to the modulating clock is determined by the loop transfer function phase angle. Output Enable/Disable All ten outputs are enabled or disabled as a group by the G enable signal. A logic-high on G input enables all the clock outputs to swing in phase with the reference clock. A logic-low on G forces all of the clock outputs to a logic-low state. The function table Table 1 shows the effect of the G enable signal on the clock outputs. ISO9001 QS9000 Tracking Skew PLL-based buffer ICs may be required to follow a spreadspectrum modulated reference clock for frequencies greater than 66MHz. Spread spectrum modulation limits peak EMI emissions by intentionally introducing jitter onto a clock signal, effectively spreading the peak energy over a range of frequencies. When the AVDD pin is pulled low, the reference clock signal bypasses the PLL and is muxed directly through to the outputs. The PLL is powered down, and device acts a fanout buffer. Note that if AVDD is re-established, the PLL requires a power-up and stabilization time to lock to the input clock. 3.2 Power-Down The spread-spectrum reference clock should be either a triangle-wave or a non-linear (Lexmark) modulation profile, with a modulation frequency of 50kHz or less. 3 FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC 5.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. MAX. UNITS AVDD VSS - 0.5 7 V VDD VSS - 0.5 7 V Input Voltage, dc VI VSS - 0.5 VDD+0.5 V Output Voltage, dc VO VSS - 0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 125 C Supply Voltage, dc, Clock Buffers (VSS = ground) Supply Voltage, dc, Core Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 260 C 2 kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 4: Operating Conditions PARAMETER SYMBOL Supply Voltage, Core and Outputs VDD Ambient Operating Temperature Range TA Output Load Capacitance CL Input Frequency fCLK CONDITIONS/DESCRIPTION 3.3V 10% MIN. TYP. MAX. 3.0 3.3 3.6 V 70 C 15 pF MHz 0 UNITS CLK 50 140 Input Duty Cycle CLK 40 60 % Input Rise/Fall Time CLK 3 ns ISO9001 QS9000 4 FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC Table 5: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Supply Current, Dynamic fCLK = 133.33MHz; VDD = 3.3V Supply Current, Static IDDL 135 mA 3 mA Outputs low; VDD = 3.3V Output Enable Input (G) High-Level Input Voltage VIH 2.0 VDD+0.3 Low-Level Input Voltage VIL VSS-0.3 0.8 V II -5 5 A Input Leakage Current V Clock Inputs (CLK, FBIN) High-Level Input Voltage VIH 2.0 VDD+0.3 V Low-Level Input Voltage VIL VSS-0.3 0.8 V -5 5 Input Leakage Current II Input Loading Capacitance * CL(in) -01 version -02 version has a pull-down on CLK 28 As seen by an external clock driver 4 A pF Clock Outputs (1Y0:9, FBOUT) High-Level Output Source Current IOH Low-Level Output Sink Current IOL VDD = 2.9V, VO = 2.0V -18 -12 VDD = 3.7V, VO = 2.0V -35 -12 VDD = 2.9V, VO = 0.8V 12 16 VDD = 3.7V, VO = 0.8V 12 17 mA mA Output Impedance zO Tristate Output Current IOZ 33 Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. -60 mA Short Circuit Sink Current * IOSL VO = 3.3V; shorted for 30s, max. 90 mA -10 10 Table 6: Clock Output Drive (1Y0:4, 2Y0:3, FBOUT) 0.1 V 0.2 V 0.4 V 0.6 V 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V 1.8 V 2.0 V 2.2 V 2.4 V 2.6 V 2.8 V 3.0 V 3.3 V ISO9001 QS9000 Low Drive Current (mA) -47 -45 -43 -40 -38 -35 -32 -29 -26 -22 -18 -15 -10 -6 -2 0 -59 -58 -56 -55 -52 -50 -47 -45 -41 -38 -35 -31 -28 -24 -20 -15 -9 High Drive Current (mA) 2 4 8 12 16 20 24 27 31 34 38 41 43 45 48 49 60 2 4 9 13 17 21 25 29 33 36 40 43 46 49 51 53 56 45 30 Output Current (mA) Voltage 15 0 0 0.5 1 1.5 2 2.5 3 3.5 -15 -30 -45 30 -60 Output Voltage (V) 5 50 90 A FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC 3.6 V ISO9001 QS9000 -2 59 6 FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC Table 7: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION tsk(o) MIN. TYP. MAX. UNITS Measured on the rising edge at 1.65V; CL = 15pF 150 ps Measured using a -0.5% 31.5kHz spread spectrum reference clock at 133.33MHz 150 ps 3 ms Overall Skew, Output to Output * Skew, Tracking * Static Phase Error * From rising edge on CLK to rising edge on FBIN Clock Stabilization Time * Time required for the PLL to achieve phase lock -120 ps Loop Bandwidth * For calculation of Tracking Skew 1.2 MHz Phase Angle * For calculation of Tracking Skew -0.031 Clock Outputs (1Y0:9, FBOUT) Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.65V 45 55 % -75 +75 ps Jitter, Cycle-Cycle * tj(CC) Adjacent cycles at 1.65V Jitter, Period (peak-peak) * tj(P) From rising edge to next rising edge at 1.65V Rise Time * tr VO = 0.4V to 2.0V; CL = 15pF 1.2 Fall Time * tf VO = 2.0V to 0.4V; CL = 15pF 1.4 ns ns Enable Delay * tDLH via G 1 10 ns Disable Delay * tDHL via G 1 10 ns Figure 3: Clock Skew Measurement Any output Figure 4: Phase Error Measurement CLK 50% VDD phase error clock skew (tsk(o)) Any output FBIN 50% VDD Figure 5: Timing Measurement Points tr tf 50% VDD 50% VDD Figure 6: Output Enable Measurement VDD 3.3V Output Enable 2.4V 50% 50% VSS 50% VDD 0.4V 50% Output dt VOL 10% tDLZ 90% tDZL VOH 50% tDHZ ISO9001 QS9000 7 tDHZ FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC 6.0 Package Information Table 8: 24-pin TSSOP Package Dimensions DIMENSIONS INCHES MIN. 24 MILLIMETERS MAX. MIN. MAX. A - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 A2 0.0315 0.0413 0.80 1.05 b 0.0075 0.0118 0.19 0.30 C 0.0035 0.0079 0.09 0.20 D 0.303 0.311 7.70 7.90 E1 0.169 0.177 4.30 4.50 E 0.252 6.40 BSC e 0.0256 0.65 BSC L 0.0177 0.0295 0.45 0.75 S 0.0079 - 0.20 - 1 0 8 0 8 2 12 REF 12 REF 3 12 REF 12 REF E1 E AMERICAN MICROSYSTEMS, INC. 1 b e 2 S A2 A D c 3 L A1 BASE PLANE 1 SEATING PLANE Table 9: 24-pin TSSOP Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS 84 C/W nH Thermal Impedance, Junction to Free-Air JA Air flow = 0 m/s Lead Inductance, Self L11 Longest lead 1.7 L12 Longest lead to any 1st adjacent lead 0.6 L13 Longest lead to any 2nd adjacent lead 0.24 C11 Longest lead to VSS 0.3 C12 Longest lead to any 1st adjacent lead 0.1 C13 Longest lead to any 2nd adjacent lead 0.007 Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual ISO9001 QS9000 8 nH pF pF FS612510-01/-02 1:10 Zero-Delay Clock Buffer IC 7.0 Ordering Information Table 10: Device Ordering Codes DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION FS612510-01 12055-102 24-pin TSSOP (Thin Shrink Small Outline Package) 0C to 70C (Commercial) Tape and Reel FS612510-02 12055-103 24-pin TSSOP (Thin Shrink Small Outline Package) 0C to 70C (Commercial) Tape and Reel Copyright (c) 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 QS9000 9