ATT1736AM20I - Agere Systems, Inc.

Data Sheet

January 1998

ATT1700A Series Serial ROM

Features

■

32K, 64K, and 128K x 1 Serial ROMs f or conﬁgura-

tion of ATT3000 and

ORCA

Series FPGAs

■

Pinout and functional replacement of

Xilinx

XC1700

series

■

Simple four-wire interface

■

Cascadable to support large FPGAs, multiple

conﬁgurations, and multiple FPGAs

■

8-pin, plastic DIP; 8-pin SONB; and 20-pin PLCC

packages

■

Programming support from leading programmer

manufacturers

■

Programmable polarity on RESET/OE pin

■

Full static operation

■

Standby current—100

A maximum

■

Operating current—10 mA maximum

■

10 MHz maximum clock rate

■

Electrostatic discharge protection: >4000 V

■

Temperature ranges:

Commercial: 0

C to 70

Industrial: –40

C to +85

Xilinx

and

XC1700

are registered trademarks of Xilinx, Inc.

Intel

is a registered trademark of Intel Corporation.

Motorola

is a registered trademark of Motorola, Inc.

Tektronix

is a registered trademark of Tektronix, Inc.

Description

The ATT1700A Series Serial ROM family provides

easy-to-use, cost-effective, nonvolatile memory for

conﬁguring ATT3000 and

ORCA

Series FPGAs. The

ATT1700A Series consists of one-time programma-

ble (OTP) devices. The ATT1700A devices are avail-

able in 8-pin, plastic DIP, 8-pin SONB, and 20-pin

PLCC packages.

The ATT1700A Series is a pinout and functional

replacement for the ATT1700 and

Xilinx XC1700

families (see Figure 1) and can be programmed by

most commercially available programmers. FPGA

development tools , such as

ORCA

Foundry, generate

conﬁguration ﬁles in

Intel

Motorola

, and

Tektronix

formats for use in programmers.

The ATT1700A Series is most often used when the

ATT3000 Series and

ORCA

Series FPGAs are con-

ﬁgured in the master serial mode. The primary

advantage of this conﬁguration mode is that it pro-

vides a simple, f our-wire interface betw een the FPGA

and serial ROM (see Figure 2).

Figure 1. Block Diagram

5-3977

ADDRESS

POINTER

RST

CK TC

MEMORY

ARRAY

SHIFT REGISTER OE

POLARITY

SELECT CEO

DATA

RESET/OE

CLOCK

Data Sheet

ATT1700A Series Serial ROM January 1998

2Lucent Technologies Inc.

Pin Information

Table 1. Pin Descriptions

Symbol Pin Numbers I/O Function

8-Pin 20-Pin

DATA 1 2 O DATA output from the serial ROM to FPGA synchronous with the

CLOCK input. DATA is 3-stated when either

or OE is inactive.

CLOCK 2 4 I CLOCK is an input used to increment the address pointer which strobes

data out of the DATA pin.

RESET/OE 3 6 I RESET/OUTPUT ENABLE is a dual-function pin used to reset and

enable the ATT1700A Series device. An active level on both

and OE

inputs enables data out of the DATA pin. An active level on RESET

resets the address pointer. When the serial ROM is programmed, the

polarity of RESET/OE is set either with RESET active-high and

active-low or with

RESET

active-low and OE active-high.

48I

CHIP ENABLE

is an input used to select the device. An active level on

both

and OE enables data out of the device. A high on

disables

the address pointer and forces the serial ROM into a low-power mode.

5 10 I Ground.

CEO

614O

CHIP ENABLE OUT

is asserted low on the clock cycle f ollowing the last bit

read from the device.

CEO

remains low as long as

and OE are both

active.

717IV

is an input used by programmers when programming the serial

ROM. The programming operations, voltages, and timing are deﬁned

later in this data sheet. For read operations, V

must be tied directly to

8 20 I Power supply.

Lucent Technologies Inc. 3

Data Sheet

January 1998 ATT1700A Series Serial ROM

FPGA Conﬁguration

The functionality of Lucent Technologies Microelectron-

ics Group’s FPGAs is determined by the contents of

the FPGA’s conﬁguration memory. The conﬁguration

memory is loaded either automatically at powerup or

with a conﬁguration command b y pulsing the

PRGM

low. The FPGAs can be programmed in a variety of

modes, and the mode used is determined by the inputs

into the FPGA’s M[2:0] pins. The conﬁguration modes

allow the FPGA to act as a master or a slave and also

allow conﬁguration data to be tr ansmitted either serially

or in parallel. The ATT1700A Series ROMs are targeted

for use when the FPGA is conﬁgured serially, primarily

in the master serial mode. Tab le 2 pro vides the conﬁgu-

ration memory requirements for Lucent’s FPGAs.

FPGA Master Serial Conﬁguration Mode

The master serial mode provides a simple interface

between the FPGA and the serial ROM. Four interface

lines, D ATA, CLOCK,

, and RESET/OE, are required

to conﬁgure the FPGA. Upon powerup or a conﬁgure

command (

PRGM

ORCA

PROG

in ATT3000), when

the FPGA’s M[2:0] pins are low, the FPGA conﬁgures

using the master serial mode. The conﬁgur ation data is

transmitted serially into the FPGA’s DIN pin from the

serial ROM’s DATA pin. To synchronize the data, the

FPGA’s CCLK output is routed into the serial ROM’s

CLOCK input.

Because the FPGA DIN signal may be unused after

FPGA conﬁguration, it is necessary to avoid an unre-

solved state once the serial R OM has ﬁnished sending

conﬁguration data. If this pin is used only for the conﬁg-

uration process, it should be conﬁgured so that it does

not ﬂoat. This can be accomplished by programming it

as an output during normal operation or by program-

ming it as an input with an internal pull-up resistor

enabled. CCLK must also be pulled up follo wing conﬁg-

uration.

Signal contention on the DIN pin must be a voided if it is

to be used for a user I/O signal after conﬁguration. To

avoid contention, the FPGA DONE signal may be pro-

grammed (selected in

ORCA

Foundry) to go high prior

to the FPGA I/O signals being enabled. An alternative

is to use the FPGA’s

LDC

to drive the serial ROM’s

pin, rather than DONE, and conﬁgure

LDC

to output a

constant logic 1 high-voltage level after conﬁguration.

Control of the serial ROM’s

and RESET/OE pins

varies, depending upon the FPGA series being used,

and is described in subsequent sections.

The FPGA serial ROM interface used also depends

upon the system and conﬁguration requirements. The

following are some typical system requirements:

■

Conﬁguring an FPGA at powerup

■

Conﬁguring an FPGA in response to a conﬁgure

command

■

One serial ROM conﬁgures an FPGA with multiple

conﬁguration programs

■

Cascaded serial ROMs conﬁgure daisy-chained

FPGAs

In addition to the clock and data lines, the FPGA pins

used in conﬁguration/start-up are

RESET

, DONE,

PRGM

LDC

, HDC, and

INIT

. Normally, only a small sub-

set of these pins is used to control the serial ROM’s

and RESET/OE pins. In some applications, the

RESET/OE signal is generated b y the system host, not

the FPGA. For example, the host may generate a sys-

tem reset, allowing the FPGA and the serial ROM to be

reset synchronously.

Table 2. Conﬁguration Requirements

Lucent FPGA Memory

Requirements

ATT3020 14,819

ATT3030 22,216

ATT3042 30,824

ATT3064 46,104

ATT3090 64,200

ATT1C03 57,144

ATT1C05 76,376

ATT1C07 98,296

ATT1C09 122,904

ATT2C04/OR2C04A/OR2T04A 65,424

ATT2C06/OR2C06A/OR2T06A 91,024

ATT2C08/OR2C08A/OR2T08A 115,600

ATT2C10/OR2C10A/OR2T10A 148,944

ATT2C12/OR2C12A/OR2T12A 179,856

ATT2C15/OR2C15A/OR2T15A 220,944

ATT2C26/OR2C26A/OR2T26A 307,024

ATT2C40/OR2C40A/OR2T40A 474,176

OR3C55/OR3T55 387,048

OR3C80/OR3T80 562,664

OR3T125 872,488

Data Sheet

ATT1700A Series Serial ROM January 1998

4 Lucent Technologies Inc.

FPGA Conﬁguration

(continued)

ATT3000 Series/

ORCA

Series Differences

While both the ATT3000 and

ORCA

Series have

RESET

LDC

, HDC,

INIT

, DIN, CCLK, and DOUT pins,

there are some conﬁguration diff erences in the FPGAs.

The ATT3000 Series DONE/

PROG

pin is a shared

open-drain I/O, while the

ORCA

Series has discrete

DONE and

PRGM

pins. When the system generates a

conﬁgure command to the ATT3000, the DONE/

PROG

pin is held low throughout the conﬁguration cycle. For

the

ORCA

Series, the

PRGM

pin is pulsed low and

returned high to initiate conﬁguration. A second differ-

ence is the internal pull-ups on the mode select pins.

For the ATT3000 Series, only M2 has an internal pull-

up during conﬁguration, but for the

ORCA

Series,

M[3:0] have pull-ups.

Conﬁguring the FPGA at Powerup

The ATT1700A Series can conﬁgure FPGAs at

powerup. There is level-sensitive, power-on-reset

circuitry included in the device that resets the address

pointer during powerup. The ATT3000 and

ORCA

FPGAs enable the serial ROM using either the DONE

(or

LDC

) and

INIT

pins. If these signals are low at pow-

erup and they are connected to the

and RESET/

pins on the serial ROM, the FPGA is programmed from

the serial ROM (see Figures 2 and 3). When these

FPGA signals go high at the end of conﬁguration, the

serial ROM is disabled.

Figure 2.

ORCA

Master Serial Conﬁguration

Conﬁguring the

ORCA

Series FPGA with a

Conﬁgure Command

The FPGA needs to enable the serial ROM’s

RESET/OE and

inputs. The polarity of the

RESET/OE input is programmable in the ATT1700A

Series. In the method shown in Figure 2, the system

generates an active-low conﬁgure pulse to the FPGA’s

PRGM

pin. This conﬁguration pulse causes the FPGA

to drive its

INIT

pin low, which forces a RESET on the

serial ROM RESET/OE pin (with the RESET/OE pin

programmed for active-low RESET and active-high

OE). The FPGA’s DONE pin is routed to the serial

ROM’s

pin. At the end of conﬁguration, DONE

returns high, disabling the serial ROM. Alternatively,

the

LDC

pin can be used instead of the DONE pin to

enable the serial ROM.

Conﬁguring the ATT3000 Series FPGA with a

Conﬁgure Command

In the method illustrated in Figure 3, the system gener-

ates an active-low conﬁgure pulse on the FPGA’s

DONE/

PROG

pin. The system then releases the open-

drain DONE/

PROG

pin, allowing the FPGA to control it

and drive it low during conﬁguration. DONE/

PROG

generally connected to both the CE and RESET/OE

pins of the serial ROM, which has been programmed

so that RESET is active-high and OE is active-low. At

the end of conﬁguration, the DONE/PROG pin returns

high, disabling and resetting the serial ROM. The LDC

pin may be used instead of the DONE/PROG pin to

enable the serial ROM, as shown.

5-4456.1

ATT1700A

DIN

ORCA

SERIES

FPGA

CCLK

DOUT

TO DAISY-

CHAINED

DEVICES

DATA

CLK

CEO

ATT1700A

DATA

CLK

RESET/OE

CEO

TO MORE

SERIAL ROMs

AS NEEDED

DONE

INIT

PROGRAM

RESET/OE

PRGM

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 5

FPGA Conﬁguration (continued)

Figure 3. ATT3000 Master Serial Conﬁguration

5-3112

DURING CONFIGURATION

THE 5 kΩ M2 PULL-DOWN

RESISTOR OVERCOMES THE

INTERNAL PULL-UP,

BUT IT ALLOWS M2 TO

BE USER I/O.

M0 M1 PWRDWN

+5 V

DOUT

HDC

LDC

INIT

OTHER

I/O PINS

ATT3000

SERIES

FPGA

GENERAL-

PURPOSE

USER I/O

PINS

DONE/PROG

PROGRAM

LDC

CCLK

DIN

CLK

DATA

RESET/OE

ATT1700A

CEO

(HIGH RESETS THE ADDRESS POINTER)

CASCADED

ATT1700A

MEMORY

OPTIONAL

IDENTICAL SLAVE

FPGAs CONFIGURED

THE SAME

CLK

DATA

RESET/OE

Programming the FPGA with the Address Pointer

Unchanged Upon Completion

In the two interfaces previously discussed, the serial

ROM is reset at the completion of conﬁgur ation. This is

typically the case when one or more serial ROMs are

used to conﬁgure one or more FPGAs with one conﬁg-

uration program. In applications in which a serial ROM

is used to conﬁgure an FPGA with multiple conﬁgura-

tion programs , the address pointer should not be reset.

This allows the ne xt conﬁguration program to be loaded

at the next internal ROM address.

When multiple FPGA conﬁgurations are stored in a

serial ROM, the OE pin of the serial ROM should be

tied low. Upon powerup, the internal address pointer is

reset and conﬁguration begins with the ﬁrst set of con-

ﬁguration data stored in memory. Since the OE pin is

held low, the address pointer is left unchanged after

conﬁguration is complete. To reprogram the FPGA with

another program, the DONE/PROG or PRGM pin is

pulled low, and conﬁguration begins at the last value of

the address pointer.

Data Sheet

ATT1700A Series Serial ROM January 1998

6 Lucent Technologies Inc.

FPGA Conﬁguration (continued)

Cascading Serial ROMs

Figure 2 and Figure 3 also illustrate the cascading of

serial ROMs. This is done to provide additional memory

f or large FPGAs and/or for conﬁguring multiple FPGAs

in a daisy chain. The serial ROMs are cascaded with

the next ROM’s CE input connected to the CEO output

of the previous serial ROM. All of the cascaded serial

ROM’s DATA lines are routed to the FPGA’s DIN input,

and the FPGA’s CCLK output is routed in parallel to all

of the serial ROMs’ CLOCK inputs.

After the last bit from the ﬁrst serial ROM is read, the

ﬁrst serial ROM asserts CEO low and disab les its DATA

output. The next serial ROM recognizes the low on its

CE input and enables its DATA output. The inactive CE

into all serial ROMs causes the inactive DATA pins to

be 3-stated after conﬁguration is ﬁnished.

The ATT3000 DONE/PROG signal and the

ORCA

DONE signal are open-drain outputs with optional inter-

nal pull-ups and can be used to control the output

enable of multiple serial ROMs. Extremely large,

cascaded serial memories ma y require additional logic

if the DONE/PROG or DONE signals are too slow to

activate many serial ROMs.

Standby Mode

The ATT1700A Series enters a low-power standby

mode when CE is high. In standby mode, the serial

ROM consumes less than 100 µA of current. The DATA

pin remains in the high-impedance state regardless of

the state of the RESET/OE input.

RESET/OE Polarity

The ATT1700A Series allows the user to select the

polarity of the dual-function RESET/OE pin. The PROM

programmer software is used to program the desired

polarity. The method used to select a polarity depends

on the PROM programmer user interface.

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 7

Absolute Maximum Ratings

Stresses in e xcess of the absolute maxim um ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Electrical Characteristics

Parameter Symbol Min Max Unit

Supply Voltage Relative to GND VDD –0.6 6.6 V

Programming Voltage Relative to GND VPP –0.6 14.0 V

Input Voltage with Respect to GND VIN –0.6 VDD + 0.6 V

Voltage Applied to 3-state Output VTS –0.6 VDD + 0.6 V

Ambient Storage Temperature Tstg –65 150 °C

Maximum Soldering Temperature TSOL — 300 °C

Maximum Junction Temperature TJ— 125 °C

Table 3. dc Electrical Characteristics

Commercial: 0 °C ≤ T A ≤ 70 °C, VDD = 5.0 V ± 5%; Industrial: –40 °C ≤ T A ≤ +85 °C, VDD = 5.0 V ± 10%.

Parameter Symbol Conditions Min Max Unit

High-level Input Voltage VIH — 2.0 VDD V

Low-level Input Voltage VIL — –0.3 0.8 V

High-level Output Voltage VOH

VOH VDD = 3.0 V, IOH = –4.0 mA

VDD = 4.5 V, IOH = –4.0 mA 2.40

3.86 —

—V

Low-level Output Voltage VOL VDD = 5.5 V, IOL = 4.0 mA — 0.32 V

Supply Voltage Relative to VSS:

Commercial

Industrial —

——

—4.75

4.50 5.25

5.50 V

Standby Supply Current IDDSB VIN = VDD = 5.5 V

VIN = VDD = 3.6 V —

—100

50 µA

µA

Operating Supply Current IDD VDD = 5.5 V, clock = 10 MHz

VDD = 3.6 V, clock = 2.5 MHz —

—10

2mA

Input Leakage Current IIL VDD = 5.5 V,

VIN = VDD and 0 V –10 10 µA

Output Leakage Current IIL VDD = 5.5 V,

VIN = VDD and 0 V –10 10 µA

Pin Capacitance CIN VCC = 5 V, TA = 25 °C,

FCLK = 1 MHz —10pF

Data Sheet

ATT1700A Series Serial ROM January 1998

8Lucent Technologies Inc.

Electrical Characteristics (continued)

Figure 4. Read Characteristics

Table 4. ac Characteristics During Read

Commercial: 0 °C ≤ T A ≤ 70 °C, VDD = 5.0 V ± 5%; Industrial: –40 °C ≤ T A ≤ +85 °C, VDD = 5.0 V ± 10%.

Parameter Symbol Test

Conditions

Limits

3.0 V ≤ VDD ≤ 6.0 V Limits

4.5 V ≤ VDD ≤ 6.0 V Unit

Min Max Min Max

OE to Data Delay TOE — —45—45ns

CE to Data Delay TCE — —60—50ns

CLOCK to DATA Delay TCAC — — 200 — 60 ns

DATA Hold from CE, OE, or CLOCK TOH — 0—0—ns

CE or OE to DATA Float Delay TDF — —50—50ns

CLOCK Frequency TCLK — — 2.5 — 10 MHz

CLOCK Low Time TCL — 100 — 25 — ns

CLOCK High Time TCH — 100 — 25 — ns

CE Setup Time to CLOCK

(Guarantees correct counting.) TSCE — 40—25—ns

CE Hold Time from CLOCK

(Guarantees correct counting.) THCE — 0—0—ns

OE High Time

(Guarantees counters are reset.) THOE CE high

or low 100 — 20 — ns

5-3870

CAC

SCE

HCE

SCE

HOE

RESET/OE

CLOCK

DATA

CLK

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 9

Electrical Characteristics (continued)

Figure 5. Read Characteristics at End of Array

Table 5. ac Characteristics at End of Read

Commercial: 0 °C ≤ T A ≤ 70 °C, VDD = 5.0 V ± 5%; Industrial: –40 °C ≤ T A ≤ +85 °C, VDD = 5.0 V ± 10%.

Parameter Symbol Limits

3.0 V ≤ VDD ≤ 6.0 V Limits

4.5 V ≤ VDD ≤ 6.0 V Unit

Min Max Min Max

CLOCK to DATA Disable Delay TCDF —50—50ns

CLOCK to CEO Delay TOCK —65—40ns

CE to CEO Delay TOCE —45—40ns

OE to CEO Delay TOOE —40—40ns

5-3871

TOOE

TCDF

CLOCK

DATA

CEO

RESET/OE

FIRST BITLAST BIT

TOCE

TOCK

Data Sheet

ATT1700A Series Serial ROM January 1998

10 Lucent Technologies Inc.

Electrical Characteristics (continued)

Note: V erify CEO has gone LOW one clock after last bit.

Figure 6. ATT1700A Programming

5-3869

Start

Check Device ID

Device Power Off

Device Power On

1. V

= V

CCP

= V

PP2

CE = OE = V

2. V

= V

PP1

for 2 CLK Rising Edges

3. V

= V

PP2

for 1 CLK Rising Edge

Enter Programming Mode

32-bit data word to be

programmed =

FFFFFFFFhex

CE low to clear

EPROM internal data

latches

Yes

Load 32-bit word to be

programmed

Pulse V

to V

PP1

(13 V) for T

PGM

(500 µs)

Last Word?

Verify

All Data Bits (Read Mode)

= V

CCL

and

= V

CCH

(see note)

Exit Programming Mode

Device Power Off

Device Power On

Yes

Device Passed

Pass

1st Pass? Fail

Device Failed

Yes

Increment Address

Counter

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 11

Electrical Characteristics (continued)

* No overshoot is permitted on this signal. VPP must not be allowed to exceed 14 V.

Table 6. dc Programming Speciﬁcations

Commercial: 0 °C ≤ T A ≤ 70 °C, VDD = 5.0 V ± 5%; Industrial: –40 °C ≤ T A ≤ +85 °C, VDD = 5.0 V ± 10%.

Parameter Symbol Min Max Unit

Supply Voltage During Programming VCCP 5.0 6.0 V

Low-level Input Voltage VIL 0.0 0.5 V

High-level Input Voltage VIH 2.4 VCC V

Low-level Output Voltage VOL — 0.4 V

High-level Output Voltage VOH 3.7 — V

Programming Voltage* VPP1 12.5 13.5 V

Programming Mode Access Voltage VPP2 VCCP VCCP + 1 V

Supply Current in Programming Mode IPPP — 100 mA

Input or Output Leakage Current IL–10 10 µA

First-pass, Low-level Supply Voltage for Final Veriﬁcation VDDL 2.8 3.0 V

Second-pass, High-level Supply Voltage for Final Veriﬁcation VDDH 6.0 8.2 V

Data Sheet

ATT1700A Series Serial ROM January 1998

12 Lucent Technologies Inc.

Electrical Characteristics (continued)

* This parameter is periodically sampled and is not 100% tested.

Note:While in programming mode, CE should only be changed while OE is HIGH and has been HIGH for 200 ns, and OE should only be

changed while CE is HIGH and has been HIGH for 200 ns.

Table 7. ac Programming Speciﬁcations

Commercial: 0 °C ≤ T A ≤ 70 °C, VDD = 5.0 V ± 5%; Industrial: –40 °C ≤ T A ≤ +85 °C, VDD = 5.0 V ± 10%.

Parameter Test Conditions Symbol Min Max Unit

10% to 90% Rise Time of VPP *TRPP 1—µs

90% to 10% Fall Time of VPP *TFPP 1—µs

VPP Programming Pulse Width — TPGM 0.5 1.05 ms

VPP Setup to Clock for Entering Programming

Mode *TSVC 100 — ns

CE Setup to Clock for Entering Programming Mode * T SVCE 100 — ns

OE Setup to Clock for Entering Programming

Mode *TSVOE 100 — ns

VPP Hold from Clock for Entering Programming

Mode *THVC 300 — ns

Data Setup to Clock for Programming — TSDP 50 — ns

Data Hold from Clock for Programming — THDP 0—ns

CE Low Time to Clear Data Latches — TLCE 100 — ns

CE Setup to Clock for Programming/Verifying — TSCC 100 — ns

OE Setup to Clock for Incrementing Address

Counter —TSIC 100 — ns

OE Hold from Clock for Incrementing Address

Counter —THIC 0—ns

OE Hold from VPP *THOV 200 — ns

Clock to Data Valid — TPCAC — 400 ns

Data Hold from Clock — TPOH 0—ns

CE Low to Data Valid — TPCE — 250 ns

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 13

Electrical Characteristics (continued)

Figure 7. Entering and Exiting Programming Mode

* The CEO pin is high impedance when VPP = VPP1.

† 32 clocks.

Figure 8. Programming Cycle Overview

SVCE

CLOCK

DATA

RESET/OE

PP2

CCP

PP1

RPP

SVC

FPP

HVC

SVC

SVOE

ENTER PROGRAMMING MODE

PP2

CE V

CCP

1 ms

RESET/OE V

CLOCK V

EXIT PROGRAMMING MODE

5-3864

5-3865

CLOCK

RESET/OE

PP1

= V

PP2

ENTER

PROGRAMMING

MODE

= V

CCP

CEO

500 µs

PROGRAMMING

MODE

500 µs

PROGRAMMING

MODE

500 µs

PROGRAMMING

MODE

500 µs

PROGRAMMING

MODE

†

LOAD

WORD 5

†

LOAD

WORD 4

†

LOAD

WORD 3

†

LOAD

WORD 2

†

LOAD

WORD 1

2 CLKS

CE LOW TO CLEAR

DATA LATCHES

CLOCK INCREMENTS

ADDRESS COUNTER

***** HIGH IF RESET/OE CONFIGURED

LOW IF RESET/OE CONFIGURED

Data Sheet

ATT1700A Series Serial ROM January 1998

14 Lucent Technologies Inc.

Electrical Characteristics (continued)

* The programmer must ﬂoat the data pin while CE is low to avoid bus contention.

Figure 9. Details of Programming Cycle

Figure 10. Read Manufacturer and Device ID Overview

5-3866

CLOCK

DATA

CLEAR PROM

INTERNAL DATA

LATCHES

LOAD PROM

INTERNAL

DATA LATCHES

FPP

RPP

HIC

HOV

INCREMENT

WORD COUNTER

PROGRAM

PULSE

32 LAST

BIT

SCC

SDP

HDP

RESET/OE

SIC

PGM

LCE

5-3867

CLOCK

7 CLOCKS TO READ

MANUFACTURER ID 8 CLOCKS TO

READ DEVICE ID

MICROCHIP ID

DEVICE

LSB FIRST

FLOATS

29 HEX ATT17128A = 72 HEX

ATT1765A = 71 HEX

ATT1736A = 70 HEX

CEO

DATA

RESET/OE

LOW IF RESET/OE CONFIGURED

HIGH IF RESET/OE CONFIGURED

= V

CCP

PP1

= V

PP2

ENTER

PROGRAMMING

MODE

CLOCK PAST USER MEMORY ARRAY TO ID LOCATION ATT17128A NEEDS 4104 CLOCKS

ATT1736A/65A NEEDS 2056 CLOCKS

()

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 15

Electrical Characteristics (continued)

Figure 11. Details of Read Manufacturer and Device ID

CLOCK

DATA

RESET/OE

PCAC

PCH

0 0 1 0 1 0 0 LSB

DEVICE IDVENDOR ID = 29 HEX

217654321

LSB = 1

PCE

5-3868

Data Sheet

ATT1700A Series Serial ROM January 1998

16 Lucent Technologies Inc.

Outline Diagrams

8-Pin, Plastic DIP

Controlling dimensions are in inches.

5-2641

0.310

MAX

0.400

MAX

0.400 MAX

0.160

MAX

0.100 TYP 0.023 MAX

0.155

MAX

0.060

MAX

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 17

Outline Diagrams (continued)

8-Pin SONB

Controlling dimensions are in inches.

5-3979

0.050 TYP 0.020 MAX

0.068

MAX

0.060 MAX

0.200 MAX

0.158 MAX

0.240 ± 0.003

DETAIL A

0.008

REF

0.025 MAX

DETAIL A

Data Sheet

ATT1700A Series Serial ROM January 1998

18 Lucent Technologies Inc.

Outline Diagrams (continued)

20-Pin PLCC

Controlling dimensions are in inches.

5-2035

0.050 TYP.

0.146/

0.156

DETAIL A 0.026/0.032

0.013/0.021

0.385/0.395 SQ.

913

0.350/0.355

0.020 MIN

DETAIL A

Data Sheet

January 1998 ATT1700A Series Serial ROM

Lucent Technologies Inc. 19

Ordering Information

ATT1736A; one-time programmable; 8-pin, plastic DIP; industrial temperature

Table 8. Device Type

Device Size

ATT1736A 36,288

ATT1765A 65,536

ATT17128A 131,072

Table 9. Programmability

Designation Programmability

Blank or A One-time Programmable

Table 10. Package Type

Designation Package

P8 8-pin, plastic DIP

G8 8-pin SONB

M20 20-pin PLCC

Table 11. Temperature Range

Designation Type Operating Range

Blank Commercial 0 °C to 70 °C

I Industrial –40 °C to +85 °C

Example: ATT1736A P8 I

DEVICE TYPE

PROGRAMMABILITY PA CKAGE TYPE

TEMPERATURE RANGE

For FPGA technical applications support, please call 1-800-327-9374 or e-mail orcafpga@lucent.com. Outside North America, please call 1-610-712-4331.

For additional information, contact your Microelectronics Group Account Manager or the following:

INTERNET: http://www.lucent.com/orca

E-MAIL: docmaster@micro.lucent.com

U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148

Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell),

FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),

ITALY : (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No

rights under any patent accompany the sale of any such product(s) or information.

ORCA

is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.

Printed in U.S.A.

January 1998

DS98-048FPGA (Replaces DS96-239FPGA)