Data Sheet January 1998 ATT1700A Series Serial ROM Features 32K, 64K, and 128K x 1 Serial ROMs for configuration of ATT3000 and ORCA(R) Series FPGAs Pinout and functional replacement of Xilinx XC1700 1 series Simple four-wire interface Cascadable to support large FPGAs, multiple configurations, and multiple FPGAs 8-pin, plastic DIP; 8-pin SONB; and 20-pin PLCC packages Programming support from leading programmer manufacturers Programmable polarity on RESET/OE pin Full static operation Standby current--100 A maximum Operating current--10 mA maximum 10 MHz maximum clock rate Electrostatic discharge protection: >4000 V Temperature ranges: Commercial: 0 C to 70 C Industrial: -40 C to +85 C Description The ATT1700A Series Serial ROM family provides easy-to-use, cost-effective, nonvolatile memory for configuring ATT3000 and ORCA Series FPGAs. The ATT1700A Series consists of one-time programmable (OTP) devices. The ATT1700A devices are available in 8-pin, plastic DIP, 8-pin SONB, and 20-pin PLCC packages. The ATT1700A Series is a pinout and functional replacement for the ATT1700 and Xilinx XC1700 families (see Figure 1) and can be programmed by most commercially available programmers. FPGA development tools, such as ORCA Foundry, generate configuration files in Intel 2 , Motorola3 , and Tektronix 4 formats for use in programmers. The ATT1700A Series is most often used when the ATT3000 Series and ORCA Series FPGAs are configured in the master serial mode. The primary advantage of this configuration mode is that it provides a simple, four-wire interface between the FPGA and serial ROM (see Figure 2). CE POLARITY SELECT CEO RESET/OE 1. 2. 3. 4. Xilinx and XC1700 are registered trademarks of Xilinx, Inc. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc. Tektronix is a registered trademark of Tektronix, Inc. CLOCK RST ADDRESS POINTER CK TC MEMORY ARRAY OE SHIFT REGISTER DATA 5-3977 Figure 1. Block Diagram Data Sheet January 1998 ATT1700A Series Serial ROM Pin Information Table 1. Pin Descriptions Pin Numbers Symbol I/O Function 8-Pin 20-Pin DATA 1 2 O DATA output from the serial ROM to FPGA synchronous with the CLOCK input. DATA is 3-stated when either CE or OE is inactive. CLOCK 2 4 I RESET/OE 3 6 I CE 4 8 I VSS CEO 5 6 10 14 I O VPP 7 17 I VDD 8 20 I CLOCK is an input used to increment the address pointer which strobes data out of the DATA pin. RESET/OUTPUT ENABLE is a dual-function pin used to reset and enable the ATT1700A Series device. An active level on both CE and OE inputs enables data out of the DATA pin. An active level on RESET resets the address pointer. When the serial ROM is programmed, the polarity of RESET/OE is set either with RESET active-high and OE active-low or with RESET active-low and OE active-high. CHIP ENABLE is an input used to select the device. An active level on both CE and OE enables data out of the device. A high on CE disables the address pointer and forces the serial ROM into a low-power mode. Ground. CHIP ENABLE OUT is asserted low on the clock cycle following the last bit read from the device. CEO remains low as long as CE and OE are both active. VPP is an input used by programmers when programming the serial ROM. The programming operations, voltages, and timing are defined later in this data sheet. For read operations, VPP must be tied directly to VDD. Power supply. 2 Lucent Technologies Inc. Data Sheet January 1998 FPGA Configuration ATT1700A Series Serial ROM Table 2. Configuration Requirements The functionality of Lucent Technologies Microelectronics Group's FPGAs is determined by the contents of the FPGA's configuration memory. The configuration memory is loaded either automatically at powerup or with a configuration command by pulsing the PRGM pin low. The FPGAs can be programmed in a variety of modes, and the mode used is determined by the inputs into the FPGA's M[2:0] pins. The configuration modes allow the FPGA to act as a master or a slave and also allow configuration data to be transmitted either serially or in parallel. The ATT1700A Series ROMs are targeted for use when the FPGA is configured serially, primarily in the master serial mode. Table 2 provides the configuration memory requirements for Lucent's FPGAs. Lucent FPGA ATT3020 ATT3030 ATT3042 ATT3064 ATT3090 ATT1C03 ATT1C05 ATT1C07 ATT1C09 ATT2C04/OR2C04A/OR2T04A ATT2C06/OR2C06A/OR2T06A ATT2C08/OR2C08A/OR2T08A ATT2C10/OR2C10A/OR2T10A ATT2C12/OR2C12A/OR2T12A ATT2C15/OR2C15A/OR2T15A ATT2C26/OR2C26A/OR2T26A ATT2C40/OR2C40A/OR2T40A OR3C55/OR3T55 OR3C80/OR3T80 OR3T125 FPGA Master Serial Configuration Mode The master serial mode provides a simple interface between the FPGA and the serial ROM. Four interface lines, DATA, CLOCK, CE, and RESET/OE, are required to configure the FPGA. Upon powerup or a configure command (PRGM in ORCA, PROG in ATT3000), when the FPGA's M[2:0] pins are low, the FPGA configures using the master serial mode. The configuration data is transmitted serially into the FPGA's DIN pin from the serial ROM's DATA pin. To synchronize the data, the FPGA's CCLK output is routed into the serial ROM's CLOCK input. Because the FPGA DIN signal may be unused after FPGA configuration, it is necessary to avoid an unresolved state once the serial ROM has finished sending configuration data. If this pin is used only for the configuration process, it should be configured so that it does not float. This can be accomplished by programming it as an output during normal operation or by programming it as an input with an internal pull-up resistor enabled. CCLK must also be pulled up following configuration. Signal contention on the DIN pin must be avoided if it is to be used for a user I/O signal after configuration. To avoid contention, the FPGA DONE signal may be programmed (selected in ORCA Foundry) to go high prior to the FPGA I/O signals being enabled. An alternative is to use the FPGA's LDC to drive the serial ROM's CE pin, rather than DONE, and configure LDC to output a constant logic 1 high-voltage level after configuration. Control of the serial ROM's CE and RESET/OE pins varies, depending upon the FPGA series being used, and is described in subsequent sections. Lucent Technologies Inc. Memory Requirements 14,819 22,216 30,824 46,104 64,200 57,144 76,376 98,296 122,904 65,424 91,024 115,600 148,944 179,856 220,944 307,024 474,176 387,048 562,664 872,488 The FPGA serial ROM interface used also depends upon the system and configuration requirements. The following are some typical system requirements: Configuring an FPGA at powerup Configuring an FPGA in response to a configure command One serial ROM configures an FPGA with multiple configuration programs Cascaded serial ROMs configure daisy-chained FPGAs In addition to the clock and data lines, the FPGA pins used in configuration/start-up are RESET, DONE, PRGM, LDC, HDC, and INIT. Normally, only a small subset of these pins is used to control the serial ROM's CE and RESET/OE pins. In some applications, the RESET/OE signal is generated by the system host, not the FPGA. For example, the host may generate a system reset, allowing the FPGA and the serial ROM to be reset synchronously. 3 Data Sheet January 1998 ATT1700A Series Serial ROM FPGA Configuration (continued) Configuring the ORCA Series FPGA with a Configure Command ATT3000 Series/ORCA Series Differences The FPGA needs to enable the serial ROM's RESET/OE and CE inputs. The polarity of the RESET/OE input is programmable in the ATT1700A Series. In the method shown in Figure 2, the system generates an active-low configure pulse to the FPGA's PRGM pin. This configuration pulse causes the FPGA to drive its INIT pin low, which forces a RESET on the serial ROM RESET/OE pin (with the RESET/OE pin programmed for active-low RESET and active-high OE). The FPGA's DONE pin is routed to the serial ROM's CE pin. At the end of configuration, DONE returns high, disabling the serial ROM. Alternatively, the LDC pin can be used instead of the DONE pin to enable the serial ROM. While both the ATT3000 and ORCA Series have RESET, LDC, HDC, INIT, DIN, CCLK, and DOUT pins, there are some configuration differences in the FPGAs. The ATT3000 Series DONE/PROG pin is a shared open-drain I/O, while the ORCA Series has discrete DONE and PRGM pins. When the system generates a configure command to the ATT3000, the DONE/PROG pin is held low throughout the configuration cycle. For the ORCA Series, the PRGM pin is pulsed low and returned high to initiate configuration. A second difference is the internal pull-ups on the mode select pins. For the ATT3000 Series, only M2 has an internal pullup during configuration, but for the ORCA Series, M[3:0] have pull-ups. Configuring the ATT3000 Series FPGA with a Configure Command Configuring the FPGA at Powerup The ATT1700A Series can configure FPGAs at powerup. There is level-sensitive, power-on-reset circuitry included in the device that resets the address pointer during powerup. The ATT3000 and ORCA FPGAs enable the serial ROM using either the DONE (or LDC) and INIT pins. If these signals are low at powerup and they are connected to the CE and RESET/OE pins on the serial ROM, the FPGA is programmed from the serial ROM (see Figures 2 and 3). When these FPGA signals go high at the end of configuration, the serial ROM is disabled. DATA DOUT DIN In the method illustrated in Figure 3, the system generates an active-low configure pulse on the FPGA's DONE/PROG pin. The system then releases the opendrain DONE/PROG pin, allowing the FPGA to control it and drive it low during configuration. DONE/PROG is generally connected to both the CE and RESET/OE pins of the serial ROM, which has been programmed so that RESET is active-high and OE is active-low. At the end of configuration, the DONE/PROG pin returns high, disabling and resetting the serial ROM. The LDC pin may be used instead of the DONE/PROG pin to enable the serial ROM, as shown. TO DAISYCHAINED DEVICES CCLK CLK ATT1700A CE RESET/OE DONE INIT ORCA SERIES FPGA CEO DATA CLK PRGM ATT1700A CE RESET/OE CEO TO MORE SERIAL ROMs AS NEEDED M2 M1 M0 PROGRAM 5-4456.1 Figure 2. ORCA Master Serial Configuration 4 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM FPGA Configuration (continued) +5 V DURING CONFIGURATION THE 5 k M2 PULL-DOWN RESISTOR OVERCOMES THE INTERNAL PULL-UP, BUT IT ALLOWS M2 TO BE USER I/O. M0 M1 PWRDWN DOUT * * M2 HDC GENERALPURPOSE USER I/O PINS LDC OPTIONAL IDENTICAL SLAVE FPGAs CONFIGURED THE SAME INIT OTHER I/O PINS ATT3000 SERIES FPGA PROGRAM ATT1700A DONE/PROG DIN CCLK LDC DATA DATA CLK CLK CE RESET/OE (HIGH RESETS THE ADDRESS POINTER) CEO CASCADED ATT1700A MEMORY CE RESET/OE 5-3112 Figure 3. ATT3000 Master Serial Configuration Programming the FPGA with the Address Pointer Unchanged Upon Completion In the two interfaces previously discussed, the serial ROM is reset at the completion of configuration. This is typically the case when one or more serial ROMs are used to configure one or more FPGAs with one configuration program. In applications in which a serial ROM is used to configure an FPGA with multiple configuration programs, the address pointer should not be reset. This allows the next configuration program to be loaded at the next internal ROM address. Lucent Technologies Inc. When multiple FPGA configurations are stored in a serial ROM, the OE pin of the serial ROM should be tied low. Upon powerup, the internal address pointer is reset and configuration begins with the first set of configuration data stored in memory. Since the OE pin is held low, the address pointer is left unchanged after configuration is complete. To reprogram the FPGA with another program, the DONE/PROG or PRGM pin is pulled low, and configuration begins at the last value of the address pointer. 5 Data Sheet January 1998 ATT1700A Series Serial ROM FPGA Configuration (continued) Standby Mode Cascading Serial ROMs The ATT1700A Series enters a low-power standby mode when CE is high. In standby mode, the serial ROM consumes less than 100 A of current. The DATA pin remains in the high-impedance state regardless of the state of the RESET/OE input. Figure 2 and Figure 3 also illustrate the cascading of serial ROMs. This is done to provide additional memory for large FPGAs and/or for configuring multiple FPGAs in a daisy chain. The serial ROMs are cascaded with the next ROM's CE input connected to the CEO output of the previous serial ROM. All of the cascaded serial ROM's DATA lines are routed to the FPGA's DIN input, and the FPGA's CCLK output is routed in parallel to all of the serial ROMs' CLOCK inputs. After the last bit from the first serial ROM is read, the first serial ROM asserts CEO low and disables its DATA output. The next serial ROM recognizes the low on its CE input and enables its DATA output. The inactive CE into all serial ROMs causes the inactive DATA pins to be 3-stated after configuration is finished. RESET/OE Polarity The ATT1700A Series allows the user to select the polarity of the dual-function RESET/OE pin. The PROM programmer software is used to program the desired polarity. The method used to select a polarity depends on the PROM programmer user interface. The ATT3000 DONE/PROG signal and the ORCA DONE signal are open-drain outputs with optional internal pull-ups and can be used to control the output enable of multiple serial ROMs. Extremely large, cascaded serial memories may require additional logic if the DONE/PROG or DONE signals are too slow to activate many serial ROMs. 6 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit Supply Voltage Relative to GND Programming Voltage Relative to GND Input Voltage with Respect to GND Voltage Applied to 3-state Output Ambient Storage Temperature Maximum Soldering Temperature Maximum Junction Temperature VDD VPP VIN VTS Tstg TSOL TJ -0.6 -0.6 -0.6 -0.6 -65 -- -- 6.6 14.0 VDD + 0.6 VDD + 0.6 150 300 125 V V V V C C C Electrical Characteristics Table 3. dc Electrical Characteristics Commercial: 0 C TA 70 C, VDD = 5.0 V 5%; Industrial: -40 C TA +85 C, VDD = 5.0 V 10%. Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Supply Voltage Relative to VSS: Commercial Industrial Standby Supply Current Symbol Conditions Min Max Unit VIH VIL VOH VOH VOL -- -- VDD = 3.0 V, IOH = -4.0 mA VDD = 4.5 V, IOH = -4.0 mA VDD = 5.5 V, IOL = 4.0 mA 2.0 -0.3 2.40 3.86 -- VDD 0.8 -- -- 0.32 V V V V V -- -- -- -- IDDSB VIN = VDD = 5.5 V VIN = VDD = 3.6 V VDD = 5.5 V, clock = 10 MHz VDD = 3.6 V, clock = 2.5 MHz VDD = 5.5 V, VIN = VDD and 0 V VDD = 5.5 V, VIN = VDD and 0 V VCC = 5 V, TA = 25 C, FCLK = 1 MHz 4.75 4.50 -- -- -- -- -10 5.25 5.50 100 50 10 2 10 V V A A mA mA A -10 10 A -- 10 pF Operating Supply Current IDD Input Leakage Current IIL Output Leakage Current IIL Pin Capacitance CIN Lucent Technologies Inc. 7 Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) Table 4. ac Characteristics During Read Commercial: 0 C TA 70 C, VDD = 5.0 V 5%; Industrial: -40 C TA +85 C, VDD = 5.0 V 10%. Parameter Symbol OE to Data Delay CE to Data Delay CLOCK to DATA Delay DATA Hold from CE, OE, or CLOCK CE or OE to DATA Float Delay CLOCK Frequency CLOCK Low Time CLOCK High Time CE Setup Time to CLOCK (Guarantees correct counting.) CE Hold Time from CLOCK (Guarantees correct counting.) OE High Time (Guarantees counters are reset.) TOE TCE TCAC TOH TDF TCLK TCL TCH TSCE Limits Limits Test 3.0 V VDD 6.0 V 4.5 V VDD 6.0 V Conditions Min Max Min Max -- -- 45 -- 45 -- -- 60 -- 50 -- -- 200 -- 60 -- 0 -- 0 -- -- -- 50 -- 50 -- -- 2.5 -- 10 -- 100 -- 25 -- -- 100 -- 25 -- -- 40 -- 25 -- Unit ns ns ns ns ns MHz ns ns ns THCE -- 0 -- 0 -- ns THOE CE high 100 -- 20 -- ns or low CE THCE TSCE TSCE RESET/OE TCL TCH TCLK THOE CLOCK TOE TOH TCE TDF DATA TCAC TOH 5-3870 Figure 4. Read Characteristics 8 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) Table 5. ac Characteristics at End of Read Commercial: 0 C TA 70 C, VDD = 5.0 V 5%; Industrial: -40 C TA +85 C, VDD = 5.0 V 10%. Parameter Symbol CLOCK to DATA Disable Delay CLOCK to CEO Delay CE to CEO Delay OE to CEO Delay TCDF TOCK TOCE TOOE Limits 3.0 V VDD 6.0 V Limits 4.5 V VDD 6.0 V Min Max Min Max -- -- -- -- 50 65 45 40 -- -- -- -- 50 40 40 40 Unit ns ns ns ns RESET/OE CE CLOCK TCDF DATA LAST BIT FIRST BIT TOOE TOCK CEO TOCE 5-3871 Figure 5. Read Characteristics at End of Array Lucent Technologies Inc. 9 Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) Start Check Device ID Device Power Off Device Power On Enter Programming Mode 1. VCC = VCCP VPP = VPP2 CE = OE = VIH 2. VPP = VPP1 for 2 CLK Rising Edges 3. VPP = VPP2 for 1 CLK Rising Edge 32-bit data word to be programmed = FFFFFFFFhex Yes No CE low to clear EPROM internal data latches Load 32-bit word to be programmed Pulse VPP to VPP1 (13 V) for TPGM (500 s) Increment Address Counter No Last Word? Yes Exit Programming Mode Device Power Off Device Power On Yes 1st Pass? No Device Failed Fail Verify All Data Bits (Read Mode) VCC = VPP = VCCL and VCC = VPP = VCCH (see note) Pass Device Passed 5-3869 Note: Verify CEO has gone LOW one clock after last bit. Figure 6. ATT1700A Programming 10 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) Table 6. dc Programming Specifications Commercial: 0 C TA 70 C, VDD = 5.0 V 5%; Industrial: -40 C TA +85 C, VDD = 5.0 V 10%. Parameter Supply Voltage During Programming Low-level Input Voltage High-level Input Voltage Low-level Output Voltage High-level Output Voltage Programming Voltage* Programming Mode Access Voltage Supply Current in Programming Mode Input or Output Leakage Current First-pass, Low-level Supply Voltage for Final Verification Second-pass, High-level Supply Voltage for Final Verification Symbol Min Max Unit VCCP VIL VIH VOL VOH VPP1 VPP2 IPPP IL VDDL VDDH 5.0 0.0 2.4 -- 3.7 12.5 VCCP -- -10 2.8 6.0 6.0 0.5 VCC 0.4 -- 13.5 VCCP + 1 100 10 3.0 8.2 V V V V V V V mA A V V * No overshoot is permitted on this signal. VPP must not be allowed to exceed 14 V. Lucent Technologies Inc. 11 Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) Table 7. ac Programming Specifications Commercial: 0 C TA 70 C, VDD = 5.0 V 5%; Industrial: -40 C TA +85 C, VDD = 5.0 V 10%. Parameter Test Conditions Symbol Min Max Unit 10% to 90% Rise Time of VPP 90% to 10% Fall Time of VPP VPP Programming Pulse Width VPP Setup to Clock for Entering Programming Mode CE Setup to Clock for Entering Programming Mode OE Setup to Clock for Entering Programming Mode VPP Hold from Clock for Entering Programming Mode Data Setup to Clock for Programming Data Hold from Clock for Programming CE Low Time to Clear Data Latches CE Setup to Clock for Programming/Verifying OE Setup to Clock for Incrementing Address Counter OE Hold from Clock for Incrementing Address Counter OE Hold from VPP Clock to Data Valid Data Hold from Clock CE Low to Data Valid * * -- * TRPP TFPP TPGM TSVC 1 1 0.5 100 -- -- 1.05 -- s s ms ns * * TSVCE TSVOE 100 100 -- -- ns ns * THVC 300 -- ns -- -- -- -- -- TSDP THDP TLCE TSCC TSIC 50 0 100 100 100 -- -- -- -- -- ns ns ns ns ns -- THIC 0 -- ns * -- -- -- THOV TPCAC TPOH TPCE 200 -- 0 -- -- 400 -- 250 ns ns ns ns * This parameter is periodically sampled and is not 100% tested. Note: While in programming mode, CE should only be changed while OE is HIGH and has been HIGH for 200 ns, and OE should only be changed while CE is HIGH and has been HIGH for 200 ns. 12 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) VDD VCCP VPP2 VPP VPP1 VPP VSS VCCP VPP2 TFPP VDD TSVC TRPP VSS THVC TSVC 1 ms CLOCK CE VSS DATA RESET/OE VSS TSVCE CE CLOCK VSS TSVOE RESET/OE ENTER PROGRAMMING MODE EXIT PROGRAMMING MODE 5-3864 Figure 7. Entering and Exiting Programming Mode VDD = VCCP VDD VPP1 VPP = VPP2 VPP ENTER 500 s PROGRAMMING PROGRAMMING MODE MODE 500 s PROGRAMMING MODE 500 s PROGRAMMING MODE 500 s PROGRAMMING MODE CLOCK 2 CLKS LOAD WORD 1 LOAD WORD 2 LOAD WORD 3 LOAD WORD 4 LOAD WORD 5 CLOCK INCREMENTS ADDRESS COUNTER CE LOW TO CLEAR DATA LATCHES CE RESET/OE HIGH IF RESET/OE CONFIGURED CEO * * * * * LOW IF RESET/OE CONFIGURED 5-3865 * The CEO pin is high impedance when VPP = VPP1. 32 clocks. Figure 8. Programming Cycle Overview Lucent Technologies Inc. 13 Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) CLEAR PROM INTERNAL DATA LATCHES TRPP LOAD PROM INTERNAL DATA LATCHES VPP TFPP TPGM CLOCK TSDP DATA * 1 THIC TSIC THDP 32 LAST BIT 2 TSCC CE THOV TLCE RESET/OE PROGRAM PULSE INCREMENT WORD COUNTER 5-3866 * The programmer must float the data pin while CE is low to avoid bus contention. Figure 9. Details of Programming Cycle VDD = VCCP VDD VPP1 VPP = VPP2 VPP ENTER PROGRAMMING MODE CLOCK PAST USER MEMORY ARRAY TO ID LOCATION NEEDS 4104 CLOCKS (ATT17128A ATT1736A/65A NEEDS 2056 CLOCKS) CLOCK 7 CLOCKS TO READ MANUFACTURER ID 8 CLOCKS TO READ DEVICE ID CE RESET/OE HIGH IF RESET/OE CONFIGURED CEO LOW IF RESET/OE CONFIGURED MICROCHIP ID LSB FIRST DATA FLOATS DEVICE ID X 29 HEX ATT17128A = 72 HEX ATT1765A = 71 HEX ATT1736A = 70 HEX 5-3867 Figure 10. Read Manufacturer and Device ID Overview 14 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM Electrical Characteristics (continued) VENDOR ID = 29 HEX 1 2 3 DEVICE ID 4 5 6 7 1 2 CLOCK TPCAC TPCH LSB = 1 DATA 0 0 1 0 1 0 0 LSB TPCE CE RESET/OE 5-3868 Figure 11. Details of Read Manufacturer and Device ID Lucent Technologies Inc. 15 Data Sheet January 1998 ATT1700A Series Serial ROM Outline Diagrams 8-Pin, Plastic DIP Controlling dimensions are in inches. 0.400 MAX 8 5 1 4 0.155 MAX 0.160 MAX 0.100 TYP 16 0.310 MAX 0.060 MAX 0.023 MAX 0.400 MAX 5-2641 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM Outline Diagrams (continued) 8-Pin SONB Controlling dimensions are in inches. 0.200 MAX 8 5 0.008 REF 0.025 MAX DETAIL A 1 4 0.068 MAX 0.060 MAX 0.050 TYP Lucent Technologies Inc. 0.020 MAX 0.158 MAX DETAIL A 0.240 0.003 5-3979 17 Data Sheet January 1998 ATT1700A Series Serial ROM Outline Diagrams (continued) 20-Pin PLCC Controlling dimensions are in inches. 0.385/0.395 SQ. 0.350/0.355 1 4 18 8 14 9 13 0.020 MIN 0.026/0.032 DETAIL A DETAIL A 0.146/ 0.156 0.013/0.021 0.050 TYP. 18 5-2035 Lucent Technologies Inc. Data Sheet January 1998 ATT1700A Series Serial ROM Ordering Information Example: ATT1736A P8 I TEMPERATURE RANGE DEVICE TYPE PACKAGE TYPE PROGRAMMABILITY ATT1736A; one-time programmable; 8-pin, plastic DIP; industrial temperature Table 8. Device Type Device Size ATT1736A ATT1765A ATT17128A 36,288 65,536 131,072 Table 9. Programmability Designation Programmability Blank or A One-time Programmable Table 10. Package Type Designation Package P8 G8 M20 8-pin, plastic DIP 8-pin SONB 20-pin PLCC Table 11. Temperature Range Designation Type Operating Range Blank I Commercial Industrial 0 C to 70 C -40 C to +85 C Lucent Technologies Inc. 19 For FPGA technical applications support, please call 1-800-327-9374 or e-mail orcafpga@lucent.com. Outside North America, please call 1-610-712-4331. For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/orca E-MAIL: docmaster@micro.lucent.com U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Bracknell), FRANCE: (33) 1 41 45 77 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 2 6601 1800 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc. Copyright (c) 1998 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. January 1998 DS98-048FPGA (Replaces DS96-239FPGA)