PCX8245MTPU300D - E2V Technologies (UK), Ltd.

2171D–HIREL–06/04

Features

•300 MHz - 333 MHz To Be Confirmed-PC603e Processor Core Im plementing the

PowerPC® Architecture

•32-bit PCI Interface Operating at up to 66 MHz

•Memory Controller Offering SDRAM Support up to 133 MHz Operation, Support up to

2GB

•General Purpose I/O and ROM Interface Support

•Two Channel DMA Controller that Supports Chaining

•Messaging Unit with I2O Messaging Support Capability

•Industry-standard I2C Interface

•Programmable Interrupt Controller with Multiple Timers and Counters

•16550-compatible DUART

Description

The PC8245 combines a PC603e core microprocessor with a PCI bridge. The PCI

suppor t on the PC8245 will allow system designers to rapidly design systems using

peripherals already designed for PCI and the other standard interfaces. The PC8245

also integ r ates a high -per formance memory controller which supports various type s of

ROM and SDRAM.

The PC8245 is the second of a family of products that provid es system-level suppor t

for industry standard interfaces with a PC603e processor core.

This document describes per tinent electrical and physical characteristics of the

PC8245. For functional characteristics of the processor, refer to the Motorola’s docu-

mentation "MPC8245 Integrated Processor User’s Manual" (MPC8245UM/D).

Screening/Quality/Packaging

This product is manufactured in full compliance with:

• Upscreening based upon Atmel standards

• Military temperature range (Tc = -55°C, Tc = +125°C)

• Core power supply:

2.0 ± 100 mV

• I/O po wer supply: 3.3V ± 0.3V

• 352 Tape Ball Grid Array (TBGA)

TP suffix

TBGA352

Tape Ball Grid Array

Integrated

Processor

Family

PC8245

Product

Specification

Rev. 2171D–HIREL–06/04

2PC8245 2171D–HIREL–06/04

General Description

Block Diagram The PC8245 integrated processor is comprised of a periphe ral logic block and a 32-bit

superscalar PowerPC 603e core, as shown in Figure 1.

Figure 1. Block Diagram

Peripheral Logic

Instruction Unit

Address

Translator

DLL

Fanout

Buffers

PCI

Arbiter

I2C

Controller

DMA

Controller

EPIC

Interrupt

Controller

/Timers

DUART

Watchpoint

Facility

PCI Bus

Interface Unit

Data Path

ECC Controller

Memory

Controller

Central

Control

Unit

Oscillator

Input

Five Request/

Grant Pairs

I2C

5 IRQs/

16 Serial

Interrupts

Processor Core Block

Peripheral Logic Block

Processor

PLL

Instruction

MMU

(64-bit) Two-instruction fetch

(64-bit) Two-instruction dispatch

Peripheral Logic

PLL

SDRAM Clocks

PCI_SYNC_IN

PCI Bus

Clocks

Data (64-bit)

Address

(32-bit)

Data Bus

(32- or 64-bit)

with 8-bit Parity

or ECC

Memory/ROM/PortX

Address and Control

64-bit

32-bit

PCI Interface

Branch

Processing

Unit

(BPU)

System

Unit

(SRU)

Floating

Point

Unit

(FPU)

Integer

Unit

(IU)

Load/Store

Unit

(LSU)

Bus

Performance

Monitor

Data

MMU

16-Kbyte

Data

Cache

16-Kbyte

Instruction

Cache

Configuration

Registers

Additional features:

• Prog I/O with Watchpoint

• JTAG/COP Interface

• Power Management

PC8245

SDRAM_SYNC_IN

Message

Unit

(with I2O)

PC8245

2171D–HIREL–06/04

The peripheral logic integrates a PCI bridge, dual universal asynchronous

receiver/transmitter (DUART), memory contro ller, DMA controller, EPIC interrupt con-

troller, a message unit (and I2O interface), and a I2C inteface controller. The processor

core is a full-featured, high-performance processor with floating-point support, memory

management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power manage-

ment features. The integration reduces the over all packaging requirements and the

number of discrete device s required for an embedded system.

The PC8245 contains an internal peripheral logic bus that interfaces the processor core

to the peripheral logic. The core can operate at a variety of frequencies, allowing the

designer to trade-off performance for power consumption. The processor core is

clocked from a separate PLL, which is referenced to the peripheral logic PLL. This

allows the microprocessor and the peripheral logic block to operate at different frequen-

cies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit

data bus (depending on memo ry data bus width) and a 32-bit address bus along with

control sig nals that enable the in terface betwee n the processor and peripheral logic to

be optimized for performance. PCI accesses to the PC8245 memory space are passed

to the processor bus for sn ooping when snoop mode is enabled.

The proces sor core and pe ripheral lo gic are gene ral-purpo se in order to serve a variety

of embedded applications. The PC8245 can be used as either a PCI host or PCI agent

controller.

General Parameters The following list provides a su mmary of the general parameters of the PC8245:

Technology0 .2 5 µm CMO S , five -la ye r me ta l

Die size 49.2 mm2

Transistor count4.5 million

Logic designFully static

PackagesSurface-mount 352 tap e ball grid array (TBGA)

Core power supply:2.0V ± 100 mV DC

(nominal; see Table “ Recommended Operating Conditions” on page 12

for details

I/O power supply3.0 to 3.6V DC

Features Major features of the PC8245 are as follows:

• Processor core

– High-performance, superscalar processor core

– Integer unit (IU), floating-point unit (FPU) (software enabled or disabled),

load/store unit (LSU), system register unit (SRU), and a branch processing

unit (BPU)

– 16-Kbyte instruction cache

– 16-Kbyte data cache

– Lockable L1 caches — entire cache or on a per-way basis up to three of four

ways

– Dynamic pow er management — supports 60x nap, doze, and sleep modes

4PC8245 2171D–HIREL–06/04

• Peripheral logic

Peripheral Logic Bus

– Supports various operating fr equencies and bus divider ratios

– 32-bit address bus, 64-bit data bus

– Supports full memory coherency

– Decoupled address and data buses for pipelining of peripheral logic bus

accesses

– Store gathering on peripheral logic bus-to-PCI writes

Memory interface

– Supports up to 2 Gbytes of SDRAM memory

– High-bandwidth data bus (32- or 64-bit) to SDRAM

– Programmable timing supporting SDRAM

– Supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices

– Write buffering for PCI an d processor accesses

– Supports normal parity, read-modify-write (RMW), or ECC

– Data-path buffering betw een memory interface and processor

– Low-voltage TTL logic (LVTTL) interfaces

– 272 Mbytes of base and extended ROM/Flash/PortX space

– Base ROM space supports 8-bit data path or same size as the SDRAM data

path (32- or 64-bit)

– Extended R O M space supports 8-, 16-, 32-bit gathering dat a path, 3 2- or 6 4-

bit (wide) data path

– Por tX: 8-, 16-, 32-, or 64-bit general-pur pose I/O port using ROM controller

interface with programmable address strobe timing, data ready input signal

(DRDY), and 4 chip selects

32-bit PCI interface

– Operates up to 66 MHz

– PCI 2.2-compliant

– PCI 5.0V tolerance

– Support f or d ual address cycle (DAC) for 64-bit PCI addressing (master only)

– Support for PCI locked accesses to memory

– Support for accesses to PCI memory, I/O, and configuration spaces

– Selectable big- or little-endian operation

– Store gathering of processor-to-PCI write and PCI-to-memory write

accesses

– Memory prefet ching of PCI read accesses

– Selectable hardware-enforced coherency

– PCI bus arbitration unit (five request/grant pairs)

– PCI agent mode capability

– Address translation with two inbound and outbound units (ATU)

– Some internal configuration registers accessible from PCI

Two-channel integr ated DMA controller (writes to ROM/PortX not suppo rted)

PC8245

2171D–HIREL–06/04

– Supports direct mode or chaining mode (automatic linking of DMA transfers)

– Supports scatter gathering — read or write discontinuo us mem o ry

– 64-byte transfer queue per channel

– Interrupt on completed segmen t, chain, and error

– Local-to-local memory

– PCI-to-PCI memory

– Local-to-PCI memory

– PCI memory-to-local memory

Message unit

– Two doorbell regi st er s

– Two inbound an d two ou tb ou n d me ssaging regist er s

–I

2O message interface

Two-wire interface controller with full master/slave support that accepts broadcast

messages

Embedded programma ble interrupt controller (EPIC)

– Five hardware interrupts (IRQs) or 16 serial interrupts

– Four programmable timers with cascade

Two (dual) universal asynchronous receiver/transmitters (UARTs)

Integrated PCI bus and SDRAM clock generation

Programmable PCI bus and memory interface output drivers

• System level performance monitor facility

• Debug features

– Memory attribute and PCI attribute signals

– Debug address signals

–MIV

signal: marks valid address and data bus cycles on the memory

bus

– Programmable input and output signals with watchpoint capability

– Error injection/capture on data path

– IEEE 1149.1 (JTAG)/test interface

6PC8245 2171D–HIREL–06/04

Pinout Listing Table 1 provides the pino ut listing for the PC8245, 352 TBGA package.

Table 1. PC8245 Pinout Listing

Signal Name Pin Number Type Power

Supply Output Driver Type Notes

PCI Interface Signals

C/BE[3:0] P25 K23 F23 A25 I/O OVDD DRV_PCI (6)(15)

DEVSEL H26 I/O3 OVDD DRV_PCI (8)(15)

FRAME J24 I/O OVDD DRV_PCI (8)(15)

IRDY K25 I/O OVDD DRV_PCI (8)(15)

LOCK J26 Input OVDD –(8)

AD[31:0]

V25 U25 U26 U24 U23 T25 T26

R25 R26 N26 N25 N23 M26 M25

L25 L26 F24 E26 E25 E23 D26

D25 C26 A26 B26 A24 B24 D19

B23 B22 D22 C22

I/O3 OVDD DRV_PCI (6)(15)

PAR G25 I/O OVDD DRV_PCI (15)

GNT[3:0] W25 W24 W23 V26 Output OVDD DRV_PCI (6)(15)

GNT4/DA5 W26 Output OVDD DRV_PCI (7)(14)(15)

REQ[3:0] Y25 AA26 AA25 AB26 Input OVDD –(6)(12)

REQ4/DA4 Y26 I/O OVDD –(12)(14)

PERR G26 I/O OVDD DRV_PCI (8)(15)(18)

SERR F26 I/O OVDD DRV_PCI (8)(15)(16)

STOP H25 I/O OVDD DRV_PCI (8)(15)

TRDY K26 I/O OVDD DRV_PCI (8)(15)

INTA AC26 Output OVDD DRV_PCI (15)(16)

IDSEL P26 Input OVDD –

Memory Interface Signals

MDL[0:31]

AD17 AE17 AE15 AF15 AC14

AE13 AF13 AF12 AF11 AF10 AF9

AD8 AF8 AF7 AF6 AE5 B1 A1 A3

A4 A5 A6 A7 D7 A8 B8 A10 D10

A12 B11 B12 A14

I/O GVDD DRV_STD_MEM (5)(6)

MDH[0:31]

AC17 AF16 AE16 AE14 AF14

AC13 AE12 AE11 AE10 AE9 AE8

AC7 AE7 AE6 AF5 AC5 E4 A2 B3

D4 B4 B5 D6 C6 B7 C9 A9 B10

A11 A13 B13 A15

I/O GVDD DRV_STD_MEM (6)

DQM[0:7] AB1 AB2 K3 K2 AC1 AC2 K1 J1 Output GVDD DRV_MEM_CTRL (6)

CS[0:7] Y4 AA3 AA4 AC4 M2 L2 M1 L1 Output GVDD DRV_MEM_CTRL (6)

FOE H1 I/O GVDD DRV_MEM_CTRL (3)(4)

RCS0 N4 Output GVDD DRV_MEM_CTRL (3)(4)

RCS1 N2 Output GVDD DRV_MEM_CTRL

PC8245

2171D–HIREL–06/04

RCS2/TRIG_IN AF20 I/O OVDD –(10)(14)

RCS3/TRIG_OUT AC18 Output GVDD DRV_MEM_CTRL (14)

SDMA[1:0] W1 W2 I/O GVDD DRV_MEM_CTRL (3)(4)(6)

SDMA[11:2] N1 R1 R2 T1 T2 U4 U2 U1 V1 V3 Output GVDD DRV_MEM_CTRL (6)

DRDY B20 Input OVDD –(9)(14)

SDMA12/SRESET B16 I/O GVDD DRV_MEM_CTRL (10)(14)

SDMA13/TBEN B14 I/O GVDD DRV_MEM_CTRL (10)(14)

SDMA14/CHKSTOP_IN D14 I/O GVDD DRV_MEM_CTRL (10)(14)

SDBA1 P1 Output GVDD DRV_MEM_CTRL

SDBA0 P2 Output GVDD DRV_MEM_CTRL

PAR[0:7] AF3 AE3 G4 E2 AE4 AF4 D2 C2 I/O GVDD DRV_STD_MEM (6)

SDRAS AD1 Output GVDD DRV_MEM_CTRL (3)

SDCAS AD2 Output GVDD DRV_MEM_CTRL (3)

CKE H2 Output GVDD DRV_MEM_CTRL (3)(4)

WE AA1 Output GVDD DRV_MEM_CTRL

AS Y1 Output GVDD DRV_MEM_CTRL (3)(4)

EPIC Control Signals

IRQ0/S_INT C19 Input OVDD –

IRQ1/S_CLK B21 I/O OVDD DRV_PCI

IRQ2/S_RST AC22 I/O OVDD DRV_PCI

IRQ_3/S_FRAME AE24 I/O OVDD DRV_PCI

IRQ_4/ L_INT A23 I/O OVDD DRV_PCI

Two-wire Interface Control Signals

SDA AE20 I/O OVDD DRV_STD_MEM (10)(16)

SCL AF21 I/O OVDD DRV_STD_MEM (10)(16)

DUART Control Signals

SOUT1/PCI_CLK0 AC25 Output GVDD DRV_PCI_CLK (13)(14)

SIN1/PCI_CLK1 AB25 I/O GVDD DRV_PCI_CLK (13)(14)

SOUT2/RTS1/PCI_CLK2 AE26 Output GVDD DRV_PCI_CLK (13)(14)

SIN2/CTS1/PCI_CLK3 AF25 I/O GVDD DRV_PCI_CLK (13)(14)

Clock Out Signals

PCI_CLK0/SOUT1 AC25 Output GVDD DRV_PCI_CLK (13)(14)

PCI_CLK1/SIN1 AB25 I/O GVDD DRV_PCI_CLK (13)(14)

PCI_CLK2/RTS1/SOUT2 AE26 Output GVDD DRV_PCI_CLK (13)(14)

PCI_CLK3/CTS1/SIN2 AF25 I/O GVDD DRV_PCI_CLK (13)(14)

Table 1. PC8245 Pinout Listing (Continued)

Signal Name Pin Number Type Power

Supply Output Driver Type Notes

8PC8245 2171D–HIREL–06/04

PCI_CLK4/DA3 AF26 Output GVDD DRV_PCI_CLK (13)(14)

PCI_SYNC_OUT AD25 Output GVDD DRV_PCI_CLK

PCI_SYNC_IN AB23 Input GVDD –

SDRAM_CLK [0:3] D1 G1 G2 E1 Output GVDD DRV_MEM_CTRL or

DRV_MEM_CLK (6)(21)

SDRAM_SYNC_OUT C1 Output GVDD DRV_MEM_CTRL or

DRV_MEM_CLK (21)

SDRAM_SYNC_IN H3 Input GVDD –

CKO/DA1 B15 Output OVDD DRV_STD_MEM (14)

OSC_IN AD21 Input OVDD –(19)

Miscellaneous Sig nals

HRST_CTRL A20 Input OVDD –

HRST_CPU A19 Input OVDD –

MCP A17 Output OVDD DRV_STD_MEM (3)(4)(17)

NMI D16 Input OVDD –

SMI A18 Input OVDD –(10)

SRESET/SDMA12 B16 I/O GVDD DRV_MEM_CTRL (10)(14)

TBEN/SDMA13 B14 I/O GVDD DRV_MEM_CTRL (10)(14)

QACK/DA0 F2 Output OVDD DRV_STD_MEM (3)(4)(14)

CHKSTOP_IN/SDMA14 D14 I/O GVDD DRV_MEM_CTRL (10)(14)

TRIG_IN/RCS2 AF20 I/O OVDD –(10)(14)

TRIG_OUT/RCS3 AC18 Output GVDD DRV_MEM_CTRL (14)

MAA[0:2] AF2 AF1 AE1 Output GVDD DRV_STD_MEM (3)(4)(6)

MIV A16 Output OVDD –(24)

PMAA[0:1] AD18 AF18 Output OVDD DRV_STD_MEM (3)(4)(6)(15)

PMAA[2] AE19 Output OVDD DRV_STD_MEM (4)(6)(15)

Test/Configuration Signals

PLL_CFG[0:4]/DA[10:6] A22 B19 A21 B18 B17 I/O OVDD DRV_STD_MEM (6)(14)(20)

TEST0 AD22 Input OVDD –(1)(9)

DRDY B20 Input OVDD –(9)(10)(14)

RTC Y2 Input GVDD –(11)

TCK AF22 Input OVDD –(9)(12)

TDI AF23 Input OVDD –(9)(12)

TDO AC21 Output OVDD –(24)

TMS AE22 Input OVDD –(9)(12)

TRST AE23 Input OVDD –(9)(12)

Table 1. PC8245 Pinout Listing (Continued)

Signal Name Pin Number Type Power

Supply Output Driver Type Notes

PC8245

2171D–HIREL–06/04

Notes: 1. Place a pull-up resistor of 120Ω or less on the TEST0 pin.

2. Treat these pins as no connects (NC) unless using debug address functionality.

Power and Ground Signals

GND

AA2 AA23 AC 12 AC15 AC24 AC3

AC6 AC9 AD11 AD14 AD16 AD19

AD23 AD4 AE18 AE2 AE21 AE25

B2 B25 B6 B9 C11 C13 C16 C23

C4 C8 D12 D15 D18 D21 D24 D3

F25 F4 H24 J25 J4 L24 L3 M23 M4

N24 P3 R23 R4 T24 T3 V2 V23 W3

Ground – –

LVDD AC20 AC23 D20 D23 G23 P23 Y23 Reference

voltage

3.3V, 5.0V LVDD –

GVDD

AB3 AB4 AC10 AC11 AC8 AD10

AD13 AD15 AD3 AD5 AD7 C10

C12 C3 C5 C7 D13 D5 D9 E3 G3

H4 K4 L4 N3 P4 R3 U3 V4 Y3

Power for

Memory Drivers

3.3V GVDD –

OVDD

AB24 AD20 AD24 C14 C20 C24

E24 G24 J23 K24 M24 P24 T23

Y24

PCI/Stnd

3.3V OVDD –

VDD

AA24 AC16 AC19 AD12 AD6 AD9

C15 C18 C21 D11 D8 F3 H23 J3

L23 M3 R24 T4 V24 W4

Power for Core

1.8/2.0V VDD –(22)

No Connect D17 – – – (23)

AVDD C17

Power for PLL

(CPU Core

Logic)

1.8/2.0V

AVDD –(22)

AVDD2AF24 Power for PLL

(Peripheral

Logic) 1.8/2.0V AVDD2– (22)

Debug/Manufacturi ng Pins

DA0/QACK F2 Output OVDD DRV_STD_MEM (3)(4)(14)

DA1/CKO B15 Output OVDD DRV_STD_MEM (14)

DA2 C25 Output OVDD DRV_PCI (2)

DA3/PCI_CLK4 AF26 Output GVDD DRV_PCI_CLK (14)

DA4/REQ4 Y26 I/O OVDD –(12)(14)

DA5/GNT4 W26 Output OVDD DRV_PCI (7)(14)(15)

DA[10:6]/PLL_CFG[0:4] A22 B19 A21 B18 B17 I/O OVDD DRV_STD_MEM (6)(14)(20)

DA[11] AD26 Output OVDD DRV_PCI (2)

DA[12:13] AF17 AF19 Output OVDD DRV_STD_MEM (2)(6)

DA[14:15] F1 J2 Output GVDD DRV_MEM_CTRL (2)(6)

Table 1. PC8245 Pinout Listing (Continued)

Signal Name Pin Number Type Power

Supply Output Driver Type Notes

10 PC8245 2171D–HIREL–06/04

3. This pin has an internal pul l-up resisto r which is en abled only when the PC8245 is i n the reset state. The value of the inte r-

nal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset.

4. This pin is a reset configuration pin.

5. DL[0] is a reset co nfiguration p in and h as a n internal p ull-up re sistor wh ich is enabled only whe n the PC8 245 is in the rese t

state. The value of the internal pu ll-up re sisto r is no t g uaranteed, but is sufficient to ensure that a logic 1 is read into co nfig-

uration bits during reset.

6. Multi-pin signal s such as AD[31:0] or MDL[0:31] have their physical package pin numbers listed in order, corresponding to

the signal names. Example: AD0 is on pin C22, AD1 is on pin D22, ..., AD31 is on pin V25.

7. GNT4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the PC8245 is in the reset

state.

8. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this PCI control pin to LVDD.

9. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 4 on page 23.

10.Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to OVDD.

11.Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to GVDD.

12.This pin has an internal pull-up resistor which is enabled at all times. The value of the internal pull-up resistor is not guaran-

teed, but is sufficient to prevent unused inputs from floating.

13.External PCI clocking source or fan-out buffer may be required for system if using the PC8245 DUART functionality since

PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.

14.This pin is a multiplexed signal and appears more than once in this table.

15.This pin is affected by programmable PCI_HOLD_DEL parameter.

16.This pin is an open drain signal.

17.This pin can be programmed to be driven (default) or can be programmed (in PMCR2) to be open drain.

18.This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.

19.OSC_IN utilizes the 3.3V PCI interface driver which is 5V tolerant, see Table “Recommended Operating Conditions” on page

12 for details.

20.PLL_CFG[0:4] signals are sampled a fe w clocks after the negatio n of HRST_CPU an d HRST_CTRL.

21.SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals use

DRV_MEM_CLK for chip Rev 1.2 (B).

22.The 266 and 300 MHz part offerings can be ran at a source voltage of 1.8 ± 100 mV or 2.0 ± 100 mV. Note that source volt-

age should be 2.0 ± 100 mV for 333- and 350-MHz parts.

23.This pin was formally LAVDD on the PC8240. It is a no connect on the PC8245. This should not pose a problem when

replacing an PC8240 with an PC8245.

24.The driver capability of this pin is hardwired to 40Ω and cannot be changed.

PC8245

2171D–HIREL–06/04

Electrical and Thermal

Characteristics This section provides the AC and DC electrical specifications and thermal characteris-

tics for the PC8245.

DC Electrical Characteristics This section covers rat ings, conditions, and other characteristics.

Absolute Maximum

Ratings The tables in this section describe the PC82 45 DC electrical characteristics. Following

table provides the absolute maximum ratings.

Notes: 1. Functional and tested operating conditions are given in Table. Absolute maximum rat-

ings are stress ratings only and functional operation at the maximums is not

guaranteed. Stresses beyond those listed may affect device reliability or cause per-

manent damage to the device.

2. PCI inputs with LVDD = 5 V ± 5% V DC may be correspondingly stressed at voltages

exceeding LVDD + 0.5V DC.

Absolute Maximum Ratings

Symbol Characteristic(1) Value Unit

VDD Supply Voltage – CPU Core and Peripheral Logic -0.3 to 2.1 V

GVDD Supply Voltage – Memory Bus Drivers -0.3 to 3.6 V

OVDD Supply Voltage – PCI and Standard I/O Buffers -0.3 to 3.6 V

AVDD/AVDD2 Supply Voltage – PLLs -0.3 to 2.1 V

LVDD Supply Voltage – PCI Reference -0.3 to 5.4 V

VIN Input Voltage(2) -0.3 to 3.6 V

TSTG Storage Temperature Range -65 to 150 °C

12 PC8245 2171D–HIREL–06/04

Recommended

Operating Conditions Fo llowing table provides the r ecommended operating conditions for the PC8245.

Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 5.0V DC pow er supply.

3. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 3.3V DC pow er supply.

4. Caution: Input voltage (VIN) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5V at all times

including during power-on reset. Input voltage (VIN) must not be greater than GVDD/OVDD by more than 0.6V at all times

including during power-on reset.

5. Caution: OVDD must no t exceed VDD/AVDD/AVDD2 by more than 1.8V at any time including during power-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

6. Caution: VDD/AVDD/AVDD2 must not exceed OVDD by more than 0.6V at any time including du ring p ower-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

7. Caution: GVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8V at any time including dur ing power-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

8. Caution: LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4V at any time including during power-on reset. This limit

may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

9. Caution: LVDD must not exceed OVDD by more than 3.0V at any time including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-d own sequences.

Recommended Operating Conditions

Symbol Characteristic(1)(6) Recommended Value Unit Notes

VDD Supply Voltage 2.0 ± 100 mV V (5)

OVDD I/O Buffer supply for PCI and Sta ndard 3.3 ± 0.3 V (5)

GVDD Supply Voltages for Memory Bus Drivers 3.3 ± 5 % V (7)

AVDD CPU PLL Supply Voltage 2.0 ± 100 mV V (5)

AVDD2 PLL Supply Voltag e – Peripheral Logic 2.0 ± 100 mV V (5)

LVDD PCI Reference 5.0 ± 5 % V (2)(8)(9)

3.3 ± 0.3 V (3)(8)(9)

VIN Input Voltage PCI Inputs 0 to 3.6 or 5.75 V (2)(3)

All Other Inputs 0 to 3.6 V (4)

TcTcase -55 to 125 °C

PC8245

2171D–HIREL–06/04

Figure 2 shows supply voltage sequencing and separation cautions.

Figure 2. Supply Voltage Sequencing and Separation Cautions

Notes: 1. Numbers associated with waveform separations correspond to caution numbers listed in Table “Recommended Operating

Conditions” on page 12.

2. Refer to section for additional information.

3. Refer to Table 7 on page 25 for additional informatio n on PLL Relock and reset signal assertion timing requirements.

4. Refer to Table 9 on page 31 for additional informa tion on reset configuration pin setup timing requirements.

5. HRST_CPU/HRST_CTRL must transition from a logi c 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the

device to be in the non-reset state.

GVdd_OVdd/(LVdd at 3.3V ----)

Vdd/AVdd/AVdd2

LVdd at 5V

Time

3.3V

2.0V

10 9

6.8

DC Power Supply Voltage

Voltage

Regulator

Delay(2)

Reset

Configuration Pins

HRST_CPU &

HRST_CTRL

asserted 255

external memory

Clock cycles(3)

9 external memory

clock cycles setup time

(4)

HRST_CPU,

HRST_CTRL

Vdd Stable

See Note (1)

VM = 1.4V

Maximum rise time must be less than

one external memory clock cycle(5)

100 µs

PLL

Relock

Time

(3)

Power Supply Ramp Up

(2)

14 PC8245 2171D–HIREL–06/04

Figure 3 shows the undershoot and overshoot voltage of the memory interface of the

PC8245.

Figure 3. Overshoot/Undershoot Voltage

Thermal Characteristics Table 2 provides the package thermal characteristics for the PC8245. For further infor-

mation, see Section “Thermal Management Information” on page 15.

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the cold plate used for case temperature.

6. Thermal characterization parameter indicating the temperature difference between package top and the junction tempera-

ture per JEDEC JESD 51-2. When Greek letters are no t available, the ther mal characterization pa rameter is written as Psi-

JT.

GVdd_OVvdd + 5%

VIH

VIL

GVdd_OVdd

GND/GNDRING Q - 1.0V

GND/GNDRING - 0.3V

GND/GNDRING

Not to exceed 10%

of tSDRAM_CLK

Table 2. Thermal Characterization Data

Symbol Characteristic Value Unit

RθJA Junction-to-ambient natural convection (Single-layer board—1s)(1)(2) 16.1 °C/W

RθJMA Junction-to-ambient natural convection (F our-layer board—2s2p)(1)(3) 12.0 °C/W

RθJMA Junction-to-ambient (at 200 ft/min) (Single-layer board—1s)(1)(3) 11.6 °C/W

RθJMA Junction-to-ambient (at 200 ft/min)(Four layer board—2s2p)(1)(3) 9.0 °C/W

RθJB Junction-to-Board(4) 4.8 °C/W

RθJC Junction-to-Case(5) 1.8 °C/W

ΨJT Junction-to-package top (natural convection)(6) 1.0 °C/W

PC8245

2171D–HIREL–06/04

Thermal Management

Information This section provides thermal management information for the tape ball grid array

(TBGA) package for air-cooled applications. Depending on the application environment

and the operating frequency, heat sinks may be required to maintain junction tempera-

ture within specifications. Proper thermal control design is primarily dependent upon the

system-level design: the heat sink , airflow, and thermal int erface mater ial. To reduce t he

die-junction temp erature, heat sin ks may be attached to the package by several meth -

ods: adhesive, spri ng clip to holes in the printed-circ uit board or package, or mou nting

clip and screw assembly; see Figure 4.

Figure 4. Package Exploded Cross-Se ctional View with Several Heat Sink Options

Figure 5 depicts the die junction-to-ambient thermal resistance for four typical cases:

• A heat sink is not attached to the TBGA pac kag e and there e xists a hig h board-level

thermal loading from adjacent component s.

• A heat sink is not attached to the TBGA package and there exists a low board-level

thermal loading from adjacent component s.

• A heat sink (for example, ChipCoolers #HTS255-P) is attached to the TBGA

package and there exists high board-level thermal loading from adjacent

components.

• A heat sink (for example, ChipCoolers #HTS255-P) is attached to the TBGA

pac kage and there exists low board-level thermal loading from adjacent

components.

Adhesive

Thermal Interface

Material

Die

Heat Sink TBGA Package

Heat Sink

Clip

Printed-Circuit Board Option

16 PC8245 2171D–HIREL–06/04

Figure 5. Die Junction-to-Ambient Resistance

0 0.5 1 1.5 2 2.5

Airflow Velocity (m/s)

Die Junction-to-Ambient Thermal Resistance (°C/W)

No heat sink and high thermal board-level loading of

adjacent components

No heat sink and low thermal board-level loading of

adjacent components

Attached heat sink and high thermal board-level loading of

adjacent components

Attached heat sink and low thermal board-level loading of

adjacent components

PC8245

2171D–HIREL–06/04

The board designer can choose be tween several types of heat sinks to place on the

PC8245. There are several commercially available heat sinks for the PC8245 provided

by the following vendors:

Ultimately, the final selection of an appropriat e heat sink depe nds on many factors, such

as thermal performance at a given air velocity, spatial volume, mass, attachment

method, assembly, and cost. Other heat sinks offered by Aavid Thermalloy, Alpha

Novatech, The Bergquist Company, IERC, Chip Coolers, and Wakefield Engineering

offer different heat sink-to-ambient thermal resistances, and may or may not need

airflow.

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Inter net: www.aavidthermalloy.com

603-224-9988

Alpha Novatech

473 Sapena Ct. #15

Santa Clara, CA 95054

Inter net: www.alphanovatech.com

408-749-7601

The Bergquist Company

18930 West 78th St.

Chanhassen, MN 55317

Inter net: www.bergquistcompany.com

800-347-4572

Inter national Electronic Research Corporation (IERC)

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

818-842-7277

Tyco Electronics

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Inter net: www.chipcoolers.com

800-522-6752

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

603-635-5102

18 PC8245 2171D–HIREL–06/04

Internal Package Conduction

Resistance For the TBGA, cavity down, packaging technology, shown in Figure 6 , the intrinsic con-

duction thermal resistance paths are as follows:

• the die junctio n -to - case thermal resistan c e,

• the die junction-to-ball thermal resistance.

Figure 6 depicts the primary heat transfer path for a package with an attached heat sink

mounted to a printed-circuit board.

Figure 6. TBGA Package with Heat Sink Mounted to a Printed-Circuit Board

For this die-up, wire-bond TBGA package, heat generated on the active side of the chip

is conducted mainly through the mold cap, the heat sink attach material (or thermal

interface material), and finally through the heat sink where it is removed by forced-air

convection.

Adhesives and Thermal

Interface Mate ria ls A thermal interface ma terial is recommended between the top of the mold cap and the

bottom of the heat sink to minimize the thermal contact resistance. For those applica-

tions where the heat sink is attached by spring clip mechanism, Figure 7 shows the

thermal performance of three thin-sheet thermal-interface materials (silicone, graph-

ite/oil, floroet her oil) , a ba re joint, and a joint with therma l grease as a funct ion of contact

pressure. As shown, the performan ce of these thermal int erface materi als improves with

increasing contact pressure. The use of thermal grease significantly reduces the inter-

face thermal resistance. That is, the bare joint results in a thermal resistance

approximately seven times gr eater than the thermal grease joint.

Heat sinks are attached to the p ackage by means of a spri ng clip to holes in t he p rinte d-

circuit board (s ee F igur e 7). There for e, the sy nthe tic gre ase of fers th e best therm al per-

formance, considering the low interface pressure. Of course, the selection of any

thermal interfa ce material depends on many fact ors: therma l performanc e requirements,

manufacturability, service temperature, dielectric properties, cost, etc.

External Resistance

External Re sistance

Internal Resistance

(Note the internal versus external package resistance)

Radiation Convection

Heat Sink

Printed-Circuit Board

Thermal Interface Material

Die/Substrate/C5 Solder Balls

Die Junction

Mold Cap

PC8245

2171D–HIREL–06/04

Figure 7. Thermal Performance of Select Thermal Interface Material

Contact Pressure (PSI)

Specific Thermal Resistance (K-in.2/W)

Silicone Sheet (0.006 inch)

Bare Joint

Floroether Oil Sheet (0.007 inch)

Graphite/Oil Sheet (0.005 inch)

Synthetic Grease

00 1020304050607080

0.5

1.5

20 PC8245 2171D–HIREL–06/04

The board designer can choose between several types of thermal interface. Heat sink

adhesive materials should be selected based upon high conductivity, yet adequate

mechanical str ength to meet equipment shock/vibra tion requireme nts. There a re several

commercially-available thermal interfaces and adhe sive materials provided by the fol-

lowing vendors:

Heat Sink Usage An estimation of the chip junction temperature, TJ, can be obtained from the equation:

TJ = TA + (RθJA x PD)

where

TA = ambient tempe rature for the package (°C)

RθJA = junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The junction-to- ambien t the rmal resist ance is an indu stry-st andard value tha t provides a

quick and easy estimation of thermal performance. Unfortunately, two values are in

common usage: the value deter mined on a singl e layer bo ard and t he value ob tained on

a board with two plan es. For packa ges such as the TBGA, these values can be diffe rent

by a factor of two. Which value is closer to the application depends on the power dissi-

pated by other components on the board. The value obtained on a single layer board is

appropriate for the tightly packed printed-circuit board. The value obtained on the board

with the internal pla nes is usu ally appr opria te if th e board has low powe r dissipation and

the components are well separated.

When a heat sink is used, the thermal resistance is expressed as th e su m of a junct ion -

to-case thermal resistance and a case-to-ambient thermal resistance:

RθJA = RθJC + RθCA

where

RθJA = junction-to-ambient thermal resistance (°C/W)

RθJC = junction-to-case thermal resistance (°C/W)

RθCA = case-to-ambient thermal resistance (°C/W)

Chomerics, Inc.

77 Dragon Ct.

Woburn, MA 01888-401 4

Inter net: www.chomerics.com

781-935-4850

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

Midland, MI 48686-0997

Inter net: www.dow.com

800-248-2481

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

Inter net: www.microsi.com

888-642-7674

Thermagon Inc.

4707 Detroit Ave.

Cleveland, OH 4410 2

Inter net: www.thermagon.com

888-246-9050

PC8245

2171D–HIREL–06/04

RθJC is device-related and cannot be influenced by the user. The user cont rols the ther-

mal environment to change the case-to-ambient thermal resistance, RθCA. For instance,

the user can change the size of the heat sink, the air flow around the device, the inter-

face material, the mounting arrangement on the printed-circuit board, or the thermal

dissipation on th e pr int ed -c i rcu it bo ar d surr ou n din g th e de vice .

To determine the junction temperature of the device in the application when heat sinks

are not used, the thermal characterization parameter (θJT) can be used to determine the

junction temperature with a measurement of the temperature at the top center of the

package case using the following equation:

TJ = TT + (θJT x PD)

where:

TT = thermocouple temperature atop the package (°C)

θJT = thermal characterization parameter (°C/W)

PD = power dissipation in package (W)

The thermal characterization parameter is measured per JESD51-2 specification using

a 40-gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction re sts on the pack-

age. A small amount o f epoxy is placed over the ther mocouple jun ction and over about 1

mm of wire extending from t he juncti on. The t hermocouple wire is placed fl at aga inst the

package case to avoi d measur em ent err or s cau sed by coo ling eff ects of t he t he rmoco u-

ple wire.

When a heat sink is used, the junction temperature is determined from a thermocouple

inserted at the interface between the case of the package and the interface material. A

clearance slot or hole is normally required in the heat sink. Minimizing the size of the

clearance is important to minimize the change in thermal performance caused by

removing part of the thermal interface to the heat sink. Because of the experimental dif-

ficulties with this technique, many engineers measure the heat sink temperature and

then back calculate the case temperature using a separate measurement of the thermal

resistance of th e inte r face.

From this case temperature, the junction tem perature is det ermined from the junction-to-

case thermal resistance.

In many cases, it is appropriate to simulate the system environment using a computa-

tional fluid dynamics thermal simulation tool. In such a tool, the simplest thermal model

of a package which has demonstrat ed reasonable accuracy (about 20%) is a two-resis-

tor model consisting of a junction-to-board and a junction-to-case thermal resistance.

The junction-to-case covers the situation where a heat sink will be used or where a sub-

stantial amount of heat is dissipated from the top of the package. The junction-to-board

thermal resistance describes the thermal performance when most of the heat is con-

ducted to the printed-circuit board.

References Semiconductor Equipment and Materials International

805 East Middlefield Rd.

Mountain View, CA 9404 3

(415) 964-5111

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering

Documents at 800-854-7179 or 303 -397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

22 PC8245 2171D–HIREL–06/04

Power Characteristics Table 3 provides power consump tion data for the PC8245.

Notes: 1. The values include VDD, AVDD, and AVDD2 but do not include I/O supply power, see Section “Power Supply Sizing” on page

49, for information on OVDD and GVDD supply power. Values shown in parenthesis ( ) indicate power consumption at

VDD/AVDD/AVDD2 = 1.8V

2. Maximum – FP po wer is measured at VDD = 2.1V with dynamic pow er management enabled while running an entirely cache-

resident, looping, floatin g-point multiplication instruction.

3. Maximum – INT power is measured at VDD = 2.1V with dynamic power management enabled while runn ing entirely cache-

resident, looping, integer instructions.

4. Power sa ving mode maximums are measured at VDD = 2.1V while the device is in doze, nap, or sleep mode.

5. Typical power is measured at VDD = AVDD = 2.0V, OVDD = 3.3V wher e a nominal FP value, a nominal INT value, and a value

where there is a continuous flush o f cache lines with alter nating ones and zeros on 64-bit bounda ries to local memor y are

averaged.

6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled

7. The typical minimum I/O power values were results of the PC8245 performing cache resident integer operations at the slow-

est frequency combination of 33:66:200 (PCI:Mem:CPU) MHz

8. The typical maximum OVDD value resulted from th e PC8245 operating at the fastest frequency combination of 66:100:350

(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines wi th alternating ones and zeros to PCI memory.

9. The typical maximum GVDD val ue resulted from the PC8245 operating at the fastest frequ ency combination of 66:100:350

(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit bound-

aries to local memory.

10.Power consumption of PLL supply pins (AVDD and AVDD2) < 15 mW. Guarante ed by design and is not tested.

Table 3. Power Consumption

Mode

PCI Bus Clock/Memory Bus Clock

CPU Clock Frequency (MHz)

Unit Notes66/66/266 66/133/266 66/66/300 66/100/300 33/83/333 66/133/333

Typical 1.7

(1.5) 2.0

(1.8) 1.8

(1.7) 2.0

(1.8) 2.0 2.3 W (1)(5)

Max – FP 2.2

(1.9) 2.4

(2.1) 2.3

(2.)) 2.5

(2.2) 2.6 2.8 W (1)(2)

Max – INT 1.8

(1.6) 2.1

(1.8) 2.0

(1.8) 2.1

(1.8) 2.2 2.4 W (1)(3)

Doze 1.1

(1.0) 1.4

(1.3) 1.2

(1.1) 1.4

(1.3) 1.4 1.6 W (1)(4)(6)

Nap 0.4

(0.4) 0.7

(0.7) 0.4

(0.4) 0.6

(0.6) 0.5 0.7 W (1)(4)(6)

Sleep 0.2

(0.2) 0.4

(0.4) 0.2

(0.4) 0.3

(0.3) 0.3 0.4 W (1)(4)(6)

I/O Power Supplies(10)

Mode Minimum Maximum Unit Notes

Typ – OVDD 134 (121) 334 (301) mW (7)(8)

Typ – GVDD 324 (292) 800 (720) mW (7)(9)

PC8245

2171D–HIREL–06/04

DC Electrical

Characteristics

Static Characteristics Table 4 provides the DC electrical characteristics for the PC8245 at recommended

operating conditions (see Table “Recommended Operating Conditions” on page 12).

Notes: 1. See Table 1 on page 6 for pins with internal pull-up resistors.

2. See Table 5 on page 24 for the typical drive capability of a specific si gnal p in base d on th e type of output dr iver associated

with that pin as listed in Table 1 on page 6.

3. These specifications are for the default driver strengths indicated in Table 5 on page 24.

4. Leakage current is measured on input and output pins in the high-impedance state. The leakage current is measured for

nominal OVDD/LVDD and VDD or both OVDD/LVDD and VDD must vary in the same direction.

Table 4. DC Electrical Specifications

Characteristics Conditions(3) Symbol

Value

UnitMin Max

Input High Voltage(1) PCI only VIH 0.65 x OVDD LVDD V

Input Low Voltage PCI only VIL – 0.3 x OVDD V

Input High Voltage All other pins (GVDD = 3.3V) VIH 2.0 3.3 V

Input Low Voltage All inputs except

PC_SYNC_IN VIL GND 0.8 V

PCI_SYNC_IN Input High Voltage CVIH 2.4 – V

PCI_SYNC_IN Input Low Voltage CVIL GND 0.4 V

Input Leakage Current(4) for pins

using DRV_PC I driver 0.5V ≤ VIN ≤ 2.7V

at LVDD = 4.75 IL– ±70 µA

Input Leakage Current(4)

All others LVDD = 3.6V

GVDD ≤ 3.465 IL– ±10 µA

Output High Voltage IOH = Driver Dependent(2)

(GVDD = 3.3V) VOH 2.4 – V

Output Low Voltage IOL = Driver Dependent(2)

(GVDD = 3.3V) VOL –0.4V

Capacitance(2) VIN = 0V, f = 1 MHz CIN –7.0pF

24 PC8245 2171D–HIREL–06/04

Output Driver

Characteristic Table 5 on page 24 provides information on the characteristics of the output drivers ref-

erenced in Table 1 on page 6. The va lues are preliminary estimates from an IBIS m odel

and are not tested.

Notes: 1. Fo r DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column , at the 0.33V label by inter polating between

the 0.3V and 0.4V table entries’ current values which corresponds to the PCI VOH = 2.97 = 0.9 × OVDD (OVDD = 3.3V) where

table entry voltage = OVDD – PCI VOH.

2. For all others with GVDD or OVDD = 3.3V, IOH read from the IBIS listing in the pull-up mode, I(Min) column , at the 0.9V table

entr y which corresponds to the VOH = 2.4V where table entry voltage = GVDD/OVDD – VOH.

3. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33V = PCI VOL = 0 × OVDD (OVDD =

3.3V) by interpolating between the 0.3V and 0.4V table entries.

4. For all others with GVDD or O VDD = 3. 3V, IOL read from th e IBIS l isting i n the pu ll-do wn mode , I(M in) col umn, at the 0. 4V tab l e

entry.

5. See driver bit details for output driv er control register (0x72) in the "MPC8245 Integrated Processor User’s Manual".

6. See Chip Errata No. 19 in the PC8245/PC8241 RISC Microprocessor Chip Errata’s Motorola.

AC Electrical

Characteristics This section provides the AC electrical characteristics for the PC8245. After fabrication,

functional parts are sorted by maximum processor core frequency as shown in Table 6

and tested fo r conformance to the AC specifications for th at frequency. The processor

core frequency is determ ined by the bus (PCI_SYNC_IN) clock frequency and the set-

tings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core

frequency. See “Ordering Information” on page 56.

Table 7 provides the operating frequency information for the PC8245 at recommended

operating conditions (see Table “Recommended Operating Conditions” on page 12)

with LVDD = 3.3V ± 0.3 V.

Table 5. Drive Capability of PC8245 Output Pins(5)

Driver Type Programmable Output

Impedanc e (Ω) Supply Voltage (V) IOH IOL Unit Notes

DRV_STD_MEM 20

OVDD = 3.3V

36.6 18.0 mA (2)(4)(6)

40 (default) 18.6 9.2 mA (2)(4)(6)

DRV_PCI 20 12.0 12.4 mA (1)(3)

40 (default) 6.1 6.3 mA (1)(3)

DRV_MEM_CTRL

DRV_PCI_CLK

DRV_MEM_CLK

6 (default)

GVDD = 3.3V

89.0 42.3 mA (2)(4)

20 36.6 18.0 mA (2)(4)

40 18.6 9.2 mA (2)(4)

PC8245

2171D–HIREL–06/04

Notes: 1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral

logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:4] signal description in Section “PLL Configuration” on page 45 for v alid PLL_CFG[0:4]

settings and PCI_SYNC_IN frequencies.

2. See Table 16 on page 45 and Table 17 on page 47 for more details on VCO limitations for memory and CPU VCO frequen-

cies of various PLL configurations.

3. There are no available PLL_CFG[0:4] settings which suppor t 133 MHz memory interface operation at 300 MHz CPU and

at 350 MHz operation, since the multipliers do not allow a 300:133 and 350:133 ratio relation. However, running these parts

are slower speeds may produce ratios that will run above 100 MHz. See Table 16 on page 45 for the PLL setti ngs.

Clock AC Specifications Tab le 7 provides the Clock AC timin g specifications at re commended operatin g condi-

tions, as defined in Section “Input AC Timing Specifications” on page 31. These

specifications are for the default driver strengths indicate d in Table 5 on page 24.

At recommended operating conditions (see Table “Recommended Operating Condi-

tions” on page 12) with LVDD = 3.3V ± 0.3V

Notes: 1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4V.

Table 6. Operating Frequency

Characteristic(2)

266 MHz 300 MHz 333 MHz 350 MHz

UnitVDD/AVDD/AVDD2 = 2.0 ± 100 mV VDD/AVDD/AVDD2 = 2.0 ± 100 mV

Processor Frequency (CPU) 100 – 266 100 – 300 100 – 333 100 – 350 MHz

Memory Bus F r eq u enc y 50 – 133 5 0 – 100(3) 50 – 133 50 – 100(3) MHz

PCI Input F requency 25 – 66 MHz

Table 7. Clock AC Timing Specifications

Num Characteristics and Conditions Min Max Unit Notes

1a Frequency of Operation (PCI_SYNC_IN) 25 66 MHz

2, 3 PCI_SYNC_IN Rise and Fall Times – 2.0 ns (1)

4 PCI_SYNC_IN Duty Cycle Measured at 1.4V 40 60 %

5a PCI_SYNC_IN Pulse Width High Measured at 1.4V 6 9 ns (2)

5b PCI_SYNC_IN Pulse Width Low Measured at 1.4V 6 9 ns (2)

7 PCI_SYNC_IN Jitter – 150 ps

8a PCI_CLK[0:4] Skew (Pin-to-Pin) – 250 ps

8b SDRAM_CLK[0:3] Skew (Pin-to-Pin) – 190 ps (3)

10 Internal PLL Relock Time – 100 µs (2)(4)(5)

15 DLL Lock Range with DLL_EXTEND = 0 Disabled (Default) (N x TCLK – Tdp(max)) ≤ Tloop

≤ (N x TCLK – Tdp(min)) ns (6)

16 DLL Lock Range with DLL_EXTEND = 1 Enabled ((N – 0.5) x TCLK – Tdp(max))

≤ Tloop ≤ ((N – 0.5) TCLK –

Tdp(min)) ns (6)

17 Frequency of Operation (OSC_IN) 25 66 MHz

19 OSC_IN Rise and Fall Times – 5 ns (7)

20 OSC_IN Duty Cycle Measured at 1.4V 40 60 %

21 OSC_IN Frequency Stability – 100 ppm

26 PC8245 2171D–HIREL–06/04

2. Specification value at maximum frequency of operation.

3. Pin-to-pin skew includes quantifying the additional amount of clock ske w (or jitter) from the DLL besides any intentional skew

added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance

between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew betw een

SDRAM_CLKs can be measured, the relationship between the inter nal sys_logic_clk and the external SDRAM_SYNC_IN

cannot be measured and is guaranteed by design.

4. Relock time is guaranteed by design and characterization. Relock time is not tested.

5. Relock timing is guaranteed by design. PLL-relock time is the ma ximum amount of time required for PLL lock after a stable

VDD and PCI_SYNC_IN are reached dur ing th e reset sequen ce. This specification also applies when the PLL has been dis-

abled and subsequently re-enabled duri ng sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asser ted for

a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.

6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). TCLK is the period of one

SDRAM_SYNC_OUT clock cycle in ns. Tloop is the propaga tion delay of the DLL synchroniza tion feedback loo p (PC board

runner) from SDRAM_SYNC_OUT to SD RAM_ SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) cor-

responds to approximately 1 ns of delay. Tfix0 is a fixed delay inherent in the design when the DLL is at tap point 0 and the

DLL is contributing no delay; Tfix0 equals approximately 3 ns. See Figure 9 through Figure 12 for DLL locking ranges.

7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input r ise a nd fall times are

not tested.

Figure 8. PCI_SYNC-IN Inpu t Clock Timing Diagram

Figure 9 through Figure 12 show the DLL locking range loop delay vs. frequency of operation.These graphs define the

areas of DLL locking for various modes. The grey areas represent where the DLL will lock.

Note also that the DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished by

increasing the time between each of the 128 tap points in the delay line. Although this increased time makes it easier to

guarantee that the refer ence clock will be within the DLL lock range, it also means there may be slightly more jitter in the

output clock of the DLL, should the phase comparator shift the clock between adjacent tap points.

5a 5b

VM VM VM CVIH

CVIL

VM = Midpoint Voltage (1.4V)

PCI_SYNC_IN

Table 8. Tdp(max) and Tdp(min)

Mode Tdp (min) Tdp (max) Unit

Nor m al tap delay : Bit 2 (DLL_MAX_DELAY) at offset 0 x 76 is cleared 7.58 12.97 ns

Maximum tap delay: Bit 2 (DLL_MAX_DELAY) at offset 0 x 76 is set 8.28 17.57 ns

PC8245

2171D–HIREL–06/04

Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1 and Normal Ta p Delay

Tclk SDRAM_OUT Period (ns)

Tloop Propagation Delay Time (ns)

27.5

22.5

17.5

12.5

7.5

01234

N = 1

N = 2

28 PC8245 2171D–HIREL–06/04

Figure 10. DLL Locking Range Loop Delay vs. Freq uency of Operation for DLL_Extend = 1 and Tap Max Delay

Tclk SDRAM_OUT Period (ns)

Tloop Propagation Delay Time (ns)

27.5

22.5

17.5

12.5

7.5

01234

N = 1

N = 2

PC8245

2171D–HIREL–06/04

Figure 11. DLL Locking Range Loop Delay vs. Frequency of Operat ion for DLL_Extend = 0 and Norma l Tap Delay

Tclk SDRAM_OUT Period (ns)

Tloop Propagation Delay Time (ns)

22.5

17.5

12.5

7.5

01234

N = 1

N = 2

30 PC8245 2171D–HIREL–06/04

Figure 12. DLL Locking Range Loop Delay vs. Frequency of Operat ion for DLL_Extend = 0 and Norma l Tap Delay

Tclk SDRAM_OUT Period (ns)

Tloop Propagation Delay Time (ns)

22.5

17.5

12.5

7.5

01234

N = 1

N = 2

PC8245

2171D–HIREL–06/04

Input AC Timing

Specifications Table 9 provides the input AC timing specifications at recommended ope rating condi-

tions (see Table “Recommended Operating Conditions” on page 12) with LVDD = 3.3V ±

0.3V. See Figure 13 and Figure 14.

Notes: 1. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 x OVDD of the signal in question for

3.3V PCI signaling levels. See Figure 14.

2. All memor y and related inte rface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in

question to the VM = 1.4V of the rising ed ge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same

as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memor y bus clock r ising edges occur on

every rising and falling edge of PCI_SYNC_IN). See Figure 13.

3. Input timings are measured at the pin.

4. TCLK is the time of one SDRAM_SYNC_IN clock cycle.

5. All mode select input signals specifications are measured from the TTL lev e l (0.8 or 2.0V) of the signal in question to the VM

= 1.4V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 15.

6. The memor y interface input setup and hold times a re programmable to fo ur possible combinations by programming bits 5:4

of register offset <0x77> to select the desired in put setup and hold times.

7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present

on the SDRAM_SYNC_IN sign al with respect to the sys_logic_ clk inputs to the DLL, the resulting SDRAM clocks become

offset by the delay amount. The feedback tr ace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened by

this amount relative to the SDRAM clock output trace lengths to maintain phase-alignment of the memory clocks with

respect to sys_logic_clk. Note that the DLL locking range graphs of Figure 9 through Figure 12 compensate for

Tos and there is no additional requirement to shorten Tloop by the duration of Tos. Refer to Motorola Applica-

tion Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more details on accommodating

for the proble m of Tos and trace measurements in general.

Table 9. Input AC Timing Specifications

Num Characteristic Min Max Unit Notes

10a PCI Input Signals Valid to PCI_SYNC_IN (Input Setup) 3.0 – ns (1)(3)

10b Memory Input Signals Valid to SDRAM_SYNC_IN (Input Setup )

10b0 Tap 0, Register Offset <0x77>, Bits 5:4 = 0b10 2.6 –

ns (2)(3)(6)

10b1 Tap 1, Register Offset <0x77>, Bits 5:4 = 0b11 1.9 –

10b2 Tap 2, Register Offset <0x77>, Bits 5:4 = 0b00 (Default) 1.2 –

10b3 Tap 3, Register Offset <0x77>, Bits 5:4 = 0b01 0.5 –

10c Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup) 3.0 – ns (2)(3)

10d Two-wire interface Input Signals Valid to SDRAM_SYNC_IN (Input Setup) 3.0 – ns (2)(3)

10e Mode Select Inputs Valid to HRST_CPU/HRST_CTRL (Input Setup) 9 x TCLK –ns

(2)(3)(4)(5)

11 Tos – SDRAM_SYNC_IN to sys_logi c_clk offset time 0.65 1.0 ns (7)

11a SDRAM_SYNC_IN to Memory Signal Inputs Invalid (Input Hold)

11a0 Tap 0, Register Offset <0x77>, Bits 5:4 = 0b10 0 –

ns (2)(3)(6)

11a1 Tap 1, Register Offset <0x77>, Bits 5:4 = 0b11 0.7 –

11a2 Tap 2, Register Offset <0x77>, Bits 5:4 = 0b00 (Default) 1.4 –

11a3 Tap 3, Register Offset <0x77>, Bits 5:4 = 0b01 2.1 –

11b HRST_CPU/HRST_CTRL to Mode Select Inputs Invalid (Input Hold) 0 – ns (2)(3)(5)

11c PCI_SYNC_IN to Inputs Invalid (Input Hold) 1.0 – ns (1)(2)(3)

32 PC8245 2171D–HIREL–06/04

Figure 13. Input – Output Timing Diagram Referenced to SDRAM_SYNC_IN

Notes:

VM = midpoint voltage (1.4V).

11a = input hold time of SDRAM_SYNC_IN to memory.

12b-d = SDRAM_SYNC_IN to output valid timing.

13b = output hold time for non-PCI signals.

14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.

Tos = offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal is adjusted by

the DLL to accommodate for inter nal delay. This causes SDRAM_SYNC_IN to be seen before sys_logic_clk once the DLL

locks, if no ot her accommodation is made for the delay.

10b-d = input signals valid timing.

Figure 14. Input – Output Timing Diagram Referenced to PCI_SYNC_IN

11a

Memory

10b-d

Inputs/Outputs

13b

14b

SDRAM_SYNC_IN

Input Timing Output Timing

12b-d

2.0 V

0.8 V

2.0 V

T os

sys_logic_clk VM

PCI_SYNC_IN VM

(After DLL Locks

Shown in 2:1 Mode

if no compensation

for T os is made)

OVdd/2

10a

11c

PCI_SYNC_IN

PCI

12a 13a

14a

OVdd/2

0.4*OVdd 0.615*OVdd

0.285*OVdd

Input Timing Output Timing

INPUTS/OUTPUTS

PC8245

2171D–HIREL–06/04

Figure 15. Input Timing Diagram for Mode Select Signals

Output AC Timing

Specification Table 10 provides the processor bus AC timing specifications for the PC8245 at recom-

mended operating conditions (see Table “Recommended Operating Conditions” on

page 12) with LVDD = 3.3V ± 0.3V. See Figure 13 on pa ge 32. All output timings assume

a purely resistive 50Ω load (see Figure 16 on page 34). Output timings are measured at

the pin; time -of-flight delays must b e added for t race lengt hs, vias, and con nectors in the

system. These specifications are for the default driver strengths indicated in Table 5 on

page 24.

Notes: 1. All PCI signals a re measured from GVDD_OVDD/2 of the rising edge of PCI_SYNC_IN to 0.2 85 × OVDD or 0.615 × OVDD of

the signal in question for 3.3V PCI signaling levels. See Figure 14 on page 32.

2. All memory and related interf ace output signal specifications are specified from the VM = 1.4V of the rising edge of the mem-

or y bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as

PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on

every rising and fa lling edge of PCI_SYNC_IN). See Figure 13 on page 32.

VM = Midpoint Voltage (1.4V)

11b

MODE PINS

10e

HRST_CPU/HRST_CTRL

2.0V

0.8V

Table 10. Output AC Timing Specifications

Num Characteristics Min Max Unit Notes

12a PCI_SYNC_IN to Output Valid, see Figure 17 on page 35

12a0 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (Default) – 6.0

ns (1)(3)

12a1 Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10 – 6.5

12a2 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI – 7.0

12a3 Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00 – 7.5

12b SDRAM_SYNC_IN to Output Valid (Memory Control and Data Signals) – 4.5 ns (2)

12c SDRAM_SYNC_IN to Output Valid (For All Others) – 7.0 ns (2)

12d SDRAM_SYNC_IN to Output Valid (For Two-wire interface)–5.0ns

(2)

12e SDRAM_SYNC_IN to Output Valid (ROM/Flash/PortX) – 6.0 ns (2)

13a Output Hold (PCI), see Figure 17

13a0 Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (Default) 2.0 –

ns (1)(3)(4)

13a1 Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10 2.5 –

13a2 Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI 3.0 –

13a3 Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00 3.5 –

13b Output Hold (All Others) 1.0 – ns (2)

14a PCI_SYNC_IN to Output High Impedance (For PCI) – 14.0 ns (1)(3)

14b SDRAM_SYNC_IN to Output High Impedance (For All Others) – 4.0 ns (2)

34 PC8245 2171D–HIREL–06/04

3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP, DEVSEL,

PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, INTA.

4. In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 and 66 MHz PCI systems, the

PC8245 has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also affected).

The initial value of the output hold delay is de termined by the values on the MCP and CKE reset configuration signals; the

values on these two signals are inver ted then stored as the initial setting s of PCI_HOLD_DEL = PMCR2[5:4] (power man-

agement configuration register 2 <0x72>), respectively. Since MCP and CKE have internal pull-up resistors, the default

value of PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the

PCI_HOLD_DEL value of the PMCR2 configuration register. See Fig ure 17 on page 35.

Figure 16. AC Test Load for the PC82 45

OUTPUT Z0 = 50ΩOVDD/2 for PCI

OVDD/2 for Memory

RL = 50Ω

Output measurements are made at the device pin

PC8245

2171D–HIREL–06/04

Figure 17. PCI_HOLD_DEL Affect on Output Valid and Hold Time

Note: Diagram not to scale

PCI_SYNC_IN

PCI INPUTS/OUTPUTS

33 MHz PCI

12a, 8 ns for 33 MHz PCI

PCI_HOLD_DEL = 10

12a0, 5.5 ns for 66 MHz PCI

PCI_HOLD_DEL = 00

13a, 2.1 ns for 33 MHz PCI

PCI_HOLD_DEL = 10

13a0, 1 ns for 66 MHz PCI

PCI_HOLD_DEL = 00

OUTPUT VALID OUTPUT HOLD

As PCI_HOLD_DEL

values decrease

As PCI_HOLD_DEL

values increase

PCI INPUTS

and OUTPUTS

PCI INPUTS/OUTPUTS

66 MHz PCI

0Vdd/2 0Vdd/2

36 PC8245 2171D–HIREL–06/04

I2C AC Timing Specifications Table 11 provides the I2C interf ace input AC ti ming spe cificat ions fo r the PC8245 a t rec-

ommended operating conditions (see Table “Recommended Operating Conditions” on

page 12) with LVDD = 3.3V ± 0.3V.

Notes: 1. Units for these specifications are in SDRAM_CLK units.

2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency divider

register I2CFDR. Therefore, the n oted timings in the above table are all relative to qualified signals. The qualified SCL a nd

SDA are delayed signals from what is seen in real time on the I2C interface bus. The qualified SCL, SDA signals are

delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay va lue is added to

the value in the table (where this note is referenced). See Figure 19 on page 39.

3. Timing is relative to the Sampling Clock (not SCL).

4. FDR[x] refers to the Frequen cy Divider Register I2CFDR bit x.

5. Input clock low and high periods in combination with the FDR value in the Freque ncy Divider Register (I2CFDR) deter mine

the maximum I2C interface input frequency. See Table 12.

Table 11. I2C interface Input AC Timing Specifications

Number Characteristics Min Max Unit Notes

1 Start condition hold time 4.0 – CLKs (1)(2)

Clock low period

(time before the PC8245 will drive SCL low as a

transmitting slave after detecting SCL low as driven

by an external master.)

8.0 + (16 x 2FDR[4:2]) x (5 -

4({FDR[5],FDR[1 ]} == b’10) -

3({FDR[5],FDR[1 ]} == b’11) -

2({FDR[5],FDR[1 ]} == b’00) -

1({FDR[5],FDR[1]} == b’01))

–CLKs

(1)(2)(4)(5)

3 SCL/SDA rise time (from 0.5V to 2.4V) – 1 ms

4 Data hold time 0 – ns (2)

5 SCL/SDA fall time (from 2.4V to 0.5V) – 1 ms

6Clock high period

(Time needed to either receive a data bit or

generate a START or STOP.) 5.0 – CLKs (1)(2)(5)

7 Data setup time 3.0 – ns (3)

8Start condition setup time (for repeated start

condition only) 4.0 – CLKs (1)(2)

9 Stop condition setup time 4.0 – CLKs (1)(2)

PC8245

2171D–HIREL–06/04

Table 12 provides the I2C Interface Frequency Divider Register (I2CFDR) information for the PC8245.

Notes: 1. Values are in kHz unless otherwise specified.

2. FDR Hex and Divider (Dec) values are listed in corresponding order.

3. Multiple Divider (Dec) values will generate the same input frequency, but each Divider (Dec) value will generate a unique

output frequency as shown in Table 13.

Table 12. PC8245 Ma xim u m I2C Interface Input Frequency

FDR Hex(2) Divider (Dec)(2)(3)

Max I2C Interface Input Frequency(1)

SDRAM_CLK

at 33 MHz SDRAM_CLK

at 50 MHz SDRAM_CLK

at 100 MHz SDRAM_CLK

at 133 MHz

20, 21 160, 192 1.13 MHz 1.72 MHz 3.44 MHz 4.58 MHz

22, 23, 24, 25 224, 256, 320, 384 733 1.11 MHz 2.22 MHz 2.95 MHz16

0, 1 288, 320 540 819 1.63 MHz 2.18 MHz

2, 3, 26, 27, 28, 29 384, 448, 480, 5 12, 640, 768 428 649 1.29 MHz 1.72 MHz

4, 5 576, 640 302 458 917 1.22 MHz

6, 7, 2A, 2B, 2C, 2D 768, 896, 960, 1024, 1280, 1536 234 354 709 943

8, 9 1152, 1280 160 243 487 648

A, B, 2E, 2F, 30, 31 1536, 1792, 1920, 2048, 2560,

3072 122 185 371 494

C, D 2304, 2560 83 125 251 335

E, F, 32, 33, 34, 35 3072, 3584, 3840, 4096, 5120,

6144 62 95 190 253

10, 11 4608, 5120 42 64 128 170

12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192, 10240,

12288 31 48 96 128

14, 15 9216, 10240 21 32 64 85

16, 17, 3A, 3B, 3C, 3D 12288, 14336, 15360, 16384,

20480, 24576 16 24 48 64

18, 19 18432, 20480 10 16 32 43

1A, 1B, 3E, 3F 245 76, 28672, 30720, 32768 8 12 24 32

1C, 1D 36864, 40960 5 8 16 21

1E, 1F 49152, 61440 4 6 12 16

38 PC8245 2171D–HIREL–06/04

Table 13 provides the I2C interface output AC timing specifications for the PC8245 at recommended operating conditions

(see Table “Recommended Operating Conditions” on page 12) with LVDD = 3.3V ± 0.3V.

Notes: 1. Units for these specifications are in SDRAM_CLK units.

2. The actual values depend on the setting of the digital filter frequency sampling rate (DFFSR) bits in the frequency divider

register I2CFDR. Therefore, the n oted timings in the above table are all relative to qualified signals. The qualified SCL a nd

SDA are delayed signals from what is seen in real time on the I2C interface bus. The qualified SCL, SDA signals are

delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay va lue is added to

the value in the table (where this note is referenced). See Figure 19.

3. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to Ta ble 10-5 in the "MPC8245 Integrated Processor

User’s Manual". FDR[x] refers to the frequency divider register I2CFDR bit x. N is equal to a variable number that would

make the result of the divide (data hold time value) equal to a number less than 16. M is equal to a variable number that

would make the result of the divide (data hold time value) equal to a number less than 9.

4. Since SCL and SDA are open-drain type outputs, which the PC8245 can only drive low, the time required for SCL or SDA to

reach a high level depends on external signal capacitance and pull-up resistor values.

5. Specified at a nominal 50 pF load.

Figure 18. I2C Interface Timin g Dia gr am I

Table 13. I2C Interface Outp ut AC Timin g Spe cif ica tio ns

Number Characteristics Min Max Unit Notes

1 Start condition hold time (FDR[5] == 0) x (DFDR/16)/2N +

(FDR[5] == 1) x (DFDR/16)/2M –CLKs

(1)(2)(3)

2 Clock low period DFDR/2 – CLKs (1)(2)(3)

3 SCL/SDA rise time (from 0.5V to 2.4V) – – ms (4)

4 Data hold time

8.0 + (16 x 2FDR[4:2]) x (5 -

4({FDR[5],FDR[1]} == b’10) -

3({FDR[5],FDR[1]} == b’11) -

2({FDR[5],FDR[1]} == b’00) -

1({FDR[5],FDR[1]} == b’01))

–CLKs

(1)(2)(3)

5 SCL/SDA fall time (from 2.4V to 0.5V) < 5 ns (5)

6 Clock high time DFDR/2 – CLKs (1)(2)(3)

7 Data setup time (PC8245 as a master only) (DFDR/2) – (Output data hold time) – CLKs (1)(3)

8Start condition setup time (for repeated start

condition only) DFDR + (Output start condition hold

time) –CLKs

(1)(2)(3)

9 Stop condition setup ti me 4.0 – CLKs (1)(2)

SCL

SDA

VM VM

1 4

PC8245

2171D–HIREL–06/04

Figure 19. I2C Interface Timin g Dia gr am II

Figure 20. I2C Interface Timin g Dia gr am III

Figure 21. I2C Interface Timin g Dia gr am IV (Qualified signal)

SCL

SDA

VM VL

INPUT DATA VALID

DFFSR FILTER CLK (1)

SDA

Note 1: DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value.

SCL/SDArealtime VM

SCL/SDAqualified VM

Delay (1)

Note 1: The delay is the Local Memory clock times DFFSR times 2 plus 1 Local Memory clock.

40 PC8245 2171D–HIREL–06/04

EPIC Serial Interrupt Mode AC

Timing Specifications Table 14 provides the EPIC serial interrupt mode AC timing specifications for the

PC8245 at recommended operating conditions (see Table “Recommended Operating

Conditions” on page 12) with GVDD = 3.3V ± 5% and LVDD = 3.3V ± 0.3V.

Notes: 1. See the "MPC8245 Integrated Processor User’s Manual" for a description of the EPIC interrupt control register (EICR)

describing S_CLK frequency programming.

2. S_RST, S_FRAME, and S_INT shown in Figure 22 and Figure 23, depict timing relationships to sys_logic_clk and S_CLK

and do not describe functional relationships between S_RST, S_FRAME, and S_INT. See the "MPC8245 Integrated Proces-

sor User’s Manual" for a complete descrip tion of the functional relationships between these signals.

3. The sys_logic_clk wa veform is the clocking signal of the inter nal peripheral logic from the output of the peripheral logic PLL;

sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is

implemented and the DLL is locked. See the "MPC8245 Integrated Processor User’s Manual" for a complete clocking

description.

Figure 22. EPIC Serial Inte rru p t Mo de Out put Tim i n g Dia gr am

Table 14. EPIC Serial Interrupt Mode AC Timing Specifications

Number Characteristics Min Max Unit Notes

1 S_CLK Frequency 1/14 SDRAM_SYNC_IN 1/2 SDRAM_SYNC_IN MHz (1)

2 S_CLK Duty Cycle 40 60 % –

3 S_CLK Output Valid Time –6ns–

4 Output Hold Time 0 –ns –

5S_FRAME, S_RST Output Valid

Time –1 sys_logic_clk period + 6 ns (2)(3)

6 S_INT Input Setup Time to S_CLK 1 sys_logic_clk period + 2 –ns (2)(3)

7 S_INT Inputs Invalid (Hold Time)

to S_CLK – 0ns

(2)

S_CLK

S_RST

S_FRAME

sys_logic_clk3

PC8245

2171D–HIREL–06/04

Figure 23. EPIC Serial Interrupt Mode Input Timing Diagram

IEEE 1149.1 (JTAG) AC Timing

Specifications Table 15 provides th e JTAG AC timing specifications for the PC8245 while in the JTAG

operating mode at recommended operating conditions (see Table “Recommended

Operating Cond itio n s ” on pa ge 12 ) with LVDD = 3.3V ± 0.3V. Timings are independent of

the system clock (PCI_SYNC_IN).

Notes: 1. TRST is an asynchronous signal. Th e setup time is for test purpo s es only.

2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.

3. Nontest (other than TDO) signal output timing with respect to TCK.

Figure 24. JTAG Clock Input Timing Diagram

S_CLK

S_INT

Table 15. JTAG AC Timing Specifications (Independent of PCI_SYNC_IN)

Number Characteristics Min Max Unit Notes

TCK Frequency of Operation 0 25 MHz

1 TCK Cycle Time 40 –ns

2 TCK Clock Pulse Width Measured at 1.5V 20 –ns

3 TCK Rise and Fall Times 0 3 ns

4TRST

Setup Time to TCK Falling Edge 10 –ns (1)

5TRST Assert Time 10 –ns

6 Input Data Setup Time 5 –ns (2)

7 Input Data Hold Time 15 –ns (2)

8 TCK to Output Data Valid 0 30 ns (3)

9 TCK to Output High Impedance 0 30 ns (3)

10 TMS, TDI Data Setup Time 5 –ns

11 TMS, TDI Data Hold Time 15 –ns

12 TCK to TDO Data Valid 0 15 ns

13 TCK to TDO High Impedance 0 15 ns

TCK

22 1

VM = Midpoint Voltage

42 PC8245 2171D–HIREL–06/04

Figure 25. JTAG TRST Timing Diagram

Figure 26. JTAG Boundary Scan Timing Diag ram

Figure 27. Test Access Port Timing Diagram

TRST

TCK

DATA INPUTS INPUT VALID DATA

OUTPUT VALID DATADATA OUTPUTS

DATA OUTPUTS

10 11

TCK

TDI, TMS INPUT VALID DATA

OUTPUT VALID DATATDO

TDO

PC8245

2171D–HIREL–06/04

Package Description This section details package parameters, pin assignments, an d dimensions.

Package Parameters for

the PC8245 The PC8245 uses a 35 mm x 35 mm, cavity up, 352-pin tape ball grid array (TBGA)

package. The package parameters are as follows:.

Package Outline 35 mm x 35 mm

Interconnects 352

Pitch 1.27 mm

Solder Balls 62 Sn/36 Pb/2 Ag

Solder Balls Diameter 0.75 mm

Maximum Module Height 1.65 mm

Co-planarity Specification 0.15 mm

Maximum Fo rce 6.0 lbs. total, unifo rmly distributed over package (8 grams/ball)

44 PC8245 2171D–HIREL–06/04

Pin Assignments and

Package Dimensions Figure 28 shows the top surface, side profile, and pinout of the PC8245, 352 TBGA

package.

Figure 28. PC8245 Package Dimensions and Pinout Assignments

- E -

- F -

0.150

- T -

25 23 21 19 17 15 13 11 9 7 5 3 1

352X ∅ D

Top View

26 24 22 20 18 16 14 12 10 8 6 4 2

CORNER

Bottom View

1. Drawing not to scale.

2. All measurements are in millimeters (mm).

Notes:

Min Max

A 34.8 35.2

B 34.8 35.2

C 1.45 1.65

D 0.60 0.90

G 1.27 BASIC

H 0.85 0.95

K 31.75 BASIC

L 0.50 0.70

PC8245

2171D–HIREL–06/04

PLL Configuration The internal PLLs of the PC8245 are config ured by the PLL_CFG[0:4] signals. For a

given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the

peripheral lo gic/memory bus PLL (VCO) frequency of op eration for the PCI-to-mem ory

frequency multiplying an d the PC603e CPU PLL (VCO) frequen cy of operat ion for mem-

ory-to-CPU frequency multiplying. The PLL configurations for the PC8245 is shown in

Table 16 and Table 17.

Table 16. PLL Configurations (266 and 300 MHz Parts)

Ref PLL_ CFG

[0:4](10)(13)

266 MHz Part(9) 300 MHz Part(9) Multipliers

PCI Clock

Input (PCI_

SYNC_IN)

Range(1)

(MHz)

Periph

Logic/

Mem Bus

Clock

Range

(MHz)

CPU Clock

Range

(MHz)

PCI Clock

Input

(PCI_

SYNC_IN)

Range(1)

(MHz)

Periph

Logic/Mem

Bus Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI to

Mem

(Mem

VCO)

Mem to

CPU

(CPU

VCO)

0 00000(12) 25 – 35(5)(16) 75 – 105 188 – 263 25 – 40(5) 75 – 120 188 – 300 3(2) 2.5(2)

1 00001(12) 25 – 29(5) 75 – 88 225 – 264 25 – 33(5) 75 – 99 225 – 297 3(2) 3(2)

2 00010(11) 50(18) – 59(5) 50 – 59 225 – 26 6 50(18) –

66(1) 50 – 66 225 – 297 1(4) 4.5(2)

3 00011(11)(14) 50(4) – 66(1) 50 – 66 100 – 133 50(4) – 66(1) 50 – 66 100 – 133 1 (Bypass) 2(4)

4 00100(12) 25 – 46(4) 50 – 92 100 – 184 25 – 46(4) 50 – 92 100 – 184 2(4) 2(4)

5 00101 Reserved Reserved Note (20)

6 00110(15) Bypass Bypass Bypass

7 00111(14) 60(6) – 66(1) 60 – 66 180 – 198 60(6) – 66(1) 60 – 66 180 – 198 1 (Bypass) 3(2)

8 01000(12) 60(6) – 66(1) 60 – 66 180 – 198 60(6) – 66(1) 60 – 66 180 – 198 1(4) 3(2)

9 01001(19) 45(6) – 66(1) 90 – 132 180 – 264 45(6) – 66(1) 90 – 132 180 – 264 2(2) 2(2)

A 01010(12) 25 – 29(5) 50 – 58 225 – 261 25 – 33(5) 50 – 66 225 – 297 2(4) 4.5(2)

B 01011(19) 45(3) – 59(5) 68 – 88 204 – 264 45(3) – 66(1) 68 – 99 204 – 297 1.5(2) 3(2)

C 01100(12) 36(6) – 46(4) 72 – 92 180 – 230 36(6) – 46(4) 72 – 92 180 – 230 2(4) 2.5(2)

D 01101(19) 45(3) – 50(5) 68 – 75 238 – 263 45(3) – 57(5) 68 – 85 238 – 298 1.5(2) 3.5(2)

E 01110(12) 30(6) – 44(5) 60 – 88 180 – 264 30(6) – 46(4) 60 – 92 180 – 276 2(4) 3(2)

F 01111(19) 25(5) 75 263 25 – 28(5) 75 – 85 263 – 298 3(2) 3.5(2)

10 10000(12) 30(6) –

44(2)(5) 60 – 132 180 – 264 30(6) – 44(2) 60 – 132 180 – 264 3(2) 2(2)

11 10001(19) 25 – 26(5) 100 – 106 250 – 266 25 – 29(2) 100 – 116 250 – 290 4(2) 2.5(2)

12 10010(12) 60(6) – 66(1) 90 – 99 180 – 198 60(6) – 66(1) 90 – 99 180 – 198 1.5(2) 2(2)

13 10011(19) Not Available 25(2) 100 300 4(2) 3(2)

14 10100(12) 26(6) – 38(5) 52 – 76 182 – 266 26(6) – 42(5) 52 – 84 182 – 294 2(4) 3.5(2)

15 10101(19) Not Available 27(3) – 30(5) 68 – 75 272 – 300 2.5(2) 4(2)

16 10110(12) 25 – 33(5) 50 – 66 200 – 264 25 – 37(5) 50 – 74 200 – 296 2(4) 4(2)

17 10111(19) 25 – 33(5) 100 – 132 200 – 264 25 – 33(2) 100 – 132 200 – 264 4(2) 2(2)

18 11000(12) 27(3) – 35(5) 68 – 88 204 – 26 4 27(3) – 40(5) 68 – 100 204 – 300 2.5(2) 3(2)

46 PC8245 2171D–HIREL–06/04

Notes: 1. Limited by maximum PCI input frequency (66 MHz).

2. Limited by maximum system memory interface operating frequency (100 MHz at 350 MHz CPU).

3. Limited by minimum memory VCO frequency (133 MHz).

4. Limited due to maximum memory VCO frequency (372 MHz).

5. Limited by maximum CPU operating frequency (266 MHz).

6. Limited by minimum CPU VCO frequency (360 MHz).

7. Limited by maximum CPU VCO frequency (800 MHz).

8. In clock off mode, no clocking occurs inside the PC8245 regardless of the PCI_SYNC_IN input.

9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.

10.PLL_CFG[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved.

11.Mult ip l i er ratios for this PLL_CFG[0:4] setting ar e di fferent from the PC8240 and are not backwards-compatible.

12.PCI_SYNC_IN range for this PLL_CFG[0:4] setting is diff erent from the PC8240 and may not be fully backw ards-compatible .

13.Bits 7– 4 of register offset <0xE2> contain the PLL_ C FG[0:4] setting value.

14.In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is dis-

abled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling suppor t.

The AC timing specifications given in this document do not apply in PLL bypass mode.

15.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic

PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input sig-

nal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The

PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling

support. The AC timing specifications given in this document do not apply in dual PLL bypass mode.

16.Limited by maximum system memory interface operating frequency (133 MHz at 266 MHz CPU).

17.Limited by minimum CPU operating frequency (100 MHz).

18.Limited by minimum memory bus frequency (50 MHz).

19.PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the PC8240 and may not be fully backwards-

compatible.

20.No longer supported.

19 11001(19) 36(6) – 53(5) 72 – 106 180 – 265 36(6) – 59(2) 72 – 118 180 – 295 2(2) 2.5(2)

1A 11010(12) 50(18) – 66(1) 50 – 66 200 – 264 50(18) –

66(1) 50 – 66 200 – 264 1(4) 4(2)

1B 11011(19) 33(6) – 44(5) 66 – 88 198 – 264 33(6) – 50(5) 66 – 100 198 – 300 2(2) 3(2)

1C 11100(12) 44(6) – 59(5) 66 – 88 198 – 26 4 44(6) – 66(1) 66 – 99 198 – 297 1.5(2) 3(2)

1D 11101(12) 48(6) – 66(1) 72 – 99 198 – 248 48(6) – 66(1) 72 – 99 180 – 248 1.5(2) 2.5(2)

1E 11110(8) Not Usable Not Usable Off Off

1F 11111(8) Not Usable Not Usable Off Off

Table 16. PLL Configurations (266 and 300 MHz Parts) (Continued)

Ref PLL_ CFG

[0:4](10)(13)

266 MHz Part(9) 300 MHz Part(9) Multipliers

PCI Clock

Input (PCI_

SYNC_IN)

Range(1)

(MHz)

Periph

Logic/

Mem Bus

Clock

Range

(MHz)

CPU Clock

Range

(MHz)

PCI Clock

Input

(PCI_

SYNC_IN)

Range(1)

(MHz)

Periph

Logic/Mem

Bus Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI to

Mem

(Mem

VCO)

Mem to

CPU

(CPU

VCO)

PC8245

2171D–HIREL–06/04

Table 17. PLL Configurations (333 and 350 MHz Parts)

Ref PLL_ CFG

[0:4](10)(13)

333 MHz Part(9) 350 MHz Part(9) Multipliers

PCI Clock

Input

(PCI_

SYNC_IN)

Range(1)

(MHz)

Periph

Logic/

Mem Bus

Clock

Range

(MHz)

CPU Clock

Range

(MHz)

PCI Clock

Input

(PCI_

SYNC_IN)

Range(1)

(MHz)

Periph

Logic/ Mem

Bus Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI to

Mem

(Mem

VCO)

Mem to

CPU

(CPU

VCO)

0 00000(12) 25 – 44(16) 75 – 132 188 – 330 25 – 44(16) 75 – 132 188 – 330 3(2) 2.5(2)

1 00001(12) 25 – 37(5) 75 – 111 225 – 333 25 – 38(5) 75 – 114 225 – 342 3(2) 3(2)

2 00010(11) 50(18) –

66(1) 50 – 66 225 – 297 50(18) –

66(1) 50 – 66 225 – 297 1(4) 4.5(2)

3 00011(11)(14) 50(4) – 66(1) 50 – 66 100 – 133 50(4) – 66(1) 50 – 66 100 – 133 1 (Bypass) 2(4)

4 00100(12) 25 – 46(4) 50 – 92 100 – 184 25 – 46(4) 50 – 92 100 – 184 2 (4) 2(4)

5 00101 Reserved Reserved Note(20)

6 00110(15) Bypass Bypass Bypass

7 00111(14) 60(6) – 66(1) 60 – 66 180 – 198 60(6) – 66(1) 60 – 66 180 – 198 1 (Bypass) 3(2)

8 01000(12) 60(6) – 66(1) 60 – 66 180 – 198 60(6) – 66(1) 60 – 66 180 – 198 1(4) 3(2)

9 01001(19) 45(6) – 66(1) 90 – 132 180 – 264 45(6) – 66(1) 90 – 132 180 – 264 2(2) 2(2)

A 01010(12) 25 – 37(5) 50 – 74 225 – 333 25 – 38(5) 50 – 76 225 – 342 2 (4) 4.5(2)

B 01011(19) 45(3) – 66(1) 68 – 99 204 – 297 45(3) – 66(1) 68 – 99 204 – 297 1.5(2) 3(2)

C 01100(12) 36(6) – 46(4) 72 – 92 180 – 230 36(6) – 46(4) 72 – 92 180 – 230 2(4) 2.5(2)

D 01101(19) 45(3) – 63(5) 68 – 95 238 – 333 45(3) – 66(1) 68 – 99 238 – 347 1.5(2) 3.5(2)

E 01110(12) 30(6) – 46(4) 60 – 92 180 – 276 30(6) – 46(4) 60 – 92 180 – 276 2(4) 3(2)

F 01111(19) 25 – 31(5) 75 – 93 263 – 326 25 – 33(5) 75 – 99 263 – 347 3 (2) 3.5(2)

10 10000(12) 30(6) – 44(2) 60 – 132 180 – 264 30(6) – 44(2) 60 – 132 180 – 264 3(2) 2(2)

11 10001(19) 25 – 33(2) 100 – 132 250 – 330 25 – 33(2) 100 – 132 250 – 330 4(2) 2.5(2)

12 10010(12) 60(6) – 66(1) 90 – 99 180 – 198 60(6) – 66(1) 90 – 99 180 – 198 1.5(2) 2(2)

13 10011(19) 25 – 27(5) 100 – 108 300 – 324 25 – 29(5) 100 – 116 300 – 348 4(2) 3(2)

14 10100(12) 26(6) – 47(4) 52 – 94 182 – 329 26(6) – 47(4) 52 – 94 182 – 329 2(4) 3.5(2)

15 10101(19) 27(3) – 33(5) 68 – 83 272 – 332 27(3) – 34(5) 68 – 85 272 – 340 2.5(2) 4(2)

16 10110(12) 25 – 41(5) 50 – 82 200 – 328 25 – 43(5) 50 – 86 200 – 344 2 (4) 4(2)

17 10111(19) 25 – 33(2) 100 – 132 200 – 264 25 – 33(2) 100 – 132 200 – 264 4(2) 2(2)

18 11000(12) 27(3) – 44(5) 68 – 110 204 – 330 27(3) – 46(5) 68 – 115 204 – 345 2.5(2) 3(2)

19 11001(19) 36(6) – 66(1) 72 – 132 180 – 330 36(6) – 66(1) 72 – 132 180 – 330 2(2) 2.5(2)

1A 11010(12) 50(18) –

66(1) 50 – 66 200 – 264 50(18) –

66(1) 50 – 66 200 – 264 1(4) 4(2)

1B 11011(19) 33(6) – 55(5) 66 – 110 198 – 330 33(6) – 58(5) 66 – 116 198 – 348 2(2) 3(2)

1C 11100(12) 44(6) – 66(1) 66 – 99 198 – 297 44(6) – 66(1) 66 – 99 198 – 297 1.5(2) 3(2)

48 PC8245 2171D–HIREL–06/04

Notes: 1. Limited by maximum PCI input frequency (66 MHz).

2. Limited by maximum system memory interface operating frequency (100 MHz at 350 MHz CPU).

3. Limited by minimum memory VCO frequency (133 MHz).

4. Limited due to maximum memory VCO frequency (372 MHz).

5. Limited by maximum CPU operating frequency (266 MHz).

6. Limited by minimum CPU VCO frequency (360 MHz).

7. Limited by maximum CPU VCO frequency (800 MHz).

8. In clock off mode, no clocking occurs inside the PC8245 regardless of the PCI_SYNC_IN input.

9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.

10.PLL_CFG[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved.

11.Mult ip l i er ratios for this PLL_CFG[0:4] setting ar e di fferent from the PC8240 and are not backwards-compatible.

12.PCI_SYNC_IN range for this PLL_CFG[0:4] setting is diff erent from the PC8240 and may not be fully backw ards-compatible .

13.Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.