Distinguishing Features Applications 150, 135, 110, 80 MHz Operation High-Resolution Color 1:1, 4:1, or 5:1 Multiplexed Pixel Graphics Ports CAE/CAD/CAM 256x 24 Color Palette RAM Image Processing * 16x 24 Overlay Color Palette Video Reconstruction 1x to 16x Integer Zoom Support 1, 2, 4, or 8 Bits per Pixel * Frame Buffer Interleave Support Related Products * Pixel Panning Support * Bt438, Bt439 * On-Chip User-Definable 64 x 64 Bt460, Bt462, Bt468 Cursor Programmable Setup (0 or 7.5 IRE) * X Windows Support for Overlays/ Cursor * 132-pin PGA or PQFP Package Functional Block Diagram CLOCK* CLOCK VAA GND FS ADJUST VREF a | BLINK +e IOR 40 g | 256x24 ne : 5 be} COLOR reap | BUNK PALETTE MASK | MASK 16x24 tl 20 4 | OVERLAY oN : oy po 3x24 5 2 | cuRSOR i. 108 OLE (A -E) CURSOR = [-"*|_ PALETTE GENERATION Le PLL SYNC* BLANK* | BUS CONTROL || ADDR REG | | R | G | B | {3 fs CE* RW CO Cl DO- D7 Brooktree Corporation * 9950 Barnes Canyon Rd. * San Diego, CA 92121-2790 (619) 452-7580 #1 (800) 2 BT APPS * TLX: 383 596 * FAX: (619) 452-1249 L459001 Rev. N 150 MHz Monolithic CMOS 256 x 24 Color Palette RAMDAC Product Description The Bt459 triple 8-bit RAMDAC is designed specifically for high-performance, high- resolution color graphics. The multiple pixel ports and internal multiplexing enable TTL-compatible interfacing to the frame buffer, while maintaining the 135 MHz video data rates required for sophisticated color graphics. On-chip features include a 256 x 24 color palette RAM, 16 x 24 overlay color palette RAM, programmable 1:1, 4:1, or 5:1 input multiplexing of the pixel and overlay ports, bit plane masking and _ blinking, programmable setup (0 or 7.5 IRE), pixel panning support, 1x to 16x integer zoom support, and independent cursor generation. Pixel data may be input as 1, 2, 4, or 8 bits per pixel. Overlay and cursor information may optionally be enabled on a pixel-by-pixel basis for X Windows hardware support. The Bt459 has an on-chip three-color 64 x 64 pixel cursor and a three-color full-screen (or full- window) cross hair cursor. The PLL current output enables the synchronization of multiple devices with subpixel resolution. This literature is brought to you by = . CC. CONEXANT = What's next in communication technologies = ROCKS00258Bt459 Brooktree Circuit Description MPU Interface As illustrated in the functional block diagram, the Bt459 supports a standard MPU bus interface, allowing the MPU direct access to the intemal control registers and color palettes. The dual-port color palette RAMs and dual-port overlay RAM allow color updating without contention with the display refresh process. As detailed in Table 1, the CO and C1 control inputs, in conjunction with the internal address register, speci- fy which control register or color palette location will be accessed by the MPU. The 16-bit address register eliminates the requirement for external address multi- plexers. ADDRO is the least significant bit. To write color data, the MPU loads the address reg- ister with the address of the primary color palette RAM, overlay RAM, or cursor color register location to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and C1 to select either the primary color palette RAM, overlay RAM, or cursor color registers. After the blue write cycle, the address register then incre- ments to the next location, which the MPU may modi- fy by writing another sequence of red, green, and blue data. Reading color data is similar to writing it, except the MPU executes read cycles when it reads color data. When the MPU is accessing the color palette RAM, overlay RAM, or cursor color registers, the address register increments after each blue read or write cycle. To keep track of the red, green, and blue read/write cy- cles, the address register has two additional bits (AD- DRa, ADDRb) that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 12 bits of the address register (ADDRO-11) are accessible to the MPU. ADDR12-ADDR1S5 are al- ways a logical zero. ADDRO and ADDR8 correspond to DO. The only time the address register resets to $0000 is after accessing location $0FFF (due to wraparound). Although the color palette RAM, overlay RAM, and cursor color registers are dual ported, if the pixel and overlay data is addressing the same palette entry being written to by the MPU during the write cycle, it is pos- sible for one or more of the pixels on the display screen to be disturbed. A maximum of 1 pixel is dis- turbed if the write data from the MPU is valid during the entire chip enable time. ADDRO-15 | C1,CO Addressed by MPU Sxxxx 00 address register (ADDRO-7) $xxxx 01 address register (ADDR8-15) $0000-$O00FF 10 Teserved $0100 10 overlay color 0 (Note 1) : 10 : $010F 10 overlay color 15 (Note 1) $0181 10 cursor color register 1 (Note 1) : : cursor color register 2 (Note 1) $0183 10 cursor color register 3 (Note 1) $0200 10 ID register ($4A) $0201 10 command register_0 $0202 10 command register_1 $0203 10 command register_2 $0204 10 pixel read mask register $0205 10 reserved ($00) $0206 10 pixel blink mask register $0207 10 reserved ($00) $0208 10 overlay read mask register $0209 10 overlay blink mask register $020A 10 interleave register $020B 10 test register $020C 10 red signature register $020D 10 green signature register $020E 10 blue signature register $0220 10 revision register $0300 10 cursor command register $0301 10 cursor (x) low register $0302 10 cursor (x) high register $0303 10 cursor (y) low register $0304 10 cursor (y) high register $0305 10 window (x) low $0306 10 window (x) high $0307 10 window (y) low $0308 10 window (y) high $0309 10 window width low register $030A 10 window width high register $030B 10 window height low register $030C 10 window height high register $0400-$07FF 10 cursor RAM $0000-$00FF 11 color palette RAM (Note 1) Note 1: Indicates a requirement of three read/write cyclesRGB. Table 1. Address Register (ADDR) Operation.Brooktree* Circuit Description (continued) - The control registers and cursor RAM are also ac- cessed through the address register in conjunction with the CO and C1 inputs, as specified in Table 1. All con- trol registers may be written to or read by the MPU at any time. When accessing the control registers and cur- sor RAM, the address register increments following a read or write cycle. If an invalid address is loaded into the address regis- ter, data written to the device will be ignored and in- valid data will be read by the MPU. Figure 1 illustrates the MPU read/write timing of the Bt459. Bt459 Reading/Writing Color Data (RGB Mode) To write color data, the MPU loads the address register with the address of the color palette RAM location or overlay register to be modified. The MPU performs three successive write cycles (8 bits each of red, green, and blue), using CO and C1 to select either the color palette RAM or the overlay registers. After the blue write cycle, the address register then increments to the Bt459 next location, which the MPU may modify by writing another sequence of red, green, and blue data. Reading color data is similar to writing it, except the MPU exe- cutes read cycles when it reads color data. This mode is useful if only an 8-bit data bus is avail- able. Each Bt459 is programmed to be a red, green, or blue RAMDAC and will respond only to the assigned color read or write cycle. In this application, the Bt459s share a common 8-bit data bus. The CE* in- puts of all three Bt459s must be asserted simultaneous- ly only during color read/write cycles and address reg- ister write cycles. When accessing the color palette RAM, the address register resets to $00 after a blue read or write cycle to location $FF. When accessing the overlay registers, the address register increments to $04 following a blue read or write cycle to overlay register 3. To keep track of the red, green, and blue read/write cycles, the ad- dress register has two additional bits that count modulo three. They are reset to zero when the MPU reads or writes to the address register. The MPU does not have access to these bits. The other 8 bits of the address register (ADDRO-7) are accessible to the MPU. RW, , Cl x VALID x CE* \ LP DO - D7 (READ) DATA OUT (R/W = 1) > DO - D7 (WRITE) x DATA IN (R/W = 0) x Figure 1. MPU Read/Write Timing.Bt459 Brooktree* Circuit Description (continued) Frame Buffer interface To enable pixel data to be transferred from the frame buffer at TTL data rates, the Bt459 incorporates inter- nal latches and multiplexers. As illustrated in Figure 2, on the rising edge of LD*, sync and blank information, color, and overlay information, for either one, four, or five consecutive pixels, are latched into the device. With this configuration, the sync and blank timing will be recognized only with one, four, or five pixel resolu- tion. Typically, the LD* signal is used to clock exter- nal circuitry to generate the basic video timing and to clock the video DRAMs. For 4:1 or 5:1 input multiplexing, the Bt459 outputs color information each clock cycle based on the {A} inputs, followed by the {B} inputs, followed by the (C) inputs, etc., until all four or five pixels have been output. At this point, the cycle repeats. In the 1:1 input multiplexing mode, the {B}, {C}, (D}, and (E} inputs are ignored. The overlay inputs may have pixel timing, facilitat- ing the use of additional bit planes in the frame buffer to control overlay selection on a pixel basis, or they may be controlled by external circuitry. To simplify the frame buffer interface timing, LD* may be phase shifted in any amount, relative to CLOCK. This enables the LD* signal to be derived by externally dividing CLOCK by 4 or 5, independent of the propagation delays of the LD* generation logic. As a result, the pixel and overlay data are latched on the rising edge of LD*, independent of the clock phase. Internal logic maintains an internal LOAD signal, synchronous to CLOCK, and is guaranteed to follow the LD* signal by at least one but not more than three clock cycles. This LOAD signal transfers the latched pixel and overlay data into a second set of latches, which are then internally multiplexed at the pixel clock rate. If 4:1 multiplexing is specified, only one rising edge of LD* should occur every four clock cycles. If 5:1 multiplexing is specified, only one rising edge of LD* should occur every five clock cycles. Otherwise, the internal LOAD generation circuitry assumes it is not locked onto the LD* signal and will continuously at- tempt to resynchronize itself to LD*. If 1:1 multiplexing is specified, LD* is also used to clock the Bt459 (at a maximum of 50 MHz). The rising edge of LD* still latches the PO-P7 {A}, OLO-OL3 {A}, OLE {A}, SYNC*, and BLANK* inputs. How- ever, analog information is output following the rising edge of LD* rather than CLOCK. CLOCK must still run but is ignored. ef Nf Nf NSN PO-P7 (A-E}, OLB (A-B} OLO - OL3 {A-E}, Xx DATA SYNC*, BLANK* TOR, IOG, IOB, PLL Figure 2. Video Input/Output Timing.Brooktree Bt459 Circuit Description (continued) Read and Blink Masking Each clock cycle, 8 bits of color information (PO-P7) and 4 bits of overlay information (OLO-OL3) for each pixel are processed by the read mask, blink mask, and command registers. Through the control registers, indi- vidual pixel and overlay inputs may be enabled or disa- bled for display, and/or blinked at one of four blink rates and duty cycles. To ensure that a color change caused by blinking does not occur during the active display time (i.e., in the middle of the screen), the Bt459 monitors the BLANK* input to determine vertical retrace intervals (any BLANK* pulse longer than 256 LD* cycles). The processed pixel data is used to select which col- or palette entry or overlay register is to provide color information. PO is the LSB when the MPU is address- ing the color palette RAMs, and OLO is the LSB when addressing the overlay palette RAM. The read and blink mask registers are not initialized. They must be initialized by the user after power-up for proper operation. Pixel Panning Panning is achieved through the delay of SYNC* and BLANK* by an additional one, two, three, or four clock cycles. To support pixel panning, command register_1 specifies the number of clock cycles to pan. Only the pixel inputs and underlays are pannedoverlays and cursors are not. If 0 pixel panning is specified, pixel (A) is output first, followed by pixel {B}, followed by pixel {C}, etc., until all 4 or 5 pixels have been output. At this point, the cycle repeats (assuming the interleave select is pixel {A}). If 1-pixel panning is specified, pixel (B} will be first, followed by pixel {C}, followed by pixel (D}, etc. Pixel {A} will have been processed during the last clock cycle of the blanking interval and will not be seen on the display screen. At the end of the active dis- play line, pixel {A} will be output. Pixels {B}, {C}, {D}, and {E} will be output during the blanking interval and will not be seen on the display screen. The process is similar for panning by 2, 3, or 4 pix- els. When a panning value other than 0 pixels is speci- fied, valid pixel data must be loaded into the Bt459 during the first LD* cycle that BLANK is a logical zero. In the 1:1 multiplex mode, 0-pixel panning should be specified. The cursor position does not change relative to the edge of the display screen during panning. Pixel Zoom The Bt459 supports 1x to 16x integer zoom through pixel replication. Only the PO-P7 inputs are zoomed. If 2x zooming is specified, the {A} pixel is output for two clock cycles, followed by the (B} pixel for two clock cycles, followed by the {C} pixel for two clock cycles, etc. The 3x zooming is similar, except each pix- el is output for three clock cycles. For 1:1 multiplex- ing, only the {A} pixel is output. LD* must be the pixel clock (1:1 multiplex mode), or one fourth or one fifth the CLOCK rate. Regardless of the zoom factor, PO-P7 data is latched every LD* cycle. During 2x zoom, new PO-P7 data must be presented every two LD* cycles. During 3x zoom, new PO-P7 data must be presented every three LD* cycles. The pix- el data must be held at the PO-P7 {AE} inputs for the appropriate number of LD* cycles until new POP7 in- formation is needed. OLOQ-OL3, OLE, SYNC*, and BLANK* information are still latched every LD* cycle. In the 1:1 multiplex mode, 1x zoom must be specified. Also, while in the block mode (1, 2, or 4 bits per pixel), 1x zoom must be specified. Figure 3 illustrates the zoom timing. Block Mode Operation The Bt459 supports loading of pixel data at 1, 2, 4, or 8 bits per pixel. Only the POP7 inputs are affected. LD* must be the pixel clock (1:1 multiplex mode), or one fourth or one fifth the CLOCK rate. Regardless of the block mode, PO-P7 data is latched every LD* cycle. For 8 bits per pixel, new PO-P7 information must be presented every LD* cycle. For 4 bits per pixel, new PO-P7 information must be presented every two LD* cycles. For 2 bits per pixel, new PO-P7 information must be presented every four LD* cycles. For 1 bit per pixel, new PO-P7 information must be presented every eight LD* cycles. The pixel data must be held at the POP7 inputs for the appropriate number of LD* cycles until new PO-P7 information is needed. OLO-OL3, OLE, SYNC* and BLANK * information are still latched every LD* cycle. Figure 4 illustrates the block mode timing (4 bits per pixel). Tables 2 and 3 detail the block mode operation and address of the color palette RAM. In the 1:1 multiplex mode, 8 bits per pixel must be specified. Also, for block modes other than 8 bits per pixel, a 0-pixel interleave must be selected.Bt459 Brooktree Circuit Description (continued) LD* OLO - OL3 {A - E), SYNC*, BLANK*, OLE {A -E} PO-P7{A-E} BLANK* LD* OLO - OL3 {A - E}, SYNC*, BLANK*, OLE {A -E} PO-P7{A-E} BLANK* X _X X A A B B c c D D_ = OUTPUT SEQUENCE Figure 3. Zoom Input Timing (8 Bits per Pixel, 2x Zoom). Sf \ Sf \ SNS NL X X x X __/ X UA LA UB LB uc LC UD LD = OUTPUT SEQUENCE UA =P4-P7 {A}; LA =PO-P3 {A} UB = P4-P7 (B}; LB = PO - P3 {B} UC = P4-P7 (C}; LC = PO - P3 {C} UD = P4-P7 {D}; LD = PO-P3 {D} Figure 4. Block Mode Input Timing (4 Bits per Pixel, 1x Zoom, 4:1 Multiplexing).Brooktree Circuit Description (continued) Bt459 Bits per Pixels per Pixels per Pixels per Colors Pixel LD* LD* LD* Displayed (1:1 muxing) | (4:1 muxing) | (5:1 muxing) 1 8 32 40 2 2 N/A 16 20 4 4 N/A 10 16 8 N/A 4 5 256 Table 2. Block Mode Operation. 1 Bit per Pixel | 2 Bits per Pixel 4 Bits per Pixel 8 Bits per Pixel (RA1-RA7 =0) | (RA2-RA7 = 0) (RA4-RA7 = 0) RA7-RAO = RAO = RA1, RAO = RA3-RAD = P7A P7A, P6A P7A, P6A, PSA, P4A P7A, P6A, PSA, P4A, P3A, P2A, PIA, POA P6A PSA, P4A P3A, P2A, PIA, POA P7B, P6B, PSB, P4B, P3B, P2B, P1B, POB (4:1) : P3A, P2A P7B, P6B, PSB, P4B (4:1) PTC, P6C, PSC, PAC, P3C, P2C, PIC, POC (4:1) POA PIA, POA P3B, P2B, P1B, POB (4:1) P7D, P6D, PSD, P4D, P3D, P2D, PID, POD (4:1) P7B (4:1) P7B, P6B (4:1) P7C, P6C, PSC, PAC (4:1) P7E, P6E, PSE, P4E, P3E, P2E, PIE, POE (5:1) P6B (4:1) P5B, P4B (4:1) P3C, P2C, PIC, POC (4:1) : P3B, P2B (4:1) | P7D, P6D, PSD, P4D (4:1) POB (4:1) P1B, POB (4:1) | P3D, P2D, P1D, POD (4:1) P7C (4:1) PTC, P6C (4:1) P7E, P6E, PSE, P4E (5:1) P6C (4:1) PSC, P4C (4:1) P3E, P2E, PIE, POE (5:1) P3C, P2C (4:1) POC (4:1) PIC, POC (4:1) P7D (4:1) P7D, P6D (4:1) P6D (4:1) PSD, P4D (4:1) P3D, P2D (4:1) POD (4:1) PID, POD (4:1) P7E (5:1) P7E, P6E (5:1) P6E (5:1) PSE, P4E (5:1) P3E, P2E (5:1) POE (5:1) PIE, POE (5:1) Each line represents one pixel clock cycle. A column represents one LD* cycle loading new PQP7 data. All entries with "4:1" descriptor are also valid for 5:1 mode. Table 3. Block Mode Operation (RA = Color Palette RAM Address).Bt459 Brooktree Circuit Description (continued) On-Chip Cursor Operation The Bt459 has an on-chip, three-color, 64 x 64 pixel user-definable cursor. The cursor operates only with a noninterlaced video system. The pattern for the cursor is provided by the cursor RAM, which may be accessed by the MPU at any time. The cursor is positioned through the cursor (x,y) register. The Bt459 expects (x) to increase to the right and (y) to increase down, as displayed on the screen. The cursor (x) position is relative to the first rising edge of LD* following the falling edge of SYNC*. The cursor (y) position is relative to the second sync pulse during vertical blanking. (See Figure 5.) Three-Color 64 x 64 Cursor The 64 x 64 x 2 cursor RAM provides 2 bits of cursor information every clock cycle during the 64 x 64 cur- sor window, selecting the appropriate cursor color reg- ister as follows: planet planed cursor color 0 0 cursor not displayed 0 1 cursor color register 1 1 0 cursor color register 2 1 1 cursor color register 3 A (0,0) enables the color palette RAM and overlay RAM to be selected as normal. Each plane of cursor information may also be independently enabled or dis- abled for display via the cursor command register (bits CR47 and CR46). The cursor pattern and color may be changed by changing the contents of the cursor RAM. SYNC* __ Pa Xo The cursor is centered about the value specified by the cursor (x,y) register. Thus, the cursor (x) register specifies the location of the thirty-first column of the 64 x 64 array (assuming the columns start with O for the left-most pixel and increment to 63). Similarly, the cursor (y) register specifies the location of the thirty- first row of the 64 x 64 array (assuming the rows start with 0 for the top-most pixel and increment to 63). Cross Hair Cursor The three-color cross hair cursor is also positioned through the cursor (x,y) register. The intersection of the cross hair cursor is specified by the cursor (x,y) register. If the thickness of the cross hair cursor is greater than 1 pixel, the center of the intersection is the reference position. During times that cross hair cursor information is to be displayed, the cursor command register (bits CR45 and CR44) specifies the color of the cross hair cursor. CR45 CR44 cross hair color 0 0 cross hair not displayed 0 1 cursor color register 1 1 0 cursor color register 2 1 1 cursor color register 3 The cross hair cursor is displayed only within the cross hair window, which is specified by the window (x,y), window width, and window height registers. Since the cursor (x,y) register must specify a point within the window boundaries, the software must en- sure that the cursor (x,y) register does not specify a point outside of the cross hair cursor window. *ONASA TWNYSLLNI CURSOR (X,Y) REGISTER 64 x 64 | CURSOR AREA 0 DISPLAY SCREEN Figure 5. Cursor Positioning.Brooktree Bt459 Circuit Description (continued) If a full-screen cross hair cursor is desired, the win- dow (x,y) registers should contain $0000, and the win- dow width and height registers should contain $0FFF. Again, the cursor (x) position is relative to the first rising edge of LD* following the falling edge of SYNC*. The cursor (y) position is relative to the sec- ond sync pulse during vertical blanking. (See Figure 6.) Dual-Cursor Positioning Both the user-definable cursor and the cross hair cursor may be enabled for display simultaneously, enabling the generation of custom cross hair cursors. The cursor (x,y) register specifies the location of bit (31, 31) of the cursor RAM. As the user-definable cur- sor contains an even number of pixels in the horizontal and vertical direction, it will be 1 pixel off from being truly centered about the cross hair cursor. Figure 7 illustrates dual-cursor display. In the 64 x 64 pixel area in which the user-definable cursor is displayed, each plane of the 64 x 64 cursor may be individually logically ORed or exclusive-ORed with the cross hair cursor information. Thus, the color of the displayed cursor will depend on the cursor pat- SYNC* tern, whether it is logically ORed or XORed, and the in- dividual cursor display enable and blink enable bits. Figure 8 shows the equivalent cursor generation circuitry. X Windows Cursor Mode In the X Windows mode, planel of the cursor RAM is a cursor display enable and planeO of the cursor RAM selects either cursor color 2 or 3. The operation is as follows: plane1 | planed Selection 0 0 no cursor 0 1 no cursor 1 0 cursor color 2 1 1 cursor color 3 Figure 12 in the Internal Registers section shows the organization of the cursor RAM while in the X Win- dows mode. CROSS HAIR +ONASA TVNYAINI Ng g .| CURSOR (X,Y) J REGISTER DISPLAY SCREEN N CROSS HAIR WINDOW Figure 6. Cross Hair Cursor Positioning.Bt459 Circuit Description (continued) SYNC* CURSOR (X,Y) REGISTER 64x 64 CURSOR AREA 64X64 X2 CURSOR RAM PLANE 0 PLANE 1 CR46 CR45 CROSS HAIR CR44 CR43 D OR CR47 CROSS HAIR CURSOR ot SCREEN ZZ DISPLAY \ Figure 7. Dual-Cursor Positioning. XOR \ CROSS HAIR WINDOW XOR }-\ MUX OR *ONASA TWNUALNI \t | _ pe CR40 CR21 MUX Brooktree CURSOR 1 TT) CURSOR 0 10 Figure 8. Cursor Control Circuitry.Brooktree Bt459 Circuit Description (continued) Overlay/Underlay Operation The overlay inputs (OLO-OL3 and OLE) may operate in three modes: normal overlays, X Windows over- lays, or an underlay, as specified in Tables 4 and 5. Overlay and underlay information may be displayed on a pixel basis. Overlays and underlay may both be used. If X Windows overlays are used, the underlay is The priority of display operation is: 1. 2. 3. 4. Cursor Overlays Pixel Data Underlays The Bt459 must be reset to an eight-cycle pipeline not available. delay for proper cursor pixel alignment. Cursor1, | CR30 | CR22 | OLE | CROS | OLO-OL3 | POP7 | Addressed by frame buffer | Overlay Mode Cursor0 11 x x Xx x $x $xx cursor color 3 10 x x Xx x $x $xx cursor color 2 01 x x x x $x $xx cursor color 1 00 0 0 x x $F $xx overlay color 15 normal 00 0 0 x x $1 $xx overlay color 1 00 0 0 1 $0 $xx overlay color 0 00 0 0 x 0 $0 $00 RAM location $00 00 0 0 Xx 0 $0 $01 RAM location $01 00 0 0 x 0 $0 $FF RAM location $FF 00 x 1 1 x $F $xx overlay color 15 X Windows 00 X 1 Xx $1 Sxx overlay color 1 00 x 1 1 x $0 $xx overlay color 0 00 x 1 0 0 $x $00 RAM location $00 00 x 1 0 0 $x $01 RAM location $01 00 x 1 0 0 $x $FF RAM location $FF 00 1 0 x x $F $xx overlay color 15 underlay 00 1 0 x X $1 $xx overlay color 1 00 1 0 1 x $0 $00 overlay color 0 (underlay) 00 1 0 0 0 $x $00 RAM location $00 00 1 0 x 0 $x $01 RAM location $01 00 1 0 X 0 $x $FF RAM location $FF Figure 8 shows generation of Cursor] and Cursor0 control bits. Table 4. Palette and Overlay Select Truth Table. 11Bt459 Brooktree Circuit Description (continued) In normal overlay mode, the overlay enable inputs OLE {A-E} are ignored. Typically, only 15 overlays are available. Graphics information (POP7) is dis- played only when no overlay information is present (OLO-OL3 = 0000). In the X Windows overlay mode, the overlay enable inputs specify whether overlay information is present (OLE = 1) or not (OLE = 0). If OLE = 1, overlay in- formation is displayed as determined by OLO-OL3. If OLE = 0, the OLO-OL3 inputs are ignored and PO-P7 pixel data is displayed. In the underlay mode (CR30 = 1), if OLE = 0, pixel data is displayed. If OLE = 1, the underlay is dis- played if PO-P7 = 0; if PO-P7 # 0, pixel data is dis- played. Overlay color 0 is used for underlay color information. PO-P7 Pixel Inputs 1:1 Mux Block interleave] Panning | Zooming | Overlays | Underlay Mode Block Mode no - yes yes n/s n/a n/a Interleave ns yes - yes yes yes yes Panning n/s n/s yes - yes n/a yes Zooming n/s n/s yes yes - n/a n/a Overlays yes yes yes n/a n/a - yes Underlay yes yes yes yes n/a yes - Cursor n/a n/a n/a n/a n/a n/a n/a yes: fully functional together. n/s: n/a: functions not supported together. functions operate together, but do not affect each other. Table 5. Features and Function Compatibility Table. 12Brooktree Bt459 Circuit Description (continued) Video Generation Every clock cycle, the selected 24 bits of color infor- mation are presented to the three 8-bit D/A converters. The SYNC* and BLANK* inputs, pipelined to maintain synchronization with the pixel data, add ap- propriately weighted currents to the analog outputs, producing the specific output levels required for video applications, as illustrated in Figures 9 and 10. Com- mand Register 2 specifies whether a 0 IRE or 7.5 IRE blanking pedestal is to be generated and whether sync information is to be encoded on the video output. A 0 IRE pedestal will force the black level and the blank level to be the same. The varying output current from the D/A converters produces a corresponding voltage level, which is used to drive the CRT monitor. Tables 6 and 7 detail how the SYNC* and BLANK* inputs modify the output levels. The D/A converters on the Bt459 use a segmented architecture in which bit currents are routed to either the current output or GND by a sophisticated decoding scheme. This architecture eliminates the need for pre- cision component ratios and greatly reduces the switch- ing transients associated with turning current sources on or off. Monotonicity and low glitch are guaranteed by using identical current sources and current steering their outputs. An on-chip operational amplifier stabi- lizes the full-scale output current against temperature and power supply variations. 13Bt459 Circuit Description (continued) RED, BLUE GREEN MA 19.05 1.44 0.00 0.714 | 26.67 1.000 0.054 ] 9.05 0.340 0.000 | 7.62 0.286 0,00 0.000 Note: 92.5 IRE WHITE LEVEL 7.5 IRE BLACK LEVEL 40 IRE BLANK LEVEL SYNC LEVEL 75 Q doubly-terminated load, RSET = 523 Q, and VREF = 1.235 V. Blank pedestal = and tolerances are assumed on all levels. 7.5 IRE. RS-343A levels Figure 9. Composite Video Output Waveform (SETUP = 7.5 IRE). Description 10G IOR, 1OB SYNC* BLANK* DAC (mA) (mA) Input Data WHITE 26.67 19.05 1 1 SFF DATA data+9.05 | data+ 1.44 1 1 data DATA - SYNC data+ 1.44 | data+ 1:44 0 1 data BLACK 9.05 1.44 1 1 $00 BLACK - SYNC 1.44 1.44 0 1 $00 BLANK 7.62 0 1 0 $xx SYNC 0 0 0 0 $xx Note: Typical with full-scale IOG = 26.67 mA. RSET =523 and VREF = 1.235 V. Blank 14 pedestal = 7.5 IRE. Table 6. Video Output Truth Table (SETUP = 7.5 IRE).Brooktree* Circuit Description (continued) RED, BLUE GREEN 18.60 ] 0.698 | 26.67 1,000 0.00 | 0.000 | 8.05 0.302 0.00 0.000 Note: 100 IRE WHITE LEVEL 43 IRE SYNC LEVEL 75 Q doubly-terminated load, RSET = 495 Q, and VREF = 1.235 V. Blank pedestal = OIRE. RS-343A levels and tolerances are assumed on all levels. Figure 10. Composite Video Output Waveform (SETUP = 0 IRE). Description 10G IOR, (OB SYNC* BLANK* DAC (mA) (mA) Input Data WHITE 26.67 18.60 1 1 $FF DATA data + 8.05 data 1 1 data DATA - SYNC data data 0 1 data BLACK 8.05 0 1 1 $00 BLACK - SYNC 0 0 0 1 $00 BLANK 8.05 0 1 0 $xx SYNC 0 0 0 0 $xx Note: Typical with full-scale IOG = 26.67 mA. RSET = 495 Q and VREF = 1.235 V. Blank pedestal = 0 IRE. Table 7. Video Output Truth Table (SETUP = 0 IRE). BLACK/BLANK LEVELBt459 Internal Registers Command Register_0 This register may be written to or read by the MPU at any time and is not initialized. CROO corresponds to data bus bit DO. CRO7, CRO6 CROS CRO4 CRO3, CRO2 CRO1, CROO 16 Multiplex select (00) reserved (01) 4:1 multiplexing (10) 1:1 multiplexing (11) 5:1 multiplexing Overlay 0 enable (0) use color palette RAM (1) use overlay color 0 reserved (logical zero) Blink rate selection (00) 16 on, 48 off (25/75) (01) 16 0n, 16 off (0/50) (10) 32 on, 32 off (50/50) (11) 64 on, 64 off (50/50) Block mode (00) 8 bits per pixel (01) 4 bits per pixel (10) 2 bits per pixel (11) 1 bit per pixel These bits specify whether 1:1, 4:1, or 5:1 multiplexing is to be used for the pixel and overlay inputs. If 4:1 is specified, the {E} pixel and overlay inputs are ignored and should be connected to GND, and the LD* input should be one fourth the CLOCK rate. If 5:1 is specified, all of the pixel and overlay inputs are used, and the LD* input should be one fifth the CLOCK rate. If 1:1 is specified, the {B}, {C}, {D}, and {E} inputs are ignored. In the 1:1 multiplex mode, the maximum clock rate is 66 MHz. LD* is used for the pixel clock. Although CLOCK is ignored in the 1:1 mode, it must remain running. It is possible to reset the pipeline delay of the Bt459 to a fixed eight clock cycles. In this instance, each time the input multiplexing is changed, the Bt459 must again be reset to a fixed pipeline delay. When in the normal overlay mode, this bit specifies whether to use the color palette RAM or overlay color 0 to provide color information when the overlay inputs are $0. See Table 4. These 2 bits specify the blink rate cycle time and duty cycle, and are specified as the number of vertical retrace intervals. The numbers in parentheses specify the duty cycle (percent on/off). The counters that determine the blink rate are reset when command register_0 is written to. These bits specify whether the pixel data is input as 1, 2, 4, or 8 bits per pixel. Only the PO-P7 inputs are affected.Brooktree Bt459 Internal Registers (continued) Command Register_1 This register may be written to or read by the MPU at any time and is not initialized. CR10 corresponds to data bus bit DO. CR17-CRI5 Pan select (000) Opixels {pixel A} (001) 1 pixel {pixel B} (010) 2pixels {pixel C} (011) 3pixels {pixel D} (100) 4 pixels {pixel E} (101) reserved (110) reserved (111) reserved CR14 reserved (logical zero) CRi3-CR10 Zoom factor (0000) Ix (0001) 2x (1111) 16x These bits specify the number of pixels to be panned. These bits are typically modified only during the vertical retrace interval, and should be set to 000 in the 1:1 multiplex mode. The {pixel A} indicates pixel A will be output first following the blanking interval, {pixel B} indicates pixel B will be output first, {pixel C} indicates pixel C will be output first, etc. Only pixel and underlay information is panned. Overlay and cursor information is not panned. In the 1:1 multiplex mode, 0 pixels should be specified. These bits specify the amount of zooming to implement. For 2x zoom, pixel {A} is output for two clock cycles, followed by pixel (B} for two clock cycles, followed by pixel {C} for two clock cycles, etc. For 3x zoom, pixel {A} is output for three clock cycles, and so on. In the 1:1 multiplex mode, only the {A} pixels are output, and 1x zoom should be selected. Only PO-P7 are zoomed. 17Bt459 Brooktree Internal Registers (continued) Command Register_2 This register may be written to or read by the MPU at any time and is not initialized. CR20 corresponds to data bus bit DO. CR27 Sync enable (0) disable sync (1) enable sync CR26 Pedestal enable (0) O IRE pedestal (1) 7.5 IRE pedestal CR25, CR24 Load palette RAM select (00) normal (01) red RAMDAC (10) green RAMDAC (11) blue RAMDAC CR23 PLL select (0) SYNC* (1) BLANK* CR22 X Windows overlay select (0) normal overlays (1) X Windows overlays CR21 X Windows cursor select (0) normal cursor (1) X Windows cursor CR20 Test mode select (O) signature analysis test (1) data strobe test 18 This bit specifies whether sync information is to be output onto IOG (logical one) or not (logical zero). This bit specifies whether a 0 or 7.5 IRE blanking pedestal is to be generated on the video outputs. 0 IRE specifies that the black and blank levels are the same. If (00) is specified, color data is loaded into the Bt459 with three write cycles (red, green, and blue), and color data is output with three read cycles (red, green, and blue). Modes (01), (10), and (11) enable the Bt459 to emulate a single-channel RAMDAC using only the green channel. The Bt459 expects color data to be input and output with (red, green, blue) cycles. The exact value indicates during which one of the three color cycles it is to load or output color information. The value is loaded into or read from the green color palette RAM. This bit specifies whether the PLL output uses SYNC* or BLANK* to generate PLL information. This bit specifies whether the overlays are to operate normally (logical zero) or in an X Windows environment (logical one). This bit specifies whether the cursor is to operate normally (logical zero) or in an X Windows-compatible mode (logical one). This bit determines the method of high-speed test used. The signature analysis registers are used to hold the test result for both test methods.Brooktree* Bt459 Internal Registers (continued) interleave Register This register may be written to or read by the MPU at any time and is not initialized. CR30 corresponds to data bus bit DO. The interleave register is for support of frame buffer systems configured for interleave operation. CR37-CR35 Interleave select (000) (001) (010) (011) (100) (101) (110) (111) 0 pixels 1 pixel 2 pixels 3 pixels 4 pixels reserved reserved reserved CR34-CR32 First pixel select (000) (001) (010) (O11) (100) (101) (110) (111) pixel {A} pixel {B} pixel (C} pixel (D} pixel (E} reserved reserved reserved CR31 Overlay interleave enable (0) interleaving disabled (1) interleave enabled CR30 Underlay enable (0) underlay disabled (1) underlay enabled These bits specify the order in which the pixels are to be output, as listed in Table 8. The order is repeated every LD* cycle for a given scan line. Thus, if the output sequence is DABC, it is that sequence for all pixels on that scan line. The phrase repeats every x" in Table 8 means that the output sequence repeats every x scan lines. Thus, for 4:1 multiplexing and a 1-pixel interleave select, ABCD would be repeated every fourth scan line. When the Bt459 is in the 1:1 input multiplex mode, a value of 0 pixels(000) must be specified. These bits are used to support panning in the Y direction with an interleaved frame buffer. Because of the interleave capability, the value of the first pixel must be specified on the first scan line following a vertical retrace. The pixel (E} selection is only used in the 5:1 multiplex mode. , These bits are ignored when the Bt459 is in the 1:1 multiplex mode. This bit specifies whether OLO-OL3 and OLE are to be interleaved. If interleaving is enabled, the interleave factor and first pixel selection are the same as that for PO-P7. If interleaving is disabled, pixel {A} is output first, and no interleaving occurs. If command bit CR22 is a logical zero, this bit enables or disables the underlay display. If CR22 is a logical one, this bit is ignored. If the underlay is enabled (and CR22 is a logical zero), the OLE imputs function as follows: If OLE = 0, PO-P7 data is displayed. If OLE = 1, the underlay is displayed if PO-P7 = 0, if PO-P7 # 0, normal pixel data is displayed. The underlay uses overlay color 0 to provide underlay color information. 19Bt459 Brooktree Internal Registers (continued) Interleave Register (continued) :1 multiplexing 4:1 multiplexing interleave output scan line output scan line select sequence number sequence number 0 ABCDE each line ABCD each line 1 ABCDE n ABCD n BCDEA n+l BCDA n+1 CDEAB n+2 CDAB n+2 DEABC n+3 DABC n+3 EABCD n+4 (repeats every 4) (repeats every 5) 2 ABCDE n ABCD n CDEAB n+1 CDAB n+l EABCD n+2 ABCD n+2 BCDEA n+3 CDAB n+3 DEABC n+4 (repeats every 2) (repeats every 5) 3 ABCDE n ABCD n DEABC n+1 DABC n+1 BCDEA n+2 CDAB n+2 EABCD n+3 BCDA n+3 CDEAB n+4 (repeats every 4) (repeats every 5) 4 ABCDE n invalid invalid EABCD n+1 DEABC n+2 CDEAB n+3 BCDEA n+4 (repeats every 5) Table 8. interleave Operation (First Pixel Select = Pixel A). 20Brooktree Bt459 internal Registers (continued) Interleave Zoom Enable If zooming while interleaving, the IZE* input pin indi- cates when to change the interleave sequence. For example, while interleaving with 3x zoom, the IZE* pin should be a logical zero during the blanking interval of every third scan line (as shown in Figure 11). IZE* may be asserted coincident with the falling edge of BLANK* but must remain low at least 16 LD* cycles after the falling edge of BLANK*. If zooming is not required (1x zoom), the IZE* should be a logical zero or be connected directly to GND. BLANK* | VERTICAL |_| [| LPL IZE* LTH Figure 11. Interleave and Zoom Operation (3x Zoom Example). 21Bt459 Brooktree internal Registers (continued) ID Register This 8-bit register may be read by the MPU to determine the type of RAMDAC being used in the system. The value is different for each RAMDAC. For the Bt459, the value read by the MPU will be $4A. Data written to this register is ignored. Pixel Read Mask Register The 8-bit pixel read mask register is used to enable (logical one) or disable (logical zero) a bit plane from addressing the color palette RAM. Each register bit is logically ANDed with the corresponding bit plane input. This register may be written to or read by the MPU at any time and is not initialized. For proper operation, it must be initialized by the user after power-up. DO corresponds to PO. Pixel Blink Mask Register The 8-bit pixel blink mask register is used to enable (logical one) or disable (logical zero) a bit plane from blinking at the blink rate and duty cycle specified by command register_0. This register may be written to or read by the MPU at any time and is not initialized. For proper operation, it must be initialized by the user after power-up. DO corresponds to PO. Overlay Read Mask Register The 8-bit overlay read mask register is used to enable (logical one) or disable (logical zero) an overlay plane from addressing the overlay palette RAM. DO corresponds to overlay plane 0 (OLO {A-E}), and D3 corresponds to over- lay plane 3 (OL3 {A-E}). Bits DO-D3 are logically ANDed with the corresponding overlay plane input. D4D7 are always a logical zero. This register may be written to or read by the MPU at any time and is not initialized. For proper operation, it must be initialized by the user after power-up. Overlay Blink Mask Register The 8-bit overlay blink mask register is used to enable (logical one) or disable (logical zero) an overlay plane from blinking at the blink rate and duty cycle specified by command register_0. DO corresponds to overlay plane 0 (OLO {A-E}), and D3 corresponds to overlay plane 3 (OL3 {A-E}). In order for an overlay plane to blink, the corre- sponding bit in the overlay read mask register must be a logical one. D4D7 are always a logical zero. This register may be written to or read by the MPU at any time and is not initialized. For proper operation, it must be initialized by the user after power-up. Revision Register (Revision B only) This 8-bit register is a read-only register, specifying the revision of the Bt459. The 4 most significant bits signify the revision letter B in hexidecimal form. The 4 least significant bits do not represent any value and should be ig- nored. Data written to this register is ignored. Since the Revision A device does not have a revision register, address $0220 will contain the last data read to or written from the internal bus. 22Brooktree Bt459 Internal Registers (continued) Red, Green, and Blue Signature Registers Signature Operation These three 8-bit signature registers (one each for red, green, and blue) may be read by the MPU while BLANK* is a logical zero. While BLANK* is a logical one, the three registers are concatenated and a 24-bit signature is ac- quired. The MPU may read from or write to the signature registers while BLANK* is a logical zero to load the seed value. By loading a test display into the frame buffer, a deterministic value for the red, green, and blue signature regis- ters will be read from these registers if all circuitry is working properly. The Application Information, Test Register section contains more information. Data Strobe Operation If command bit CR20 selects "data strobe testing," the operation of the signature registers changes. Rather than de- termining the signature, they capture red, green, and blue data being presented to the three DACs. Each LD* cycle, the three signature registers capture the color values being presented to the DACs. As only one of the (AE) pixels can be captured each LD* cycle, DO-D2 of the test register are used to specify which pixel (A E) is to be captured. 23Bt459 Internal Registers (continued) Test Register This 8-bit register is used to test the Bt459. If 1:1 pixel multiplexing is specified, signature analysis is performed on every pixel; if 4:1 pixel multiplexing is specified, signature analysis is performed on every fourth pixel; if 5:1 pixel multiplexing is specified, signature analysis is performed on every fifth pixel. DO-D2 are used for 4:1 and 5:1 mul- tiplexing to specify whether to use the A, B, C, D, or E pixel inputs, as follows: D2-D0 Selection 000 pixel A 001 pixel B 010 pixel C 011 pixel D 100 pixel E 101 reserved 110 reserved 111 reserved In 1:1 multiplexing mode, DOD2 should select pixel A. D3-D7 are used to compare the analog RGB outputs to each other and to a 150 mV reference. This enables the MPU to determine whether the CRT monitor is connected to the analog RGB outputs and whether the DACs are functional. D7, D6 D Q--D3 DS, D4 D7 D6 D5 D4 D3 aN red green blue 145 mV ref. | result select select select select LL CURSOR _! D7-D4 If D3 =1 lf D3=0 0000 normal operation - - 1010 red DAC compared to blue DAC red > blue blue > red 1001 red DAC compared to 150 mV reference red > 150 mV red < 145 mV 0110 green DAC compared to blue DAC green > blue blue > green 0101 green DAC compared to 150 mV reference green > 150 mV green < 145 mV The above table lists the valid comparison combinations. A logical one enables that function to be compared; the result is D3. The comparison result is strobed into D3 on the left edge of the 64 x 64 cursor area. The output levels of the DACs should be constant for 5 Us before the left edge of the cursor. For normal operation, D3-D7 must be a logical zero. 24Brooktree Bt459 Internal Registers (continued) Cursor Command Register This command register is used to control various cursor functions of the Bt459. It is not initialized, and may be written to or read by the MPU at any time. CR40 corresponds to data bus bit DO. CR47 CR46 CR45 CR44 CR43 CR42, CR41 CR40 64 x 64 cursor plane! display enable (0) disable planel (1) enable planel 64 x 64 cursor planeO display enable (0) disable planeO (1) enable planed Cross hair cursor plane1 display enable (0) disable plane1 (1) enable plane! Cross hair cursor planeO display enable (0) disable planeO (1) enable planeO Cursor format (0) XOR (1) OR Cross hair thickness (00) 1 pixel (01) 3 pixels (10) 5 pixels (11) 7 pixels Cursor blink enable (0) blinking disabled (1) _ blinking enabled This bit specifies whether plane! of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). This bit specifies whether planeO of the 64 x 64 cursor is to be displayed (logical one) or not (logical zero). This bit specifies whether planel of the cross hair cursor is to be displayed (logical one) or not (logical zero). This bit specifies whether planeO of the cross hair cursor is to be displayed (logical one) or not (logical zero). PlaneO and plane! contain the same information. If both the 64 x 64 cursor and the cross hair cursor are enabled for display, this bit specifies whether the contents of the cursor RAM are to be logically exclusive-ORed Cogical zero) or ORed (logical one) with the cross hair cursor. This bit specifies whether the vertical and horizontal thickness of the cross hair is 1, 3, 5, or 7 pixels. The segments are centered about the value in the cursor (x,y) register. This bit specifies whether the cursor is to blink (logical one) or not (logical zero). If both cursors are displayed, both will blink. The blink rate and duty cycle are as specified by command register_0. 25Bt459 Brooktree Internal Registers (continued) Cursor (x,y) Registers These registers are used to specify the (x,y) coordinate of the center of the 64 x 64 pixel cursor window or the inter- section of the cross hair cursor. The cursor (x) register is made up of the cursor (x) low register (CXLR) and the cursor (x) high register (CXHR); the cursor (y) register is made up of the cursor (y) low register (CYLR) and the cursor (y) high register (CYHR). They are not initialized, and may be written to or read by the MPU at any time. The cursor position is not updated until the vertical retrace interval after CYHR has been written to by the MPU. CXLR and CXHR are cascaded to form a 12-bit cursor (x) register. Similarly, CYLR and CYHR are cascaded to form a 12-bit cursor (y) register. Bits D4-D7 of CKHR and CYHR are always a logical zero. Cursor (x) High Cursor (x) Low (CXHR) (CXLR) Data Bit D3 D2 D1 DO D7 D6 D5 D4 D3 D2 D1 DO X Address X11 X10 X9 X8 X7 X6 XS =. X4 x3 X2 X1 X0 Cursor (y) High Cursor (y) Low (CYHR) (CYLR) Data Bit D3 D2 DiI DO D7 D6 DS D4 D3 D2 D1 DO Y Address Y1l Y10 Y9 Y8 Y7 Y6 Y5 Y4 3 Y2 Yl YO The cursor (x) value to be written is calculated as follows: Cx = desired display screen (x) position + H-P where P = 37 if 1:1 input multiplexing, 52 if 4:1 input multiplexing, 57 if 5:1 input multiplexing H = number of pixels between the first rising edge of LD* following the falling edge of SYNC* to active video Values from $0000 to $0FFF may be written into the cursor (x) register. The cursor (y) value to be written is calculated as follows: Cy = desired display screen (y) position + V-32 where V = number of scan lines from the second sync pulse during vertical blanking to active video Values from $0FCO (64) to $0FBF (+4031) may be loaded into the cursor (y) register. The negative values (S$OFCO to $OFFF) are used in situations where V < 32, and the cursor must be moved off the top of the screen. 26Brooktree Bt459 Internal Registers (continued) Window (x,y) Registers These registers are used to specify the (x,y) coordinate of the upper left corner of the cross hair cursor window. The window (x) register is made up of the window (x) low register (WXLR) and the window (x) high register (WXHR); the window (y) register is made up of the window (y) low register (WYLR) and the window (y) high register (WYHR). They are not initialized, and may be written to or read by the MPU at any time. The window position is not updated until the vertical retrace interval after WYHR has been written to by the MPU. WXLR and WXHR are cascaded to form a 12-bit window (x) register. Similarly, WYLR and WYHR are cascaded to form a 12-bit win- dow (y) register. Bits D4d-D7 of WXHR and WYHR are always a logical zero. Window (x) High Window (x) Low (WXHR) (WXLR) Data Bit D3 D2 D1 DO D7 D6 DS D4 D3 D2 D1 DO X Address X11 X10 X9 X8 X7 X6 XS x4 x3 x2 Xi X0 Window (y) High Window (y) Low (WYHR) (WYLR) Data Bit D3 D2 D1 DO D7 D6 DS D4 D3 D2 Di DO Y Address Yl Y10 Y9 Y8 Y7 Y6 YS Y4 Y3 Y2 Yl YO The window (x) value to be written is calculated as follows: Wx = desired display screen (x) position + H-P where P=5 if 1:1 input multiplexing, 20 if 4:1 input multiplexing, 25 if 5:1 input multiplexing H = number of pixels between the first rising edge of LD* following the falling edge of HSYNC* to active video The window (y) value to be written is calculated as follows: Wy = desired display screen (y) position + V . where V = number of scan lines from the second sync pulse during vertical blanking to active video Values from $0000 to $OFFF may be written to the window (x) and window (y) registers. A full-screen cross hair is implemented by loading the window (x,y) registers with $0000, and the window width and height registers with SOFFF. 27Bt459 Brooktree Internal Registers (continued) Window Width and Height Registers These registers are used to specify the width and height (in pixels) of the cross hair cursor window. The window width register is made up of the window width low register (WWLR) and the window width high register (WWHR); the window height register is made up of the window height low register (WHLR) and the window height high regis- ter (WHHR). They are not initialized, and may be written to or read by the MPU at any time. The window width and height are not updated until the vertical retrace interval after WHHR has been written to by the MPU. WWLR and WWHER are cascaded to form a 12-bit window width register. Similarly, WHLR and WHHR are cas- caded to form a 12-bit window height register. Bits D4~D7 of WWHR and WHHR are ajways a logical zero. Window Width High Window Width Low (WWHR) (WWLR) Data Bit D3 D2 Di DO D7 D6 DS D4 D3 D2 Di DO X Address X11 = X10 X9 X8 X7 X6 X5 x4 X3 X2 Xl X0 Window Height High Window Height Low (WHHR) (WHLR) Data Bit D3 D2 D1 DO D7 D6 DS D4 D3 D2 D1 DO Y Address Yli = -Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Yl YO The actual window width is 2, 8, or 10 pixels more than the value specified by the window width register, depend- ing on whether 1:1, 4:1, or 5:1 input multiplexing is specified. The actual window height is 2 pixels more than the value specified by the window height register. Therefore, the minimum window width is 2, 8, or 10 pixels for 1:1, 4:1, and 5:1 multiplexing, respectively. The minimum window height is 2 pixels. Values from $0000 to $OFFF may be written to the window width and height registers. 28Brooktree Bt459 Internal Registers (continued) Cursor RAM This 64 x 64 x 2 RAM is used to define the pixel pattern within the 64 x 64 pixel cursor window and is not initialized. For Revision A, the cursor RAM should not be written to by the MPU during the horizontal sync time and for the two LD* cycles after the end of the horizontal sync. The cursor RAM may otherwise be written to or read by the MPU at any time without contention. If writing to the cursor RAM asynchronously to horizontal sync, it is recom- mended that the user position the cursor offscreen in the Y direction [i.e., write to the cursor (y) registers and wait for the vertical sync interval to move the cursor offscreen], write to the cursor RAM, then reposition the cursor back to the original position. An alternative is to perform a write-then-read sequence, and if the correct cursor RAM data was not written, perform another write then read sequence. Since the contention occurs only during horizontal sync at the Y locations coincident with the cursor, the second write/read sequence bypasses the window of time when cur- sor RAM is in contention. For Revision B, cursor contention has been eliminated. The cursor RAM may be written to or read by the MPU at any time without contention. During MPU accesses to the cursor RAM, the address register is used to address the cursor RAM. Figure 12 illus- trates the internal format of the cursor RAM as it appears on the display screen. Addressing starts at location $400 as specified in Table 1. In the X Windows mode, planel serves as a cursor display enable while planeO selects one of two cursor colors (if enabled). In both modes of operation, planel = D7, D5, D3, D1; and planeO = D6, D4, D2, DO. UPPER LEFT CORNER AS DISPLAYED ON SCREEN 64 PIXELS BYTE $400 | BYTE $401 BYTE $40F BYTE $410 | BYTE $411 BYTE $41F 64 PIXELS BYTE $7F0 | BYTE $7F1 BYTE $7FF ZO 4 PIXELS NN D7, D6| DS, D4 | D3, D2} D1, DO Normal Mode: 00 = color palette or overlay RAM 01 = cursor color 1 10 = cursor color 2 11 = cursor color 3 X-Windows Mode: 00 = color palette or overlay RAM 01 = color palette or overlay RAM 10 = cursor color 2 11 = cursor color 3 Figure 12. Cursor RAM as Displayed on the Screen. 29Bt459 Pin Descriptions Pin Name Description BLANK* SYNC* LD* PO-P7 {A-E} OLO- OL3 {A-E} OLE {A-E} TOR, 10G, IOB PLL IZE* VAA GND Composite blank control input (TTL compatible). A logical zero drives the analog output to the blanking level, as specified in Tables 6 and 7. BLANK* is latched on the rising edge of LD*. When BLANK is a logical zero, the pixel and overlay inputs are ignored. Composite sync control inputs (TTL compatible). A logical zero typically switches off a 40 IRE current source on the IOG output (see Figures 9 and 10). SYNC* does not override any other contro] or data input, as shown in Tables 6 and 7; therefore, it should be asserted only during the blanking interval. SYNC* is latched on the rising edge of LD*. Load control input (TTL compatible). The PO-P7 {A-E}, OLO-OL3 {A-E}, OLE {A-E}, BLANK*, and SYNC* inputs are latched on the rising edge of LD*, While LD* is the output clock (1:1 multiplex mode) or while LD* is one fourth or one fifth of CLOCK, LD* may be phase independent of the CLOCK and CLOCK* inputs. LD* may have any duty cycle within the limits specified in the AC Characteristics section. Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which location of the color palette RAM is to be used to provide color information (see Table 4). Either 1, 4, or 5 consecutive pixels (up to 8 bits per pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected to GND. Typically, the {A) pixel is output first, followed by the {B} pixel, followed by the {C} pixel, etc., until all pixels (1, 4, or 5) have been output, at which point the cycle repeats. Overlay select inputs (ITL compatible). These inputs are latched on the rising edge of LD* and, in conjunction with CRO5 in command register_0, specify which palette is to be used for color information, as detailed in Table 4. When the overlay palette RAM is being accessed, the PO-P7 {A-E} inputs are ignored. Overlay information (up to 4 bits per pixel) for either 1, 4, or 5 consecutive pixels is input through this port. Unused inputs should be connected to GND. Overlay enable inputs (TTL compatible). In the X Windows mode for overlays, a logical one indicates overlay information is to be displayed. A logical zero indicates PO-P7 information is to be displayed. In the normal mode for overlays, these inputs are ignored. They are latched on the rising edge of LD*. Unused inputs should be connected to GND. Red, green, and blue current outputs. These high-impedance current sources can directly drive a doubly-terminated 75 Q coaxial cable (Figure 13). All outputs, whether used or not, should have the same output load. Phase lock loop output current. This high-impedance current source is used to enable multiple Bt459s to be synchronized with subpixel resolution when used with an external PLL. A logical one for SYNC* or BLANK* (as specified by CR23 in command register_2) results in no current being output onto this pin, while a logical zero results in the following current being output: PLL (mA) = 3,227 * VREF (V) / RSET (Q) If subpixel synchronization of multiple devices is not required, this output should be connected to GND either directly or through a resistor of up to 150 Q. Interleave zoom enable input (TTL compatible). This input should be a logical zero for a minimum of 16 LD* cycles after the falling edge of BLANK* during scan lines that require an interleave shift. If zoom while interleaving is not supported, this pin may be connected directly to GND. Analog power. All VAA pins must be connected together on the same PCB plane to prevent latchup. Analog ground. All GND pins must be connected together on the same PCB plane to prevent latchup.Brooktree* Bt459 Pin Descriptions (continued) Pin Name Description COMP Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 pF ceramic capacitor must be connected between this pin and VAA (Figure 13). When the capacitor is connected to VAA rather than to GND, the highest possible power supply noise rejection is provided. The COMP capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum and maximize the capacitor's self-resonant frequency to be greater than the LD* frequency. The PC Board Layout Considerations section contains critical layout criteria. FS ADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal (Figure 13). The IRE relationships in Figures 9 and 10 are maintained regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG is: RSET (Q) = Ki * VREF (V) /IOG (mA) The full-scale output current on IOR and IOB for a given RSET is: IOR, IOB (mA) = K2 * VREF (V) / RSET (Q) where K1 and K2 are defined as: Setup 10G IOR, |OB 7.5 IRE K1 = 11,294 K2 = 8,067 0 IRE K1 = 10,684 K2 = 7,457 VREF Voltage reference input. An external voltage reference circuit, such as the one shown in Figure 13, must supply this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not recommended, as any low-frequency power supply noise on VREF will be directly coupled onto the analog outputs. A 0.1 HF ceramic capacitor is used to decouple this input to WAA, as shown in Figure 13. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. The decoupling capacitor must be as close to the device as possible to keep lead lengths to an absolute minimum. CLOCK, Clock inputs. These differential clock inputs are designed to be driven by ECL logic configured for CLOCK* single supply (+5 V) operation. The clock rate is typically the pixel clock rate of the system. CE* Chip enable control input (TTL compatible). This input must be a logical zero to enable data to be written to or read from the device. During write operations, data is internally latched on the rising edge of CE*, Care should be taken to avoid glitches on this edge-triggered input. R/W Read/write control input (TTL compatible). To write data to the device, both CE* and R/W must be a logical zero. To read data from the device, CE* must be a logical zero and R/W must be a logical one. R/W is latched on the falling edge of CE*. co, C1 Command control inputs (TTL compatible). CO and C1 specify the type of read or write operation being performed, as specified in Table 1. They are latched on the falling edge of CE*. DO0-D7 Data bus (TTL compatible). Data is transferred into and out of the device over this 8-bit bidirectional data bus. D0 is the least significant bit. 31Bt459 Brooktree Pin Descriptions (continued)132-pin PGA Package Pin Pin Pin Signal Number Signal Number Signal Number BLANK* Ll OLOA El GND H1 SYNC* K3 OLOB F2 GND H2 LD* AS OLOC Fl GND H3 CLOCK Kl OLOD G3 GND C7 CLOCK* K2 OLOE G2 GND G12 IZE* B5 GND M8 OLIA Ml GND M7 POA E3 OLIB L2 GND N7 POB D2 OL1C Nl POC D1 OLID L3 COMP N9 POD E2 OLIE M2 FS ADJUST M10 POE F3 VREF P9 OL2A M3 PIA Al OL2B N2 CE* Pi3 P1B D3 OL2C Pl R/W Ni2 PIC C2 OL2D P2 Cl P12 PID Bl OL2E N3 Co Mill PIE Cl OL3A M4 DO L13 P2A A3 OL3B P3 D1 M14 P2B B3 OL3C N4 D2 L12 P2C A2 OL3D P4 D3 M13 P2D C3 OL3E M5 D4 N14 P2E B2 DS P14 OLEA N5 D6 N13 P3A A8 OLEB PS D7 M12 P3B AT OLEC M6 P3C B7 OLED N6 reserved G14 P3D A6 OLEE P6 reserved G13 P3E B6 reserved F14 10G P10 reserved F13 P4A cg IOB Pll reserved E14 P4B B9 IOR N10 reserved J13 P4C A9 PLL Nil reserved J14 P4D C8 reserved H12 P4E B8 VAA Jl reserved H13 VAA J2 reserved H14 PSA Bll VAA J3 reserved C5 P5B All VAA C6 Teserved A4 P5C C10 VAA F12 reserved B4 P5D B10 VAA M9 reserved C4 PSE Al0 VAA P7 reserved ci4 VAA P8 reserved C13 P6A Al4 VAA N8 reserved Bi4 P6B Al3 reserved C12 P6C B12 reserved B13 P6D Cll reserved L14 P6E Al2 reserved K12 reserved Ji2 PTA E13 reserved K14 P7B E12 reserved K13 P7C D14 P7D D13 PVE D12 32Brooktree Bt459 Pin Descriptions (continued)132-pin PGA Package Alignment Marker (on Top) 14 10 P6A NIC NIC PTC NIC NIC NIC NIC NIC N/C N/C Di D4 DS P6B NIC N/C P7D P7A NIC NIC NIC NIC N/C DO D3 D6 CE* P6E P6C NIC PTE P7B VAA GND N/IC NIC N/C D2 Db? RW cl PSB PSA P6D co PLL IOB PSE PSD PSC FSADJ IOR 10G P4c P4B P4A B t 4 5 9 VAA COMP VREF P3A P4E P4D GND VAA- VAA P3B P3C GND GND GND VAA P3D P3E VAA (TOP VIEW) OLEC OLED OLEE LD* IZE* NIC OL3E OLEA OLEB NIC NIC NIC OL3A OL3C OL3D P2A P2B P2D PIB POA POE OLOD GND VAA SYNC* OLID OL2A OL2E OL3B P2C P2E Pic POB POD OLOB OLOE GND VAA_ CLK* OLIB OLIE OL2B OL2D PIA PID PIE PoC OLOA OLOC NIC GND VAA CLK BLK* OLIA OLIC OL2C A B c D E F 6 H Ij K L M N P DS D4 Di NC NIC NIC NIC NIC NIC NIC P7C NIC NIC P6A CE* D6 D3 DO NIC NIC N/C NIC N/C PTA P7D NIC NIC P6B cl R/w D7 D2 NIC NIC NIC GND VAA P7B PIE NIC P6C P6E IOB PLL co P6D PSA PSB 10G 1OR FS ADJ PSC PSD PSE VREF COMP VAA P4A P4B Pac VAA VAA GND P4D P4E P3A VAA GND GND (B OTTOM VIEW) GND P3C P3B OLEE OLED OLEC VAA P3E P3D OLEB OLEA OL3E NIC IZE* LD* OL3D OL3C OL3A NIC NIC NIC OL3B OL2E OL2A OLID SYNC* VAA GND OLOD POE POA PIB P2D P2B P2A OL2D OL2B OLIE OLIB CLK* VAA GND OLOE OLOB POD POB PIC P2E P2c OL2C OLIC OLIA BLK* CLK VAA_ GND NIC OLOC OLOA POC PIE PID PIA P N M L K J H G F E D c B A 33Bt459 Brooktree Pin Descriptions (continued)132-pin PQFP Package Pin Pin Pin Number Signal Number Signal Number Signal 1 OLOE 44 P6E 88 PLL 2 OLOD 45 P6D 89 IOB 3 OLOC 46 P6C 4 OLOB 47 P6B 90 FS ADJUST 5 OLOA 48 P6A 91 IOR 92 10G 6 POE 49 reserved 93 VAA 7 POD 50 reserved 94 VAA 8 POC 51 reserved 95 COMP 9 POB 96 VREF 10 POA 52 P7E 97 GND 53 P7D 98 VAA 11 PIE 54 P7C 99 VAA 12 PID 55 P7B 100 GND 13 P1iC 56 PTA 101 GND 14 PIB 1 PIA 57 reserved 102 QLEE 58 VAA 103 OLED 16 P2E 59 VAA 104 OLEC 17 P2D 60 reserved 105 OLEB 18 P2C 61 reserved 106 OLEA 19 P2B 62 GND 20 P2A 63 GND 107 OL3E 64 reserved 108 OL3D 21 reserved 65 reserved 109 OL3C 22 reserved 110 OL3B 23 reserved 66 reserved 111 OL3A 24 reserved 67 reserved 25 IZE* 68 reserved 112 OL2E 69 reserved 113 OL2D 26 LD* 70 reserved 114 OL2C 27 VAA 115 OL2B 71 reserved 116 OL2A 28 P3E 72 reserved 29 P3D 73 reserved 117 OL1E 30 GND 74 reserved 118 OL1ID 31 P3C 75 reserved 119 OL1C 32 P3B 120 OLiB 33 P3A 76 DO 121 OL1A 77 D1 34 P4E 78 D2 122 SYNC* 35 P4D 79 D3 123 BLANK* 36 P4Cc 80 D4 124 CLOCK* 37 P4B 81 D5 125 CLOCK 38 P4A 82 D6 83 D7 126 VAA 39 PSE 127 VAA 40 PSD 84 CE* 128 GND 41 PSC 85 R/W 129 GND 42 PSB 86 Cl 43 PSA 87 Co 130 reserved 131 reserved 132 reserved 34Bt459 Brooktree Pin Descriptions (continued)132-pin PQFP Package sd atTO arto dTO acl0 veto az10 daz1o 3710 qdz10 Vo10 OO AR A ee LLL PL Pe g L6 86 ooL tor Cl 01 yOl sol GOL tol 3 0) v7 82. pe wt BOL. = OPE: tt tH ut PIL Stl StL i] ps ao [] ps 79 T] v3 78 1] p 7.7) pi 76 1] Do 81 751] Nec 74] nic 7m Nic 2a: T) we r] Nic 70. nrc W 69 -] Nc 6] Nc (TOP VIEW) [] GND 62 -[] GND oy 1] Nec 6] nrc 6s] we 6 T] nrc r] nc 6: ] nec so PF] vAA 58] VAA 37] Nc s (] pva 55 [] PB s42f] prc sz] PID sx] PE st] nec 63 61 6P Le oF Sr tr. ep Op. 6 gt Le 9E Se ze le of 62 8% iz 9% st e% ira 61 $1 ovie [} 117 oLip EF} 1s ovic T] 119 oLip [120 OLIA [] 121 sync* [] 122 BLANK* [] 123 cLocks fF} 124 clock [125 vaa [126 vaa [] 127 GND [] 128 GND [J 129 ne [130 wc [}131 [] oN [J oN Ay va [] sod [] 294 [] aod [] aod Lr] vsd [J asd [] Osa rj asa [} asd [] ved [] abd [] ord [] dra [] abd [] ved [] aed [] Jed [] aNo [] aca [| aed | vvA [J +aT r] +32Z1 Pr] ON Tr] ON [] ON ] ON [] ved [] sz [] 2% 35Bt459 Brooktree PC Board Layout Considerations PC Board Considerations For optimum performance of the Bt459, proper CMOS RAMDAC layout techniques should be studied in the Bt451/7/8 Evaluation Module Operation and Measure- ments, Application Note (AN-16), before PC board layout is begun. This application note can be found in Brooktree's Applications Handbook. The layout should be optimized for lowest noise on the Bt459 power and ground planes by providing good decoupling. The trace length between groups of VAA and GND pins should be as short as possible to mini- mize inductive ringing. A well-designed power distribution network is criti- cal to eliminating digital switching noise. The ground plane must provide a low-impedance return path for the digital circuits. A PC board with a minimum of six layers is recommended. The ground layer should be a shield to isolate noise from the analog traces with layer 1 (top) for the analog traces, layer 2 for the ground plane, layer 3 for the analog power plane, and the re- maining layers used for digital traces and digital power supplies. Component Placement Components should be placed as close as possible to the associated RAMDAC pin. Whenever possible, components should be placed so traces can be connect- ed point to point. The optimum layout enables the Bt459 to be located as close as possible to the power supply connector and the video output connector. Ground Planes For optimum performance, a common digital and ana- log ground plane is recommended. Power Planes Separate digital and analog power planes are recom- mended. The digital power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all Bt459 power pins, VREF circuitry, and COMP and VREF decou- pling. There should be at least a 1/8-inch gap between the digital power plane and the analog power plane. The analog power plane should be connected to the digital power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 13. This bead should be located within 3 inches of the Bt459. The 36 bead provides resistance to switching currents, acting as a resistance at high frequencies. A low-resistance bead should be used, such as Ferroxcube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. Device Decoupling For optimum performance, all capacitors should be lo- cated as close as possible to the device and should use the shortest possible leads (consistent with reliable op- eration) to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance. Radi- al lead ceramic capacitors may be substituted for chip capacitors and are better than axial lead capacitors for self-resonance. Values are chosen to have self- resonance above the pixel clock. Power Supply Decoupling The best power supply decoupling is obtained with a 0.1 uF ceramic capacitor in parallel with a 0.01 LF chip capacitor, decoupling each of the four groups of VAA pins to GND. The capacitors should be placed as close as possible to the device VAA and GND pins, and should be connected with short, wide traces. The 33 pF capacitor shown in Figure 13 is for low- frequency power supply ripple. The 0.1 F and 0.01 pF capacitors are for high-frequency power supply noise rejection. When a linear regulator is used, the power-up se- quence must be verified to prevent latchup. A linear regulator is recommended to filter the analog power supply if the power supply noise is greater than or equal to 200 mV. This is especially important when a switching power supply is used and the switching fre- quency is close to the raster scan frequency. About 10 percent of the power supply hum and ripple noise less than 1 MHz will couple onto the analog outputs. COMP Decoupling The COMP pin must be decoupled to VAA, typically with a 0.1-}HF ceramic capacitor. Low-frequency sup- ply noise will require a larger value. The COMP capac- itor must be as close as possible to the COMP and VAA pins. A surface-mount ceramic chip capacitor is preferred for minimal lead inductance, which degrades the noise rejection of the circuit. Short, wide traces will also reduce lead inductance. If the display has a ghosting problem, additional ca- pacitance in parallel with the COMP capacitor may help.Brooktree Bt459 PC Board Layout Considerations (continued) VREF Decoupling A 0.1 uF ceramic capacitor should be used to decouple this input to VAA. If VAA is excessively noisy, better performance may be obtained by decoupling VREF to GND. Alternate PCB pads (one to VAA and one to GND) are recommended for the VREF decoupling capacitor. Digital Signal Interconnect The digital inputs to the Bt459 should be isolated as much as possible from the analog outputs and other an- alog circuitry. Also, these input signals should not overlay the analog power and output signals. Most noise on the analog outputs will be caused by excessive edge rates (less than 3 ns), overshoot, under- shoot, and ringing on the digital inputs. The digital edge rates should not be faster than nec- essary, as feedthrough noise is proportional to the digi- tal edge rates. Lower-speed applications will benefit from using lower-speed logic (3-5 ns edge rates) to re- duce data-related noise on the analog outputs. Transmission lines will mismatch if the lines do not match the source and destination impedance. This will degrade signal fidelity if the line length reflection time is greater than one fourth the signal edge time (refer to Brooktree Application Notes AN-11 and AN-12). Line termination or line-length reduction is the solution. For example, logic edge rates of 2 ns require line lengths of less than 4 inches without using termination. Ringing may be reduced by damping the line with a series resis- tor (30-300 Q). Radiation of digital signals can also be picked up by the analog circuitry. This is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing with damping resistors, and minimizing coupling through PC board capacitance by routing the digital signals at a 90 degree angle to any analog signals. The clock driver and all other digital devices must be adequately decoupled to prevent noise generated by the digital devices from coupling into the analog circuitry. Analog Signal Interconnect The Bt459 should be located as close as possible to the output connectors to minimize noise pickup and reflec- tions due to impedance mismatch. The analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under or adjacent to the analog output traces. To maximize the high-frequency power supply rejec- tion, the video output signals should not overlay the an- alog power plane. For maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same. The load resistor connection be- tween the video outputs and GND should be as close as possible to the Bt459 to minimize reflections. Unused analog outputs should be connected to GND. Analog output video edges exceeding the CRT mon- itor bandwidth can be reflected, producing cable-length dependent ghosts. Simple pulse filters can reduce high- frequency energy, reducing EMI and noise. The filter impedance must match the line impedance. Analog Output Protection The Bt459 analog output should be protected against high-energy discharges, such as those from monitor arc-over or from hot-switching AC-coupled monitors. The diode protection circuit shown in Figure 13 can prevent latchup under severe discharge conditions with- out adversely degrading analog transition times. The 1N4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface- mountable pairs (BAV99 or MMBD7001). 37Bt459 PC Board Layout Considerations (continued) COMP VAA VWREF Bt459 GND PLL FS ADJUST JOR 10G 1OB (POWER SUPPLY a clo ANALOG POWER PLANE wt Lo C2-C5 C6-C9 Li T T 4 +5 (VCC) + 2 C12 cl GROUND CONNECTOR) RSET Ss RI R2 | R3 @ TO CP)- VIDEO CONNECTOR (?P) VS Note: Each pair of device VAA and GND pins must be separately decoupled with 0.1 UF and 0.01 YF capacitors. DAC OUTPUT VAA 1N4148/9 TO MONITOR 1N4148/9 GND Location Description Vendor Part Number C1-CS5, C10, Cll C6-C9 C12 Ll R1, R2, R3 R4 RSET Zl 0.1 pF ceramic capacitor 0.01 pF ceramic chip capacitor 33 pF tantalum capacitor ferrite bead 75 {21% metal film resistor 1000 Q 1% metal film resistor 23 Q 1% metal film resistor 1.2 V voltage reference Erie RPE110Z5U104MS50V AVX 12102T103QA1018 Mallory CSR13F336KM Fair-Rite 2743001111 Dale CMF-55C Dale CMF-55C Dale CMF-55C National Semiconductor LM385Z-1.2 The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not affect the performance of the Bt459. 38 Figure 13. Typical Connection Diagram and Parts List.Brooktree Bt459 Application Information Clock Interfacing Because of the high clock rates at which the Bt459 may operate, it is designed to accept differential clock signals (CLOCK and CLOCK*). These clock inputs are generated by ECL logic operating at +5 V. The CLOCK and CLOCK* inputs require termination re- sistors (220 Q to GND) that should be located as close as possible to the clock driver. A 150 Q chip resistor connected between the RAMDAC's CLOCK and CLOCK* pins is also required to ensure proper termi- nation. It should be located as close as possible to the RAMDAC. (See Figure 14.) The CLOCK and CLOCK* inputs must be differen- tial signals and greater than 0.6 V peak-to-peak be- cause of the noise margins of the CMOS process. The Bt459 will not function using a single-ended clock with CLOCK* connected to ground. Typically, LD* is generated by dividing CLOCK by four or five (depending on whether 4:1 or 5:1 multi- plexing was specified), and translating the result to TTL levels. As LD* may be phase shifted relative to CLOCK, the designer need not worry about propaga- tion delays in deriving the LD* signal. LD* may be used as the shift clock for the video DRAMs and to generate the fundamental video timing of the system (SYNC*, BLANK*, etc.). For display applications where a single Bt459 is be- ing used, it is recommended that the Bt438 Clock Generator Chip be used to generate the clock and load +5V 14 +5 V CLOCK MONITOR PRODUCTS 970E 330 | 7 220 CLOCK* Bt438 LDA VREF signals. It supports the 4:1 and 5:1 input multiplexing of the Bt459, and will optionally set the pipeline de- lay of the Bt459 to eight clock cycles. The Bt438 may also be used to interface the Bt459 to a TTL clock. Figure 14 illustrates the Bt438 used with the Bt459. When using a single Bt459, the PLL output is ig- nored and should be connected to GND (either directly or through a resistor of up to 150 9). Using Multiple Bt459s For display applications where up to four Bt459s are being used, it is recommended that the Bt439 Clock Generator Chip be used to generate the clock and load signals. It supports the 4:1 and 5:1 input multiplexing of the Bt459, synchronizes them to subpixel resolution and sets the pipeline delay of the Bt459 to eight clock cycles. The Bt439 may also be used to interface the Bt459 to a TTL clock. Figure 15 illustrates the Bt439 used with the Bt459. Subpixel synchronization is supported by the PLL output. Essentially, PLL provides a signal to indicate the amount of analog output delay of the Bt459, rela- tive to CLOCK. The Bt439 compares the phase of the PLL signals generated by up to four Bt459s, and ad- justs the delay of each of the CLOCK and CLOCK* signals to the Bt459s to minimize the PLL delay differ- ence. There should be minimal layout skew in the CLOCK and PLL trace paths to ensure proper clock alignment. @>| CLOCK 220 150 Bt459 CLOCK* Lb* VAA or GND 0. be AVAY, + VREF 1K Figure 14. Generating the Bt459 Clock Signals. 39Bt459 Brooktree Application Information (continued) If subpixel synchronization of multiple Bt459s is not CLOCK and CLOCK* lines. The PLL outputs of the Bt459s will not be used and should be connected to necessary, the Bt438 Clock Generator Chip may be used rather than the Bt439. In this instance, the CLOCK, CLOCK*, and LD* inputs of up to four Bt459s are connected together and driven by a single Bt438 (daisy chain with single balanced termination for <100 MHz or through a 10H116 buffer for >100 MHz). The VREF inputs of the Bt459s must still have a 0.1 pF bypass capacitor to VAA, and individual voltage refer- ences. The designer must minimize skew on the GND (either directly or through a resistor of up to 150 Q). When multiple Bt459s are used, each Bt459 should have its own power plane ferrite bead and voltage refer- ence. Each Bt459 must still have its own RSET resistor, analog output termination resistors, power supply by- pass capacitors, COMP capacitor, and VREF capacitor. +5V PLLO asv CLOCKO 14 CLOCKo* MONITOR 220 PRODUCTS 970E 330 |? Bt439 +5V PLL CLOCK1 2.2K 2N3904 TO BT439 430 FROM BT459 ae a Figure 15. Generating the Clock Signals for Multiple Bt459s. 40 CLOCK1* PLL2 CLOCK2 CLOCK2* LD PLL (ai) cock (RI) | CLOCK* Bt459 r=] LD* VAA # 1 4 T 0.1 VREF LM385Z.- 1.2 J PLL H(Rt) CLOCK RI CLOCK* @)- Bt4s9 eo Lp VAA #2 1K Ss t 0.1 VREF LM385Z.- 1.2 a} PLL (a1) (e) CLOCK H(i} CLOCK* Bt459 Lp* VAA #3 IK 0.1 VREF LM385Z - 1.2Brooktree Bt459 Application Information (continued) Setting the Pipeline Delay The pipeline delay of the Bt459, although fixed after a power-up condition, may be anywhere from six to ten clock cycles. The Bt459 contains additional circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438, Bt439, and Bt440 Clock Generator Chips support this mode of operation when used with the Bt459. It is strongly recommended that the Bt438, Bt439, or Bt440 be used for clock generation when multiple Bt459s are used or when a fixed pipeline of eight clock cycles is necessary. To reset the Bt459, it should be powered up with LD*, CLOCK, and CLOCK* running. The CLOCK and CLOCK* signals should be stopped with CLOCK high and CLOCK* low for at least three rising edges of LD*. There is no upper limit on how long the device can be held with CLOCK and CLOCK* stopped. CLOCK and CLOCK* should be restarted so that the first edge of the signals is as close as possible to the rising edge of LD*. (The falling edge of CLOCK leads the rising edge of LD* by no more than 1 clock cycle or follows the rising edge of LD* by no more than 1.5 clock cycles.) When the clocks are restarted, the minimum clock pulse width must not be violated. To ensure that the Bt459 has the proper configura- tion, all the command registers must be initialized prior to a fixed pipeline reset. Because of this requirement, Scan Line Output Sequence ABCDABCD... DABCDABC... CDABCDAB... BCDABCDA... ABCDABCD... DABCDABC... CDABCDAB... BCDABCDA... NAW PWN Table 9. Interleave Example. the power-up that occurs prior to initialization of the command registers cannot be used to assume the fixed pipeline. An additional reset is required after command register writes. When the Bt459 is reset to an eight-clock-cycle pipeline delay, the blink counter circuitry is not reset. Therefore, if the multiple Bt459s are used in parallel, the on-chip blink counters may not be synchronized. In this instance, the blink mask register should be $00 and the overlay blink enable bits a logical zero. Blinking may be done under software control through the read mask register and overlay display enable bits. The Bt459 must be reset to an eight-clock-cycle pipeline delay for proper cursor pixel alignment. Interleave Operation To support interleaved frame buffers, the Bt459 may be configured for various interleave factors, as shown in Table 8. Table 9 is an example of interleave opera- tion for 4:1 multiplexing, an interleave select of 3, and starting with pixel {A}. Table 10 is an example of the same operation with pixel {B} selected as the starting pixel (with the display panned down three scan lines). Scan line number 0 corresponds to the top of the dis- play screen and is the first displayed scan line after a vertical blanking interval. The output sequence is shown starting at the left-most displayed pixel. Scan Line Output Sequence BCDABCDA... ABCDABCD... DABCDABC... CDABCDAB... BCDABCDA... ABCDABCD... DABCDABC... CDABCDAB... _ WINN WNKE CO Table 10. interleave Example. 41Bt459 Brooktree Application Information (continued) ESD and Latchup Considerations Correct ESD-sensitive handling procedures are re- quired to prevent device damage, which can produce symptoms of catastrophic failure or erratic device be- havior with somewhat leaky inputs. All logic inputs should be held low until power to the device has settled to the specified tolerance. DAC power decoupling networks with large time constants should be avoided. They could delay VAA power to the device. Ferrite beads must be used only for analog power VAA decoupling. Inductors cause a time con- stant delay that induces latchup. Latchup can be prevented by ensuring that all VAA pins are at the same potential and that the VAA supply voltage is applied before the signal pin voltages. The correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V. Test Features of the Bt459 The Bt459 contains two dedicated test registers and an analog output comparator that assist the user in evalu- ating the performance and functionality of the part. This section explains the operating use of these test features. Signature Register (Signature Mode) The signature register, in the active mode, operates with the 24 bits of data that are output from the color palette RAM. These 24-bit vectors represent a single pixel color. They are presented as inputs simultaneous- ly to the red, green, and blue signature analysis regis- ters (SARs), as well as to the three on-chip DACs. The SARs act as a 24-bit wide linear feedback shift register on each succeeding pixel that is latched. It is important to note that in either the 4:1 or 5:1 multi- plexed mode the SARs latch only 1 pixel per load group. Thus, the SARs are operating on only every fourth or fifth pixel in the multiplexed modes. The user determines which pixel phase (A, B, C, D, or E) is latched to generate new signatures by setting bits DO- D2 in the test register. In 1:1 mux mode, the SARs will generate signatures truly on each succeeding pixel in the input stream. In this case, the user should always select pixel "A" (Test Register DO, D1, and D2 = 000) when in the 1:1 mode, since the "A" pixel pins are the only active pixel inputs. 42 The Bt459 will only generate signatures while it is in "active-display" (BLANK* negated). The SARs are available for reading and writing via the MPU port when the Bt459 is in a blanking state (BLANK? assert- ed). Specifically, it is safe to access the SARs after the DAC outputs are in the blanking state (up to 15 pixel clock periods after BLANK* is asserted). Typically, the user will write a specific 24-bit seed value into the SARs. Then, a known pixel stream, e.g., one scan line or one frame buffer of pixels, will be in- put to the chip. At the succeeding blank state, the resul- tant 24-bit signature can be read by the MPU. The 24- bit signature register data is a result of the same cap- tured data that is fed to the DACs. Thus, overlay and cursor data validity is also tested with the signature registers. Assuming the chip is running 4:1 or 5:1 mux modes, the above process would be repeated with all different pixel phases (A, B, C, etc.) selected. The linear feedback configuration is shown in Fig- ure 16. Each register internally uses XORs at each in- put bit (Dp) with the output (result) by 1 least signifi- cant bit (Qp-1). Experienced users have developed tables of specific seeds and pixel streams, and recorded the signatures that result from those inputs applied to known-good parts. A good signature from one given pixel stream can by used as the seed for the succeeding stream to be tested. Any signature is deterministically created from a starting seed, and the succeeding pixel stream is fed to the SARs. Signature Register (Data-Strobe Mode) Setting command bit CR20 to 1" puts the SARs into data-strobe mode. In this instance, the linear feedback circuits of the SARs are disabled, which stops the gen- eration of signatures by the SARs. Instead, the SARs capture and hold the respective pixel phase that is selected. Any MPU data written to the SARs is ignored. How- ever, each pixel color value that is strobed into the SARs can be directly checked. To read out a captured color in the middle of a pixel stream, the user should first freeze all inputs to the Bt459. The levels of most inputs do not matter except that CLOCK should be high and CLOCK* should be low. Then, the user may read out the pixel color by doing three successive MPU reads from the red, green, and blue SARs, respectively.Brooktiree Bt459 Application Information (continued) In general, the color read out will correspond to a pixel latched on the previous load. However, because the data path is pipelined, the color may come from an earlier load cycle. To read successive pixels: 1. Toggle LD*. 2. Pulse the CLOCK pins according to the mux state (one, four, or five periods). 3. Hold all pixel-related inputs. 4, Perform the three MPU reads as described. This process is best done on a sophisticated VLSI semiconductor tester. Analog Comparator The other dedicated test structure in the Bt459, the ana- log output comparator, allows the user to measure the DACs against each other, as well as against a specific reference voltage. Four combinations of tests are selected through the test register. With a given setting, the respective sig- nals (DAC outputs or the 145 mV reference) will be continuously input to the comparator. The result of the comparator is latched into the test register on each of the 64 scan lines of the 64 x 64 user-defined cursor block. (The 64 x 64 cursor must be enabled for dis- play.) On each of these 64 scan lines, the capture oc- curs over one LD* period that corresponds to the cur- sor (x) position, set by the 12-bit cursor (x) register. To obtain a meaningful comparison, the cursor should be located on the visible screen. There is no significance to the cursor pattern data in the cursor RAM. For a visual reference, the capture point occurs over the left-most edge of the 64 x 64 cursor block. Because the comparator is a simple design, it is rec- ommended that the DAC outputs be stable for 5 pus be- fore capture. At a display rate of 100 MHz, 5 jis corre- sponds to 500 pixels. In this case, the cursor (x) position should be set to well over 500 pixels to ensure an adequate supply of pixels. Furthermore, either the color palette RAM or the pixel inputs (or both) should be configured to guarantee a single continuous output from the DACs under test, until capture. Typically, users will create screen-wide test bands of various colors. Various comparison cases are set up by moving the cursor up and down (by changing the 12-bit cursor (y) register) over these bands. For each test, the result is obtained by reading test register bit D3. RO-R7 GO-G7 BQ. B7 FROM LOOKUP TABLE FROM LOOKUP TABLE FROM LOOKUP TABLE RED GREEN BLUE IN 012345 67 IN 01234567 a Mi MPU SAR READ BIT diiltdad at Figure 16. Signature Analysis Register Circuit. 43Bt459 Application Information (continued) Initializing the Bt459 Following a power-on sequence, the Bt459 must be initialized. This sequence will configure the Bt459 as follows: * 4:1 multiplexed operation * no overlays, no blinking, and no interleave 64x 64 block cursor and no cross hair cursor * 8 bits per pixel, no panning, and no zoom * sync enabled on IOG and a 7.5 IRE blanking pedestal Control Register Initialization Write $01 to address register low Write $02 to address register high Write $40 to command register_0 Write $00 to command register_1 Write $CO to command register_2 Write $FF to pixel read mask register Write $00 to reserved location Write $00 to pixel blink mask register Write $00 to reserved location Write $00 to overlay read mask register Write $00 to overlay blink mask register Write $00 to interleave register Write $00 to test register Write $00 to address register low Write $03 to address register high Write $CO to cursor command register Write $00 to cursor (x) low register Write $00 to cursor (x) high register Write $00 to cursor (y) low register Write $00 to cursor (y) high register Write $00 to window (x) low register Write $00 to window (x) high register Write $00 to window (y) low register Write $00 to window (y) high register Write $00 to window width low register Write $00 to window width high register Write $00 to window height low register Write $00 to window height high register 44 C1, CO 00 01 10 10 10 10 10 10 10 10 10 10 10 00 01 10 10 10 10 10 10 10 10 10 10 10 10 10 Load Cursor RAM Pattern Write $00 to address register low Write $04 to address register high Write $FF to cursor RAM (location $000) Write $FF to cursor RAM (location $001) Write $FF to cursor RAM (location $3FF) Color Palette RAM Initialization Write $00 to address register low Write $00 to address register high Write red data to RAM (location $00) Write green data to RAM (location $00) Write blue data to RAM (location $00) Write red data to RAM (location $01) Write green data to RAM (location $01) Write blue data to RAM (location $01) Write red data to RAM (location $FF) Write green data to RAM (location $FF) Write blue data to RAM (location $FF) Overlay Color Palette Initialization Write $00 to address register low Write $01 to address register high Write red data to overlay (location $0) Write green data to overlay (location $0) Write blue data to overlay (location $0) Write red data to overlay (location $1) Write green data to overlay (location $1) Write blue data to overlay (location $1) Write red data to overlay (location $F) Write green data to overlay (location $F) Write blue data to overlay (location $F) Cursor Color Palette Initialization Write $81 to address register low Write $01 to address register high Write red data to cursor (location $0) Write green data to cursor (location $0) Write blue data to cursor (location $0) Write red data to cursor (location $1) Write green data to cursor (location $1) Write blue data to cursor (location $1) Write red data to cursor (location $2) Write green data to cursor (location $2) Write blue data to cursor (location $2) 01 10 10 01 11 11 1] 11 11 11 11 11 11 01 10 10 10 10 10 10 10 10 10 01 10 10 10 10 10 10 10 10 10Brooktree Bt459 Recommended Operating Conditions Parameter Symbol Min Typ Max Units Power Supply VAA 4.75 5.00 5.25 v Ambient Operating Temperature TA 0 +70 C Output Load RL 37.5 Q Reference Voltage VREF 1.20 1.235 1.26 v FS ADJUST Resistor RSET 523 Q Air Flow (Note 1) 50 Lf.p.m. Note 1: Required for Bt459KPF150 only. Absolute Maximum Ratings Parameter Symbol Min Typ Max Units VAA (measured to GND) 6.5 Vv Voltage on Any Signal Pin GND-0.5 VAA + 0.5 Vv (Note 1) Analog Output Short Circuit Duration to any Power Supply or Common ISC indefinite Ambient Operating Temperature TA -55 +125 C Storage Temperature TS -65 +150 C Junction Temperature TJ PQFP TJ +150 C PGA TJ +175 C Soldering Temperature TSOL 260 C (5 seconds, 1/4" from pin) Vapor Phase Soldering TVSOL 220 C (1 minute) Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup. 45Bt459 DC Characteristics 46 Parameter Symbol Min Typ Max Units Analog Outputs Resolution (each DAC) 8 8 8 Bits Accuracy (each DAC) Integral Linearity Error IL +1 LSB Differential Linearity Error DL +1 LSB Gray Scale Error +5 % Gray Scale Monotonicity guaranteed Coding Binary Digital Inputs (except CLOCK, CLOCK*) Input High Voltage VIH 2.0 VAA + 0.5 Vv Input Low Voltage VIL GND-0.5 0.8 Vv Input High Current (Vin = 2.4 V) NH 1 pA Input Low Current (Vin = 0.4 V) IIL -1 pA Input Capacitance CIN 4 10 pF (f = 1 MHz, Vin = 2.4 V) Clock Inputs (CLOCK, CLOCK*) Differential Input Voltage AVIN 6 6 Vv Input High Current (Vin = 4.0 V) IKIH 1 pA Input Low Current (Vin = 0.4 V) IKIL -l pA Input Capacitance CKIN 4 10 pF (f = 1 MHz, Vin = 4.0 V) Digital Outputs (D0-D7) Output High Voltage VOH 2.4 Vv (IOH = -400 WA) Output Low Voltage VOL 0.4 Vv (IOL = 3.2 mA) 3-state Current I0Z 10 pA Output Capacitance CDOUT 10 pF See test conditions on next page.Brooktree Bt459 DC Characteristics (continued) Parameter Symbol Min Typ Max Units Analog Outputs Output Current White Level Relative to Blank 17.69 19.05 20.40 mA White Level Relative to Black 16.74 17.62 18.50 mA Black Level Relative to Blank SETUP = 7.5 IRE 0.95 1.44 1,90 mA SETUP = 0 IRE 0 5 50 pA Blank Level on IOG 6.29 7.62 8.96 mA Blank Level on IOR, IOB 0 5 50 pA Sync Level on IOG 0 5 50 pA LSB Size 69.1 pA DAC-to-DAC Matching 2 5 % Output Compliance voc -0.5 +1.2 Volts Output Impedance RAOUT 50 kQ Output Capacitance CAOUT 13 20 pF (f = 1 MHz, IOUT = 0 mA) PLL Analog Output PLL Output Current SYNC*/BLANK* = 0 6.00 7.62 9.00 mA SYNC*/BLANK* = | 0 5 50 HA Output Compliance ~0.5 +25 Volts Output Impedance 50 kQ Output Capacitance 8 15 pF (f = 1 MHz, PLL = 0 mA) Voltage Reference Input Current IREF Rev. A 500 pA Rev. B 10 pA Power Supply Rejection Ratio PSRR 0.5 %o 1% AVAA (COMP = 0.1 pF, f = 1 kHz) Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 Q and VREF = 1.235 V. SETUP = 7.5 IRE. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V. 47Bt459 Brooktree AC Characteristics Parameter Symbol | Min/Typ/ 150 135 110 80 Units Max MHz MHz MHz MHz Clock Rate Fmax max 150 135 110 80 MHz LD* Rate LDmax 1:1 multiplexing max 50 50 50 50 MHz 4:1 multiplexing max 37.50 33.75 27.5 20 MHz 5:1 multiplexing max 30 27 22 16 MHz R/W, CO, C1 Setup Time 1 min 0 0 0 0 ns R/W, CO, C1 Hold Time 2 min 10 10 10 10 ns CE* Low Time 3 min 40 40 40 40 ns CE* High Time 4 min 20 20 20 20 ns CE* Asserted to Data Bus Driven 5 min 10 10 10 10 ns CE* Asserted to Data Valid 6 max 75 75 75 75 ns CE* Negated to Data Bus 3-Stated 7 max 15 15 15 15 ns Write Data Setup Time 8 min 15 15 15 {5S ns Write Data Hold Time 9 min 2 2 2 2 ns Pixel and Control Setup Time 10 min 3 3 3 3 ns Pixel and Control Hold Time 11 min 2 2 2 2 ns Clock Cycle Time 12 min 6.67 7.4 9.09 12.5 ns Clock Pulse Width High Time 13 min 2.7 3.2 4 5 ns Clock Pulse Width Low Time 14 min 2.7 3.2 4 5 ns LD* Cycle Time 15 1:1 multiplexing min 20 20 20 20 ns 4:1 multiplexing min 26.67 29.63 36.36 50 ns 5:1 multiplexing min 33.33 37.04 45.45 62.5 ns LD* Pulse Width High Time 16 1:1 multiplexing min 7 7 7 7 ns 4:1 or 5:1 multiplexing min 11 12 15 20 ns LD* Pulse Width Low Time 17 1:1 multiplexing min 7 7 7 7 ns 4:1 or 5:1 multiplexing min 11 12 15 20 ns See test conditions on next page.Brooktree Bt459 AC Characteristics (continued) Parameter Symbol | Min/Typ/ 150 135 110 80 Units Max MHz MHz MHz MHz Analog Output Delay 18 typ 12 12 12 12 ns Analog Output Rise/Fall Time 19 typ 1.5 1.5 1.5 2 ns Analog Output Settling Time 20 max 8 8 8 12 ns Clock and Data Feedthrough typ 28 -28 28 -28 dB (Note 1) Glitch Impulse (Note 1) typ 50 50 50 50 pV - sec Analog Output Skew typ 0 0 0 0 ns max 2 2 2 2 ns Pipeline Delay min 6 6 6 6 Clocks max 10 10 10 10 Clocks VAA Supply Current (Note 2) IAA typ 260 240 220 200 mA max 385 360 335 300 mA Test conditions (unless otherwise specified): Signature Analysis Register (SAR) functionality is not guaranteed at 150 MHz. "Recommended Operating Conditions with RSET = 523 Q and VREF = 1.235 V. TTL input values are 0-3 V with input rise/fall times < 4 ns, measured between the 10-percent and 90-percent points. ECL input values are VAA-0.8 to VAA-1.8 V with input rise/fall times < 2 ns, measured between the 20-percent and 80-percent points. Timing reference points at 50 percent for inputs and outputs. Analog output load < 10 pF and DO-D7 output load < 75 pF. See timing notes in Figure 18. As the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V. Note 1: Clock and data feedthrough is a function of the number of edge rates, and the amount of overshoot and undershoot on the digital inputs. For this test, the TTL digital inputs have a 1 kQ resistor to GND and are driven by 74HC logic. Settling time does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough; and -3 dB test bandwidth = 2x clock rate. Note 2: At Fmax. IAA (typ) at VAA = 5.0 V and TA = 20 C. IAA (max) at VAA = 5.25 V and TA =0C. 49Bt459 Brooktree Timing Waveforms 2 1 RW, CO, Cl VALID 3 CE* N / 4 | 6 5 7 DO-D7(READ) = _______--______----_______| DATA OUT (R/W = 1) DO - D7 (WRITE) DATA IN (R/W = 0) 8 9 Figure 17. MPU Read/Write Timing Dimensions. 15 16 | 17 - y\ Ne eee eee PO-P7{A-E}, OLE {A-E}, OLO-OL3 {A-E}, DATA Xx Xx SYNC*, BLANK* 10 IOR, 10G, IOB, PLL cxoce YN S\S\S Note I: Output delay time is measured from 50-percent point of the rising clock edge to 50-percent point of full-scale transition. Note 2: Output settling time is measured from 50-percent point of full-scale transition to output settling within +1 LSB. Note 3: Output rise/fall timeis measured between 10-percent and 90-percent points of full-scale transition. Figure 18. Video Input/Output Timing. 50Brooktree Bt459 Ordering Information Ambient Model Number Speed Package Temperature Range Bt459KG150 150 MHz 132-pin Ceramic PGA 0 to +70 C Bt459KG135 135 MHz 132-pin Ceramic PGA 0 to +70 C Bt459KG110 110 MHz 132-pin CeramicPGA 0 to +70 C Bt459KG80 80 MHz 132-pin Ceramic PGA 0 to +70 C Bt459KPF150 150 MHz 132-pin Plastic 0 to +70 C Quad Flatpack with 50 LFPM Airflow Bt459KPF135 135 MHz 132-pin Plastic 0 to +70 C Quad Flatpack Bt4S9KPF110 110 MHz 132-pin Plastic 0 to +70 C Quad Flatpack Bt459KPF80 80 MHz 132-pin Plastic 0 to +70 C Quad Flatpack 51Bt459 Brooktree Package Drawing132-pin Plastic Quad Flatpack (PQFP) 52 1.075/1.085 [27.30/27 55] $Q + r 0,025 [0.635] TYP Aon vs} ro a a 3 oa an <= a PIN NO. t = 925 IDENTIFIER A * oo oa - on = = Ss Am SS 2 R423) = 3 Sp Oo] > es 56 9 os 3 2 = gz + 3 = = = 2 23 3 aa = & = oO Ss x 2 g S tt S&B 3 = 3 3 | 0.800 [20.32] REF __ x nye UAUUUUCUUUEGEEUEGUUAUUUUAHEAULUEL 17 W7 PIN} me 8 16m -_ = = _ = = = = = = = = = = = = = = = _= = = = = = = = = = ++ = = mm = = = = = = = = = = = = = = = = = = = -_ = = = -_ = m 50 84 = 51 83 invncsuay jana FOOTPRINT Notes: Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xxx + 0.005 [0.127]. 0.180 [4.572] MAX 0.020 (0.508) MIN - - 0.020/0,030 (0.508 /0.762] | LENGTH OF TERMINAL FOR | L SOLDERING TO A SUBSTRATE 0.007/0.009 [0.177/0.228] DETAIL A ROTATED 90 3. PQFP packages are intended for surface mounting on solder lands on 0.025 [0.635] centers.Brooktree. Bt459 Package Drawing132-pin Ceramic PGA 1.300 (33.02) re- 0.100 [2.540] Lt O @ O O@ @ O ORO) OVOODDOOOOOO @ 1.400 [35.56] SQ 0.770 (19.56) SQ OO OCOD OCOAOO OD OODOOOQOXOG OO OCOCOOCOAUOOG - HOGOOOOCOOOO VNIOODOOOOOGCO OOOOQOOOOOO 4 PIN NO.1 IDENT 3 596 7 8 9 1011 121314 0.085 (21593 see peta A 0.045 [1.143] Si 0.024 [0.609] e.o16-0.020 _ || | oto c4.5723 0.050 [1.271 (0.406-0.508) tf 7 petait A 4 PL \ sunenrazcaress Notes: Unless otherwise specified: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xxx + 0.005 [0.127]. 3. Pins are intended for insertion in hole rows on 0.100" [2.54] centers. 53Bt459 Revision History 54 Datasheet Revision Device Revision B Change from Previous Revision Revised Figures 14 and 15. Revised Figures 14 and 15. Added 132-pin PQFP package, expanded PC Board Layout Considerations section, added use of test features to Application Information section, added Figure 16 and associated text in Application Information section, and revised Figure 15. Clarified MPU contention with cursor RAM in Cursor RAM subsection of Internal Registers section. Added double reset, modified PLL feedback circuitry, added Revision Register section, reduced IREF, and eliminated write contention for revision B devices. Added 150 MHz speed grade. Changed slow port timing parameters and revised PC Board Layout Considerations section. Datasheet changed from Preliminary to Final status. Reduced IREF, eliminated write contention, enhanced CE* noise immunity, and added revision register.Brooktree Bt459 55Brookxtree Brooktree Corporation. 9950 Barnes Canyon Rd. San Diego, CA 92121-2790 (619) 452-7580 1(800) 2-BT-APPS TLX: 383 596 FAX: (619) 452-1249 L459001 Rev. N ae Rockwell semiconductor ystems Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Brooktree Corporation. Copyright 1993 Brooktree Corporation. Specifications are subject to change without notice. CAUTION A Ais\ ESD-sensitive device. Permanent damage may occur on unconnected devices subjected to high-energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Do not insert this device into powered sockets. Remove power before insertion or removal. Printed in the U.S.A. Print date: 06/11/93 wn 7 Text printed on recycled pap