APW7105BBTI-TRG - Anpec Electronics Corp.

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and

advise customers to obtain the latest version of relevant information to verify before placing orders.

1.5MHz, 1A Synchronous Buck Regulator

FeaturesGeneral Description

•1A Output Current

•Wide 2.5V~6.0V Input Voltage

•Fixed 1.5MHz Switching Frequency

•Low Dropout Operating at 100% Duty Cycle

•20µA Quiescent Current

•Integrate Synchronous Rectifier

•<0.5µA Input Current During Shutdown

•Current-Mode Operation with Internal

Compensation

- Stable with Ceramic Output Capacitors

- Fast Line Transient Response

•Short-Circuit Protection

•Over-Temperature Protection with Hysteresis

•Available in TSOT-23-5A Packages

•Lead Free and Green Devices Available

(RoHS Compliant)

APW7105A/B is a 1.5MHz high efficiency monolithic syn-

chronous buck regulator. Design with current mode

scheme, the APW7105A/B is stable with ceramic output

capacitor. Input voltage from 2.5V to 6.0V makes the

APW7105A/B ideally suited for single Li-Ion battery pow-

ered applications. 100% duty cycle provides low dropout

operation, extending battery life in portable electrical

devices. The internally fixed 1.5MHz operating frequency

allows the using of small surface mount inductors and

capacitors. The synchronous switches included inside

increase the efficiency and eliminate the need of an ex-

ternal Schottky diode.

The APW7105A/B is available in TSOT-23-5A packages.

Simplified Application Circuit

Applications

•HD STB

•BT Mouse

•PND Instrument

•Portable Instrument

Pin Configuration

VIN

GND

RUN

3FB 4

APW7105A/B

SW 5

VIN VOUT

10µF

(MLCC)

2.2µH

4.7µF

(MLCC)

R1 C3

4 FB

5 SW

GND 2

RUN 3

VIN 1

TSOT-23-5A

(Top View)

APW7105A/B

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw2

Ordering and Marking Information

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which

are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for

MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen

free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by

weight).

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit

VIN Input Bias Supply Voltage (VIN to GND) -0.3 ~ 7 V

RUN, FB, SW to GND Voltage -0.3 ~ VIN+0.3 V

PD Power Dissipation Internally Limited W

Maximum Junction Temperature 150 oC

TSTG Storage Temperature -65 ~ 150 oC

TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Thermal Characteristics

Symbol Parameter Typical Value Unit

θJA Junction-to-Ambient Resistance in Free Air (Note 2) TSOT-23-5A

220 oC/W

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Symbol Parameter Range Unit

VIN Input Bias Supply Voltage (VIN to GND) 2.5 ~ 6 V

VOUT Converter Output Voltage VREF ~ VIN V

IOUT Converter Output Current 0 ~ 1 A

L1 Converter Output Inductor 1.0 ~ 10 µH

CIN Converter Input Capacitor 4.7 ~100 µF

COUT Converter Output Capacitor 4.7 ~100 µF

TA Ambient Temperature -40 ~ 85 oC

TJ Junction Temperature -40 ~ 125 oC

Recommended Operating Conditions (Note 3)

Note 3: Refer to the typical application circuit

APW7105

Handling Code

Temperature Range

Package Code

Assembly Material

APW7105A/B BT : W5YX Y - Reference Voltage Code X - Date Code

Reference Voltage Code

A : 0.5V B : 0.6V

Package Code

BT: TSOT-23-5A

Operating Ambient Temperature Range

I : -40 to 85 oC

Handling Code

TR : Tape & Reel

Assembly Material

G : Halogen and Lead Free Device

Reference Voltage Code

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw3

Electrical Characteristics

APW7105A/B

Symbol

Parameter Test Conditions Min. Typ. Max.

Unit

SUPPLY VOLTAGE AND CURRENT

VIN Input Voltage Range 2.5 - 6 V

IDD Quiescent Current VFB = 0.7V - 20 30 µA

ISD Shutdown Input Current RUN = GND - - 0.5 µA

POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS

UVLO Threshold 2.0 2.2 2.4 V

UVLO Hysteresis - 0.1 - V

REFERENCE VOLTAGE

TA = 25 oC APW7105A 0.493

0.5 0.507

TA = 25 oC APW7105B 0.591

0.6 0.609

VREF Regulated Voltage

TA = -40~85 oC APW7105A/B -2 - +2 %

Output Voltage Accuracy 0A < IOUT < 1A -2.5 - +2.5 %

IFB FB Input Current -50 - 50 nA

INTERNAL POWER MOSFETS

FSW Switching Frequency 1.2 1.5 1.8 MHz

Foldback Frequency VFB = 0.1V - 210 310 kHz

Foldback Threshold Voltage on FB VFB Falling - 0.2 - V

Foldback Hysteresis - 50 - mV

RP-FET

High Side N-FET Switch ON Resistance

ISW=200mA - 0.28 0.35 Ω

RN-FET

Low Side P-FET Switch ON Resistance ISW=200mA - 0.25 0.32 Ω

Minimum On-Time - - 100 ns

Maximum Duty Cycle - - 100 %

PROTECTION

ILIM Maximum Inductor Current-Limit IP-FET, 2.5V≦VIN≦6V 1.4 1.6 2 A

TOTP Over-Temperature Protection TJ Rising - 150 -

Over-Temperature Protection Hysteresis

TJ Falling - 30 - °C

START-UP AND SHUTDOWN

TSS Soft-Start Duration (Note 4) - 0.7 - ms

RUN Input High Threshold VIN = 2.5V~6V - - 1 V

RUN Input Low Threshold VIN = 2.5V~6V 0.4 - - V

RUN Leakage Current VRUN = 5V, VIN = 5V -1 - 1 µA

Unless otherwise specified, these specifications apply over VIN=3.6V and TA= -40 ~ 85 oC. Typical values are at

TA=25oC.

Note 4: Guarantee by design, not production test.

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw4

Pin Description

NO. NAME FUNCTION

1 VIN Device and Converter Supply Pin. Must be closely decoupled to GND with a 4.7µF or greater ceramic

capacitor.

2 GND Power and Signal Ground.

3 RUN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V shuts it

down. In shutdown, all functions are disabled to decrease the supply current below 0.5µA. Do not leave

RUN pin floating.

4 FB Feedback Input Pin. The buck regulator senses feedback voltage via FB and regulates the FB voltage at

0.5V. Connecting FB with a resistor-divider from the output sets the output voltage of the buck converter.

5 SW Switch Node Connected to Inductor. This pin connects to the drains of the internal main and synchronous

power MOSFETs switches.

Block Diagram

Oscillator

Logic Control SW

Over-

Temperature

Protection

VREF

EAMP

COMP

ICMP

Soft-

Start

Error

Amplifier

Zero-

Crossing

Comparator

Current

-Limit

Slope

Compensation

VIN

Current

Sense

Amplifier

Shutdown

Control

∑

RUN

GND

Gate

Driver

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw5

Typical Application Circuit

VIN

GND

RUN

3FB 4

APW7105A/B

SW 5

VIN

2.5~6V

VOUT

0.5V~VIN

0~1A

2.2µH

R1 C3

4.7µF

(MLCC)

10µF

(MLCC)

IIN

R1 ≤ 1.8MΩ is recommended

R2 ≤ 400kΩ is recommended

R1 x C3 = 3x10-6 ~ 8x10-6ΩF

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw6

Function Description

Main Control Loop

The APW7105A/B is a constant frequency, synchronous

rectifier and current-mode switching regulator. In normal

operation, the internal P-channel power MOSFET is

turned on every cycle. The peak inductor current at which

ICMP turn off the P-FET is controlled by the voltage on the

COMP node, which is the output of the error amplifier

(EAMP). An external resistive divider connected between

VOUT and ground allows the EAMP to receive an output

feedback voltage VFB at FB pin. When the load current

increases, it causes a slightly decrease in VFB relative to

the reference voltage, VREF, which in turn causes the COMP

voltage to increase until the average inductor current

matches the new load current.

Under-Voltage Lockout

An under-voltage lockout function prevents the device from

operating if the input voltage on VIN is lower than approxi-

mately 1.8V. The device automatically enters the shut-

down mode if the voltage on VIN drops below approxi-

mately 1.8V. This under-voltage lockout function is imple-

mented in order to prevent the malfunctioning of the

converter.

Soft-Start

The APW7105A/B has a built-in soft-start to control the

output voltage rise during start-up. During soft-start, an

internal ramp voltage, connected to the one of the posi-

tive inputs of the error amplifier, raises up to replace the

reference voltage until the ramp voltage reaches the ref-

erence voltage. Then, the voltage on FB regulated at ref-

erence voltage.

Enable/Shutdown

Driving RUN to the ground places the APW7105A/B in

shutdown mode. When in shutdown, the internal power

MOSFETs turn off, all internal circuitry shuts down and

the quiescent supply current reduces to 0.5µA maximum.

Pulse Frequency Modulation Mode (PFM)

The APW7105A/B is a fixed frequency, peak current mode

PWM step-down converter. At light loads, the

APW7105A/B will automatically enter in pulse frequency

mode operation to reduce the dominant switching losses.

In PFM operation, the inductor current may reach zero or

reverse on each pulse. A zero current comparator turns

off the N-FET, forcing DCM operation at light load. These

controls get very low quiescent current, help to maintain

high efficiency over the complete load range.

Slope Compensation and Inductor Peak Current

The APW7105A/B is a peak current mode PWM step down

converter. To prevent sub-harmonic oscillations, the

APW7105A/B senses the peak current and adds slope

compensation to stable the converter. It is accomplished

internally by adding a compensating ramp to the inductor

current signal at duty cycles in excess of 40%. Normally,

this results in a reduction of maximum inductor peak cur-

rent for duty cycles > 40%. However, the APW7105A/B

uses a special scheme that counteracts this compen-

sating ramp, which allows the maximum inductor peak

current to remain unaffected throughout all duty cycles.

Adaptive Shoot-Through Protection

The gate driver incorporates adaptive shoot-through pro-

tection to high-side and low-side MOSFETs from con-

ducting simultaneously and shorting the input supply.

This is accomplished by ensuring the falling gate has

turned off one MOSFET before the other is allowed to

rise.

During turn-off the low-side MOSFET, the internal LGATE

voltage is monitored until it is below 1.5V threshold, at

which time the UGATE is released to rise after a constant

delay. During turn-off the high-side MOSFET, the UGATE

voltage is also monitored until it is above 1.5V threshold,

at which time the LGATE is released to rise after a con-

stant delay.

Dropout Operation

As the input supply voltage decreases to a value ap-

proaching the output voltage, the duty cycle increases

toward the maximum on time. Further, reduction of the

supply voltage forces the main switch to remain on for

more than one cycle until it reaches 100% duty cycle. The

input voltage minus the voltage drop will determine the

output voltage across the P-FET and the inductor.

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw7

Function Description (Cont.)

Dropout Operation (Cont.)

An important detail to remember is that on resistance of

P-FET switch will increase at low input supply voltage.

Therefore, the user should calculate the power dissipa-

tion when the APW7105A/B is used at 100% duty cycle

with low input voltage.

Over-Temperature Protection (OTP)

The over-temperature circuit limits the junction tempera-

ture of the APW7105A/B. When the junction temperature

exceeds 150oC, a thermal sensor turns off the both power

MOSFETs, allowing the devices to cool. The thermal sen-

sor allows the converters to start a soft-start process and

regulate the output voltage again after the junction tem-

perature cools by 30oC. The OTP is designed with a 30oC

hysteresis to lower the average Junction Temperature

(TJ) during continuous thermal overload conditions, in-

creasing the lifetime of the device.

Short-Circuit Protection

When the output is shortened to the ground, the frequency

of the oscillator is reduced to about 210kHz, 1/7 of the

nominal frequency. This frequency foldback ensures that

the inductor current has more time to decay, thereby pre-

venting runaway. The oscillator’s frequency will progres-

sively increase to 1.5MHz when VFB or VOUT rises above

0V.

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw8

Application Information

Input Capacitor Selection

Because buck converters have a pulsating input current,

a low ESR input capacitor is required. This results in the

best input voltage filtering, minimizing the interference

with other circuits caused by high input voltage spikes.

Also, the input capacitor must be sufficiently large to sta-

bilize the input voltage during heavy load transients. For

good input voltage filtering, usually a 4.7µF input capaci-

tor is sufficient. It can be increased without any limit for

better input-voltage filtering. Ceramic capacitors show

better performance because of the low ESR value, and

they are less sensitive against voltage transients and

spikes compared to tantalum capacitors. Place the input

capacitor as close as possible to the input and GND pin of

the device for better performance.

Inductor Selection

For high efficiencies, the inductor should have a low DC

resistance to minimize conduction losses. Especially at

high-switching frequencies, the core material has a

higher impact on efficiency. When using small chip

inductors, the efficiency is reduced mainly due to higher

inductor core losses. This needs to be considered when

selecting the appropriate inductor. The inductor value de-

termines the inductor ripple current. The larger the induc-

tor value, the smaller the inductor ripple current and the

lower the conduction losses of the converter. Conversely,

larger inductor values cause a slower load transient

response. A reasonable starting point for setting ripple

current, ∆IL, is 40% of maximum output current. The rec-

ommended inductor value can be calculated as below:

LSW

OUT

IFV

L∆⋅











−

≥

IL(MAX) = IOUT(MAX) + 1/2 x ∆IL

To avoid the saturation of the inductor, the inductor should

be rated at least for the maximum output current of the

converter plus the inductor ripple current.

Output Voltage Setting

In the adjustable version, the output voltage is set by a

resistive divider. The external resistive divider is con-

nected to the output, allowing remote voltage sensing as

shown in “Typical Application Circuits.” A suggestion of

maximum value of R2 is 400kΩ to keep the minimum

current that provides enough noise rejection ability through

the resistor divider. The output voltage can be calculated

as below:

Output Capacitor Selection

The current-mode control scheme of the APW7105A/B

allows the use of tiny ceramic capacitors. The higher ca-

pacitor value provides the good load transients response.

Ceramic capacitors with low ESR values have the lowest

output voltage ripple and are recommended. If required,

tantalum capacitors may be used as well. The output

ripple is the sum of the voltages across the ESR and the

ideal output capacitor.











⋅⋅

+⋅

⋅











−⋅

≅∆OUTSWSW

OUT

OUT CF81

ESR

LFV

When choosing the input and output ceramic capacitors,

choose the X5R or X7R dielectric formulations. These

dielectrics have the best temperature and voltage char-

acteristics of all the ceramics for a given value and size.

VIN

VOUT

N-FET

IOUT

CIN

COUT

IIN

ESR

P-FET

IP-FET











+⋅=











+⋅=2R1R

15.0

2R1R

1VV REFOUT

R2 ≤ 400kΩ

APW7105A/B

GND

VOUT

R1≤1.8MΩ

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw9

Application Information (Cont.)

Thermal Consideration

In most applications, the APW7105A/B does not dissi-

pate much heat due to its high efficiency. But, in applica-

tions where the APW7105A/B is running at high ambient

temperature with low supply voltage and high duty cycles,

the heat dissipated may exceed the maximum junction

temperature of the part. If the junction temperature reaches

approximately 150°C, both power switches will be turned

off and the SW node will become high impedance.

To avoid the APW7105A/B from exceeding the maximum

junction temperature, the user will need to do some ther-

mal analysis. The goal of the thermal analysis is to deter-

mine whether the power dissipated exceeds the maxi-

mum junction temperature of the part. The power dissi-

pated by the part is approximated:

PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D))

The temperature rise is given by:

TR = (PD)(θJA)

Where PD is the power dissipated by the regulator, D is

duty cycle of main switch

D = VOUT/VIN

The θJA is the thermal resistance from the junction of the

die to the ambient temperature. The junction temperature,

TJ, is given by:

TJ = TA + TR

Where TA is the ambient temperature.

Output Capacitor Selection (Cont.)

ILIM

IPEAK

IOUT

IP-FET

∆IL

The maximum power dissipation on the device can be

shown as the following figure:

Junction Temperature (oC)

Maximum Power Disspation (W)

-50 -25 0 25 50 75 100 125 150

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Layout Consideration

For all switching power supplies, the layout is an impor-

tant step in the design; especially at high peak currents

and switching frequencies. If the layout is not carefully

done, the regulator might show noise problems and duty

cycle jitter.

1. The input capacitor should be placed close to the VIN

and GND. Connecting the capacitor and VIN/GND with

short and wide trace without any via holes for good

input voltage filtering. The distance between VIN/GND

to capacitor less than 2mm respectively is

recommended.

2. To minimize copper trace connections that can inject

noise into the system, the inductor should be placed

as close as possible to the SW pin to minimize the

noise coupling into other circuits.

3. The output capacitor should be placed closed to VOUT

and GND.

4. Since the feedback pin and network is a high imped-

ance circuit, the feedback network should be routed

away from the inductor. The feedback pin and feed-

back network should be shielded with a ground plane

or trace to minimize noise coupling into this circuit.

5. A star ground connection or ground plane minimizes

ground shifts and noise is recommended.

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw10

Package Information

TSOT-23-5A

LMIN. MAX.

1.00

0.01

0.08 0.22

0.10

MILLIMETERS

b0.30 0.50

0.95 BSC

TSOT-23-5A

0.30 0.60

0.037 BSC

MIN. MAX.

INCHES

0.039

0.000

0.028 0.035

0.003 0.009

0.012 0.024

0.004

A2 0.70 0.90

0.012 0.020

1.90BSC 0.075 BSC

1.40 1.80

2.60 3.00

2.70 3.10 0.106 0.122

0.055 0.071

0.102 0.118

Note : 1. Followed from JEDEC TO-178 AA.

2. Dimension D and E1 do not include mold flash, protrusions or gate

burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per

side.

0.70 0.028

SEE VIEW A

A2A1

VIEW A

LSEATING PLANE

GAUGE PLANE

0.25

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw11

Application

A H T1 C d D W E1 F

178.0±2.00

50 MIN.

8.4+2.00

-0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

8.0±0.30

1.75±0.10

3.5±0.05

P0 P1 P2 D0 D1 T A0 B0 K0

TSOT-23-5A

4.0±0.10

2.0±0.05

1.5+0.10

-0.00

1.0 MIN.

0.6+0.00

-0.40

3.20±0.20

3.10±0.20

1.50±0.20

(mm)

Devices Per Unit

Carrier Tape & Reel Dimensions

Package Type Unit Quantity

TSOT-23-5A Tape & Reel 3000

OD0

BA0

SECTION B-B

SECTION A-A

OD1

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw12

Taping Direction Information

Classification Profile

TSOT-23-5A

USER DIRECTION OF FEED

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw13

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Preheat & Soak

Temperature min (Tsmin)

Temperature max (Tsmax)

Time (Tsmin to Tsmax) (ts)

100 °C

150 °C

60-120 seconds

150 °C

200 °C

60-120 seconds

Average ramp-up rate

(Tsmax to TP) 3 °C/second max. 3 °C/second max.

Liquidous temperature (TL)

Time at liquidous (tL) 183 °C

60-150 seconds 217 °C

60-150 seconds

Peak package body Temperature

(Tp)* See Classification Temp in table 1 See Classification Temp in table 2

Time (tP)** within 5°C of the specified

classification temperature (Tc) 20** seconds 30** seconds

Average ramp-down rate (Tp to Tsmax)

6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Table 2. Pb-free Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 °C 260 °C 260 °C

1.6 mm – 2.5 mm 260 °C 250 °C 245 °C

≥2.5 mm 250 °C 245 °C 245 °C

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 235 °C 220 °C

≥2.5 mm 220 °C 220 °C

Test item Method Description

SOLDERABILITY JESD-22, B102 5 Sec, 245°C

HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C

PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C

TCT JESD-22, A104 500 Cycles, -65°C~150°C

HBM MIL-STD-883-3015.7 VHBM≧2KV

MM JESD-22, A115 VMM≧200V

Latch-Up JESD 78 10ms, 1tr≧100mA

Reliability Test Program

Rev. A.1 - Dec., 2010

APW7105A/B

www.anpec.com.tw14

Customer Service

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838