APW7105A/B 1.5MHz, 1A Synchronous Buck Regulator Features General Description * 1A Output Current * Wide 2.5V~6.0V Input Voltage APW7105A/B is a 1.5MHz high efficiency monolithic synchronous buck regulator. Design with current mode * Fixed 1.5MHz Switching Frequency * Low Dropout Operating at 100% Duty Cycle * 20A Quiescent Current * Integrate Synchronous Rectifier * <0.5A Input Current During Shutdown * Current-Mode Operation with Internal scheme, the APW7105A/B is stable with ceramic output capacitor. Input voltage from 2.5V to 6.0V makes the APW7105A/B ideally suited for single Li-Ion battery powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable electrical devices. The internally fixed 1.5MHz operating frequency allows the using of small surface mount inductors and capacitors. The synchronous switches included inside Compensation - Stable with Ceramic Output Capacitors - Fast Line Transient Response increase the efficiency and eliminate the need of an external Schottky diode. * Short-Circuit Protection The APW7105A/B is available in TSOT-23-5A packages. * Over-Temperature Protection with Hysteresis * Available in TSOT-23-5A Packages * Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration Applications * HD STB * BT Mouse APW7105A/B VIN 1 * PND Instrument * Portable Instrument RUN 3 C1 4.7F (MLCC) L1 2.2H 1 VIN VOUT SW 5 C3 APW7105A/B 3 RUN FB 4 GND 2 R1 4 FB TSOT-23-5A (Top View) Simplified Application Circuit VIN 5 SW GND 2 C2 10F (MLCC) R2 ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 1 www.anpec.com.tw APW7105A/B Ordering and Marking Information Reference Voltage Code A : 0.5V B : 0.6V Package Code BT: TSOT-23-5A Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7105 Assembly Material Handling Code Temperature Range Package Code Reference Voltage Code APW7105A/B BT : Y - Reference Voltage Code W5YX X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VIN Parameter Input Bias Supply Voltage (VIN to GND) RUN, FB, SW to GND Voltage PD Power Dissipation TSDR Unit V -0.3 ~ VIN+0.3 V Internally Limited Maximum Junction Temperature TSTG Rating -0.3 ~ 7 Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds W 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol JA Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) TSOT-23-5A Unit o 220 C/W Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol VIN Parameter Range 2.5 ~ 6 V VOUT Converter Output Voltage VREF ~ VIN V IOUT Converter Output Current 0~1 A L1 Converter Output Inductor 1.0 ~ 10 H CIN Converter Input Capacitor 4.7 ~100 F Converter Output Capacitor 4.7 ~100 F Ambient Temperature -40 ~ 85 o -40 ~ 125 o COUT TA TJ Input Bias Supply Voltage (VIN to GND) Unit Junction Temperature C C Note 3: Refer to the typical application circuit Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 2 www.anpec.com.tw APW7105A/B Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=3.6V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APW7105A/B Test Conditions Min. Typ. Unit Max. SUPPLY VOLTAGE AND CURRENT VIN Input Voltage Range 2.5 - 6 V IDD Quiescent Current VFB = 0.7V - 20 30 A ISD Shutdown Input Current RUN = GND - - 0.5 A UVLO Threshold 2.0 2.2 2.4 V UVLO Hysteresis - 0.1 - V APW7105A 0.493 0.5 0.507 V APW7105B 0.591 0.6 0.609 V POWER-ON-RESET (POR) and LOCKOUT VOLTAGE THRESHOLDS REFERENCE VOLTAGE TA = 25 oC VREF Regulated Voltage o TA = 25 C o TA = -40~85 C Output Voltage Accuracy IFB APW7105A/B 0A < IOUT < 1A FB Input Current -2 - +2 % -2.5 - +2.5 % -50 - 50 nA 1.2 1.5 1.8 MHz - 210 310 kHz INTERNAL POWER MOSFETS FSW Switching Frequency Foldback Frequency VFB = 0.1V Foldback Threshold Voltage on FB VFB Falling Foldback Hysteresis - 0.2 - V - 50 - mV RP-FET High Side N-FET Switch ON Resistance ISW =200mA - 0.28 0.35 RN-FET Low Side P-FET Switch ON Resistance ISW =200mA - 0.25 0.32 Minimum On-Time - - 100 ns Maximum Duty Cycle - - 100 % 1.4 1.6 2 A PROTECTION ILIM Maximum Inductor Current-Limit IP-FET, 2.5VVIN6V TOTP Over-Temperature Protection TJ Rising - 150 - Over-Temperature Protection Hysteresis TJ Falling - 30 - Soft-Start Duration (Note 4) - 0.7 - ms RUN Input High Threshold VIN = 2.5V~6V - - 1 V RUN Input Low Threshold VIN = 2.5V~6V 0.4 - - V RUN Leakage Current VRUN = 5V, VIN = 5V -1 - 1 A C START-UP AND SHUTDOWN TSS Note 4: Guarantee by design, not production test. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 3 www.anpec.com.tw APW7105A/B Pin Description PIN FUNCTION NO. NAME 1 VIN Device and Converter Supply Pin. Must be closely decoupled to GND with a 4.7F or greater ceramic capacitor. 2 GND Power and Signal Ground. 3 RUN Enable Control Input. Forcing this pin above 1.0V enables the device. Forcing this pin below 0.4V shuts it down. In shutdown, all functions are disabled to decrease the supply current below 0.5A. Do not leave RUN pin floating. 4 FB Feedback Input Pin. The buck regulator senses feedback voltage via FB and regulates the FB voltage at 0.5V. Connecting FB with a resistor-divider from the output sets the output voltage of the buck converter. 5 SW Switch Node Connected to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFETs switches. Block Diagram Current Sense Amplifier RUN VIN Shutdown Control Logic Control SW OverTemperature Protection Gate Driver Current -Limit Slope Compensation ZeroCrossing Comparator GND Oscillator ICMP Error Amplifier FB COMP EAMP SoftStart Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 4 VREF www.anpec.com.tw APW7105A/B Typical Application Circuit IIN VIN L1 2.2H 1 SW VIN VOUT 5 2.5~6V C1 4.7F (MLCC) APW7105A/B 3 RUN FB R1 C3 0.5V~VIN C2 0~1A 10F (MLCC) 4 GND 2 R2 R1 1.8M is recommended R2 400k is recommended R1 x C3 = 3x10-6 ~ 8x10-6F Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 5 www.anpec.com.tw APW7105A/B Function Description Main Control Loop mode operation to reduce the dominant switching losses. The APW7105A/B is a constant frequency, synchronous rectifier and current-mode switching regulator. In normal In PFM operation, the inductor current may reach zero or reverse on each pulse. A zero current comparator turns operation, the internal P-channel power MOSFET is turned on every cycle. The peak inductor current at which off the N-FET, forcing DCM operation at light load. These controls get very low quiescent current, help to maintain ICMP turn off the P-FET is controlled by the voltage on the COMP node, which is the output of the error amplifier high efficiency over the complete load range. Slope Compensation and Inductor Peak Current (EAMP). An external resistive divider connected between VOUT and ground allows the EAMP to receive an output The APW7105A/B is a peak current mode PWM step down converter. To prevent sub-harmonic oscillations, the feedback voltage VFB at FB pin. When the load current increases, it causes a slightly decrease in VFB relative to APW7105A/B senses the peak current and adds slope compensation to stable the converter. It is accomplished the reference voltage, V , which in turn causes the COMP REF voltage to increase until the average inductor current matches the new load current. internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, Under-Voltage Lockout this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the APW7105A/B uses a special scheme that counteracts this compensating ramp, which allows the maximum inductor peak An under-voltage lockout function prevents the device from operating if the input voltage on VIN is lower than approximately 1.8V. The device automatically enters the shut- current to remain unaffected throughout all duty cycles. down mode if the voltage on VIN drops below approximately 1.8V. This under-voltage lockout function is imple- Adaptive Shoot-Through Protection mented in order to prevent the malfunctioning of the converter. The gate driver incorporates adaptive shoot-through pro- Soft-Start The APW7105A/B has a built-in soft-start to control the This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to output voltage rise during start-up. During soft-start, an internal ramp voltage, connected to the one of the posi- rise. During turn-off the low-side MOSFET, the internal LGATE tive inputs of the error amplifier, raises up to replace the reference voltage until the ramp voltage reaches the ref- voltage is monitored until it is below 1.5V threshold, at which time the UGATE is released to rise after a constant erence voltage. Then, the voltage on FB regulated at reference voltage. delay. During turn-off the high-side MOSFET, the UGATE voltage is also monitored until it is above 1.5V threshold, Enable/Shutdown at which time the LGATE is released to rise after a constant delay. tection to high-side and low-side MOSFETs from conducting simultaneously and shorting the input supply. Driving RUN to the ground places the APW7105A/B in Dropout Operation shutdown mode. When in shutdown, the internal power MOSFETs turn off, all internal circuitry shuts down and As the input supply voltage decreases to a value ap- the quiescent supply current reduces to 0.5A maximum. proaching the output voltage, the duty cycle increases toward the maximum on time. Further, reduction of the Pulse Frequency Modulation Mode (PFM) supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The The APW7105A/B is a fixed frequency, peak current mode P W M s t e p - d o w n c o n v e r t e r. At light loads, the input voltage minus the voltage drop will determine the output voltage across the P-FET and the inductor. APW7105A/B will automatically enter in pulse frequency Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 6 www.anpec.com.tw APW7105A/B Function Description (Cont.) Dropout Operation (Cont.) An important detail to remember is that on resistance of P-FET switch will increase at low input supply voltage. Therefore, the user should calculate the power dissipation when the APW7105A/B is used at 100% duty cycle with low input voltage. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7105A/B. When the junction temperature exceeds 150oC, a thermal sensor turns off the both power MOSFETs, allowing the devices to cool. The thermal sensor allows the converters to start a soft-start process and regulate the output voltage again after the junction temperature cools by 30oC. The OTP is designed with a 30oC hysteresis to lower the average Junction Temperature (TJ) during continuous thermal overload conditions, increasing the lifetime of the device. Short-Circuit Protection When the output is shortened to the ground, the frequency of the oscillator is reduced to about 210kHz, 1/7 of the nominal frequency. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing runaway. The oscillator's frequency will progressively increase to 1.5MHz when VFB or VOUT rises above 0V. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 7 www.anpec.com.tw APW7105A/B Application Information Input Capacitor Selection shown in "Typical Application Circuits." A suggestion of Because buck converters have a pulsating input current, a low ESR input capacitor is required. This results in the maximum value of R2 is 400k to keep the minimum current that provides enough noise rejection ability through best input voltage filtering, minimizing the interference with other circuits caused by high input voltage spikes. the resistor divider. The output voltage can be calculated as below: R1 R1 VOUT = VREF 1 + = 0.5 1 + R 2 R 2 Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For good input voltage filtering, usually a 4.7F input capacitor is sufficient. It can be increased without any limit for VOUT better input-voltage filtering. Ceramic capacitors show better performance because of the low ESR value, and R11.8M FB they are less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input R2 400k APW7105A/B capacitor as close as possible to the input and GND pin of the device for better performance. GND Inductor Selection Output Capacitor Selection For high efficiencies, the inductor should have a low DC The current-mode control scheme of the APW7105A/B allows the use of tiny ceramic capacitors. The higher ca- resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a pacitor value provides the good load transients response. higher impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. If required, inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value de- tantalum capacitors may be used as well. The output ripple is the sum of the voltages across the ESR and the termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the ideal output capacitor. lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient VOUT response. A reasonable starting point for setting ripple current, IL, is 40% of maximum output current. The rec- V VOUT 1 - OUT VIN FSW L 1 ESR + 8 FSW COUT When choosing the input and output ceramic capacitors, ommended inductor value can be calculated as below: choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage char- V VOUT 1 - OUT VIN L FSW IL acteristics of all the ceramics for a given value and size. VIN IL(MAX) = IOUT(MAX) + 1/2 x IL IIN IP-FET To avoid the saturation of the inductor, the inductor should IL be rated at least for the maximum output current of the converter plus the inductor ripple current. CIN Output Voltage Setting P-FET VOUT SW N-FET In the adjustable version, the output voltage is set by a resistive divider. The external resistive divider is con- IOUT ESR COUT nected to the output, allowing remote voltage sensing as Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 8 www.anpec.com.tw APW7105A/B Application Information (Cont.) Output Capacitor Selection (Cont.) The maximum power dissipation on the device can be shown as the following figure: IL 0.8 Maximum Power Disspation (W) ILIM IPEAK IL IOUT IP-FET 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 Junction Temperature (oC) Thermal Consideration Layout Consideration In most applications, the APW7105A/B does not dissipate much heat due to its high efficiency. But, in applica- For all switching power supplies, the layout is an impor- tions where the APW7105A/B is running at high ambient temperature with low supply voltage and high duty cycles, tant step in the design; especially at high peak currents and switching frequencies. If the layout is not carefully the heat dissipated may exceed the maximum junction done, the regulator might show noise problems and duty cycle jitter. temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned 1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND with off and the SW node will become high impedance. To avoid the APW7105A/B from exceeding the maximum short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GND junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to deter- to capacitor less than 2mm respectively is recommended. mine whether the power dissipated exceeds the maximum junction temperature of the part. The power dissi- 2. To minimize copper trace connections that can inject noise into the system, the inductor should be placed pated by the part is approximated: as close as possible to the SW pin to minimize the noise coupling into other circuits. PD IOUT2 x (RP-FET x D+RN-FET x (1-D)) The temperature rise is given by: 3. The output capacitor should be placed closed to VOUT and GND. TR = (PD)(JA) 4. Since the feedback pin and network is a high impedance circuit, the feedback network should be routed Where PD is the power dissipated by the regulator, D is duty cycle of main switch away from the inductor. The feedback pin and feedback network should be shielded with a ground plane D = VOUT/VIN The JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, or trace to minimize noise coupling into this circuit. 5. A star ground connection or ground plane minimizes TJ, is given by: ground shifts and noise is recommended. TJ = TA + TR Where TA is the ambient temperature. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 9 www.anpec.com.tw APW7105A/B Package Information TSOT-23-5A D e E E1 SEE VIEW A c b 0.25 A GAUGE PLANE SEATING PLANE A1 A2 e1 L VIEW A S Y M B O L A TSOT-23-5A MILLIMETERS INCHES MIN. MAX. MIN. MAX. 0.70 1.00 0.028 0.039 A1 0.01 0.10 0.000 0.004 A2 0.70 0.90 0.028 0.035 b 0.30 0.50 0.012 0.020 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 E 2.60 3.00 0.102 0.118 E1 1.40 1.80 0.055 0.071 e 0.95 BSC 0.037 BSC e1 1.90BSC 0.075 BSC L 0.30 0.60 0 0 8 0.012 0 0.024 8 Note : 1. Followed from JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 10 www.anpec.com.tw APW7105A/B Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSOT-23-5A A H T1 C d D W E1 F 178.02.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.00.30 1.750.10 3.50.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.00.10 4.00.10 2.00.05 1.5+0.10 -0.00 1.0 MIN. 0.6+0.00 -0.40 3.200.20 3.100.20 1.500.20 (mm) Devices Per Unit Package Type Unit Quantity TSOT-23-5A Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 11 www.anpec.com.tw APW7105A/B Taping Direction Information TSOT-23-5A USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 12 www.anpec.com.tw APW7105A/B Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3 C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Volume mm <350 235 C 220 C 3 Volume mm 350 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 13 Description 5 Sec, 245C 1000 Hrs, Bias @ Tj=125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA www.anpec.com.tw APW7105A/B Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Dec., 2010 14 www.anpec.com.tw