GT93C56A
2Kb Microwire Serial EEPROM Advanced
Copyright © 2010 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without
notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance
and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers
are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
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1. Features
Industry-standard Microwire Interface
Wide-voltage Operation
– VCC = 1.8V to 5.5V
Speed
– 1 MHz (1.8V), 2 MHz (2.5V), 3 MHz (5.5V)
Standby current
– 1uA (max.) 1.8V
Operating current
– 1mA (max.) 1.8V
User Configured Memory Organization
– 128x16-bit (ORG = VCC or Floating)
– or 256x8-bit (ORG = 0V)
Self timed write cycle: 5 ms (max.)
Hardware and software write protection
– Defaults to write-disabled state at power-up
– Software instructions for write-enable/disable
CMOS technology
Versatile, easy-to-use interface
– Automatic erase-before-write
– Programming status indicator
– Byte, Word and chip single erasable
– Chip select enables power savings
Noise immunity on inputs, besides Schmitt trigger
High-reliability
– Endurance: 1 million cycles
– Data retention: 100 years
Packages: SOIC/SOP, TSSOP, and UDFN
Lead-free, RoHS, Halogen free, Green
2. General Description
The GT93C56A is 2kb non-volatile serial EEPROM with
memory array of 2,048 bits. The array can be organized as
either 256 bytes of 8 bits or 128 words of 16 bits via the
ORG control. Utilizing the CMOS design and process, these
products provide low standby current and low power
operations. The devices can operate in a wide supply
voltage range from 1.8V to 5.5V, with frequency up to
3MHz.
When the ORG pin is connected to VCC or floating, x16 is
selected. Conversely, when it is connected to ground, x8 is
chosen.
An instruction Op-code defines the various operations of
the devices, including read, write, and mode-enable
functions. To protect against inadvertent data modification,
all write and erase instructions are merely accepted while
the device is in write enable mode. A selected x8 byte or
x16 word can be modified with a single WRITE or ERASE
instruction. Additionally, the WRITE ALL or ERASE ALL
instruction can program or erase the entire array,
respectively. Once a device begins its self-timed program
procedure, the data out pin (Dout) can indicate the
READY/BUSY status by raising chip select (CS). The
devices can output any number of consecutive bytes/words
using a single READ instruction.
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3. Functional Block Diagram
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4. Pin Configuration
4.1 8-Pin SOIC/SOP and TSSOP (Top View)
4.2 8-Lead UDFN (Top View)
Note: Please see section ―Top Markings‖ for detailed Marking Information.
4.3 Pin Definition
Pin No.
Pin Name
I/O
Definition
1
CS
I
Chip Select
2
SK
I
Serial Data Clock
3
DIN
I
Serial Data Input
4
DOUT
O
Serial Data Output
5
GND
-
Ground
6
ORG
I
Organization Select
7
NC
-
Not Connect
8
VCC
-
Supply Voltage
CS
SK
DIN
DOUT
VCC
NC
ORG
GND
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5. Device Operation
The GT93C56A is controlled by a set of instructions which
are clocked-in serially on the Din pin. Before each
low-to-high transition of the clock (SK), the CS pin must
have already been raised to HIGH, and the Din value must
be stable at either LOW or HIGH. Each instruction begins
with a start bit of the logical ―1‖ or HIGH. Following this are
the Op-code, address field, and data, if appropriate. The
clock signal may be held stable at any moment to suspend
the device at its last state, allowing clock speed flexibility.
Upon completion of bus communication, CS would be
pulled LOW. The device then would enter Standby mode if
no internal programming is underway.
5.1 Read (READ)
The READ instruction is the only instruction that outputs
serial data on the DOUT pin. After the read instruction and
address have been decoded, data is transferred from the
selected memory array into a serial shift register. (Please
note that one logical ―0‖ bit precedes the actual 8 or 16-bit
output data string.) The output on DOUT changes during
the low-to-high transitions of SK (see Figure 5.10-2).
The GT93C56A is designed to output a continuous stream
of memory content in response to a single read operation
instruction. To utilize this function, the system asserts a
read instruction specifying a start location address. Once
the 8 or 16 bits of the addressed register have been clocked
out, the data in consecutively higher address locations is
output. The address will wrap around continuously with CS
HIGH until the chip select (CS) control pin is brought LOW.
This allows for single instruction data dumps to be executed
with a minimum of firmware overhead.
5.2 Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL, ERASE,
and ERAL) can be done. When VCC is applied, this device
powers up in the write disabled state. The device then
remains in a write disabled state until a WEN instruction is
executed. Thereafter, the device remains enabled until a
WDS instruction is executed or until VCC is removed. (See
Figure 5.10-3) (Note: Chip select must remain LOW until
VCC reaches its operational value.)
5.3 Write Disable (WDS)
The write disable (WDS) instruction disables all
programming capabilities. This protects the entire device
against accidental modification of data until a WEN
instruction is executed. (When VCC is applied, this part
powers up in the write disabled state.) To protect data, a
WDS instruction should be executed upon completion of
each programming operation.
5.4 Write (WRITE)
The WRITE instruction writes 8 or 16 bits of data into the
specified memory location. After the last data bit has been
applied to DIN, and before the next rising edge of SK, CS
must be brought LOW. If the device is write-enabled, then
the falling edge of CS initiates the self-timed programming
cycle (see WEN). If CS is brought HIGH, after a minimum
wait of 200 ns after the falling edge of CS (tCS) DOUT will
indicate the READY/BUSY status of the chip. Logical ―0‖
means programming is still in progress; logical ―1‖ means
the selected memory array has been written, and the part is
ready for another instruction (see Figure 5.10-4). The
READY/BUSY status will not be available if the CS input
goes HIGH after the end of the self-timed programming
cycle (Twp).
5.5 Write All Memory (WRAL)
The write all (WRALL) instruction programs entire memory
with the data pattern specified in the instruction. As with the
WRITE instruction, the falling edge of CS must occur to
initiate the self-timed programming cycle. If CS is then
brought HIGH after a minimum wait of 200 ns (tCS), the
DOUT pin indicates the READY/BUSY status of the chip
(see Figure 5.10-5).
5.6 Erase (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed internal
programming cycle. Bringing CS HIGH after a minimum of
tCS, will cause DOUT to indicate the READ/BUSY status of
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the chip: a logical ―0‖ indicates programming is still in
progress; a logical ―1‖ indicates the erase cycle is complete
and the part is ready for another instruction (see Figure
5.10-7).
5.7 Erase All Memory (ERAL)
Full chip erase is provided for ease of programming.
Erasing the entire chip involves setting all bits in the entire
memory array to a logical ―1‖ (see Figure 5.10-8).
5.8 Power-On Reset (POR)
The device incorporates a Power-On Reset (POR) circuitry
which protects the internal logic against powering up into a
wrong state. The device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This POR feature protects the device being
‗brown-out‘ due to a sudden power loss or power cycling.
In order to refrain the state machine entering into a wrong
state during power-up sequence or a power toggle off-on
condition, a power on reset (POR) circuit is embedded.
During power-up, the device does not respond to any
instruction until VCC has reached a minimum stable level
above the reset threshold voltage. Once VCC passes the
POR threshold, the device is reset and enters in Standby
mode. This can also avoid any inadvertent Write operations
during power-up stage. During power-down process, the
device must enter into standby mode, once VCC drops
below the power on reset threshold voltage. In addition, the
device will enter standby mode after current operation
completes, provided that no internal write operation is in
progress.
5.9 INSTRUCTION SET - GT93C56A (2Kb)
Start
Bit
OP
Code
8-bit Organization
(ORG = GND)
16-bit Organization
(ORG = VCC or Floating)
Address[1]
Data[1]
Required
Clock
Cycles
Address[1]
Data[1]
Required
Clock
Cycles
1
00
0 0xxx xxxx
—
12
00xx xxxx
—
11
1
00
1 1xxx xxxx
—
12
11xx xxxx
—
11
1
00
1 0xxx xxxx
—
12
10xx xxxx
—
11
1
00
0 1xxx xxxx
(D7-D0)
20
01xx xxxx
(D15-D0)
27
1
01
x(A7-A0)
(D7-D0)
20
x(A6-A0)
(D15-D0)
27
1
10
x(A7-A0)
—
x(A6-A0)
—
1
11
x(A7-A0)
—
12
x(A6-A0)
—
11
Notes: [1] x = Don't care bit.
[2] Exact number of clock cycles is required for each Op-code instruction.
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5.10 Diagrams
Figure 5.10-1. Synchronous Data Timing
Figure 5.10-2. Read Cycle Timing
Figure 5.10-3. Write Enable (WEN) Cycle Timing
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Figure 5.10-4. Write (Write) Cycle Timing
Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is
in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device
malfunction.
[2] To determine address bits An-A0 and data bits Dm-D0, see Instruction Set for the specific device.
Figure 5.10-5. Write All (WRALL) Cycle Timing
Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is
in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device
malfunction.
[2] To determine data bits Dm-D0, see Instruction Set for the appropriate device.
Figure 5.10-6. Write Disable (WDS) Timing
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Figure 5.10-7. Erase (Erase) Cycle Timing
Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is
in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device
malfunction.
[2] To determine data bits An - A0, see Instruction Set for the appropriate device.
Figure 5.10-8. Erase All (ERAL) Cycle Timing
Notes: [1] After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is
in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device
malfunction.
[2] To determine data bits An - A0, see Instruction Set for the appropriate device.
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6. Electrical Characteristics
6.1 Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VS
Supply Voltage
-0.5 to + 6.5
V
VP
Voltage on Any Pin
–0.5 to VCC + 0.5
V
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Output Current
5
mA
Note: Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other condition outside those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
6.2 Operating Range
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.8V to 5.5V
Note: Giantec offers Industrial grade for Commercial applications (0C to +70C).
6.3 Capacitance [1, 2]
Symbol
Parameter
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
CI/O
Input / Output Capacitance
VI/O = 0V
8
pF
Notes: [1] Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
[2] Test conditions: TA = 25°C, f = 1 MHz, VCC = 5.0V.
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6.4 DC Electrical Characteristic
Industrial: TA = –40°C to +85°C, VCC = 1.8V ~ 5.5V
Symbol
Parameter [1]
Test Conditions
Min.
Max.
Unit
VCC
Supply Voltage
1.8
5.5
V
VOL1
Output LOW Voltage
VCC = 1.8V~5.5V, IOL = 100 uA
—
0.2
V
VOL2
Output LOW Voltage
VCC = 2.5V~5.5V, IOL = 2.1 mA
—
0.4
V
VOH1
Output HIGH Voltage
VCC = 1.8V~5.5V, IOH = -0.1mA
VCC – 0.2
—
V
VOH2
Output HIGH Voltage
VCC = 2.5V~5.5V, IOH = -0.4mA
2.4
—
V
VIH1
Input HIGH Voltage
1.8V to 5.5V
0.7*VCC
VCC +1
V
VIH2
Input HIGH Voltage
2.5V to 5.5V
2
VCC +1
V
VIL1
Input LOW Voltage
1.8V to 5.5V
-0.3
0.3*VCC
V
VIL2
Input LOW Voltage
2.5V to 5.5V
-0.3
0.8
V
ILI
Input Leakage Current
VIN = 0V to VCC (CS, SK,DIN,ORG)
0
2.5
μA
ILO
Output Leakage Current
VOUT = 0V to VCC, CS = 0V
0
2.5
μA
Power Supply Characteristics
Industrial: TA = –40°C to +85°C, VCC = 1.8V ~ 5.5V
Symbol
Parameter [1]
VCC
Test Conditions
Min.
Typ.
Max.
Unit
VCC
Supply Voltage
1.8
5.5
V
ISB1
Standby current
1.8
CS = GND, SK = GND,
ORG = VCC or Floating
(x16), DIN = VCC or GND
—
0.1
1
μA
2.5
—
0.3
1
μA
5.5
—
0.5
1
μA
ISB2
Standby current
1.8
CS = GND, SK = GND,
ORG = GND (x8), DIN =
VCC or GND
—
0.4
1
μA
2.5
—
6
10
μA
5.5
—
10
15
μA
ICC-Read
Read current
1.8
CS = VIH, SK = 1 MHz
—
0.5
mA
2.5
CS = VIH, SK = 2 MHz
—
0.5
mA
5.5
CS = VIH, SK = 3 MHz
—
1
mA
ICC-Write
Write current
1.8
CS = VIH, SK = 1 MHz
—
1
mA
2.5
CS = VIH, SK = 2 MHz
—
1
mA
5.5
CS = VIH, SK = 3 MHz
—
2
mA
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6.5 AC Electrical Characteristic
Industrial: TA = –40°C to +85°C, Supply voltage = 1.8V to 5.5V
Symbol
Parameter [1] [2]
1.8VVCC<2.5V
2.5VVCC<4.5V
4.5VVCC5.5V
Unit
Min.
Max.
Min.
Max.
Min.
Max.
fSCK
SCK Clock Frequency
0
1
0
2
0
3
MHz
tR
Input Rise Time
—
10
—
10
—
10
ns
tF
Input Fall Time
—
10
—
10
—
10
ns
tSKH
SK High Time
250
—
200
—
200
—
ns
tSKL
SK Low Time
250
—
200
—
100
—
ns
tCS
Minimum CS LOW Time
250
—
200
—
200
—
ns
tCSS
CS Setup Time
200
—
100
—
50
—
ns
tCSH
CS Hold Time
0
—
0
—
0
—
ns
tDIS
DIN Setup Time
100
—
50
—
50
—
ns
tDIH
DIN Hold Time
50
—
50
—
50
—
ns
tPD1
Output Delay to ―1‖
—
400
—
200
—
100
ns
tPD0
Output Delay to ―0‖
—
400
—
200
—
100
ns
tSV
CS to Status Valid
—
400
—
200
—
200
ns
tDF
CS to Dout in 3-state
—
200
—
100
—
100
ns
tWP
Write Cycle Time
—
10
—
5
—
5
ms
Notes: [1] The parameters are characterized but not 100% tested.
[2] AC measurement conditions:
CL = 100 pF
Input pulse voltages: Per VIL and VIH spec
Input rise and fall times: ≤ 10 ns
Timing reference voltages: half VCC level
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7. Ordering Information
Industrial Grade: -40°C to +85°C, Lead-free
Voltage Range
Part Number*
Package (8-pin)*
1.8V to 5.5V
GT93C56A-2GLI-TR
150-mil SOIC/SOP (JEDEC)
GT93C56A-2ZLI-TR
3 x 4.4 mm TSSOP
GT93C56A-2UDLI-TR
2 x 3 x 0.55 mm UDFN
*
1. Contact Giantec Sales Representatives for availability and other package information.
2. The listed part numbers are packed in tape and reel ―-TR‖ (4K per reel). UDFN is 5K per reel.
3. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free or Green, whichever is applicable.
4. Giantec offers Industrial grade for Commercial applications (0C to +70C).
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8. Top Markings
8.1 GT93C56A-2GLI-TR (SOIC/SOP Package)
: Giantec Logo
356A-2GLI: Part Number GT93C56A-2GLI
036: Date Code, year 2010, ww36
8.2 GT93C56A-2ZLI-TR (TSSOP Package)
GT: Giantec Logo
356A-2ZLI: Part Number, GT93C56A-2ZLI
036: Date Code, year 2010, ww36
8.3 GT93C56A-2UDLI-TR (UDFN Package)
GT: Giantec Logo
31A: Part Number, GT93C56A-2UDLI
036: Date Code, year 2010, ww36
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9 Package Information
9.1 SOIC/SOP (JEDEC)
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9.2 TSSOP
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9.3 UDFN: Ultra-thin DFN
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10. Revision History
Revision
Date
Descriptions
A0
Nov. 2010
Initial version