PIC16C9XX 8-Bit CMOS Microcontroller with LCD Driver Devices included in this data sheet: Available in Die Form * PIC16C923 * PIC16C924 Microcontroller Core Features: * * * * * * * * * High performance RISC CPU Only 35 single word instructions to learn 4K x 14 on-chip EPROM program memory 176 x 8 general purpose registers (SRAM) All single cycle instructions (500 ns) except for program branches which are two-cycle Operating speed: DC - 8 MHz clock input DC - 500 ns instruction cycle Interrupt capability Eight level deep hardware stack Direct, indirect and relative addressing modes Peripheral Features: * * * * 25 I/O pins with individual direction control 25-27 input only pins Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counter, can be incremented during sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * One pin that can be configured a capture input, PWM output, or compare output - Capture is 16-bit, max. resolution 31.25 ns - Compare is 16-bit, max. resolution 500 ns - PWM max resolution is 10-bits. Maximum PWM frequency @ 8-bit resolution = 32 kHz, @ 10-bit resolution = 8 kHz * Programmable LCD timing module - Multiple LCD timing sources available - Can drive LCD panel while in Sleep mode - Static, 1/2, 1/3, 1/4 multiplex - Static drive and 1/3 bias capability - 16 bytes of dedicated LCD RAM - Up to 32 segments, up to 4 commons Common Segment Pixels 1 32 32 2 31 62 3 30 90 4 29 116 * Synchronous Serial Port (SSP) with SPI and I2C * 8-bit multi-channel Analog to Digital converter (PIC16C924 only) Special Microcontroller Features: * Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Programmable code-protection * Power saving SLEEP mode * Selectable oscillator options * In-Circuit Serial ProgrammingTM (via two pins) CMOS Technology * Low-power, high-speed CMOS EPROM technology * Fully static design * Wide operating voltage range: 2.5V to 6.0V * Commercial and Industrial temperature ranges * Low-power consumption: - < 2 mA @ 5.5V, 4 MHz - 22.5 A typical @ 4V, 32 kHz - < 1 A typical standby current @ 3.0V ICSP is a trademark of Microchip Technology Inc. I2C is a trademark of Philips Corporation. SPI is a trademark of Motorola Corporation. 1997 Microchip Technology Inc. DS30444E - page 1 PIC16C9XX RA3 RA2 VSS RA1 RA0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 Pin Diagrams 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Shrink PDIP (750 mil) PIC16C923 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE7/SEG27 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11 RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RE6/SEG11 RE5/SEG10 RE4/SEG09 RE3/SEG08 RE2/SEG07 RE1/SEG06 RE0/SEG05 RD4/SEG04 RA3 RA2 VSS RA1 RA0 RB2 RB3 MCLR/VPP RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIC16C923 MCLR/VPP RB3 RB2 RA0 RA1 VSS RA2 RA3 RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16C923 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin DS30444E - page 2 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RA4/T0CKI RA5/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI 1997 Microchip Technology Inc. PIC16C9XX RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP N/C RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 Pin Diagrams (Cont.'d) 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 PLCC 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 AVDD VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI PIC16C924 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RG7/SEG28 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Shrink PDIP (750 mil) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE7/SEG27 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11 RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RE6/SEG11 RE5/SEG10 RE4/SEG09 RE3/SEG08 RE2/SEG07 RE1/SEG06 RE0/SEG05 RD4/SEG04 RA3/AN3/VREF RA2/AN2 VSS RA1/AN1 RA0/AN0 RB2 RB3 MCLR/VPP RB4 RB5 RB7 RB6 VDD COM0 RD7/SEG31/COM1 RD6/SEG30/COM2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIC16C924 MCLR/VPP RB3 RB2 RA0/AN0 RA1/AN1 VSS RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC16C924 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RD5/SEG29/COM3 RG6/SEG26 RG5/SEG25 RG4/SEG24 RG3/SEG23 RG2/SEG22 RG1/SEG21 RG0/SEG20 RF7/SEG19 RF6/SEG18 RF5/SEG17 RF4/SEG16 RF3/SEG15 RF2/SEG14 RF1/SEG13 RF0/SEG12 RC1/T1OSI RC2/CCP1 VLCD1 VLCDADJ RD0/SEG00 RD1/SEG01 RD2/SEG02 RD3/SEG03 RD4/SEG04 RE0/SEG05 RE1/SEG06 RE2/SEG07 RE3/SEG08 RE4/SEG09 RE5/SEG10 RE6/SEG11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RA4/T0CKI RA5/AN4/SS RB1 RB0/INT RC3/SCK/SCL RC4/SDI/SDA RC5/SDO C1 C2 VLCD2 VLCD3 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI LEGEND: Input Pin Output Pin Input/Output Pin Digital Input/LCD Output Pin LCD Output Pin 1997 Microchip Technology Inc. DS30444E - page 3 PIC16C9XX Table of Contents 1.0 General Description..................................................................................................................................................................... 5 2.0 PIC16C9XX Device Varieties ...................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................ 9 4.0 Memory Organization ................................................................................................................................................................ 17 5.0 Ports .......................................................................................................................................................................................... 31 6.0 Overview of Timer Modules....................................................................................................................................................... 43 7.0 Timer0 Module .......................................................................................................................................................................... 45 8.0 Timer1 Module .......................................................................................................................................................................... 51 9.0 Timer2 Module .......................................................................................................................................................................... 55 10.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................... 57 11.0 Synchronous Serial Port (SSP) Module .................................................................................................................................... 63 12.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 79 13.0 LCD Module .............................................................................................................................................................................. 89 14.0 Special Features of the CPU ................................................................................................................................................... 103 15.0 Instruction Set Summary ......................................................................................................................................................... 119 16.0 Development Support.............................................................................................................................................................. 137 17.0 Electrical Characteristics ......................................................................................................................................................... 141 18.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 161 19.0 Packaging Information............................................................................................................................................................. 171 Appendix A: ................................................................................................................................................................................... 175 Appendix B: Compatibility ............................................................................................................................................................. 175 Appendix C: What's New................................................................................................................................................................ 176 Appendix D: What's Changed ........................................................................................................................................................ 176 Index .................................................................................................................................................................................................. 177 List of Equations And Examples ........................................................................................................................................................ 181 List of Figures..................................................................................................................................................................................... 181 List of Tables...................................................................................................................................................................................... 182 Reader Response .............................................................................................................................................................................. 186 PIC16C9XX Product Identification System ........................................................................................................................................ 187 To Our Valued Customers We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS30444E - page 4 1997 Microchip Technology Inc. PIC16C9XX 1.0 GENERAL DESCRIPTION The PIC16C9XX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with an integrated LCD Driver module, in the PIC16CXXX mid-range family. All PICmicroTM microcontrollers employ an advanced RISC architecture. The PIC16CXXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16CXXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC16C923 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The LCD module features programmable multiplex mode (static, 1/2, 1/3 and 1/4) and drive bias (static and 1/3). It is capable of driving up to 32 segments and up to 4 commons. It can also drive the LCD panel while in SLEEP mode. The PIC16C924 devices have 176 bytes of RAM and 25 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/PWM module, one serial port and one LCD module. The Synchronous Serial Port can be configured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I 2C) bus. The LCD module features programmable multiplex mode (static, 1/2, 1/3 and 1/4) and drive bias (static and 1/3). It is capable of driving up to 32 segments and up to 4 commons. It can also drive the LCD panel while in SLEEP mode. The PIC16C924 also has an 5-channel high-speed 8-bit A/D. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, and meters. mode. The user can wake up the chip from SLEEP through several external and internal interrupts and reset(s). A highly reliable Watchdog Timer with its own on-chip RC oscillator provides recovery in the event of a software lock-up. A UV erasable CERQUAD (compatible with PLCC) packaged version is ideal for code development while the cost-effective One-Time-Programmable (OTP) version is suitable for production in any volume. The PIC16C9XX family fits perfectly in applications ranging from handheld meters, thermostats, to home security products. The EPROM technology makes customization of application programs (LCD panels, calibration constants, sensor interfaces, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O flexibility make the PIC16C9XX very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions, capture and compare, PWM functions and coprocessor applications). 1.1 Family and Upward Compatibility Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXXX family of devices (Appendix B). 1.2 Development Support PIC16C9XX devices are supported by the complete line of Microchip Development tools. Please refer to Section 16.0 for more details about Microchip's development tools. The PIC16C9XX family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving 1997 Microchip Technology Inc. DS30444E- page 5 PIC16C9XX TABLE 1-1: PIC16C9XX FAMILY OF DEVICES PIC16C924 PIC16C923 Clock Memory Maximum Frequency of Operation (MHz) 8 8 EPROM Program Memory 4K 4K Data Memory (bytes) 176 176 Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 Capture/Compare/PWM Module(s) 1 1 SPI/I2C SPI/I2C Parallel Slave Port -- -- A/D Converter (8-bit) Channels -- 5 LCD Module 4 Com, 32 Seg 4 Com, 32 Seg Serial Port(s) Peripherals (SPI/I2C, USART) Features Interrupt Sources 8 9 I/O Pins 25 25 Input Pins 27 27 Voltage Range (Volts) 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Brown-out Reset -- -- Packages 64-pin SDIP, TQFP; 68-pin PLCC, Die 64-pin SDIP, TQFP; 68-pin PLCC, Die All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7. DS30444E - page 6 1997 Microchip Technology Inc. PIC16C9XX 2.0 PIC16C9XX DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C9XX Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For the PIC16C9XX family, there are two device "types" as indicated in the device number: 1. 2. 2.1 C, as in PIC16C924. These devices have EPROM type memory and operate over the standard voltage range. LC, as in PIC16LC924. These devices have EPROM type memory and operate over an extended voltage range. UV Erasable Devices The UV erasable version, offered in CERQUAD package, is optimal for prototype development and pilot programs. The UV erasable version can be erased and reprogrammed to any of the configuration modes. Microchip's PICSTART Plus and PRO MATE II programmers both support the PIC16C9XX. Third party programmers also are available; refer to the Microchip Third Party Guide for a list of sources. 2.2 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices Microchip offers a unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. One-Time-Programmable (OTP) Devices The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates and small volume applications. The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. 1997 Microchip Technology Inc. DS30444E - page 7 PIC16C9XX NOTES: DS30444E - page 8 1997 Microchip Technology Inc. PIC16C9XX 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (500 ns @ 8 MHz) except for program branches. The PIC16C923 and PIC16C924 both address 4K x 14 of program memory and 176 x 8 of data memory. PIC16CXXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register file. The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. The PIC16CXXX can directly or indirectly address its register files or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of `special optimal situations' make programming with the PIC16CXXX simple yet efficient, thus significantly reducing the learning curve. 1997 Microchip Technology Inc. DS30444E - page 9 PIC16C9XX FIGURE 3-1: PIC16C923 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0 RA1 RA2 RA3 RA4/T0CKI RA5/SS RAM File Registers 176 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr PORTB 9 Addr MUX Instruction reg RB0/INT 7 Direct Addr 8 Indirect Addr RB1-RB7 FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation Oscillator Start-up Timer Power-on Reset PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO MUX ALU PORTD 8 Watchdog Timer W reg RD0-RD4/SEGnn OSC1/CLKIN OSC2/CLKOUT RD5-RD7/SEGnn/COMn MCLR VDD, VSS PORTE RE0-RE7/SEGnn PORTF RF0-RF7/SEGnn PORTG RG0-RG7/SEGnn Timer1, Timer2, CCP1 Timer0 Synchronous Serial Port LCD DS30444E - page 10 COM0 VLCD1 VLCD2 VLCD3 C1 C2 VLCDADJ 1997 Microchip Technology Inc. PIC16C9XX FIGURE 3-2: PIC16C924 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RAM File Registers 176 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr PORTB 9 Addr MUX Instruction reg RB0/INT 7 Direct Addr 8 Indirect Addr RB1-RB7 FSR reg STATUS reg 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode & Control Power-on Reset Timing Generation PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO MUX ALU PORTD 8 Watchdog Timer W reg RD0-RD4/SEGnn OSC1/CLKIN OSC2/CLKOUT RD5-RD7/SEGnn/COMn MCLR VDD, VSS PORTE RE0-RE7/SEGnn PORTF RF0-RF7/SEGnn PORTG RG0-RG7/SEGnn Timer0 A/D Timer1, Timer2, CCP1 Synchronous Serial Port LCD 1997 Microchip Technology Inc. COM0 VLCD1 VLCD2 VLCD3 C1 C2 VLCDADJ DS30444E - page 11 PIC16C9XX TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION DIP Pin# PLCC Pin# TQFP Pin# Pin Type Buffer Type OSC1/CLKIN 22 24 14 I ST/CMOS Oscillator crystal input or external clock source input. This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. OSC2/CLKOUT 23 25 15 O -- Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 57 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. Pin Name Description PORTA is a bi-directional I/O port. The AN and VREF multiplexed functions are used by the PIC16C924 only. RA0/AN0 4 5 60 I/O TTL RA0 can also be Analog input0. RA1/AN1 5 6 61 I/O TTL RA1 can also be Analog input1. RA2/AN2 7 8 63 I/O TTL RA2 can also be Analog input2. RA3/AN3/VREF 8 9 64 I/O TTL RA3 can also be Analog input3 or A/D Voltage Reference. RA4/T0CKI 9 10 1 I/O ST RA4 can also be the clock input to the Timer0 timer/counter. Output is open drain type. RA5/AN4/SS 10 11 2 I/O TTL RA5 can be the slave select for the synchronous serial port or Analog input4. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT 12 13 4 I/O TTL/ST RB1 11 RB2 3 12 3 I/O TTL 4 59 I/O TTL RB0 can also be the external interrupt pin. This buffer is a Schmitt Trigger input when configured as an external interrupt. RB3 2 3 58 I/O TTL RB4 64 68 56 I/O TTL Interrupt on change pin. RB5 63 67 55 I/O TTL Interrupt on change pin. RB6 61 65 53 I/O TTL/ST Interrupt on change pin. Serial programming clock. This buffer is a Schmitt Trigger input when used in serial programming mode. RB7 62 66 54 I/O TTL/ST Interrupt on change pin. Serial programming data. This buffer is a Schmitt Trigger input when used in serial programming mode. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 24 26 16 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI 25 27 17 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 26 28 18 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output. RC3/SCK/SCL 13 14 5 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 14 15 6 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 15 16 7 I/O ST RC5 can also be the SPI Data Out (SPI mode). C1 16 17 8 C2 17 18 Legend: I = input O = output -- = Not used 9 DS30444E - page 12 P P P = power TTL = TTL input LCD Voltage Generation. LCD Voltage Generation. L = LCD Driver ST = Schmitt Trigger input 1997 Microchip Technology Inc. PIC16C9XX TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.'d) Pin Name COM0 DIP Pin# PLCC Pin# TQFP Pin# Pin Type 59 63 51 L Buffer Type Description Common Driver0 PORTD is a digital input/output port. These pins are also used as LCD Segment and/or Common Drivers. Segment Driver00/Digital Input/Output. RD0/SEG00 29 31 21 I/O/L ST RD1/SEG01 30 32 22 I/O/L ST Segment Driver01/Digital Input/Output. RD2/SEG02 31 33 23 I/O/L ST Segment Driver02/Digital Input/Output. RD3/SEG03 32 34 24 I/O/L ST Segment Driver03/Digital Input/Output. RD4/SEG04 33 35 25 I/O/L ST Segment Driver04/Digital Input/Output. RD5/SEG29/COM3 56 60 48 I/L ST Segment Driver29/Common Driver3/Digital Input. RD6/SEG30/COM2 57 61 49 I/L ST Segment Driver30/Common Driver2/Digital Input. RD7/SEG31/COM1 58 62 50 I/L ST Segment Driver31/Common Driver1/Digital Input. RE0/SEG05 34 37 26 I/L ST RE1/SEG06 35 38 27 I/L ST RE2/SEG07 36 39 28 I/L ST Segment Driver07. Segment Driver08. PORTE is a digital input or LCD Segment Driver port. Segment Driver05. Segment Driver06. RE3/SEG08 37 40 29 I/L ST RE4/SEG09 38 41 30 I/L ST Segment Driver09. RE5/SEG10 39 42 31 I/L ST Segment Driver10. RE6/SEG11 40 43 32 I/L ST Segment Driver11. RE7/SEG27 - 36 - I/L ST Segment Driver27 (Not available on 64-pin devices). PORTF is a digital input or LCD Segment Driver port. Segment Driver12. RF0/SEG12 41 44 33 I/L ST RF1/SEG13 42 45 34 I/L ST Segment Driver13. RF2/SEG14 43 46 35 I/L ST Segment Driver14. RF3/SEG15 44 47 36 I/L ST Segment Driver15. RF4/SEG16 45 48 37 I/L ST Segment Driver16. RF5/SEG17 46 49 38 I/L ST Segment Driver17. RF6/SEG18 47 50 39 I/L ST Segment Driver18. RF7/SEG19 48 51 40 I/L ST Segment Driver19. RG0/SEG20 49 53 41 I/L ST RG1/SEG21 50 54 42 I/L ST Segment Driver21. RG2/SEG22 51 55 43 I/L ST Segment Driver22. RG3/SEG23 52 56 44 I/L ST Segment Driver23. RG4/SEG24 53 57 45 I/L ST Segment Driver24. RG5/SEG25 54 58 46 I/L ST Segment Driver25. RG6/SEG26 55 59 47 I/L ST Segment Driver26. RG7/SEG28 -- 52 -- I/L ST Segment Driver28 (Not available on 64-pin devices). VLCDADJ 28 30 20 P LCD Voltage Generation. AVDD -- 21 -- P Analog Power (PIC16C924 only). VDD -- 21 -- P Power (PIC16C923 only). VLCD1 27 29 19 P VLCD2 18 19 10 P Legend: I = input O = output -- = Not used 1997 Microchip Technology Inc. PORTG is a digital input or LCD Segment Driver port. Segment Driver20. LCD Voltage. -- P = power TTL = TTL input LCD Voltage. L = LCD Driver ST = Schmitt Trigger input DS30444E - page 13 PIC16C9XX TABLE 3-1: PIC16C9XX PINOUT DESCRIPTION (Cont.'d) DIP Pin# PLCC Pin# TQFP Pin# Pin Type Buffer Type Description 19 20 11 P -- LCD Voltage. VDD 20, 60 22, 64 12, 52 P -- Digital power. VSS 6, 21 7, 23 13, 62 P -- Ground reference. NC -- 1 -- -- -- These pins are not internally connected. These pins should be left unconnected. L = LCD Driver ST = Schmitt Trigger input Pin Name VLCD3 Legend: I = input O = output -- = Not used DS30444E - page 14 P = power TTL = TTL input 1997 Microchip Technology Inc. PIC16C9XX 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-3. Instruction Flow/Pipelining An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 3-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase clock Q3 Q4 PC OSC2/CLKOUT (RC mode) EXAMPLE 3-1: PC PC+1 Fetch INST (PC) Execute INST (PC-1) PC+2 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h Tcy0 Tcy1 Fetch 1 Execute 1 2. MOVWF PORTB 3. CALL SUB_1 4. BSF PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Fetch 2 Tcy2 Tcy3 Tcy4 Tcy5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. 1997 Microchip Technology Inc. DS30444E - page 15 PIC16C9XX NOTES: DS30444E - page 16 1997 Microchip Technology Inc. PIC16C9XX 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C9XX family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 4K x 14 (0000h-0FFFh) is physically implemented. Accessing a location above the physically implemented addresses will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 4-1: PROGRAM MEMORY MAP AND STACK PC<12:0> CALL, RETURN RETFIE, RETLW 13 RP1:RP0 (STATUS<6:5>) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) The lower locations of each Bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers implemented as static RAM. All four banks contain special function registers. Some "high use" special function registers are mirrored in other banks for code reduction and quicker access. GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly through the File Select Register FSR (Section 4.5). Stack Level 8 User Memory Space Data Memory Organization The data memory is partitioned into four Banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits. 4.2.1 Stack Level 1 The following General Purpose Registers are not physically implemented: Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory (Page 0) 4.2 * F0h-FFh of Bank 1 * 170h-17Fh of Bank 2 * 1F0h-1FFh of Bank 3 These locations are used for common access across banks. 07FFh On-chip Program Memory (Page 1) 0800h 0FFFh 1000h 1FFFh 1997 Microchip Technology Inc. DS30444E - page 17 PIC16C9XX FIGURE 4-2: REGISTER FILE MAP File Address Indirect addr.(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES(2) ADCON0(2) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(1) 80h 81h OPTION 82h PCL 83h STATUS 84h FSR 85h TRISA 86h TRISB 87h TRISC TRISD 88h TRISE 89h 8Ah PCLATH 8Bh INTCON 8Ch PIE1 8Dh 8Eh PCON 8Fh 90h 91h 92h PR2 93h SSPADD 94h SSPSTAT 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1(2) A0h Indirect addr.(1) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h PORTF 108h PORTG 109h 10Ah PCLATH 10Bh INTCON 10Ch 10Dh LCDSE 10Eh LCDPS 10Fh LCDCON 110h LCDD00 111h LCDD01 112h LCDD02 113h LCDD03 114h LCDD04 115h LCDD05 116h LCDD06 117h LCDD07 118h LCDD08 119h LCDD09 11Ah LCDD10 11Bh LCDD11 11Ch LCDD12 11Dh LCDD13 11Eh LCDD14 11Fh LCDD15 120h EFh 7Fh Mapped in Bank 0 70h-7Fh Bank 1 Note DS30444E - page 18 File Address File Address Indirect addr.(1) OPTION PCL STATUS FSR TRISB TRISF TRISG PCLATH INTCON 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Register General Purpose Register Bank 0 File Address F0h FFh Mapped in Bank 0 70h-7Fh Bank 2 16F 170 17F 1EFh Mapped in Bank 0 70h-7Fh 1F0h 1FFh Bank 3 Unimplemented data memory locations, read as '0'. 1: Not a physical register. 2: These registers are not implemented on the PIC16C923. 1997 Microchip Technology Inc. PIC16C9XX 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the "core" functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature. TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant Byte 03h STATUS 04h FSR 05h PORTA 06h PORTB 07h PORTC 08h PORTD PORTD Data Latch when written: PORTD pins when read 0000 0000 0000 0000 09h PORTE PORTE pins when read 0000 0000 0000 0000 0Ah PCLATH -- -- -- 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF(2) -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 IRP RP1 RP0 TO 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer -- -- xxxx xxxx uuuu uuuu (4) PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read -- -- 0001 1xxx 000q quuu (4) xxxx xxxx uuuu uuuu PORTC Data Latch when written: PORTC pins when read --xx xxxx --uu uuuu Write Buffer for the upper 5 bits of the Program Counter 0Dh -- 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register 10h T1CON 11h TMR2 12h T2CON 13h SSPBUF 14h SSPCON 15h CCPR1L Capture/Compare/PWM Register (LSB) 16h CCPR1H Capture/Compare/PWM Register (MSB) 17h CCP1CON 18h -- Unimplemented -- -- 19h -- Unimplemented -- -- 1Ah -- Unimplemented -- -- 1Bh -- Unimplemented -- -- 1Ch -- Unimplemented -- -- 1Dh -- Unimplemented -- -- 1Eh(1) ADRES 1Fh(1) ADCON0 Legend: Note 1: 2: 3: 4: 5: Unimplemented ---0 0000 ---0 0000 -- -- -- xxxx xxxx uuuu uuuu T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 Timer2 module's register -- TOUTPS3 SSPOV -- -- SSPEN CCP1X CKP SSPM3 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 A/D Result Register ADCS1 ADCS0 --00 0000 --uu uuuu 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register WCOL -- xxxx xxxx uuuu uuuu --00 0000 --00 0000 xxxx xxxx uuuu uuuu CHS2 CHS1 CHS0 GO/DONE (5) ADON 0000 0000 0000 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear. 1997 Microchip Technology Inc. DS30444E - page 19 PIC16C9XX TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets Bank 1 80h INDF 81h OPTION 82h PCL 83h STATUS 84h FSR 85h TRISA Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 PD Z DC C Program Counter's (PC) Least Significant Byte IRP RP1 RP0 0000 0000 0000 0000 TO Indirect data memory address pointer -- -- 86h TRISB TRISC 88h TRISD PORTD Data Direction Register PORTE Data Direction Register --11 1111 --11 1111 PORTB Data Direction Register -- -- 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu PORTA Data Direction Register 87h 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 PORTC Data Direction Register --11 1111 --11 1111 1111 1111 1111 1111 89h TRISE 8Ah PCLATH -- -- -- 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 LCDIE ADIE(2) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 -- -- -- -- POR -- ---- --0- ---- --u- 1111 1111 1111 1111 Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 8Dh -- Unimplemented 8Eh PCON 8Fh -- Unimplemented -- -- 90h -- Unimplemented -- -- 91h -- Unimplemented -- -- -- -- -- 92h PR2 Timer2 Period Register 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 94h SSPSTAT SMP CKE -- 1111 1111 1111 1111 D/A P 0000 0000 0000 0000 S R/W UA BF 0000 0000 0000 0000 95h -- Unimplemented -- -- 96h -- Unimplemented -- -- 97h -- Unimplemented -- -- 98h -- Unimplemented -- -- 99h -- Unimplemented -- -- 9Ah -- Unimplemented -- -- 9Bh -- Unimplemented -- -- 9Ch -- Unimplemented -- -- 9Dh -- Unimplemented -- -- 9Eh -- Unimplemented -- -- ---- -000 ---- -000 9Fh(1) ADCON1 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear. Note 1: 2: 3: 4: 5: DS30444E - page 20 -- -- -- -- -- PCFG2 PCFG1 PCFG0 1997 Microchip Technology Inc. PIC16C9XX TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module's register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Significant Byte 103h STATUS 104h FSR 105h IRP RP1 RP0 TO 0000 0000 0000 0000 PD Z DC C Indirect data memory address pointer -- 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu Unimplemented -- -- 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h PORTF PORTF pins when read 0000 0000 0000 0000 108h PORTG PORTG pins when read 0000 0000 0000 0000 109h -- 10Ah PCLATH 10Bh INTCON Unimplemented -- Write Buffer for the upper 5 bits of the PC -- -- -- -- GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u SE27 SE20 SE16 SE12 SE9 SE5 SE0 1111 1111 1111 1111 ---0 0000 ---0 0000 10Ch -- 10Dh LCDSE 10Eh LCDPS -- -- -- -- LP3 LP2 LP1 LP0 ---- 0000 ---- 0000 10Fh LCDCON LCDEN SLPEN -- VGEN CS1 CS0 LMUX1 LMUX0 00-0 0000 00-0 0000 110h LCDD00 SEG07 COM0 SEG06 COM0 SEG05 COM0 SEG04 COM0 SEG03 COM0 SEG02 COM0 SEG01 COM0 SEG00 COM0 xxxx xxxx uuuu uuuu 111h LCDD01 SEG15 COM0 SEG14 COM0 SEG13 COM0 SEG12 COM0 SEG11 COM0 SEG10 COM0 SEG09 COM0 SEG08 COM0 xxxx xxxx uuuu uuuu 112h LCDD02 SEG23 COM0 SEG22 COM0 SEG21 COM0 SEG20 COM0 SEG19 COM0 SEG18 COM0 SEG17 COM0 SEG16 COM0 xxxx xxxx uuuu uuuu 113h LCDD03 SEG31 COM0 SEG30 COM0 SEG29 COM0 SEG28 COM0 SEG27 COM0 SEG26 COM0 SEG25 COM0 SEG24 COM0 xxxx xxxx uuuu uuuu 114h LCDD04 SEG07 COM1 SEG06 COM1 SEG05 COM1 SEG04 COM1 SEG03 COM1 SEG02 COM1 SEG01 COM1 SEG00 COM1 xxxx xxxx uuuu uuuu 115h LCDD05 SEG15 COM1 SEG14 COM1 SEG13 COM1 SEG12 COM1 SEG11 COM1 SEG10 COM1 SEG09 COM1 SEG08 COM1 xxxx xxxx uuuu uuuu 116h LCDD06 SEG23 COM1 SEG22 COM1 SEG21 COM1 SEG20 COM1 SEG19 COM1 SEG18 COM1 SEG17 COM1 SEG16 COM1 xxxx xxxx uuuu uuuu 117h LCDD07 SEG31 COM1(3) SEG30 COM1 SEG29 COM1 SEG28 COM1 SEG27 COM1 SEG26 COM1 SEG25 COM1 SEG24 COM1 xxxx xxxx uuuu uuuu 118h LCDD08 SEG07 COM2 SEG06 COM2 SEG05 COM2 SEG04 COM2 SEG03 COM2 SEG02 COM2 SEG01 COM2 SEG00 COM2 xxxx xxxx uuuu uuuu 119h LCDD09 SEG15 COM2 SEG14 COM2 SEG13 COM2 SEG12 COM2 SEG11 COM2 SEG10 COM2 SEG09 COM2 SEG08 COM2 xxxx xxxx uuuu uuuu 11Ah LCDD10 SEG23 COM2 SEG22 COM2 SEG21 COM2 SEG20 COM2 SEG19 COM2 SEG18 COM2 SEG17 COM2 SEG16 COM2 xxxx xxxx uuuu uuuu 11Bh LCDD11 SEG31 COM2(3) SEG30 COM2(3) SEG29 COM2 SEG28 COM2 SEG27 COM2 SEG26 COM2 SEG25 COM2 SEG24 COM2 xxxx xxxx uuuu uuuu 11Ch LCDD12 SEG07 COM3 SEG06 COM3 SEG05 COM3 SEG04 COM3 SEG03 COM3 SEG02 COM3 SEG01 COM3 SEG00 COM3 xxxx xxxx uuuu uuuu 11Dh LCDD13 SEG15 COM3 SEG14 COM3 SEG13 COM3 SEG12 COM3 SEG11 COM3 SEG10 COM3 SEG09 COM3 SEG08 COM3 xxxx xxxx uuuu uuuu 11Eh LCDD14 SEG23 COM3 SEG22 COM3 SEG21 COM3 SEG20 COM3 SEG19 COM3 SEG18 COM3 SEG17 COM3 SEG16 COM3 xxxx xxxx uuuu uuuu 11Fh LCDD15 SEG31 COM3(3) SEG30 COM3(3) SEG29 COM3(3) SEG28 COM3 SEG27 COM3 SEG26 COM3 SEG25 COM3 SEG24 COM3 xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear. Note 1: 2: 3: 4: 5: Unimplemented SE29 1997 Microchip Technology Inc. -- -- DS30444E - page 21 PIC16C9XX TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (Cont.'d) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets Bank 3 180h INDF 181h OPTION 182h PCL 183h STATUS 184h FSR Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 PD Z DC C Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 Indirect data memory address pointer 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu 185h -- 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h TRISF PORTF Data Direction Register 1111 1111 1111 1111 188h TRISG PORTG Data Direction Register 1111 1111 1111 1111 189h -- 18Ah PCLATH 18Bh INTCON Unimplemented -- Unimplemented -- -- -- -- GIE PEIE T0IE Write Buffer for the upper 5 bits of the PC INTE RBIE T0IF INTF -- -- ---0 0000 ---0 0000 RBIF 0000 000x 0000 000u 18Ch -- Unimplemented -- -- 18Dh -- Unimplemented -- -- 18Eh -- Unimplemented -- -- 18Fh -- Unimplemented -- -- 190h -- Unimplemented -- -- 191h -- Unimplemented -- -- 192h -- Unimplemented -- -- 193h -- Unimplemented -- -- 194h -- Unimplemented -- -- 195h -- Unimplemented -- -- 196h -- Unimplemented -- -- 197h -- Unimplemented -- -- 198h -- Unimplemented -- -- 199h -- Unimplemented -- -- 19Ah -- Unimplemented -- -- 19Bh -- Unimplemented -- -- 19Ch -- Unimplemented -- -- 19Dh -- Unimplemented -- -- 19Eh -- Unimplemented -- -- 19Fh -- Unimplemented -- -- Legend: Note 1: 2: 3: 4: 5: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0', shaded locations are unimplemented, read as `0'. Registers ADRES, ADCON0, and ADCON1 are not implemented in the PIC16C923, read as '0'. These bits are reserved on the PIC16C923, always maintain these bits clear. These pixels do not display, but can be used as general purpose RAM. PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. Bit1 of ADCON0 is reserved on the PIC16C924, always maintain this bit clear. DS30444E - page 22 1997 Microchip Technology Inc. PIC16C9XX 4.2.2.1 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary." STATUS REGISTER The STATUS register, shown in Figure 4-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 4-3: R/W-0 IRP STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC bit7 bit 7: R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. 1997 Microchip Technology Inc. DS30444E - page 23 PIC16C9XX 4.2.2.2 OPTION REGISTER Note: The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT pin interrupt, TMR0, and the weak pull-ups on PORTB. FIGURE 4-4: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. OPTION REGISTER (ADDRESS 81h, 181h) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit7 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 DS30444E - page 24 1997 Microchip Technology Inc. PIC16C9XX 4.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. FIGURE 4-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear interrupt) 0 = None of the RB7:RB4 pins have changed state Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. DS30444E - page 25 PIC16C9XX 4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the peripheral interrupts. FIGURE 4-6: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. PIE1 REGISTER (ADDRESS 8Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIE ADIE(1) -- -- SSPIE CCP1IE TMR2IE TMR1IE bit7 bit0 bit 7: LCDIE: LCD Interrupt Enable bit 1 = Enables the LCD interrupt 0 = Disables the LCD interrupt bit 6: ADIE: A/D Converter Interrupt Enable bit(1) 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: Bit ADIE is reserved on the PIC16C923, always maintain this bit clear. DS30444E - page 26 1997 Microchip Technology Inc. PIC16C9XX 4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the peripheral interrupts. FIGURE 4-7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. PIR1 REGISTER (ADDRESS 0Ch) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIF ADIF(1) -- -- SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 bit 7: LCDIF: LCD Interrupt Flag bit 1 = LCD interrupt occurred (must be cleared in software) 0 = LCD interrupt did not occur bit 6: ADIF: A/D Converter Interrupt Flag bit(1) 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: Bit ADIF is reserved on the PIC16C923, always maintain this bit clear. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. DS30444E - page 27 PIC16C9XX 4.2.2.6 For various reset conditions see Table 14-4 and Table 14-5. PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 -- -- -- -- -- -- POR -- bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: Unimplemented: Read as '0' DS30444E - page 28 1997 Microchip Technology Inc. PIC16C9XX 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-9 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). FIGURE 4-9: LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 PC 5 8 PCLATH<4:0> Instruction with PCL as Destination ALU result PCLATH PCH 12 11 10 PCL 8 PC GOTO, CALL 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 4.3.1 Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address. 4.4 Program Memory Paging PIC16C9XX devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack). Note: 0 7 Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. The PIC16C9XX ignores paging bit PCLATH<4>, which is used to access program memory pages 2 and 3. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products. COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note "Implementing a Table Read" (AN556). 4.3.2 STACK The PIC16CXXX family has an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 1997 Microchip Technology Inc. DS30444E - page 29 PIC16C9XX 4.5 Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the interrupt service routine (if interrupts are used). EXAMPLE 4-1: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register (FSR). Reading the INDF register itself indirectly (FSR = '0') will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-10. CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ORG 0x500 BSF PCLATH,3 CALL SUB1_P1 : : : ORG 0x900 SUB1_P1: : : RETURN Indirect Addressing, INDF and FSR Registers ;Select page 1 (800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2. ;return to Call subroutine ;in page 0 (000h-7FFh) EXAMPLE 4-2: movlw movwf clrf incf btfss goto NEXT INDIRECT ADDRESSING 0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next CONTINUE : ;yes continue FIGURE 4-10: DIRECT/INDIRECT ADDRESSING Direct Addressing from opcode RP1:RP0 6 bank select location select Indirect Addressing 0 IRP 7 bank select 00 01 10 FSR register 0 location select 11 00h 00h Data Memory 7Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure 4-2. DS30444E - page 30 1997 Microchip Technology Inc. PIC16C9XX 5.0 PORTS FIGURE 5-1: Some pins for these ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Data bus 5.1 WR Port PORTA and TRISA Register The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All RA pins have data direction bits (TRISA register) which can configure these pins as output or input. Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin. BLOCK DIAGRAM OF PINS RA3:RA0 AND RA5 D Q VDD Q CK Data Latch D WR TRIS For the PIC16C924 only, other PORTA pins are multiplexed with analog inputs and the analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as '0'. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. EXAMPLE 5-1: BCF BCF CLRF BSF MOVLW TRIS Latch MOVWF TRISA Initialize PORTA Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs RA<7:6> are always read as '0'. TTL input buffer RD TRIS Q D EN RD PORT To A/D Converter (PIC16C924 only) Note 1: I/O pins have protection diodes to VDD and VSS. FIGURE 5-2: Data bus WR PORT BLOCK DIAGRAM OF RA4/T0CKI PIN D Q CK Q N I/O pin(1) Data Latch ; Select Bank0 ; ; ; ; ; ; ; ; ; I/O pin(1) VSS Analog input mode Q CK INITIALIZING PORTA STATUS, RP0 STATUS, RP1 PORTA STATUS, RP0 0xCF N Q Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. P WR TRIS D Q CK Q VSS Schmitt Trigger input buffer TRIS Latch RD TRIS Q D EN EN RD PORT TMR0 clock input Note 1: I/O pin has protection diodes to VSS only. 1997 Microchip Technology Inc. DS30444E - page 31 PIC16C9XX TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 (1) bit0 TTL Input/output or analog input RA1/AN1 (1) bit1 TTL Input/output or analog input RA2/AN2(1) bit2 TTL Input/output or analog input bit3 TTL Input/output or analog input or VREF bit4 ST Input/output or external clock input for Timer0 Output is open drain type RA3/AN3/V REF(1) RA4/T0CKI TTL Input/output or analog input or slave select input for synchronous serial port RA5/AN4/SS (1) bit5 Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: The AN and VREF functions are for the A/D module and are only implemented on the PIC16C924. TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 05h PORTA -- -- RA5 RA4 RA3 RA2 RA1 RA0 (2) (2) 85h TRISA -- -- --11 1111 --11 1111 9Fh(1) ADCON1 -- -- ---- -000 ---- -000 PORTA Data Direction Control Register -- -- -- PCFG2 PCFG1 PCFG0 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: The ADCON1 register is implemented on the PIC16C924 only. 2: PIC16C923 reset values for PORTA: --xx xxxx for a POR, and --uu uuuu for all other resets, PIC16C924 reset values for PORTA: --0x 0000 when read. DS30444E - page 32 1997 Microchip Technology Inc. PIC16C9XX 5.2 PORTB and TRISB Register PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). EXAMPLE 5-2: This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) INITIALIZING PORTB BCF BCF CLRF BSF MOVLW STATUS, RP0 STATUS, RP1 PORTB STATUS, RP0 0xCF MOVWF TRISB b) ; Select Bank0 ; ; ; ; ; ; ; ; Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition, and allow flag bit RBIF to be cleared. Initialize PORTB Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are also disabled on a Power-on Reset. FIGURE 5-3: PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>). BLOCK DIAGRAM OF RB3:RB0 PINS This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552). The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. FIGURE 5-4: BLOCK DIAGRAM OF RB7:RB4 PINS VDD RBPU(2) Data bus WR Port weak P pull-up Data Latch D Q Data bus I/O pin(1) CK TRIS Latch D Q WR TRIS VDD RBPU(2) Data Latch D Q I/O pin(1) CK TRIS Latch D Q TTL Input Buffer CK WR Port weak P pull-up WR TRIS TTL Input Buffer CK ST Buffer RD TRIS Q RD TRIS D Q RD Port Latch D EN EN RD Port Q1 Set RBIF RB0/INT Schmitt Trigger Buffer RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit and clear the RBPU bit (OPTION<7>). Four of PORTB's pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of 1997 Microchip Technology Inc. From other RB7:RB4 pins Q D RD Port EN Q3 RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit and clear the RBPU bit (OPTION<7>). DS30444E - page 33 PIC16C9XX TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST Input/output pin or external interrupt input. Internal software programmable weak pull-up. This buffer is a Schmitt Trigger input when configured as the external interrupt. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. This buffer is a Schmitt Trigger input when used in serial programming mode. RB7 bit7 TTL/ST Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. This buffer is a Schmitt Trigger input when used in serial programming mode. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB 1111 1111 1111 1111 81h, 181h OPTION 1111 1111 1111 1111 PORTB Data Direction Control Register RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30444E - page 34 1997 Microchip Technology Inc. PIC16C9XX 5.3 PORTC and TRISC Register FIGURE 5-5: PORTC is an 6-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. VDD RBPU(2) weak P pull-up Data Latch D Q Data bus When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modify-write instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. EXAMPLE 5-3: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) WR Port I/O pin(1) CK TRIS Latch D Q WR TRIS TTL Input Buffer CK RD TRIS Q INITIALIZING PORTC BCF BCF CLRF BSF MOVLW STATUS,RP0 STATUS,RP1 PORTC STATUS,RP0 0xCF MOVWF TRISC ; ; ; ; ; ; ; ; EN RD Port ; Select Bank0 Initialize PORTC D RB0/INT Schmitt Trigger Buffer Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> always read 0 RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). TABLE 5-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output or Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture input/Compare output/PWM output RC3/SCK/SCL bit3 ST Input/output port pin or the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST Input/output port pin or the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data out Legend: ST = Schmitt Trigger input TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h PORTC -- -- 87h TRISC -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets RC5 RC4 RC3 RC2 RC1 RC0 --xx xxxx --uu uuuu --11 1111 --11 1111 PORTC Data Direction Control Register Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTC. 1997 Microchip Technology Inc. DS30444E - page 35 PIC16C9XX 5.4 PORTD and TRISD Registers FIGURE 5-6: PORTD is an 8-bit port with Schmitt Trigger input buffers. The first five pins are configurable as general purpose I/O pins or LCD segment drivers. Pins RD5, RD6 and RD7 can be digital inputs or LCD segment or common drivers. TRISD controls the direction of pins RD0 through RD4 when PORTD is configured as a digital port. Note: On a Power-on Reset these pins are configured as LCD segment drivers. PORTD<4:0> BLOCK DIAGRAM LCD Segment Data LCD Segment Output Enable Data Bus WR PORT D Q I/O pin CK Data Latch Note: To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. EXAMPLE 5-4: BCF BSF BCF BCF BSF BCF MOVLW MOVWF D WR TRIS Q CK Schmitt Trigger input buffer TRIS Latch INITIALIZING PORTD STATUS,RP0 STATUS,RP1 LCDSE,SE29 LCDSE,SE0 STATUS,RP0 STATUS,RP1 0x07 TRISD ;Select Bank2 ; ;Make RD<7:5> ;Make RD<4:0> ;Select Bank1 ; ;Make RD<4:0> ;Make RD<7:5> RD TRIS LCDSE<n> digital digital Q outputs inputs D EN EN RD PORT DS30444E - page 36 1997 Microchip Technology Inc. PIC16C9XX FIGURE 5-7: PORTD<7:5> BLOCK DIAGRAM LCD Segment Data LCD Segment Output Enable LCD Common Data LCD Common Output Enable Digital Input/ LCD Output pin LCDSE<n> Schmitt Trigger input buffer Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-7: PORTD FUNCTIONS Name Bit# Buffer Type RD0/SEG00 bit0 ST Input/output port pin or Segment Driver00 RD1/SEG01 bit1 ST Input/output port pin or Segment Driver01 RD2/SEG02 bit2 ST Input/output port pin or Segment Driver02 RD3/SEG03 bit3 ST Input/output port pin or Segment Driver03 RD4/SEG04 bit4 ST Input/output port pin or Segment Driver04 RD5/SEG29/COM3 bit5 ST Digital input pin or Segment Driver29 or Common Driver3 RD6/SEG30/COM2 bit6 ST Digital input pin or Segment Driver30 or Common Driver2 RD7/SEG31/COM1 bit7 ST Legend: ST = Schmitt Trigger input Digital input pin or Segment Driver31 or Common Driver1 Function TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Address Name 08h PORTD 88h TRISD 10Dh LCDSE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 PORTD Data Direction Control Register SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 Legend: Shaded cells are not used by PORTD. 1997 Microchip Technology Inc. DS30444E - page 37 PIC16C9XX 5.5 PORTE and TRISE Register FIGURE 5-8: PORTE is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. PORTE BLOCK DIAGRAM LCD Segment Data LCD Segment Output Enable Note 1: On a Power-on Reset these pins are configured as LCD segment drivers. LCD Common Data Note 2: To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. EXAMPLE 5-5: BCF BSF BCF BCF BCF STATUS,RP0 STATUS,RP1 LCDSE,SE27 LCDSE,SE5 LCDSE,SE9 LCD Common Output Enable Digital Input/ LCD Output pin LCDSE<n> INITIALIZING PORTE Schmitt Trigger input buffer ;Select Bank2 ; ;Make all PORTE ;and PORTG<7> ;digital inputs Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-9: PORTE FUNCTIONS Name Bit# Buffer Type RE0/SEG05 bit0 ST Digital input or Segment Driver05 RE1/SEG06 bit1 ST Digital input or Segment Driver06 RE2/SEG07 bit2 ST Digital input or Segment Driver07 RE3/SEG08 bit3 ST Digital input or Segment Driver08 RE4/SEG09 bit4 ST Digital input or Segment Driver09 RE5/SEG10 bit5 ST Digital input or Segment Driver10 RE6/SEG11 bit6 ST Digital input or Segment Driver11 RE7/SEG27 bit7 ST Legend: ST = Schmitt Trigger input Function Digital input or Segment Driver27 (not available on 64-pin devices) TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Address Name 09h PORTE 89h TRISE 10Dh LCDSE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 PORTE Data Direction Control Register SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 Legend: Shaded cells are not used by PORTE. DS30444E - page 38 1997 Microchip Technology Inc. PIC16C9XX 5.6 PORTF and TRISF Register FIGURE 5-9: PORTF is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. LCD Segment Data LCD Segment Output Enable Note 1: On a Power-on Reset these pins are configured as LCD segment drivers. LCD Common Data Note 2: To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. EXAMPLE 5-6: BCF BSF BCF BCF STATUS,RP0 STATUS,RP1 LCDSE,SE16 LCDSE,SE12 PORTF BLOCK DIAGRAM LCD Common Output Enable Digital Input/ LCD Output pin LCDSE<n> INITIALIZING PORTF Schmitt Trigger input buffer ;Select Bank2 ; ;Make all PORTF ;digital inputs Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-11: PORTF FUNCTIONS Name Bit# Buffer Type Function RF0/SEG12 bit0 ST Digital input or Segment Driver12 RF1/SEG13 bit1 ST Digital input or Segment Driver13 RF2/SEG14 bit2 ST Digital input or Segment Driver14 RF3/SEG15 bit3 ST Digital input or Segment Driver15 RF4/SEG16 bit4 ST Digital input or Segment Driver16 RF5/SEG17 bit5 ST Digital input or Segment Driver17 RF6/SEG18 bit6 ST Digital input or Segment Driver18 RF7/SEG19 bit7 ST Legend: ST = Schmitt Trigger input Digital input or Segment Driver19 TABLE 5-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 107h PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 0000 0000 0000 0000 187h TRISF 1111 1111 1111 1111 10Dh LCDSE SE12 SE9 SE5 SE0 1111 1111 1111 1111 PORTF Data Direction Control Register SE29 SE27 SE20 SE16 Legend: Shaded cells are not used by PORTF. 1997 Microchip Technology Inc. DS30444E - page 39 PIC16C9XX 5.7 PORTG and TRISG Register FIGURE 5-10: PORTG BLOCK DIAGRAM PORTG is an digital input only port. Each pin is multiplexed with an LCD segment driver. These pins have Schmitt Trigger input buffers. LCD Segment Data LCD Segment Output Enable Note 1: On a Power-on Reset these pins are configured as LCD segment drivers. LCD Common Data Note 2: To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. LCD Common Output Enable Digital Input/ LCD Output pin LCDSE<n> EXAMPLE 5-7: BCF BSF BCF BCF STATUS,RP0 STATUS,RP1 LCDSE,SE27 LCDSE,SE20 INITIALIZING PORTG Schmitt Trigger input buffer ;Select Bank2 ; ;Make all PORTG ;and PORTE<7> ;digital inputs Data Bus Q D EN EN RD PORT VDD RD TRIS TABLE 5-13: PORTG FUNCTIONS Name Bit# Buffer Type RG0/SEG20 bit0 ST Digital input or Segment Driver20 RG1/SEG21 bit1 ST Digital input or Segment Driver21 RG2/SEG22 bit2 ST Digital input or Segment Driver22 RG3/SEG23 bit3 ST Digital input or Segment Driver23 RG4/SEG24 bit4 ST Digital input or Segment Driver24 RG5/SEG25 bit5 ST Digital input or Segment Driver25 RG6/SEG26 bit6 ST Digital input or Segment Driver26 RG7/SEG28 bit7 ST Legend: ST = Schmitt Trigger input Function Digital input or Segment Driver28 (not available on 64-pin devices) TABLE 5-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 108h PORTG RG7 RG6 RG5 RG4 RG3 RG2 RG1 RG0 0000 0000 0000 0000 188h TRISG 1111 1111 1111 1111 10Dh LCDSE 1111 1111 1111 1111 PORTG Data Direction Control Register SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 Legend: Shaded cells are not used by PORTG. DS30444E - page 40 1997 Microchip Technology Inc. PIC16C9XX 5.8 I/O Programming Considerations 5.8.1 BI-DIRECTIONAL I/O PORTS EXAMPLE 5-8: Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the contents of the data latch may now be unknown. Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. Example 5-8 shows the effect of two sequential read-modify-write instructions on an I/O port. READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BCF STATUS, RP1 ; BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high). A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin ("wired-or", "wired-and"). The resulting high output currents may damage the chip. 5.8.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-11). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. FIGURE 5-11: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched PC PC + 1 MOVWF PORTB MOVF PORTB,W write to PORTB PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) RB7:RB0 where TCY = instruction cycle TPD = propagation delay Port pin sampled here TPD Instruction executed NOP MOVWF PORTB write to PORTB 1997 Microchip Technology Inc. Note: MOVF PORTB,W Therefore, at higher clock frequencies, a write followed by a read may be problematic. DS30444E - page 41 PIC16C9XX NOTES: DS30444E - page 42 1997 Microchip Technology Inc. PIC16C9XX 6.0 OVERVIEW OF TIMER MODULES Each module can generate an interrupt to indicate that an event has occurred (e.g. timer overflow). Each of these modules is explained in full detail in the following sections. The timer modules are: * Timer0 Module (Section 7.0) * Timer1 Module (Section 8.0) * Timer2 Module (Section 9.0) 6.1 Timer0 Overview chronous Serial Port (SSP). The prescaler option allows Timer2 to increment at the following rates: 1:1, 1:4, 1:16. The postscaler allows the TMR2 register to match the period register (PR2) a programmable number of times before generating an interrupt. The postscaler can be programmed from 1:1 to 1:16 (inclusive). 6.4 CCP Overview The CCP module can operate in one of these three modes: 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). The Timer0 module is a simple 8-bit timer/counter. The clock source can be either the internal system clock (Fosc/4) or an external clock. When the clock source is an external clock, the Timer0 module can be selected to increment on either the rising or falling edge. Capture mode captures the 16-bit value of TMR1 into the CCPR1H:CCPR1L register pair. The capture event can be programmed for either the falling edge, rising edge, fourth rising edge, or the sixteenth rising edge of the CCP1 pin. The Timer0 module also has a programmable prescaler option. This prescaler can be assigned to either the Timer0 module or the Watchdog Timer. Bit PSA (OPTION<3>) assigns the prescaler, and bits PS2:PS0 (OPTION<2:0>) determine the prescaler value. Timer0 can increment at the following rates: 1:1 when prescaler assigned to Watchdog timer, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256. Compare mode compares the TMR1H:TMR1L register pair to the CCPR1H:CCPR1L register pair. When a match occurs an interrupt can be generated, and the output pin CCP1 can be forced to given state (High or Low), TMR1 can be reset and start A/D conversion. This depends on the control bits CCP1M3:CCP1M0. Synchronization of the external clock occurs after the prescaler. When the prescaler is used, the external clock frequency may be higher then the device's frequency. The maximum frequency is 50 MHz, given the high and low time requirements of the clock. 6.2 PWM mode compares the TMR2 register to a 10-bit duty cycle register (CCPR1H:CCPR1L<5:4>) as well as to an 8-bit period register (PR2). When the TMR2 register = Duty Cycle register, the CCP1 pin will be forced low. When TMR2 = PR2, TMR2 is cleared to 00h, an interrupt can be generated, and the CCP1 pin (if an output) will be forced high. Timer1 Overview Timer1 is a 16-bit timer/counter. The clock source can be either the internal system clock (Fosc/4), an external clock, or an external crystal. Timer1 can operate as either a timer or a counter. When operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. Asynchronous operation allows Timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power savings of SLEEP mode. Timer1 also has a prescaler option which allows Timer1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. Timer1 can be used in conjunction with the Capture/Compare/PWM module. When used with a CCP module, Timer1 is the time-base for 16-bit capture or the 16-bit compare and must be synchronized to the device. Timer1 oscillator is also one of the clock sources for the LCD module. 6.3 Timer2 Overview Timer2 is an 8-bit timer with a programmable prescaler and postscaler, as well as an 8-bit period register (PR2). Timer2 can be used with the CCP1 module (in PWM mode) as well as the clock source for the Syn- 1997 Microchip Technology Inc. DS30444E - page 43 PIC16C9XX NOTES: DS30444E - page 44 1997 Microchip Technology Inc. PIC16C9XX 7.0 TIMER0 MODULE bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The Timer0 module has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler. Figure 7-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register. 7.1 The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. Figure 7-4 displays the Timer0 interrupt timing. Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clearing FIGURE 7-1: Timer0 Interrupt TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 1 Sync with Internal clocks 1 Programmable Prescaler RA4/T0CKI pin 8 0 TMR0 PSout (2 cycle delay) T0SE 3 Set interrupt flag bit T0IF on overflow PSA PS2, PS1, PS0 T0CS Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram). FIGURE 7-2: PC (Program Counter) TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 Instruction Fetch TMR0 T0 PC PC+1 MOVWF TMR0 MOVF TMR0,W T0+1 Instruction Executed 1997 Microchip Technology Inc. PC+2 MOVF TMR0,W PC+3 MOVF TMR0,W T0+2 NT0 NT0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 PC+4 MOVF TMR0,W NT0 Read TMR0 reads NT0 PC+5 PC+6 MOVF TMR0,W NT0+1 NT0+2 Read TMR0 reads NT0 + 1 T0 Read TMR0 reads NT0 + 2 DS30444E - page 45 PIC16C9XX FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0,W Instruction Execute PC+4 PC+5 MOVF TMR0,W PC+6 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 PC+6 NT0+1 NT0 Write TMR0 executed FIGURE 7-4: PC+3 MOVF TMR0,W T0+1 T0 TMR0 PC+2 MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 TIMER0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) Timer0 FEh T0IF bit (INTCON<2>) FFh 00h 01h 02h 1 1 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC +1 PC +1 Inst (PC+1) Inst (PC) Dummy cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4TCY where TCY = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. DS30444E - page 46 1997 Microchip Technology Inc. PIC16C9XX 7.2 Using Timer0 with an External Clock caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device. 7.2.2 TMR0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Prescaler output (2) Q1 Q2 Q3 Q4 Small pulse misses sampling (1) (3) External Clock/Prescaler Output after sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1997 Microchip Technology Inc. DS30444E - page 47 PIC16C9XX 7.3 Prescaler When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler count. When assigned to WDT, a CLRWDT instruction will clear the prescaler count along with the Watchdog Timer. The prescaler is not readable or writable. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (Figure 7-6). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus CLKOUT (=Fosc/4) 0 RA4/T0CKI pin 8 M U X 1 M U X 0 1 SYNC 2 Cycles TMR0 reg T0SE T0CS 0 Watchdog Timer 1 M U X Set flag bit T0IF on Overflow PSA 8-bit Prescaler 8 8 - to - 1MUX PS2:PS0 PSA WDT Enable bit 1 0 MUX PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). DS30444E - page 48 1997 Microchip Technology Inc. PIC16C9XX 7.3.1 SWITCHING PRESCALER ASSIGNMENT Note: The prescaler assignment is fully under software control, i.e., it can be changed "on the fly" during program execution. EXAMPLE 7-1: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This precaution must be followed even if the WDT is disabled. CHANGING PRESCALER (TIMER0WDT) Lines 2 and 3 do NOT have to be included if the final desired prescale value is other than 1:1. If 1:1 is final desired value, then a temporary prescale value is set in lines 2 and 3 and the final prescale value will be set in lines 10 and 11. 1) BSF STATUS, RP0 ;Select Bank1 2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of 3) MOVWF OPTION_REG ;other than 1:1 4) BCF STATUS, RP0 ;Select Bank0 5) CLRF TMR0 ;Clear TMR0 and prescaler 6) BSF STATUS, RP1 ;Select Bank1 7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value 8) MOVWF OPTION_REG ; 9) CLRWDT ;Clears WDT and prescaler 10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT 11) MOVWF OPTION_REG ; 12) BCF STATUS, RP0 ;Select Bank0 To change prescaler from the WDT to the Timer0 module use the precaution shown in Example 7-2. EXAMPLE 7-2: CLRWDT BSF MOVLW MOVWF BCF CHANGING PRESCALER (WDTTIMER0) STATUS, RP0 b'xxxx0xxx' OPTION_REG STATUS, RP0 ;Clear WDT and prescaler ;Select Bank1 ;Select TMR0, new prescale value and ;clock source ;Select Bank0 TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0 Address Name 01h, 101h TMR0 0Bh, 8Bh, INTCON 10Bh, 18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 module's register GIE PEIE 81h, 181h OPTION RBPU INTEDG 85h TRISA -- -- Value on Power-on Reset Value on all other resets xxxx xxxx uuuu uuuu T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 --11 1111 --11 1111 PORTA Data Direction Control Register Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. 1997 Microchip Technology Inc. DS30444E - page 49 PIC16C9XX NOTES: DS30444E - page 50 1997 Microchip Technology Inc. PIC16C9XX 8.0 TIMER1 MODULE Timer1 is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>). Timer1 can be turned on and off using the control bit TMR1ON (T1CON<0>). Timer1 also has an internal "reset input". This reset can be generated by the CCP module (Section 10.0). Figure 8-1 shows the Timer1 control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. Timer1 can operate in one of two modes: * As a timer * As a counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. FIGURE 8-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 -- -- R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC R/W-0 R/W-0 TMR1CS TMR1ON bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin T1CKI (on the rising edge) 0 = Internal clock (Fosc/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1997 Microchip Technology Inc. DS30444E - page 51 PIC16C9XX 8.1 Timer1 Operation in Timer Mode 8.2.1 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is Fosc/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. 8.2 When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TMR1 after synchronization. Timer1 Operation in Synchronized Counter Mode When the prescaler is 1:1, the external clock input is the same as the prescaler output. The synchronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T1CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the appropriate electrical specifications, parameters 45, 46, and 47. Counter mode is selected by setting bit TMR1CS. In this mode the timer increments on every rising edge of clock input on pin RC1/T1OSI when bit T1OSCEN is set or pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler is an asynchronous ripple-counter. When a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. In order for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T1CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T1CKI high and low time is that they do not violate the minimum pulse width requirements of 10 ns). Refer to the appropriate electrical specifications, parameters 40, 42, 45, 46, and 47. In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. The prescaler however will continue to increment. FIGURE 8-2: EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE TIMER1 BLOCK DIAGRAM Set flag bit TMR1IF on Overflow 0 TMR1 TMR1H Synchronized clock input TMR1L 1 TMR1ON on/off T1SYNC T1OSC RC0/T1OSO/T1CKI RC1/T1OSI Note 1 T1OSCEN Fosc/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 Synchronize det 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP input 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS30444E - page 52 1997 Microchip Technology Inc. PIC16C9XX 8.3 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow which will wake-up the processor. However, special precautions in software are needed to read-from or write-to the Timer1 register pair (TMR1H:TMR1L) (Section 8.3.2). In asynchronous counter mode, Timer1 cannot be used as a time-base for capture or compare operations. 8.3.1 EXTERNAL CLOCK INPUT TIMING WITH UNSYNCHRONIZED CLOCK If control bit T1SYNC is set, the timer will increment completely asynchronously. The input clock must meet certain minimum high time and low time requirements, as specified in timing parameters 45, 46, and 47. 8.3.2 READING AND WRITING TMR1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running, from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. Example 8-1 is an example routine to read the 16-bit timer value. This is useful if the timer cannot be stopped. EXAMPLE 8-1: READING A 16-BIT FREE-RUNNING TIMER ; All interrupts MOVF TMR1H, MOVWF TMPH MOVF TMR1L, MOVWF TMPL MOVF TMR1H, SUBWF TMPH, BTFSC GOTO are disabled W ;Read high byte ; W ;Read low byte ; W ;Read high byte W ;Sub 1st read ; with 2nd read STATUS,Z ;Is result = 0 CONTINUE ;Good 16-bit read ; ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high ; and low bytes now will read a good value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupt (if required) CONTINUE ;Continue with your code 8.4 Timer1 Oscillator A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 8-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. TABLE 8-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq C1 C2 LP 32 kHz 100 kHz 200 kHz 33 pF 15 pF 15 pF 33 pF 15 pF 15 pF These values are for design guidance only. Crystals Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM 100 kHz Epson C-2 100.00 KC-P 20 PPM 200 kHz STD XTL 200.000 kHz 20 PPM Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 1997 Microchip Technology Inc. DS30444E - page 53 PIC16C9XX 8.5 Resetting Timer1 using the CCP Trigger Output 8.6 If the CCP1 module is configured in compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: Resetting of Timer1 Register Pair (TMR1H:TMR1L) TMR1H and TMR1L registers are not reset on a POR or any other reset except by the CCP1 special event trigger. T1CON register is reset to 00h on a Power-on Reset. In any other reset, the register is unaffected. The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). 8.7 Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work. Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1. TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Address Name 0Bh, 8Bh, INTCON 10Bh, 18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF(1) -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 8Ch PIE1 LCDIE ADIE(1) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu --00 0000 --uu uuuu 0Fh TMR1H 10h T1CON -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by theTimer1 module. Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear. DS30444E - page 54 1997 Microchip Technology Inc. PIC16C9XX 9.0 TIMER2 MODULE 9.1 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16 (selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>)). The Timer2 module has an 8-bit period register, PR2. TMR2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is set during RESET. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device reset (Power-on Reset, MCLR Reset, or Watchdog Timer Reset) TMR2 will not clear when T2CON is written. 9.2 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock. FIGURE 9-1: Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. TIMER2 BLOCK DIAGRAM Fosc/4 Figure 9-2 shows the Timer2 control register. Prescaler 1:1, 1:4, 1:16 2 TMR2 reg Reset Comparator EQ PR2 reg Note FIGURE 9-2: U-0 -- Sets flag bit TMR2IF TMR2 output (1) Postscaler 1:16 to 1:1 4 1: TMR2 register output can be software selected by the SSP Module as the source clock. T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 1997 Microchip Technology Inc. R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset DS30444E - page 55 PIC16C9XX TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on Power-on Reset Value on all other resets Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0Ch PIR1 LCDIF ADIF(1) -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 8Ch PIE1 LCDIE ADIE(1) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 11h TMR2 12h T2CON 92h PR2 0000 0000 0000 0000 Timer2 module's register -- 0000 000x 0000 000u TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 Timer2 Period Register Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear. DS30444E - page 56 1997 Microchip Technology Inc. PIC16C9XX 10.0 CAPTURE/COMPARE/PWM (CCP) MODULE For use of the CCP module, refer to the Embedded Control Handbook, "Using the CCP Modules" (AN594). The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM master/slave duty cycle register. Table 10-1 shows the timer resources used by the CCP module. TABLE 10-1: CCP MODE - TIMER RESOURCE Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All three are readable and writable. CCP Mode Timer Resource Capture Compare PWM Timer1 Timer1 Timer2 Figure 10-1 shows the CCP1CON register. FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h) U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- CCP1X CCP1Y CCP1M3 bit7 R/W-0 CCP1M2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Significant bits Capture Mode Unused Compare Mode Unused PWM Mode These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (bit CCP1IF is set) 1001 = Compare mode, clear output on match (bit CCP1IF is set) 1010 = Compare mode, generate software interrupt on match (bit CCP1IF is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1) 11xx = PWM mode 1997 Microchip Technology Inc. DS30444E - page 57 PIC16C9XX 10.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1 (Figure 10-2). An event is defined as: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 10.1.1 CCP PIN CONFIGURATION If the RC2/CCP1 pin is configured as an output, a write to the port can cause a capture condition. FIGURE 10-2: CAPTURE MODE OPERATION BLOCK DIAGRAM CCP Prescaler / 1, 4, 16 Set CCP1IF PIR1<2> RC2/CCP1 pin CLRF MOVLW MOVWF CCP1CON ; Turn CCP module off NEW_CAPT_PS ; Load the W reg with ; the new prescaler ; mode value and CCP ON CCP1CON ; Load CCP1CON with ; this value Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * Driven High * Driven Low * Remains Unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, a compare interrupt is also generated. FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM CCPR1H and edge detect EXAMPLE 10-1: CHANGING BETWEEN CAPTURE PRESCALERS 10.2 In capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the first capture may be from a non-zero prescaler. Example 10-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. CCPR1L Special event trigger will reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>). Capture Enable TMR1H TMR1L Trigger CCP1CON<3:0> Q's 10.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode the capture operation may not work. 10.1.3 S R Output Logic CCPR1H CCPR1L match TRISC<2> Output Enable CCP1CON<3:0> Mode Select Comparator TMR1H TMR1L SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep enable bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear flag bit CCP1IF following any such change in operating mode. 10.1.4 Q RC2/CCP1 Set CCP1IF PIR1<2> CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter. DS30444E - page 58 10.2.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. 1997 Microchip Technology Inc. PIC16C9XX 10.2.1 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 10.2.2 FIGURE 10-4: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty cycle registers CCPR1L SOFTWARE INTERRUPT MODE When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). CCPR1H (Slave) R Comparator 10.2.3 Q SPECIAL EVENT TRIGGER RC1/CCP1 TMR2 In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair and starts an A/D conversion. This allows the CCPR1H:CCPR1L register pair to effectively be a 16-bit programmable period register for Timer1. Note: 10.3 The "special event trigger" from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: (Note 1) S TRISC<2> Comparator Clear Timer, CCP1 pin and latch D.C. PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base. A PWM output (Figure 10-5) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 10-5: PWM OUTPUT Period Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 10-4 shows a simplified block diagram of the CCP module in PWM mode. Duty Cycle For a step by step procedure on how to set up the CCP module for PWM operation, see Section 10.3.3. TMR2 = PR2 TMR2 = PR2 TMR2 = Duty Cycle 10.3.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [ (PR2) + 1 ] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H 1997 Microchip Technology Inc. DS30444E - page 59 PIC16C9XX Note: 10.3.2 EXAMPLE 10-2: PWM PERIOD AND DUTY CYCLE CALCULATION The Timer2 postscaler (Section 9.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Desired PWM frequency is 31.25 kHz, Fosc = 8 MHz TMR2 prescale = 1 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. = 63 1/31.25 kHz = 2PWM RESOLUTION * 1/8 MHz * 1 32 s = 2PWM RESOLUTION * 125 ns * 1 256 = 2PWM RESOLUTION log(256) = (PWM Resolution) * log(2) 8.0 = PWM Resolution 10.3.3 ) SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: bits log(2) 1. 2. Note: PR2 Table 10-2 lists example PWM frequencies and resolutions for Fosc = 8 MHz. TMR2 prescaler and PR2 values are also shown. Maximum PWM resolution (bits) for a given PWM frequency: = = [ (PR2) + 1 ] * 4 * 125 ns * 1 In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased. When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. FOSC FPWM 32 s At most, an 8-bit resolution duty cycle can be obtained from a 31.25 kHz frequency and a 8 MHz oscillator, i.e., 0 CCPR1L:CCP1CON<5:4> 255. Any value greater than 255 will result in a 100% duty cycle. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. ( = [ (PR2) + 1 ] * 4 * 1/8 MHz * 1 Find the maximum resolution of the duty cycle that can be used with a 31.25 kHz frequency and 8 MHz oscillator: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * Tosc * (TMR2 prescale value) log 1/31.25 kHz If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP module for PWM operation. TABLE 10-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 8 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) DS30444E - page 60 488 Hz 1.95 kHz 7.81 kHz 31.25 kHz 62.5 kHz 250 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x07 10 10 10 8 7 5 1997 Microchip Technology Inc. PIC16C9XX TABLE 10-3: REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF(1) -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 LCDIE (1) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 8Ch PIE1 ADIE 87h TRISC --11 1111 --11 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu --00 0000 --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 10h 15h T1CON -- -- -- -- PORTC Data Direction Control Register T1CKPS1 T1CKPS0 CCPR1L Capture/Compare/PWM1 (LSB) 16h CCPR1H Capture/Compare/PWM1 (MSB) 17h CCP1CON -- -- CCP1X CCP1Y T1OSCEN CCP1M3 T1SYNC CCP1M2 TMR1CS CCP1M1 TMR1ON CCP1M0 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used in these modes. Note 1: Bits ADIE and ADIF reserved on the PIC16C923, always maintain these bits clear. TABLE 10-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF(1) -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 8Ch PIE1 LCDIE ADIE(1) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 87h TRISC -- -- --11 1111 --11 1111 11h TMR2 Timer2 module's register 0000 0000 0000 0000 92h PR2 Timer2 module's Period register 1111 1111 1111 1111 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM1 (LSB) 16h CCPR1H Capture/Compare/PWM1 (MSB) 17h CCP1CON -- -- -- PORTC Data Direction Control Register CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used in this mode. Note 1: Bits ADIE and ADIF reserved on the PIC16C923, always maintain these bits clear. 1997 Microchip Technology Inc. DS30444E - page 61 PIC16C9XX NOTES: DS30444E - page 62 1997 Microchip Technology Inc. PIC16C9XX 11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE play drivers, A/D converters, etc. The SSP module can operate in one of two modes: The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, dis- * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I 2C) Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment." FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 SMP CKE R-0 R-0 R-0 R-0 R-0 R-0 D/A P S R/W UA BF bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode bit 6: CKE: SPI Clock Edge Select (Figure 11-5, Figure 11-6, and Figure 11-7) CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit was detected last) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit was detected last) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty 1997 Microchip Technology Inc. DS30444E - page 63 PIC16C9XX FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master mode, clock = FOSC/4 0001 = SPI master mode, clock = FOSC/16 0010 = SPI master mode, clock = FOSC/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C Firmware controlled master mode (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled DS30444E - page 64 1997 Microchip Technology Inc. PIC16C9XX 11.1 SPI Mode The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) RC5/SDO * Serial Data In (SDI) RC4/SDI * Serial Clock (SCK) RC3/SCK Additionally a fourth pin may be used when in a slave mode of operation: * Slave Select (SS) RA5/AN4/SS (the AN4 function is implemented on the PIC16C924 only) When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master Mode (SCK is the clock output) Slave Mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select Mode (Slave mode only) The SSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit BF (SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>) are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL (SSPCON<7>) will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 11-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The shaded instruction is only required if the received data is meaningful. 1997 Microchip Technology Inc. EXAMPLE 11-1: LOADING THE SSPBUF (SSPSR) REGISTER BCF STATUS, RP1 BSF STATUS, RP0 LOOP BTFSS SSPSTAT, BF GOTO BCF MOVF ;Select Bank1 ; ;Has data been ;received ;(transmit ;complete)? ;No ;Select Bank0 ;W reg = contents ; of SSPBUF ;Save in user RAM LOOP STATUS, RP0 SSPBUF, W MOVWF RXDATA MOVF TXDATA, W ;W reg = contents ; of TXDATA ;New data to xmit MOVWF SSPBUF The block diagram of the SSP module, when in SPI mode (Figure 11-3), shows that the SSPSR is not directly readable or writable, and can only be accessed from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status conditions. FIGURE 11-3: SSP BLOCK DIAGRAM (SPI MODE) Internal data bus Read Write SSPBUF reg SSPSR reg RC4/SDI/SDA shift clock bit0 RC5/SDO SS Control Enable RA5/AN4/SS Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TMR2 output 2 Prescaler TCY 4, 16, 64 TRISC<3> DS30444E - page 65 PIC16C9XX To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (Master mode) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example would be in master mode where you are only sending data (to a display driver), then both SDI and SS could be used as general purpose outputs by clearing their corresponding TRIS register bits. The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2) is to broadcast data by the firmware protocol. In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SCK output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "line activity monitor" mode. In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched the interrupt flag bit SSPIF (PIR1<3>) is set. The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give waveforms for SPI communication as shown in Figure 11-5, Figure 11-6, and Figure 11-7 where the MSB is transmitted first. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: Figure 11-4 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * * * * * Master sends data -- Slave sends dummy data * Master sends data -- Slave sends data * Master sends dummy data -- Slave sends data In sleep mode, the slave can transmit and receive data and wake the device from sleep. FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum bit clock frequency (at 8 MHz) of 2 MHz. When in slave mode the external clock must meet the minimum high and low times. FIGURE 11-4: SPI MASTER/SLAVE CONNECTION SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) SDI Shift Register (SSPSR) MSb SDO LSb Shift Register (SSPSR) MSb LSb Serial Clock SCK PROCESSOR 1 DS30444E - page 66 SCK PROCESSOR 2 1997 Microchip Technology Inc. PIC16C9XX The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application. Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to VDD. Note: If the SPI is used in Slave Mode with CKE = '1', then the SS pin control must be enabled. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conflict. FIGURE 11-5: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 11-6: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF 1997 Microchip Technology Inc. DS30444E - page 67 PIC16C9XX FIGURE 11-7: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS (not optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit6 bit7 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 0Bh, 8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 LCDIF ADIF(1) -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 8Ch PIE1 LCDIE ADIE(1) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA -- -- PORTA Data Direction Control Register --11 1111 --11 1111 87h TRISC -- -- PORTC Data Direction Control Register --11 1111 --11 1111 94h SSPSTAT SMP CKE 0000 0000 0000 0000 SSPEN D/A CKP P SSPM3 S SSPM2 R/W UA BF Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear. DS30444E - page 68 1997 Microchip Technology Inc. PIC16C9XX I 2C Overview 11.2 This section provides an overview of the Inter-Integrated Circuit (I 2C) bus, with Section 11.3 discussing the operation of the SSP module in I 2C mode. The I 2C bus is a two-wire serial interface developed by the Philips Corporation. The original specification, or standard mode, was for data transfers of up to 100 Kbps. An enhanced specification, or fast mode is not supported. This device will communicate with fast mode devices if attached to the same bus. The I 2C interface employs a comprehensive protocol to ensure reliable transmission and reception of data. When transmitting data, one device is the "master" which initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the "slave." All portions of the slave protocol are implemented in the SSP module's hardware, except general call support, while portions of the master protocol need to be addressed in the PIC16CXXX software. Table 11-2 defines some of the I 2C bus terminology. For additional information on the I 2C interface specification, refer to the Philips document "The I 2C bus and how to use it." #939839340011, which can be obtained from the Philips Corporation. In the I 2C interface protocol each device has an address. When a master wishes to initiate a data transfer, it first transmits the address of the device that it wishes to "talk" to. All devices "listen" to see if this is their address. Within this address, a bit specifies if the master wishes to read-from/write-to the slave device. The master and slave are always in opposite modes (transmitter/receiver) of operation during a data transfer. That is they can be thought of as operating in either of these two relations: The output stages of the clock (SCL) and data (SDA) lines must have an open-drain or open-collector in order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high level when no device is pulling the line down. The number of devices that may be attached to the I 2C bus is limited only by the maximum bus loading specification of 400 pF. 11.2.1 INITIATING AND TERMINATING DATA TRANSFER During times of no data transfer (idle time), both the clock line (SCL) and the data line (SDA) are pulled high through the external pull-up resistors. The START and STOP conditions determine the start and stop of data transmission. The START condition is defined as a high to low transition of the SDA when the SCL is high. The STOP condition is defined as a low to high transition of the SDA when the SCL is high. Figure 11-8 shows the START and STOP conditions. The master generates these conditions for starting and terminating data transfer. Due to the definition of the START and STOP conditions, when data is being transmitted, the SDA line can only change state when the SCL line is low. FIGURE 11-8: START AND STOP CONDITIONS SDA SCL S Start Condition * Master-transmitter and Slave-receiver * Slave-transmitter and Master-receiver P Change of Data Allowed Change of Data Allowed Stop Condition In both cases the master generates the clock signal. TABLE 11-2: I2C BUS TERMINOLOGY Term Description Transmitter The device that sends the data to the bus. Receiver The device that receives the data from the bus. Master The device which initiates the transfer, generates the clock and terminates the transfer. Slave The device addressed by a master. Multi-master More than one master device in a system. These masters can attempt to control the bus at the same time without corrupting the message. Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized. 1997 Microchip Technology Inc. DS30444E - page 69 PIC16C9XX ADDRESSING I 2C DEVICES 11.2.2 FIGURE 11-11: SLAVE-RECEIVER ACKNOWLEDGE There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure 11-9). The more complex is the 10-bit address with a R/W bit (Figure 11-10). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this to be a 10-bit address. Data Output by Transmitter Data Output by Receiver R/W ACK slave address S R/W ACK Sent by Slave Start Condition Read/Write pulse Acknowledge If the slave needs to delay the transmission of the next byte, holding the SCL line low will force the master into a wait state. Data transfer continues when the slave releases the SCL line. This allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. This wait state technique can also be implemented at the bit level, Figure 11-12. The slave will inherently stretch the clock, when it is a transmitter, but will not when it is a receiver. The slave will have to clear the SSPCON<4> bit to enable clock stretching when it is a receiver. S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK sent by slave = 0 for write 11.2.3 - Start Condition - Read/Write Pulse - Acknowledge TRANSFER ACKNOWLEDGE All data must be transmitted per byte, with no limit to the number of bytes transmitted per data transfer. After each byte, the slave-receiver generates an acknowledge bit (ACK) (Figure 11-11). When a slave-receiver doesn't acknowledge the slave address or received data, the master must abort the transfer. The slave must leave SDA high so that the master can generate the STOP condition (Figure 11-8). FIGURE 11-12: Clock Pulse for Acknowledgment If the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. To signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). The slave then releases the SDA line so the master can generate the STOP condition. The master can also generate the STOP condition during the acknowledge pulse for valid termination of data transfer. FIGURE 11-10: I2C 10-BIT ADDRESS FORMAT S R/W ACK 9 8 2 1 S Start Condition LSb S acknowledge SCL from Master FIGURE 11-9: 7-BIT ADDRESS FORMAT MSb not acknowledge DATA TRANSFER WAIT STATE SDA MSB acknowledgment signal from receiver byte complete interrupt with receiver acknowledgment signal from receiver clock line held low while interrupts are serviced SCL S Start Condition DS30444E - page 70 1 2 Address 7 8 9 R/W ACK 1 Wait State 2 Data 3*8 9 ACK P Stop Condition 1997 Microchip Technology Inc. PIC16C9XX is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send "commands" to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 11-15. Figure 11-13 and Figure 11-14 show Master-transmitter and Master-receiver data transfer sequences. When a master does not wish to relinquish the bus (by generating a STOP condition), a repeated START condition (Sr) must be generated. This condition is identical to the start condition (SDA goes high-to-low while SCL FIGURE 11-13: MASTER-TRANSMITTER SEQUENCE For 10-bit address: S Slave Address R/W A1 Slave Address A2 Second byte First 7 bits For 7-bit address: S Slave Address R/W A Data A Data A/A P '0' (write) data transferred (n bytes - acknowledge) A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed. From master to slave From slave to master (write) Data A A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition Data A/A P A master transmitter addresses a slave receiver with a 10-bit address. FIGURE 11-14: MASTER-RECEIVER SEQUENCE For 10-bit address: For 7-bit address: S Slave Address R/W A1 Slave Address A2 Second byte First 7 bits S Slave Address R/W A Data A Data A P '1' (read) data transferred (n bytes - acknowledge) A master reads a slave immediately after the first byte. From master to slave From slave to master (write) A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition Sr Slave Address R/W A3 Data A First 7 bits Data A P (read) A master transmitter addresses a slave receiver with a 10-bit address. FIGURE 11-15: COMBINED FORMAT (read or write) (n bytes + acknowledge) S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P (read) Sr = repeated Start Condition (write) Direction of transfer may change at this point Transfer direction of data and acknowledgment bits depends on R/W bits. Combined format: Sr Slave Address R/W A Slave Address A Data A First 7 bits Second byte Data A/A Sr Slave Address R/W A Data A First 7 bits Data A P (read) (write) Combined format - A master addresses a slave with a 10-bit address, then transmits data to this slave and reads data from this slave. From master to slave From slave to master 1997 Microchip Technology Inc. A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition DS30444E - page 71 PIC16C9XX 11.2.4 MULTI-MASTER 11.2.4.2 Clock Synchronization The I2C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur. 11.2.4.1 ARBITRATION Arbitration takes place on the SDA line, while the SCL line is high. The master which transmits a high when the other master transmits a low loses arbitration (Figure 11-16), and turns off its data output stage. A master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. When the master devices are addressing the same device, arbitration continues into the data. FIGURE 11-16: MULTI-MASTER ARBITRATION (TWO MASTERS) Clock synchronization occurs after the devices have started arbitration. This is performed using a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the concerned devices to start counting off their low period. Once a device clock has gone low, it will hold the SCL line low until its SCL high state is reached. The low to high transition of this clock may not change the state of the SCL line, if another device clock is still within its low period. The SCL line is held low by the device with the longest low period. Devices with shorter low periods enter a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start counting off their high periods. The first device to complete its high period will pull the SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure 11-17. FIGURE 11-17: CLOCK SYNCHRONIZATION transmitter 1 loses arbitration DATA 1 SDA wait state DATA 1 DATA 2 start counting HIGH period CLK 1 SDA CLK 2 counter reset SCL SCL Masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. This is because the winning master-transmitter may be addressing it. Arbitration is not allowed between: * A repeated START condition * A STOP condition and a data bit * A repeated START condition and a STOP condition Care needs to be taken to ensure that these conditions do not occur. DS30444E - page 72 1997 Microchip Technology Inc. PIC16C9XX 11.3 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). FIGURE 11-18: SSP BLOCK DIAGRAM (I2C MODE) Internal data bus Read Write SSPBUF reg RC3/SCK/SCL shift clock SSPSR reg RC4/ SDI/ SDA MSb LSb Match detect Addr Match SSPADD reg Start and Stop bit detect Set, Reset S, P bits (SSPSTAT reg) The SSP module has five registers for I2C operation. These are the: The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with start and stop bit interrupts enabled * I 2C Slave mode (10-bit address), with start and stop bit interrupts enabled * I 2C Firmware controlled Master Mode, slave is idle Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. The SSPSTAT register gives the status of the data transfer. This information includes detection of a START or STOP bit, specifies if the received byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. The SSPSTAT register is read only. The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the complete byte is received, it is transferred to the SSPBUF register and flag bit SSPIF is set. If another complete byte is received before the SSPBUF register is read, a receiver overflow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the SSPSR is lost. The SSPADD register holds the slave address. In 10-bit mode, the user needs to write the high byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of the address needs to be loaded (A7:A0). * * * * SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD) 1997 Microchip Technology Inc. DS30444E - page 73 PIC16C9XX 11.3.1 SLAVE MODE In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. These are if either (or both): a) b) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 11-3 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low time for proper operation. The high and low times of the I2C specification as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101. 11.3.1.1 address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) In 10-bit address mode, two address bytes need to be received by the slave (Figure 11-10). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for a 10-bit address is as follows, with steps 7- 9 for slave-transmitter: 1. 2. 3. 4. 5. ADDRESSING Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. 6. 7. 8. 9. Receive first (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. TABLE 11-3: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV SSPSR SSPBUF Generate ACK Pulse 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes DS30444E - page 74 1997 Microchip Technology Inc. PIC16C9XX 11.3.1.2 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. FIGURE 11-19: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address Receiving Data R/W=0 Receiving Data ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL S 1 2 3 4 5 6 SSPIF (PIR1<3>) BF (SSPSTAT<0>) 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 8 7 Cleared in software 9 P Bus Master terminates transfer SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. 1997 Microchip Technology Inc. DS30444E - page 75 PIC16C9XX 11.3.1.3 An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. TRANSMISSION When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 11-20). As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP. FIGURE 11-20: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL A7 S A6 1 2 Data in sampled SSPIF (PIR1<3>) R/W = 1 A5 A4 A3 A2 A1 3 4 5 6 7 8 9 ACK Transmitting Data ACK D7 1 SCL held low while CPU responds to SSPIF D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P cleared in software BF (SSPSTAT<0>) SSPBUF is written in software From SSP interrupt service routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) DS30444E - page 76 1997 Microchip Technology Inc. PIC16C9XX 11.3.2 11.3.3 MASTER MODE MULTI-MASTER MODE In multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP and START bits will toggle based on the start and stop conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. Master mode of operation is supported, in firmware, using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP and START bits will toggle based on the start and stop conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle with both the S and P bits clear. In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit. In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, they are: The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * Address Transfer * Data Transfer * START condition * STOP condition * Data transfer byte transmitted/received When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. Master mode of operation can be done with either the slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. TABLE 11-4: REGISTERS ASSOCIATED WITH I2C OPERATION Address Name 0Bh, 8Bh, INTCON 10Bh, 18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Value on all other resets 0Ch PIR1 LCDIF ADIF(1) -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 8Ch PIE1 LCDIE ADIE(1) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 13h SSPBUF xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port Receive Buffer/Transmit Register 2 Synchronous Serial Port (I C mode) Address Register 0000 0000 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 87h TRISC -- -- --11 1111 --11 1111 PORTC Data Direction Control Register I2 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by SSP in C mode. Note 1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear. 1997 Microchip Technology Inc. DS30444E - page 77 PIC16C9XX FIGURE 11-21: OPERATION OF THE I 2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( ACK Received = 1) { End of transmission; Go back to IDLE_MODE; } else if ( ACK Received = 0) Go back to XMIT_MODE; IDLE_MODE (10-Bit): If (High_byte_addr_match AND (R/W = 0)) { PRIOR_ADDR_MATCH = FALSE; Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { Set UA = 1; Send ACK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match) { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0; Set RCV_MODE; } } } else if (High_byte_addr_match AND (R/W = 1) { if (PRIOR_ADDR_MATCH) { send ACK = 0; set XMIT_MODE; } else PRIOR_ADDR_MATCH = FALSE; } DS30444E - page 78 1997 Microchip Technology Inc. PIC16C9XX 12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has three registers. These registers are: * A/D Result Register (ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 (ADCON1) This section applies to the PIC16C924 only. The analog-to-digital (A/D) converter module has five inputs. The ADCON0 register, shown in Figure 12-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 12-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference) or as digital I/O. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's AVDD pin or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator. FIGURE 12-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an RC oscillation) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Reserved: Always maintain this bit clear bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current 1997 Microchip Technology Inc. DS30444E - page 79 PIC16C9XX FIGURE 12-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- PCFG2 PCFG1 PCFG0 bit7 bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF 000 A A A A A AVDD 001 A A A A VREF RA3 010 A A A A A AVDD 011 A A A A VREF RA3 100 A A D D A AVDD 111 D D D D D -- A = Analog input D = Digital I/O The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 12-3. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 12.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. 2. 3. 4. 5. Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result register (ADRES), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. Configure the A/D module: * Configure analog pins / voltage reference / and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit DS30444E - page 80 1997 Microchip Technology Inc. PIC16C9XX FIGURE 12-3: A/D BLOCK DIAGRAM CHS2:CHS0 100 VAIN 011 (Input voltage) RA5/AN4 RA3/AN3/VREF 010 RA2/AN2 A/D Converter 001 RA1/AN1 AVDD 000 RA0/AN0 000 or 010 or 100 VREF (Reference voltage) 001 or 011 PCFG2:PCFG0 1997 Microchip Technology Inc. DS30444E - page 81 PIC16C9XX 12.1 A/D Acquisition Requirements Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), (Figure 12-4). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 12-1 may be used. This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified accuracy. EQUATION 12-1: Note 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. Note 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. Note 4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel. EXAMPLE 12-1: CALCULATING THE MINIMUM REQUIRED SAMPLE TIME TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + A/D MINIMUM CHARGING TIME VHOLD = (VREF - (VREF/512)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) Temperature Coefficient TACQ = 5 s + Tc + [(Temp - 25C)(0.05 s/C)] TC = Given: VHOLD = (VREF/512), for 1/2 LSb resolution -CHOLD (RIC + RSS + RS) ln(1/511) The above equation reduces to: -51.2 pF (1 k + 7 k + 10 k) ln(0.0020) TC = -(51.2 pF)(1 k - RSS + RS) ln(1/511) -51.2 pF (18 k) ln(0.0020) Example 12-1 shows the calculation of the minimum required acquisition time (TACQ). This calculation is based on the following system assumptions. -0.921 s (-6.2364) CHOLD = 51.2 pF 5.747 s TACQ = 5 s + 5.747 s + [(50C - 25C)(0.05 s/C)] 10.747 s + 1.25 s Rs = 10 k 11.997 s 1/2 LSb error VDD = 5V Rss = 7 k Temp (system max.) = 50C VHOLD = 0 @ t = 0 FIGURE 12-4: ANALOG INPUT MODEL VDD Rs RAx CPIN 5 pF VA Sampling Switch VT = 0.6V VT = 0.6V RIC 1k SS RSS CHOLD = DAC capacitance = 51.2 pF I leakage 500 nA VSS Legend CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC SS CHOLD DS30444E - page 82 = interconnect resistance = sampling switch = sample/hold capacitance (from DAC) VDD 6V 5V 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch ( k ) 1997 Microchip Technology Inc. PIC16C9XX 12.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5 TAD per 8-bit conversion. The source of the A/D conversion clock is software selected. The four possible options for TAD are: * * * * 2TOSC 8TOSC 32TOSC Internal RC oscillator 12.3 Configuring Analog Port Pins The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 12-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. Note 1: When reading the port register, all pins configured as analog inputs will read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins), may cause the input buffer to consume current that is out of the devices specification. TABLE 12-1: TAD vs. DEVICE OPERATING FREQUENCIES A/D Clock Source (TAD) Operation ADCS1:ADCS0 Device Frequency 8 MHz 250 ns(2) 5 MHz 400 ns(2) 1.25 MHz 333.33 kHz 1.6 s 6 s 2TOSC 00 8TOSC 01 1 s 1.6 s 6.4 s 24 s(3) 32TOSC 10 4 s 6.4 s 25.6 s(3) 96 s(3) 11 2-6 2-6 2-6 2 - 6 s(1) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When derived frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep mode only 5: For extended voltage devices (LC), please refer to the electrical specifications section. RC Legend: Note 1: 2: 3: 4: 1997 Microchip Technology Inc. s(1,4) s(1,4) s(1,4) DS30444E - page 83 PIC16C9XX 12.4 A/D Conversions Example 12-2 show how to perform an A/D conversion. The RA pins are configured as analog inputs. The analog reference (VREF) is the device VDD. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the RA0 pin (channel0). Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, an acquisition is automatically started on the selected channel. EXAMPLE 12-2: DOING AN A/D CONVERSION BCF BSF CLRF BSF BCF MOVLW MOVWF BCF BSF BSF ; ; ; ; STATUS, STATUS, ADCON1 PIE1, STATUS, 0xC1 ADCON0 PIR1, INTCON, INTCON, RP1 RP0 ADIE RP0 ADIF PEIE GIE ; ; ; ; ; ; ; ; ; ; Select Bank1 Configure A/D inputs Enable A/D interrupts Select Bank0 RC Clock, A/D is on, Channel 0 is selected Clear A/D interrupt flag bit Enable peripheral interrupts Enable all interrupts Ensure that the required acquisition time for the selected input channel has elapsed. Then the conversion may be started. BSF : : ADCON0, GO DS30444E - page 84 ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion. 1997 Microchip Technology Inc. PIC16C9XX 12.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF Not all applications require a result with 8-bits of resolution, but may instead require a faster conversion time. The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same. To speed up the conversion, the clock source of the A/D module may be switched so that the TAD time violates the minimum specified time (see the applicable electrical specification). Once the TAD time violates the minimum specified time, all the following A/D result bits are not valid (see A/D Conversion Timing in the Electrical Specifications section.) The clock sources may only be switched between the three oscillator versions (cannot be switched from/to RC). The equation to determine the time before the oscillator can be switched is as follows: Since the TAD is based from the device oscillator, the user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be changed. Example 12-3 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. The example is for devices operating at 8 MHz (The A/D clock is programmed for 32TOSC), and assumes that immediately after 6TAD, the A/D clock is programmed for 2TOSC. The 2TOSC violates the minimum TAD time, therefore the last 4-bits will not be converted to correct values. Conversion time = 2TAD + N * TAD + (8 - N)(2TOSC) Where: N = number of bits of resolution required. EXAMPLE 12-3: 4-BIT vs. 8-BIT CONVERSION TIMES Resolution Freq. (MHz) 4-bit 8-bit TAD 8 1.6 s 1.6 s TOSC 8 12.5 ns 125 ns 2TAD + N * TAD + (8 - N)(2TOSC) 8 10.6 s 16 s 1997 Microchip Technology Inc. DS30444E - page 85 PIC16C9XX 12.5 A/D Operation During Sleep The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: 12.6 For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit. A/D Accuracy/Error The absolute accuracy specified for the A/D converter includes the sum of all contributions for quantization error, integral error, differential error, full scale error, offset error, and monotonicity. It is defined as the maximum deviation from an actual transition versus an ideal transition for any code. The absolute error of the A/D converter is specified at < 1 LSb for VDD = VREF (over the device's specified operating range). However, the accuracy of the A/D converter will degrade as VDD diverges from VREF. scale error is that full scale does not take offset error into account. Gain error can be calibrated out in software. Linearity error refers to the uniformity of the code changes. Linearity errors cannot be calibrated out of the system. Integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code. Differential non-linearity measures the maximum actual code width versus the ideal code width. This measure is unadjusted. The maximum pin leakage current is 1 A. In systems where the device frequency is low, use of the A/D RC clock is preferred. At moderate to high frequencies, TAD should be derived from the device oscillator. TAD must not violate the minimum and should be 8 s for preferred operation. This is because TAD, when derived from TOSC, is kept away from on-chip phase clock transitions. This reduces, to a large extent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be significant if many I/O pins are active. In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This method gives high accuracy. 12.7 Effects of a RESET A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRES register is not modified for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset. For a given range of analog inputs, the output digital code will be the same. This is due to the quantization of the analog input to a digital code. Quantization error is typically 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to increase the resolution of the A/D converter. Offset error measures the first actual transition of a code versus the first ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source impedance at the analog input. Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error. This error appears as a change in slope of the transfer function. The difference in gain error to full DS30444E - page 86 1997 Microchip Technology Inc. PIC16C9XX Use of the CCP Trigger An A/D conversion can be started by the "special event trigger" of the CCP1 module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter. 12.9 Connection Considerations 12.10 Transfer Function The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) is Analog VREF / 256 (Figure 12-5). FIGURE 12-5: A/D TRANSFER FUNCTION Digital code output 12.8 FFh FEh 04h 03h 02h 01h 1997 Microchip Technology Inc. 256 LSb (full scale) 4 LSb 3 LSb 2 LSb 255 LSb An external RC filter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 k recommended specification. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. 00h 0.5 LSb 1 LSb If the input voltage exceeds the rail values (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of specification. Analog input voltage DS30444E - page 87 PIC16C9XX FIGURE 12-6: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No Yes A/D Clock = RC? SLEEP Yes Instruction? Start of A/D Conversion Delayed 1 Instruction Cycle Finish Conversion GO = 0 ADIF = 1 No No Yes Device in SLEEP? Abort Conversion GO = 0 ADIF = 0 Wake-up Yes From Sleep? Finish Conversion GO = 0 ADIF = 1 Wait 2 TAD No No SLEEP Power-down A/D Finish Conversion GO = 0 ADIF = 1 Stay in Sleep Power-down A/D Wait 2 TAD Wait 2 TAD TABLE 12-2: SUMMARY OF A/D REGISTERS Address Name 0Bh, 8Bh, INTCON 10Bh, 18Bh 0Ch PIR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u LCDIF ADIF -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 ADIE -- -- SSPIE CCP1IE TMR2IE TMR1IE 8Ch PIE1 LCDIE 1Eh ADRES A/D Result Register 1Fh ADCON0 ADCS1 9Fh ADCS0 ADCON1 -- -- 05h PORTA -- -- 85h TRISA -- -- CHS2 CHS1 CHS0 GO/DONE (1) 00-- 0000 00-- 0000 xxxx xxxx uuuu uuuu ADON 0000 0000 0000 0000 ---- -000 -- -- -- PCFG2 PCFG1 PCFG0 ---- -000 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 PORTA Data Direction Control Register Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bit1 of ADCON0 is reserved, always maintain this bit clear. DS30444E - page 88 1997 Microchip Technology Inc. PIC16C9XX 13.0 LCD MODULE Once the module is initialized for the LCD panel, the individual bits of the LCD data registers are cleared/set to represent a clear/dark pixel respectively. The LCD module generates the timing control to drive a static or multiplexed LCD panel, with support for up to 32 segments multiplexed with up to 4 commons. It also provides control of the LCD pixel data. Once the module is configured, the LCDEN (LCDCON<7>) bit is used to enable or disable the LCD module. The LCD panel can also operate during sleep by clearing the SLPEN (LCDCON<6>) bit. The interface to the module consists of 3 control registers (LCDCON, LCDSE, and LCDPS) used to define the timing requirements of the LCD panel and up to 16 LCD data registers (LCD00-LCD15) that represent the array of the pixel data. In normal operation, the control registers are configured to match the LCD panel being used. Primarily, the initialization information consists of selecting the number of commons required by the LCD panel, and then specifying the LCD Frame clock rate to be used by the panel. Figure 13-4 through Figure 13-7 provides waveforms for Static, 1/2, 1/3, and 1/4 MUX drives. FIGURE 13-1: LCDCON REGISTER (ADDRESS 10Fh) R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDEN SLPEN -- VGEN CS1 CS0 LMUX1 LMUX0 bit7 bit0 R =Readable bit W =Writable bit U =Unimplemented bit, Read as `0' -n =Value at POR reset bit 7: LCDEN: Module drive enable bit 1 = LCD drive enabled 0 = LCD drive disabled bit 6: SLPEN: LCD display sleep enable 1 = LCD module will stop operating during SLEEP 0 = LCD module will continue to display during SLEEP bit 5: Unimplemented: Read as '0' bit 4: VGEN: Voltage Generator Enable 1 = Internal LCD Voltage Generator Enabled, (powered-up) 0 = Internal LCD Voltage Generator powered-down, voltage is expected to be provided externally bit 3-2: CS1:CS0: Clock Source Select bits 00 = Fosc/256 01 = T1CKI (Timer1) 1x = Internal RC oscillator bit 1-0: LMUX1:LMUX0: Common Selection bits Specifies the number of commons and the bias method LMUX1:LMUX0 00 01 10 11 MULTIPLEX BIAS Max # of Segments Static 1/2 1/3 1/4 Static 1/3 1/3 1/3 32 31 30 29 1997 Microchip Technology Inc. (COM0) (COM0, 1) (COM0, 1, 2) (COM0, 1, 2, 3) DS30444E - page 89 PIC16C9XX FIGURE 13-2: LCD MODULE BLOCK DIAGRAM 128 LCD RAM 32 x 4 Data Bus to SEG<31:0> TO I/O PADS 32 MUX Timing Control LCDCON COM3:COM0 LCDPS TO I/O PADS LCDSE Internal RC osc T1CKI Fosc/4 Clock Source Select and Divide FIGURE 13-3: LCDPS REGISTER (ADDRESS 10Eh) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- -- LP3 LP2 LP1 LP0 bit7 bit0 R =Readable bit W =Writable bit U =Unimplemented bit, Read as `0' -n =Value at POR reset bit 7-4: Unimplemented, read as '0' bit 3-0: LP3:LP0: Frame Clock Prescale Selection bits LMUX1:LMUX0 Multiplex Frame Frequency = 00 Static Clock source / (128 * (LP3:LP0 + 1)) 01 1/2 Clock source / (128 * (LP3:LP0 + 1)) 10 1/3 Clock source / (96 * 11 1/4 Clock source / (128 * (LP3:LP0 + 1)) DS30444E - page 90 (LP3:LP0 + 1)) 1997 Microchip Technology Inc. PIC16C9XX FIGURE 13-4: WAVEFORMS IN STATIC DRIVE V1 COM0 V0 COM0 V1 SEG0 V0 V1 SEG1 V0 V1 COM0-SEG0 V0 -V1 SEG1 SEG0 SEG2 SEG7 SEG6 SEG5 SEG4 SEG3 COM0-SEG1 1997 Microchip Technology Inc. V0 1 Frame DS30444E - page 91 PIC16C9XX FIGURE 13-5: WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 SEG3 SEG2 SEG1 SEG0 V0 V3 V2 SEG1 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 1 Frame -V2 -V3 DS30444E - page 92 1997 Microchip Technology Inc. PIC16C9XX FIGURE 13-6: WAVEFORMS IN 1/3 MUX, 1/3 BIAS V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 SEG0 V0 SEG0 SEG1 SEG2 V1 V3 V2 SEG1 V1 V0 V3 V2 V1 COM0-SEG0 V0 -V1 -V2 -V3 V3 V2 V1 COM0-SEG1 V0 -V1 -V2 -V3 1 Frame 1997 Microchip Technology Inc. DS30444E - page 93 PIC16C9XX FIGURE 13-7: WAVEFORMS IN 1/4 MUX, 1/3 BIAS COM3 COM2 COM0 V3 V2 V1 V0 COM1 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 1 Frame DS30444E - page 94 1997 Microchip Technology Inc. PIC16C9XX 13.1 LCD Timing The LCD module has 3 possible clock source inputs and supports static, 1/2, 1/3, and 1/4 multiplexing. 13.1.1 TIMING CLOCK SOURCE SELECTION The clock sources for the LCD timing generation are: * Internal RC oscillator * Timer1 oscillator * System clock divided by 256 The first timing source is an internal RC oscillator which runs at a nominal frequency of 14 kHz. This oscillator provides a lower speed clock which may be used to continue running the LCD while the processor is in sleep. The RC oscillator will power-down when it is not selected or when the LCD module is disabled. The second source is the Timer1 external oscillator. This oscillator provides a lower speed clock which may be used to continue running the LCD while the processor is in sleep. It is assumed that the frequency provided on this oscillator will be 32 kHz. To use the Timer1 oscillator as a LCD module clock source, it is only necessary to set the T1OSCEN (T1CON<3>) bit. The third source is the system clock divided by 256. This divider ratio is chosen to provide about 32 kHz output when the external oscillator is 8 MHz. The divider is not programmable. Instead the LCDPS register is used to set the LCD frame clock rate. All of the clock sources are selected with bits CS1:CS0 (LCDCON<3:2>). Refer to Figure 13-1 for details of the register programming. TMR1 32 kHz crystal oscillator /4 Static /2 1/2 4-bit Programmable Prescaler /32 COM3 COM2 /256 COM1 FOSC COM0 FIGURE 13-8: LCD CLOCK GENERATION /1,2,3,4 Ring Counter 1/3 1/4 Internal RC oscillator Nominal FRC = 14 kHz LCDPS<3:0> CS1:CS0 LMUX1:LMUX0 LMUX1:LMUX0 internal data bus 1997 Microchip Technology Inc. DS30444E - page 95 PIC16C9XX 13.1.2 MULTIPLEX TIMING GENERATION The timing generation circuitry will generate 1 to 4 common clocks based on the display mode selected. The mode is specified by bits LMUX1:LMUX0 (LCDCON<1:0>). Table 13-1 shows the formulas for calculating the frame frequency. TABLE 13-1: FRAME FREQUENCY FORMULAS Multiplex Frame Frequency = Static Clock source / (128 * (LP3:LP0 + 1)) 1/2 Clock source / (128 * (LP3:LP0 + 1)) 1/3 Clock source / (96 * (LP3:LP0 + 1)) 1/4 Clock source / (128 * (LP3:LP0 + 1)) DS30444E - page 96 TABLE 13-2: APPROX. FRAME FREQ IN Hz USING TIMER1 @ 32.768 kHz OR Fosc @ 8 MHz LP3:LP0 Static 1/2 1/3 1/4 2 85 85 114 85 3 64 64 85 64 4 51 51 68 51 5 43 43 57 43 6 37 37 49 37 7 32 32 43 32 TABLE 13-3: APPROX. FRAME FREQ IN Hz USING INTERNAL RC OSC @ 14 kHz LP3:LP0 Static 1/2 1/3 1/4 0 109 109 146 109 1 55 55 73 55 2 36 36 49 36 3 27 27 36 27 1997 Microchip Technology Inc. PIC16C9XX 13.2 LCD Interrupts The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Writing pixel data at the frame boundary allows a visually crisp transition of the image. This interrupt can also be used to synchronize external events to the LCD. For example, the interface to an external segment driver, such as a Microchip AY0438, can be synchronized for segment data update to the LCD frame. A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a certain fixed time before the frame boundary as shown in Figure 13-9. The LCD controller will begin to access data for the next frame within TFWR after the interrupt. FIGURE 13-9: EXAMPLE WAVEFORMS IN 1/4 MUX DRIVE LCD Interrupt occurs Controller accesses next frame data V3 V2 V1 V0 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 1 Frame TFINT Frame Boundary TFWR Frame Boundary TFWR = TFRAME/(LMUX1:LMUX0 + 1) TFINT = (TFWR /2 - (2TCY + 40 ns)) min. (TFWR /2 - (1TCY + 40 ns)) max. 1997 Microchip Technology Inc. DS30444E - page 97 PIC16C9XX 13.3 Pixel Control 13.3.1 LCDD (PIXEL DATA) REGISTERS Table 13-4 shows the correlation of each bit in the LCDD registers to the respective common and segment signals. The pixel registers contain bits which define the state of each pixel. Each bit defines one unique pixel. Any LCD pixel location not being used for display can be used as general purpose RAM. FIGURE 13-10:GENERIC LCDD REGISTER LAYOUT R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEGs COMc SEGs COMc SEGs COMc SEGs COMc SEGs COMc SEGs COMc SEGs COMc SEGs COMc bit7 bit0 R =Readable bit W =Writable bit U =Unimplemented bit, Read as `0' -n =Value at POR reset bit 7-0: SEGsCOMc: Pixel Data Bit for segment s and common c 1 = Pixel on (dark) 0 = Pixel off (clear) DS30444E - page 98 1997 Microchip Technology Inc. PIC16C9XX 13.4 Operation During Sleep The LCD module can operate during sleep. The selection is controlled by bit SLPEN (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to sleep. Clearing the SLPEN bit allows the module to continue to operate during sleep. If a SLEEP instruction is executed and SLPEN = '1', the LCD module will cease all functions and go into a very low current consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines. Figure 13-11 shows this operation. To ensure that the LCD completes the frame, the SLEEP instruction should be executed immediately after a LCD frame boundary. The LCD interrupt can be used to determine the frame boundary. See Section 13.2 for the formulas to calculate the delay. If a SLEEP instruction is executed and SLPEN = '0', the module will continue to display the current contents of the LCDD registers. To allow the module to continue operation while in sleep, the clock source must be either the internal RC oscillator or Timer1 external oscillator. While in sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode, however the overall consumption of the device will be lower due to shutdown of the core and other peripheral functions. Note: The internal RC oscillator or external Timer1 oscillator must be used to operate the LCD module during sleep. FIGURE 13-11:SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS1:CS0 = 00 3/3V Pin COM0 2/3V 1/3V 0/3V 3/3V Pin COM1 2/3V 1/3V 0/3V 3/3V 2/3V Pin COM3 1/3V 0/3V 3/3V 2/3V Pin SEG0 1/3V 0/3V interrupted frame SLEEP instruction execution 1997 Microchip Technology Inc. Wake-up DS30444E - page 99 PIC16C9XX 13.4.1 EXAMPLE 13-1: STATIC MUX WITH 32 SEGMENTS SEGMENT ENABLES The LCDSE register is used to select the pin function for groups of pins. The selection allows each group of pins to operate as either LCD drivers or digital only pins. To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. BCF BSF BCF BCF MOVLW MOVWF . . . If the pin is a digital I/O the corresponding TRIS bit controls the data direction. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register. STATUS,RP0 STATUS,RP1 LCDCON,LMUX1 LCDCON,LMUX0 0xFF LCDSE ;Select Bank 2 ; ;Select Static MUX ; ;Make PortD,E,F,G ;LCD pins ;configure rest of LCD EXAMPLE 13-2: 1/3 MUX WITH 13 SEGMENTS Note 1: On a Power-on Reset these pins are configured as LCD drivers. BCF BSF BSF BCF MOVLW MOVWF . . . Note 2: The LMUX1:LMUX0 takes precedence over the LCDSE bit settings for pins RD7, RD6 and RD5. STATUS,RP0 STATUS,RP1 LCDCON,LMUX1 LCDCON,LMUX0 0x87 LCDSE ;Select Bank 2 ; ;Select 1/3 MUX ; ;Make PORTD<7:0> & ;PORTE<6:0> LCD pins ;configure rest of LCD FIGURE 13-12:LCDSE REGISTER (ADDRESS 10Dh) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 bit7 bit0 bit 7: SE29: Pin function select RD7/COM1/SEG31 - RD5/COM3/SEG29 1 = pins have LCD drive function 0 = pins have digital Input function The LMUX1:LMUX0 setting takes precedence over the LCDSE register. bit 6: SE27: Pin function select RG7/SEG28 and RE7/SEG27 1 = pins have LCD drive function 0 = pins have digital Input function bit 5: SE20: Pin function select RG6/SEG26 - RG0/SEG20 1 = pins have LCD drive function 0 = pins have digital Input function bit 4: SE16: Pin function select RF7/SEG19 - RF4/SEG16 1 = pins have LCD drive function 0 = pins have digital Input function bit 3: SE12: Pin function select RF3/SEG15 - RF0/SEG12 1 = pins have LCD drive function 0 = pins have digital Input function bit 2: SE9: Pin function select RE6/SEG11 - RE4/SEG09 1 = pins have LCD drive function 0 = pins have digital Input function bit 1: SE5: Pin function select RE3/SEG08 - RE0/SEG05 1 = pins have LCD drive function 0 = pins have digital Input function bit 0: SE0: Pin function select RD4/SEG04 - RD0/SEG00 1 = pins have LCD drive function 0 = pins have digital I/O function DS30444E - page 100 R =Readable bit W =Writable bit U =Unimplemented bit, Read as `0' -n =Value at POR reset 1997 Microchip Technology Inc. PIC16C9XX 13.5 Voltage Generation There are two methods for LCD voltage generation, internal charge pump, or external resistor ladder. 2*VLCD1 and VLCD3 = 3 * VLCD1. When the charge pump is not operating, Vlcd3 will be internally tied to VDD. See the Electrical Specifications section for charge pump capacitor and potentiometer values. 13.5.1 13.5.2 CHARGE PUMP The LCD charge pump is shown in Figure 13-13. The 1.0V - 2.3V regulator will establish a stable base voltage from the varying battery voltage. This regulator is adjustable through the range by connecting a variable external resistor from VLCDADJ to ground. The potentiometer provides contrast adjustment for the LCD. This base voltage is connected to VLCD1 on the charge pump. The charge pump boosts VLCD1 into VLCD2 = EXTERNAL R-LADDER The LCD module can also use an external resistor ladder (R-Ladder) to generate the LCD voltages. Figure 13-13 shows external connections for static and 1/3 bias. The VGEN (LCDCON<4>) bit must be cleared to use an external R-Ladder. FIGURE 13-13:CHARGE PUMP AND RESISTOR LADDER VDD 10 A nominal LCDEN Charge Pump VLCD3 VLCDADJ 100k* 0.47 F* VLCD2 0.47 F* VLCD1 C1 10k* C2 0.47 F* 130k* 10k* SLPEN 10k* VDD 10k* VDD 0.47 F* Connections for internal charge pump, VGEN = 1 5k* Connections for external R-ladder, 1/3 Bias, VGEN = 0 5k* Connections for external R-ladder, Static Bias, VGEN = 0 * These values are provided for design guidance only and should be optimized to the application by the designer. 1997 Microchip Technology Inc. DS30444E - page 101 PIC16C9XX 13.6 Configuring the LCD Module The following is the sequence of steps to follow to configure the LCD module. 1. Select the frame clock prescale using bits LP3:LP0 (LCDPS<3:0>). 2. Configure the appropriate pins to function as segment drivers using the LCDSE register. 3. Configure the LCD module for the following using the LCDCON register. - Multiplex mode and Bias, bits LMUX1:LMUX0 - Timing source, bits CS1:CS0 - Voltage generation, bit VGEN - Sleep mode, bit SLPEN 4. Write initial values to pixel data registers, LCDD00 through LCDD15. 5. Clear LCD interrupt flag, LCDIF (PIR1<7>), and if desired, enable the interrupt by setting bit LCDIE (PIE1<7>). 6. Enable the LCD module, by setting bit LCDEN (LCDCON<7>). TABLE 13-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE LCD MODULE Address Name 0Bh, 8Bh, 10Bh, 18Bh INTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other Resets GIE PEIE RBIE T0IF INTF RBIF 0000 000x 0000 000u 00-- 0000 T0IE INTE (1) 0Ch PIR1 LCDIF ADIF -- -- SSPIF CCP1IF TMR2IF TMR1IF 00-- 0000 8Ch PIE1 LCDIE ADIE(1) -- -- SSPIE CCP1IE TMR2IE TMR1IE 00-- 0000 00-- 0000 10h T1CON -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 10Dh LCDSE SE29 SE27 SE20 SE16 SE12 SE9 SE5 SE0 1111 1111 1111 1111 10Eh LCDPS -- -- -- -- LP3 LP2 LP1 LP0 ---- 0000 ---- 0000 10Fh LCDCON LCDEN SLPEN -- VGEN CS1 CS0 LMUX1 LMUX0 00-0 0000 00-0 0000 110h LCDD00 SEG07 COM0 SEG06 COM0 SEG05 COM0 SEG04 COM0 SEG03 COM0 SEG02 COM0 SEG01 COM0 SEG00 COM0 xxxx xxxx uuuu uuuu 111h LCDD01 SEG15 COM0 SEG14 COM0 SEG13 COM0 SEG12 COM0 SEG11 COM0 SEG10 COM0 SEG09 COM0 SEG08 COM0 xxxx xxxx uuuu uuuu 112h LCDD02 SEG23 COM0 SEG22 COM0 SEG21 COM0 SEG20 COM0 SEG19 COM0 SEG18 COM0 SEG17 COM0 SEG16 COM0 xxxx xxxx uuuu uuuu 113h LCDD03 SEG31 COM0 SEG30 COM0 SEG29 COM0 SEG28 COM0 SEG27 COM0 SEG26 COM0 SEG25 COM0 SEG24 COM0 xxxx xxxx uuuu uuuu 114h LCDD04 SEG07 COM1 SEG06 COM1 SEG05 COM1 SEG04 COM1 SEG03 COM1 SEG02 COM1 SEG01 COM1 SEG00 COM1 xxxx xxxx uuuu uuuu 115h LCDD05 SEG15 COM1 SEG14 COM1 SEG13 COM1 SEG12 COM1 SEG11 COM1 SEG10 COM1 SEG09 COM1 SEG08 COM1 xxxx xxxx uuuu uuuu 116h LCDD06 SEG23 COM1 SEG22 COM1 SEG21 COM1 SEG20 COM1 SEG19 COM1 SEG18 COM1 SEG17 COM1 SEG16 COM1 xxxx xxxx uuuu uuuu 117h LCDD07 SEG31 COM1(2) SEG30 COM1 SEG29 COM1 SEG28 COM1 SEG27 COM1 SEG26 COM1 SEG25 COM1 SEG24 COM1 xxxx xxxx uuuu uuuu 118h LCDD08 SEG07 COM2 SEG06 COM2 SEG05 COM2 SEG04 COM2 SEG03 COM2 SEG02 COM2 SEG01 COM2 SEG00 COM2 xxxx xxxx uuuu uuuu 119h LCDD09 SEG15 COM2 SEG14 COM2 SEG13 COM2 SEG12 COM2 SEG11 COM2 SEG10 COM2 SEG09 COM2 SEG08 COM2 xxxx xxxx uuuu uuuu 11Ah LCDD10 SEG23 COM2 SEG22 COM2 SEG21 COM2 SEG20 COM2 SEG19 COM2 SEG18 COM2 SEG17 COM2 SEG16 COM2 xxxx xxxx uuuu uuuu 11Bh LCDD11 SEG31 COM2(2) SEG30 COM2(2) SEG29 COM2 SEG28 COM2 SEG27 COM2 SEG26 COM2 SEG25 COM2 SEG24 COM2 xxxx xxxx uuuu uuuu 11Ch LCDD12 SEG07 COM3 SEG06 COM3 SEG05 COM3 SEG04 COM3 SEG03 COM3 SEG02 COM3 SEG01 COM3 SEG00 COM3 xxxx xxxx uuuu uuuu 11Dh LCDD13 SEG15 COM3 SEG14 COM3 SEG13 COM3 SEG12 COM3 SEG11 COM3 SEG10 COM3 SEG09 COM3 SEG08 COM3 xxxx xxxx uuuu uuuu 11Eh LCDD14 SEG23 COM3 SEG22 COM3 SEG21 COM3 SEG20 COM3 SEG19 COM3 SEG18 COM3 SEG17 COM3 SEG16 COM3 xxxx xxxx uuuu uuuu 11Fh LCDD15 SEG31 COM3(2) SEG30 COM3(2) SEG29 COM3(2) SEG28 COM3 SEG27 COM3 SEG26 COM3 SEG25 COM3 SEG24 COM3 xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the LCD Module. Note 1: These bits are reserved on the PIC16C923, always maintain these bits clear. 2: These pixels do not display, but can be used as general purpose RAM. DS30444E - page 102 1997 Microchip Technology Inc. PIC16C9XX 14.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16CXXX family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code protection * ID locations * In-circuit serial programming the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry. SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options. 14.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. The PIC16CXXX has a Watchdog Timer which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming. FIGURE 14-1: CONFIGURATION WORD CP1 CP0 CP1 CP0 CP1 CP0 -- -- CP1 bit13 CP0 PWRTE WDTE FOSC1 FOSC0 bit0 Register: Address CONFIG 2007h bit 13-8 CP1:CP0 Code protection bits (1) 5-4: 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4 of program memory code protected 00 = All memory is code protected bit 6: Unimplemented: Read as '1' bit 3: PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: All of the CP1:CP0 bits have to be given the same value to enable the code protection scheme listed. 1997 Microchip Technology Inc. DS30444E - page 103 PIC16C9XX 14.2 Oscillator Configurations 14.2.1 OSCILLATOR TYPES TABLE 14-1: CERAMIC RESONATORS Ranges Tested: The PIC16CXXX can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC 14.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor CRYSTAL OSCILLATOR/CERAMIC RESONATORS In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 14-2). The PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 14-3). Mode XT 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz HS 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz XTAL RF SLEEP C2 Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT 0.3% 0.5% 0.5% 0.5% TABLE 14-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Osc Type XT Crystal Freq Cap. Range C1 Cap. Range C2 33 pF 32 kHz 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes at bottom of page. Crystals Used OSC2 RS Note1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF All resonators used did not have built-in capacitors. OSC1 To internal logic 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF OSC2 Resonators Used: HS C1 OSC1 These values are for design guidance only. See notes at bottom of page. LP FIGURE 14-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) Freq PIC16CXXX See Table 14-1 and Table 14-2 for recommended values of C1 and C2. 32 kHz Epson C-001R32.768K-A 20 PPM 200 kHz STD XTL 200.000KHz 20 PPM 1 MHz ECS ECS-10-13-1 50 PPM 4 MHz ECS ECS-40-20-1 50 PPM 8 MHz EPSON CA-301 8.000M-C 30 PPM Note 1: A series resistor may be required for AT strip cut crystals. FIGURE 14-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 Clock from ext. system PIC16CXXX Open DS30444E - page 104 OSC2 Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 14-1). 2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. 1997 Microchip Technology Inc. PIC16C9XX 14.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance. Figure 14-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs. FIGURE 14-4: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices 10k 74AS04 4.7k 74AS04 PIC16CXXX CLKIN 10k XTAL 14.2.4 RC OSCILLATOR For timing insensitive applications the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 14-6 shows how the R/C combination is connected to the PIC16CXXX. For REXT values below 2.2 k, the oscillator operation may become unstable, or stop completely. For very high REXT values (e.g. 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 k and 100 k. Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). 10k 20 pF See characterization data for desired device for variation of oscillator frequency due to VDD for given REXT/CEXT values as well as frequency variation due to operating temperature for given R, C, and VDD values. 20 pF Figure 14-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 k resistors provide the negative feedback to bias the inverters in their linear region. The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-3 for waveform). FIGURE 14-6: RC OSCILLATOR MODE FIGURE 14-5: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT V DD REXT Internal clock OSC1 330 k 330 k 74AS04 74AS04 To Other Devices CEXT 74AS04 PIC16CXXX VSS CLKIN 0.1 F Fosc/4 OSC2/CLKOUT XTAL PIC16CXXX 1997 Microchip Technology Inc. DS30444E - page 105 PIC16C9XX 14.3 Reset The PIC16CXX differentiates between various kinds of reset: * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) the resumption of normal operation. The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 14-4. These bits are used in software to determine the nature of the reset. See Table 14-6 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 14-7. Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a "reset state" on Power-on Reset (POR), on the MCLR and WDT Reset, and on MCLR Reset during SLEEP. They are not affected by a WDT Wake-up, which is viewed as The devices all have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. FIGURE 14-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time-out VDD rise detect Power-on Reset VDD S OST/PWRT OST Chip_Reset R 10-bit Ripple counter Q OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter Enable PWRT(2) Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: See Table 14-3 for time-out situations. DS30444E - page 106 1997 Microchip Technology Inc. PIC16C9XX 14.4 14.4.1 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) 14.4.3 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP. 14.4.4 TIME-OUT SEQUENCE On power-up the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 14-8, Figure 14-9, and Figure 14-10 depict time-out sequences on power-up. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting." 14.4.2 OSCILLATOR START-UP TIMER (OST) Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 14-9). This is useful for testing purposes or to synchronize more than one PIC16CXXX device operating in parallel. POWER-UP TIMER (PWRT) The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. Table 14-5 shows the reset conditions for some special function registers, while Table 14-6 shows the reset conditions for all the registers. 14.4.5 The power-up time delay will vary from chip to chip due to VDD, temperature, and process variation. See DC parameters for details. POWER CONTROL/STATUS REGISTER (PCON) Bit1 is Power-on Reset Status bit POR. It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. TABLE 14-3: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration Power-up Wake-up from SLEEP PWRTE = 1 PWRTE = 0 XT, HS, LP 1024TOSC 72 ms + 1024TOSC 1024 TOSC RC -- 72 ms -- 1997 Microchip Technology Inc. DS30444E - page 107 PIC16C9XX TABLE 14-4: STATUS BITS AND THEIR SIGNIFICANCE POR TO PD 0 1 1 Power-on Reset 0 0 x Illegal, TO is set on POR 0 x 0 Illegal, PD is set on POR 1 0 1 WDT Reset 1 0 0 WDT Wake-up 1 u u MCLR Reset during normal operation 1 1 0 Legend: u = unchanged, x = unknown MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 14-5: RESET CONDITION FOR SPECIAL REGISTERS Program Counter Condition STATUS Register Register PCON Power-on Reset 000h 0001 1xxx ---- --0- MCLR Reset during normal operation 000h 000u uuuu ---- --u- MCLR Reset during SLEEP 000h 0001 0uuu ---- --u- WDT Reset 000h 0000 1uuu ---- --u- WDT Wake-up PC + 1 uuu0 0uuu ---- --u- Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u- Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt W 923 924 xxxx xxxx uuuu uuuu uuuu uuuu INDF 923 924 N/A N/A N/A TMR0 923 924 xxxx xxxx uuuu uuuu uuuu uuuu PCL 923 924 0000h 0000h PC + 1(2) STATUS 923 924 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 923 924 xxxx xxxx uuuu uuuu uuuu uuuu PORTA 923 924 --xx xxxx --uu uuuu --uu uuuu 0000(5) 0000(5) PORTA 923 924 PORTB 923 924 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 923 924 --xx xxxx --uu uuuu --uu uuuu --0x --0u --uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-5 for reset value for specific condition. 4: Bits PIE1<6> and PIR1<6> are reserved on the PIC16C923, always maintain these bits clear. 5: PORTA values when read. DS30444E - page 108 1997 Microchip Technology Inc. PIC16C9XX TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d) Register Applicable Devices Power-on Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt PORTD 923 924 0000 0000 0000 0000 uuuu uuuu PORTE 923 924 0000 0000 0000 0000 uuuu uuuu PCLATH 923 924 ---0 0000 ---0 0000 ---u uuuu INTCON 923 924 0000 000x 0000 000u uuuu uuuu(1) PIR1(4) 923 924 00-- 0000 00-- 0000 uu-- uuuu(1) TMR1L 923 924 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 923 924 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 923 924 --00 0000 --uu uuuu --uu uuuu TMR2 923 924 0000 0000 0000 0000 uuuu uuuu T2CON 923 924 -000 0000 -000 0000 -uuu uuuu SSPBUF 923 924 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 923 924 0000 0000 0000 0000 uuuu uuuu CCPR1L 923 924 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 923 924 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 923 924 --00 0000 --00 0000 --uu uuuu ADRES 923 924 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 923 924 0000 00-0 0000 00-0 uuuu uu-u OPTION 923 924 1111 1111 1111 1111 uuuu uuuu TRISA 923 924 --11 1111 --11 1111 --uu uuuu TRISB 923 924 1111 1111 1111 1111 uuuu uuuu TRISC 923 924 --11 1111 --11 1111 --uu uuuu TRISD 923 924 1111 1111 1111 1111 uuuu uuuu TRISE 923 924 1111 1111 1111 1111 uuuu uuuu (4) 923 924 00-- 0000 00-- 0000 uu-- uuuu PCON 923 924 ---- --0- ---- --u- ---- --u- PR2 923 924 1111 1111 1111 1111 1111 1111 SSPADD 923 924 0000 0000 0000 0000 uuuu uuuu SSPSTAT 923 924 0000 0000 0000 0000 uuuu uuuu ADCON1 923 924 ---- -000 ---- -000 ---- -uuu PORTF 923 924 0000 0000 0000 0000 uuuu uuuu PORTG 923 924 0000 0000 0000 0000 uuuu uuuu PIE1 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-5 for reset value for specific condition. 4: Bits PIE1<6> and PIR1<6> are reserved on the PIC16C923, always maintain these bits clear. 5: PORTA values when read. 1997 Microchip Technology Inc. DS30444E - page 109 PIC16C9XX TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.'d) Register Applicable Devices Power-on Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt LCDSE 923 924 1111 1111 1111 1111 uuuu uuuu LCDPS 923 924 ---- 0000 ---- 0000 ---- uuuu LCDCON 923 924 00-0 0000 00-0 0000 uu-u uuuu LCDD00 to LCDD15 923 924 xxxx xxxx uuuu uuuu uuuu uuuu TRISF 923 924 1111 1111 1111 1111 uuuu uuuu TRISG 923 924 1111 1111 1111 1111 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-5 for reset value for specific condition. 4: Bits PIE1<6> and PIR1<6> are reserved on the PIC16C923, always maintain these bits clear. 5: PORTA values when read. DS30444E - page 110 1997 Microchip Technology Inc. PIC16C9XX FIGURE 14-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 14-10:TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1997 Microchip Technology Inc. DS30444E - page 111 PIC16C9XX FIGURE 14-11:EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 14-12:EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD D VDD 33k VDD 10k R R1 40k MCLR C MCLR PIC16CXXX PIC16CXXX Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. Note 1: This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Resistors should be adjusted for the characteristics of the transistors. 2: R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). FIGURE 14-13:EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 Q1 MCLR R2 40k PIC16CXXX Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 = 0.7V VDD * R1 + R2 2: Resistors should be adjusted for the characteristics of the transistors. DS30444E - page 112 1997 Microchip Technology Inc. PIC16C9XX 14.5 Interrupts The PIC16C9XX family has up to 9 sources of interrupt: Interrupt Sources Applicable Devices External interrupt RB0/INT 923 924 TMR0 overflow interrupt 923 924 PORTB change interrupts (pins RB7:RB4) 923 924 A/D Interrupt 923 924 TMR1 overflow interrupt 923 924 TMR2 matches period interrupt 923 924 CCP1 interrupt 923 924 Synchronous serial port interrupt 923 924 LCD Module interrupt 923 924 The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the special function register PIR1. The corresponding interrupt enable bits are contained in special function register PIE1, and the peripheral interrupt enable bit is contained in special function register INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupts, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the RB0/INT pin or RB Port change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 14-15). The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. 1997 Microchip Technology Inc. DS30444E - page 113 PIC16C9XX FIGURE 14-14:INTERRUPT LOGIC TMR1IF TMR1IE Wake-up (If in SLEEP mode) T0IF T0IE INTF INTE TMR2IF TMR2IE Interrupt to CPU RBIF RBIE LCDIF LCDIE PEIF PEIE GIE CCP1IF CCP1IE SSPIF SSPIE ADIF ADIE The A/D module interrupt is implemented on the PIC16C924 only. FIGURE 14-15:INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag (INTCON<1>) Interrupt Latency 2 5 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) 0004h PC+1 -- Dummy Cycle 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF can be set anytime during the Q4-Q1 cycles. DS30444E - page 114 1997 Microchip Technology Inc. PIC16C9XX 14.5.1 14.6 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 14.8 for details on SLEEP mode. 14.5.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 7.0) 14.5.3 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 14-1 stores and restores the STATUS, W, and PCLATH registers. The register, W_TEMP, must be defined in each bank and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 0x20 in bank 0, it must also be defined at 0xA0 in bank 1). The example: a) b) c) d) e) f) Stores the W register. Stores the STATUS register in bank 0. Stores the PCLATH register. Executes the ISR code. Restores the STATUS register (and bank select bit). Restores the W and PCLATH registers. PORTB INTCON CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 5.2) EXAMPLE 14-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF BCF MOVF MOVWF : :(ISR) : MOVF MOVWF SWAPF W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH STATUS, IRP FSR, W FSR_TEMP ;Copy W to TEMP register, could be bank one or zero ;Swap status to be saved into W ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 ;Save status to bank zero STATUS_TEMP register ;Only required if using pages 1, 2 and/or 3 ;Save PCLATH into W ;Page zero, regardless of current page ;Return to Bank 0 ;Copy FSR to W ;Copy FSR from W to FSR_TEMP PCLATH_TEMP, W PCLATH STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W 1997 Microchip Technology Inc. DS30444E - page 115 PIC16C9XX 14.7 Watchdog Timer (WDT) assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently disabled by clearing configuration bit WDTE (Section 14.1). 14.7.1 The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. 14.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., and max. WDT prescaler) it may take several seconds before a WDT time-out occurs. WDT PERIOD Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. The WDT has a nominal time-out period of 18 ms, (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be FIGURE 14-16:WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 7-6) 0 WDT Timer Postscaler M U X 1 8 8 - to - 1 MUX PS2:PS0 PSA WDT Enable Bit To TMR0 (Figure 7-6) 0 1 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION register. FIGURE 14-17:SUMMARY OF WATCHDOG TIMER REGISTERS Address Name 2007h Config. bits 81h, 181h OPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (1) (1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 14-1 for operation of these bits. DS30444E - page 116 1997 Microchip Technology Inc. PIC16C9XX 14.8 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). 14.8.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of the following events: 1. 2. 3. External reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from RB0/INT pin, RB port change, or some peripheral interrupts. Other peripherals can not generate interrupts since during SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 14.8.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. External MCLR Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device reset. The PD bit, which is set on power-up is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. The following peripheral interrupts can wake the device from SLEEP: To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 1. 2. 3. 4. 5. 6. 7. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in slave mode (SPI/I2C). CCP capture mode interrupt. A/D conversion (when A/D clock source is RC). Special event trigger (Timer1 in asynchronous mode using an external clock). LCD module. 1997 Microchip Technology Inc. DS30444E - page 117 PIC16C9XX FIGURE 14-18:WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 14.9 1: 2: 3: 4: PC+1 PC+2 Inst(PC + 2) SLEEP Inst(PC + 1) 14.10 Program Verification/Code Protection Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID location are used. 14.11 PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) XT, HS or LP oscillator mode assumed. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference. If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: PC+2 Inst(PC + 1) In-Circuit Serial Programming PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. DS30444E - page 118 After reset, to place the device into program/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228). FIGURE 14-19:TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION External Connector Signals To Normal Connections PIC16CXXX +5V VDD 0V VSS VPP MCLR/VPP CLK RB6 Data I/O RB7 VDD To Normal Connections 1997 Microchip Technology Inc. PIC16C9XX 15.0 INSTRUCTION SET SUMMARY Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. For literal and control operations, 'k' represents an eight or eleven bit constant or literal value. The instruction set is highly orthogonal and is grouped into three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations FIGURE 15-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 0 b = 3-bit bit address f = 7-bit file register address General 8 7 OPCODE Description f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 label Label name TOS Top of Stack PC Program Counter PCLATH Program Counter High Latch GIE Global Interrupt Enable bit WDT Watchdog Timer/Counter TO Time-out bit PD Power-down bit dest Destination either the W register or the specified register file location [ ] Options ( ) Contents Assigned to <> Register bit field In the set of italics User defined term (font is courier) All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Table 15-2 lists the instructions recognized by the MPASM assembler. Literal and control operations 13 Field d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) TABLE 15-1: OPCODE FIELD DESCRIPTIONS 0 Figure 15-1 shows the general formats that the instructions can have. Note: k (literal) k = 8-bit immediate value All examples use the following format to represent a hexadecimal number: CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value 1997 Microchip Technology Inc. To maintain upward compatibility with future PIC16CXXX products, do not use the OPTION and TRIS instructions. 0xhh where h signifies a hexadecimal digit. DS30444E - page 119 PIC16C9XX TABLE 15-2: PIC16CXXX INSTRUCTION SET Mnemonic, Operands Description 14-Bit Opcode Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C,DC,Z Z Z Z Z Z Z Z Z C C C,DC,Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1,2 1,2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W C,DC,Z Z TO,PD Z TO,PD C,DC,Z Z 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30444E - page 120 1997 Microchip Technology Inc. PIC16C9XX 15.1 Instruction Descriptions ADDLW Add Literal and W ADDWF Add W and f Syntax: [label] ADDLW Syntax: [label] ADDWF Operands: 0 k 255 Operands: Operation: (W) + k (W) 0 f 127 d [0,1] Status Affected: C, DC, Z Operation: (W) + (f) (destination) Status Affected: C, DC, Z 11 Encoding: Description: 1 Cycles: 1 Example: kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. Words: Q Cycle Activity: 111x k Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W ADDLW 00 Encoding: f,d 0111 dfff ffff Description: Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination ADDWF FSR, 0 0x15 Before Instruction W = 0x10 After Instruction W = 0x25 Example Before Instruction W = FSR = 0x17 0xC2 After Instruction W = FSR = 1997 Microchip Technology Inc. 0xD9 0xC2 DS30444E - page 121 PIC16C9XX ANDLW AND Literal with W ANDWF AND W with f Syntax: [label] ANDLW Syntax: [label] ANDWF Operands: 0 k 255 Operands: Operation: (W) .AND. (k) (W) 0 f 127 d [0,1] Operation: (W) .AND. (f) (destination) Status Affected: Z Status Affected: Z 11 Encoding: 1001 k kkkk kkkk 00 Encoding: Description: The contents of W register are AND'ed with the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal "k" Process data Write to W ANDLW Example 0xA3 = ffff Words: 1 Cycles: 1 Q Cycle Activity: Example After Instruction W dfff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Before Instruction = 0101 Description: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination ANDWF FSR, 1 0x5F W f,d Before Instruction 0x03 W = FSR = 0x17 0xC2 After Instruction W = FSR = BCF Bit Clear f Syntax: [label] BCF Operands: 0 f 127 0b7 Operation: 0 (f<b>) Status Affected: None 01 Encoding: 0x17 0x02 f,b 00bb bfff Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Q Cycle Activity: Example ffff Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' BCF FLAG_REG, 7 Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 DS30444E - page 122 1997 Microchip Technology Inc. PIC16C9XX BTFSC Bit Test, Skip if Clear Syntax: [label] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operation: 1 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None BSF Bit Set f Syntax: [label] BSF Operands: 01 Encoding: f,b 01bb bfff Description: Bit 'b' in register 'f' is set. Words: 1 Cycles: 1 Q Cycle Activity: ffff Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' Encoding: BSF FLAG_REG, 10bb bfff ffff Description: If bit 'b' in register 'f' is '1' then the next instruction is executed. If bit 'b', in register 'f', is '0' then the next instruction is discarded, and a NOP is executed instead, making this a 2TCY instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: Example 01 Q1 Q2 Q3 Q4 Decode Read register 'f' Process data NoOperation Q3 Q4 7 Before Instruction FLAG_REG = 0x0A If Skip: After Instruction FLAG_REG = 0x8A Example (2nd Cycle) Q1 Q2 NoOperation NoOperation HERE FALSE TRUE BTFSC GOTO * * * NoNoOperation Operation FLAG,1 PROCESS_CODE Before Instruction PC = address HERE After Instruction if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE 1997 Microchip Technology Inc. DS30444E - page 123 PIC16C9XX BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 f 127 0b<7 Operands: 0 k 2047 Operation: Operation: skip if (f<b>) = 1 Status Affected: None (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None 01 Encoding: Description: bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Skip: 11bb Q1 Q2 Q3 Q4 Decode Read register 'f' Process data NoOperation Example Q1 Q2 NoOperation NoOperation HERE FALSE TRUE BTFSC GOTO * * * Q3 FLAG,1 PROCESS_CODE kkkk Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k', Push PC to Stack Process data Write to PC 2nd Cycle Example NoNoNoNoOperation Operation Operation Operation HERE CALL THERE Before Instruction PC = Address HERE After Instruction Before Instruction PC = kkkk Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two cycle instruction. Q4 NoNoOperation Operation 0kkk Description: 1st Cycle (2nd Cycle) 10 Encoding: address HERE PC = Address THERE TOS = Address HERE+1 After Instruction if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE DS30444E - page 124 1997 Microchip Technology Inc. PIC16C9XX CLRF Clear f Syntax: [label] CLRF Operands: 0 f 127 Operation: 00h (f) 1Z Status Affected: Z 00 Encoding: f 0001 1fff ffff CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1Z Status Affected: Z 00 Encoding: 0001 0xxx xxxx Description: The contents of register 'f' are cleared and the Z bit is set. Description: W register is cleared. Zero bit (Z) is set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' CLRF Example FLAG_REG = 0x5A = = 0x00 1 After Instruction FLAG_REG Z 1997 Microchip Technology Inc. Q1 Q2 Q3 Q4 Decode NoOperation Process data Write to W CLRW Before Instruction Before Instruction FLAG_REG Q Cycle Activity: W = 0x5A After Instruction W Z = = 0x00 1 DS30444E - page 125 PIC16C9XX CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: 00 Description: 0000 0110 1 Cycles: 1 Q Cycle Activity: Syntax: [ label ] COMF Operands: 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z 00 Q1 Q2 Q3 Q4 NoOperation Process data Clear WDT Counter 1001 dfff ffff The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Decode f,d Description: 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. Words: Complement f Encoding: TO, PD Encoding: COMF Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination COMF Example REG1,0 Before Instruction CLRWDT Example REG1 Before Instruction WDT counter = REG1 W ? After Instruction WDT counter = WDT prescaler= TO = PD = = 0x13 = = 0x13 0xEC After Instruction 0x00 0 1 1 DECF Decrement f Syntax: [label] DECF f,d Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z 00 Encoding: 0011 dfff ffff Description: Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination DECF CNT, 1 Before Instruction CNT Z = = 0x01 0 = = 0x00 1 After Instruction CNT Z DS30444E - page 126 1997 Microchip Technology Inc. PIC16C9XX DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 2047 Operation: Operation: (f) - 1 (destination); skip if result = 0 k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: None Status Affected: None 00 Encoding: Description: Cycles: 1(2) If Skip: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Q3 NoNoNoOperation Operation Operation Example HERE DECFSZ GOTO CONTINUE * * * kkkk GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction. Words: 1 Cycles: 2 2nd Cycle Example (2nd Cycle) Q2 kkkk Description: 1st Cycle Q1 1kkk ffff Q Cycle Activity: 1 Q Cycle Activity: dfff The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 1, the next instruction, is executed. If the result is 0, then a NOP is executed instead making it a 2TCY instruction. Words: 10 Encoding: 1011 GOTO k Q4 NoOperation Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to PC NoNoNoNoOperation Operation Operation Operation GOTO THERE After Instruction PC = Address THERE CNT, 1 LOOP Before Instruction PC = address HERE After Instruction CNT if CNT PC if CNT PC = = = = 1997 Microchip Technology Inc. CNT - 1 0, address CONTINUE 0, address HERE+1 DS30444E - page 127 PIC16C9XX INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Operation: Status Affected: Z (f) + 1 (destination), skip if result = 0 Status Affected: None 00 Encoding: Description: INCF f,d 1010 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination INCF Example 1 Cycles: 1(2) If Skip: = = 0x00 1 Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Q3 Q4 (2nd Cycle) Q1 After Instruction CNT Z ffff Words: Before Instruction 0xFF 0 dfff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. If the result is 1, the next instruction is executed. If the result is 0, a NOP is executed instead making it a 2TCY instruction. Q Cycle Activity: = = 1111 Description: CNT, 1 CNT Z 00 Encoding: INCFSZ f,d Q2 NoNoNoOperation Operation Operation Example HERE INCFSZ GOTO CONTINUE * * * NoOperation CNT, 1 LOOP Before Instruction PC = address HERE After Instruction CNT = if CNT= PC = if CNT PC = DS30444E - page 128 CNT + 1 0, address CONTINUE 0, address HERE +1 1997 Microchip Technology Inc. PIC16C9XX IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (W) .OR. k (W) 0 f 127 d [0,1] Status Affected: Z Operation: (W) .OR. (f) (destination) Status Affected: Z 11 Encoding: Description: 1 Cycles: 1 Example 1000 kkkk kkkk The contents of the W register is OR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: Q Cycle Activity: IORLW k Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W IORLW 00 Encoding: W = 0x9A After Instruction W Z = = f,d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination 0x35 Before Instruction IORWF Example IORWF RESULT, 0 Before Instruction 0xBF 1 RESULT = W = 0x13 0x91 After Instruction RESULT = W = Z = 1997 Microchip Technology Inc. 0x13 0x93 1 DS30444E - page 129 PIC16C9XX MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: 1000 dfff 1 Cycles: 1 Q Cycle Activity: Syntax: [ label ] Operands: 0 f 127 Operation: (W) (f) Status Affected: None 00 MOVWF 0000 f 1fff Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Description: Move data from W register to register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' MOVWF OPTION_REG Before Instruction OPTION = W = MOVF Example ffff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: Move W to f Encoding: 00 Encoding: MOVF f,d MOVWF FSR, 0 0xFF 0x4F After Instruction OPTION = W = After Instruction 0x4F 0x4F W = value in FSR register Z =1 MOVLW Move Literal to W Syntax: [ label ] Operands: 0 k 255 Operation: k (W) Status Affected: None 11 Encoding: MOVLW k 00xx kkkk kkkk Description: The eight bit literal 'k' is loaded into W register. The don't cares will assemble as 0's. Words: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W MOVLW 0x5A After Instruction W DS30444E - page 130 = 0x5A 1997 Microchip Technology Inc. PIC16C9XX NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS PC, 1 GIE Status Affected: None 00 Encoding: NOP 0000 Description: No operation. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 0xx0 0000 00 Encoding: Q2 Q3 0000 0000 1001 Description: Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two cycle instruction. Words: 1 Cycles: 2 Q4 NoNoNoOperation Operation Operation RETFIE NOP Example Q Cycle Activity: 1st Cycle 2nd Cycle Example Q1 Q2 Q3 Q4 Decode NoOperation Set the GIE bit Pop from the Stack NoNoNoNoOperation Operation Operation Operation RETFIE After Interrupt PC = GIE = OPTION Load Option Register Syntax: [ label ] Operands: None Operation: (W) OPTION TOS 1 OPTION Status Affected: None 00 Encoding: 0000 0110 0010 Description: The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. 1997 Microchip Technology Inc. DS30444E - page 131 PIC16C9XX RETLW Return with Literal in W RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: None Operation: k (W); TOS PC Operation: TOS PC Status Affected: None Status Affected: None RETLW k Encoding: Description: 01xx kkkk Words: 1 2 Cycles: Cycles: 2 Q Cycle Activity: 1st Cycle 2nd Cycle Decode Read literal 'k' Q3 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 1 Q2 0000 Description: Words: Q1 0000 kkkk The W register is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two cycle instruction. Q Cycle Activity: 00 Encoding: 11 RETURN Q4 NoWrite to W, Operation Pop from the Stack NoNoNoNoOperation Operation Operation Operation 1st Cycle 2nd Cycle Example Q1 Decode Q2 Q3 Q4 NoNoPop from Operation Operation the Stack NoNoNoNoOperation Operation Operation Operation RETURN After Interrupt Example CALL TABLE ;W contains table ;offset value ;W now has table value * * * TABLE ADDWF PC RETLW k1 RETLW k2 PC = TOS ;W = offset ;Begin table ; * * * RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W DS30444E - page 132 = value of k8 1997 Microchip Technology Inc. PIC16C9XX RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C 00 Encoding: Description: RLF f,d 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. C 00 Encoding: Description: Register f C 1 Words: 1 Cycles: 1 Cycles: 1 Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination RLF REG1,0 1997 Microchip Technology Inc. dfff ffff Register f Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination RRF REG1,0 Before Instruction = = 1110 0110 0 = = = 1110 0110 1100 1100 1 After Instruction REG1 W C Q Cycle Activity: Example Before Instruction REG1 C 1100 The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'. Words: Q Cycle Activity: RRF f,d REG1 C = = 1110 0110 0 = = = 1110 0110 0111 0011 0 After Instruction REG1 W C DS30444E - page 133 PIC16C9XX SLEEP SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Operation: k - (W) (W) Status Affected: C, DC, Z TO, PD Description: The W register is subtracted (2's complement method) from the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Status Affected: 00 Encoding: Description: 1 Cycles: 1 0110 0011 Q Cycle Activity: Example 1: Q1 Decode Example: 0000 Encoding: The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 14.8 for more details. Words: Q Cycle Activity: SLEEP Q2 Q3 NoNoOperation Operation 11 110x kkkk kkkk Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W SUBLW 0x02 Before Instruction Q4 W C Z Go to Sleep = = = 1 ? ? After Instruction SLEEP W C Z Example 2: = = = 1 1; result is positive 0 Before Instruction W C Z = = = 2 ? ? After Instruction W C Z Example 3: = = = 0 1; result is zero 1 Before Instruction W C Z = = = 3 ? ? After Instruction W = C = tive Z = DS30444E - page 134 0xFF 0; result is nega0 1997 Microchip Technology Inc. PIC16C9XX SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] SWAPF f,d Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) (destination) Operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None SUBWF f,d Status Affected: C, DC, Z Encoding: Description: 00 1 Cycles: 1 Example 1: dfff ffff Subtract (2's complement method) W register from register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: Q Cycle Activity: 0010 Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination SUBWF 00 Encoding: REG1 W C Z ffff Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination = = = = SWAPF REG, Example REG1 W C Z = = = = REG1 REG1 W C Z = = = = 2 2 ? ? After Instruction REG1 W C Z = = = = REG1 W = = = = 1997 Microchip Technology Inc. = = = = = = 0xA5 0x5A Load TRIS Register Syntax: [label] Operands: 5f7 Operation: (W) TRIS register f; TRIS f Status Affected: None 0 2 1; result is zero 1 1 2 ? ? After Instruction REG1 W C Z 0xA5 TRIS 00 Encoding: 0000 0110 0fff Description: The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them. Words: 1 Cycles: 1 Before Instruction REG1 W C Z = After Instruction 1 2 1; result is positive 0 Before Instruction 0 Before Instruction 3 2 ? ? After Instruction Example 3: dfff REG1,1 Before Instruction Example 2: 1110 Example 0xFF 2 0; result is negative 0 To maintain upward compatibility with future PIC16CXX products, do not use this instruction. DS30444E - page 135 PIC16C9XX XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [label] Syntax: [label] Operands: 0 k 255 Operands: Operation: (W) .XOR. k (W) 0 f 127 d [0,1] Status Affected: Z Operation: (W) .XOR. (f) (destination) Status Affected: Z Encoding: Description: 11 1 Cycles: 1 Example: 1010 kkkk kkkk The contents of the W register are XOR'ed with the eight bit literal 'k'. The result is placed in the W register. Words: Q Cycle Activity: XORLW k Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W XORLW 00 Encoding: XORWF 0110 f,d dfff ffff Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination 0xAF Before Instruction W = Example 0xB5 After Instruction W = 0x1A XORWF REG 1 Before Instruction REG W = = 0xAF 0xB5 = = 0x1A 0xB5 After Instruction REG W DS30444E - page 136 1997 Microchip Technology Inc. PIC16C9XX 16.0 DEVELOPMENT SUPPORT 16.1 Development Tools The PICmicr microcontrollers are supported with a full range of hardware and software development tools: * PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator * ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator * PRO MATE II Universal Programmer * PICSTART Plus Entry-Level Prototype Programmer * PICDEM-1 Low-Cost Demonstration Board * PICDEM-2 Low-Cost Demonstration Board * PICDEM-3 Low-Cost Demonstration Board * MPASM Assembler * MPLAB SIM Software Simulator * MPLAB-C (C Compiler) * Fuzzy Logic Development System (fuzzyTECH-MP) 16.2 PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download, and source debugging from a single environment. Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. 16.3 ICEPIC: Low-Cost PIC16CXXX In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT through Pentium based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation. 16.4 PRO MATE II: Universal Programmer The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set configuration and code-protect bits in this mode. 16.5 PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. PICSTART Plus is not recommended for production programming. PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3.x environment were chosen to best make these features available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries. 1997 Microchip Technology Inc. DS30444E - page 137 PIC16C9XX 16.6 PICDEM-1 Low-Cost PICmicro Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB. 16.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad. 16.8 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test firmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include DS30444E - page 138 an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. 16.9 MPLABTM Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains: * A full featured editor * Three operating modes - editor - emulator - simulator * A project manager * Customizable tool bar and key mapping * A status bar with project information * Extensive on-line help MPLAB allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file * Transfer data dynamically via DDE (soon to be replaced by OLE) * Run up to four emulators on the same PC The ability to use MPLAB with Microchip's simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 16.10 Assembler (MPASM) The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. MPASM allows full symbolic debugging from PICMASTER, Microchip's Universal Emulator System. 1997 Microchip Technology Inc. PIC16C9XX MPASM has the following features to assist in developing software for specific use applications. * Provides translation of Assembler source code to object code for all Microchip microcontrollers. * Macro assembly capability. * Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip's emulator systems. * Supports Hex (default), Decimal and Octal source and listing formats. MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable. 16.11 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 16.12 C Compiler (MPLAB-C) 16.14 MP-DriveWay - Application Code Generator MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually configure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip's MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation. 16.15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer's Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can significantly reduce time-to-market and result in an optimized system. 16.16 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters. The MPLAB-C Code Development System is a complete `C' compiler and integrated development environment for Microchip's PICmicro family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display. 16.13 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, edition for implementing more complex systems. Both versions include Microchip's fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. 1997 Microchip Technology Inc. DS30444E - page 139 Emulator Products Software Tools DS30444E - page 140 Programmers KEELOQ Evaluation Kit PICDEM-3 PICDEM-2 PICDEM-1 SEEVAL Designers Kit KEELOQ Programmer PRO MATE II Universal Programmer PICSTART Plus Low-Cost Universal Dev. Kit PICSTART Lite Ultra Low-Cost Dev. Kit Total Endurance Software Model fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev. Tool MP-DriveWay Applications Code Generator MPLAB C Compiler MPLAB Integrated Development Environment ICEPIC Low-Cost In-Circuit Emulator PICMASTER/ PICMASTER-CE In-Circuit Emulator PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X Available 3Q97 PIC17C75X 24CXX 25CXX 93CXX HCS200 HCS300 HCS301 TABLE 16-1: Demo Boards PIC12C5XX PIC16C9XX DEVELOPMENT TOOLS FROM MICROCHIP 1997 Microchip Technology Inc. PIC16C9XX 17.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias............................................................................................................ .-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS............................................................................................................. 0V to +14V Voltage on RA4 with respect to Vss ................................................................................................................ 0V to +14V Total power dissipation (Note 1)................................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD)............................................................................................................. 20 mA Maximum output current sunk by any I/O pin .........................................................................................................10 mA Maximum output current sourced by any I/O pin ...................................................................................................10 mA Maximum current sunk by all Ports combined ......................................................................................................200 mA Maximum current sourced by all Ports combined ................................................................................................200 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 17-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16C923-04 PIC16C923-08 PIC16LC923-04 CL Devices PIC16C924-04 PIC16C924-08 PIC16LC924-04 VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0V IDD: 5 mA max. at 5.5V RC IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.0V to 6.0V VDD: 4.5V to 5.5V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0V IDD: 5 mA max. at 5.5V XT IPD: 21 A max. at 4V IPD: 1.5 A typ. at 4V IPD: 5 A max. at 3V IPD: 21 A max. at 4V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 3.5 mA typ. at 5.5V IDD: 7 mA max. at 5.5V IDD: 7 mA max. at 5.5V HS Do not use in HS mode IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V IPD: 1.5 A typ. at 4.5V Freq: 4 MHz max. Freq: 8 MHz max. Freq: 8 MHz max. VDD: 4.0V to 6.0V VDD: 2.5V to 6.0V VDD: 2.5V to 6.0V IDD: 22.5 A typ. IDD: 30 A max. IDD: 30 A max. at 32 kHz, 3.0V LP at 32 kHz, 4.0V Do not use in LP mode at 32 kHz, 3.0V IPD: 5 A max. at 3.0V IPD: 1.5 A typ. at 4.0V IPD: 5 A max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required. OSC 1997 Microchip Technology Inc. DS30444E - page 141 PIC16C9XX 17.1 DC Characteristics: PIC16C923/924-04 (Commercial, Industrial) PIC16C923/924-08 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage D001A VDD 4.0 4.5 - 6.0 5.5 V V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D010 Supply Current (Note 2) IDD - 2.7 5 mA D011 - 22.5 48 A D012 - 3.5 7 mA IPD - 1.5 21 A VDD = 4.0V IWDT - 6.0 20 A VDD = 4.0V D020 Power-down Current (Note 3) XT, RC and LP osc configuration HS osc configuration See Power-on Reset section for details V/ms (Note 6) See Power-on Reset section for details XT and RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) LP osc configuration, FOSC = 32 kHz, VDD = 4.0V HS osc configuration FOSC = 8 MHz, VDD = 5.5V Module Differential Current (Note 5) D021 Watchdog Timer D022* LCD Voltage Generation ILCDRC w/internal RC osc enabled - 40 55 A VDD = 4.0V (Note 7) D024* LCD Voltage Generation ILCDT1 w/Timer1 @ 32.768 kHz - 33 60 A VDD = 4.0V (Note 7) D025* Timer1 oscillator IT1OSC - 10.6 17 A VDD = 4.0V D026* A/D Converter IAD - 1.0 - A A/D on, not converting * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: PWRT must be enabled for slow ramps. 7: LCDT1 and LCDRC includes the current consumed by the LCD Module and the voltage generation circuitry. This does not include current dissipated by the LCD panel. DS30444E - page 142 1997 Microchip Technology Inc. PIC16C9XX 17.2 DC Characteristics: PIC16LC923/924-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial DC CHARACTERISTICS Param No. Characteristic Sym Min Typ Max Units Conditions D001 Supply Voltage VDD 2.5 - 6.0 V D002* RAM Data Retention Voltage (Note 1) VDR - 1.5 - V D003 VDD start voltage to ensure internal Power-on Reset signal VPOR - VSS - V D004* VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 - - D010 Supply Current (Note 2) IDD - 2.0 3.8 mA - 13.5 30 A IPD - 0.9 5 A VDD = 3.0V IWDT - 6.0 20 A VDD = 3.0V D011 D020 Power-down Current (Note 3) LP, XT, RC osc configuration See Power-on Reset section for details V/ms (Note 6) See Power-on Reset section for details XT and RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration, FOSC = 32 kHz, VDD = 4.0V Module Differential Current (Note 5) D021 Watchdog Timer D022* LCD Voltage Generation ILCDRC w/internal RC osc enabled - 36 50 A VDD = 3.0V (Note 7) D024* LCD Voltage Generation ILCDT1 w/Timer1 @ 32.768 kHz - 15 29 A VDD = 3.0V (Note 7) D025* Timer1 oscillator IT1OSC - 3.1 6.5 A VDD = 3.0V D026* A/D Converter IAD - 1.0 - A A/D on, not converting * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD MCLR = VDD. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 6: PWRT must be enabled for slow ramps. 7: LCDT1 and LCDRC includes the current consumed by the LCD Module and the voltage generation circuitry. This does not include current dissipated by the LCD panel. 1997 Microchip Technology Inc. DS30444E - page 143 PIC16C9XX 17.3 DC Characteristics: DC CHARACTERISTICS Param No. D030 D031 D032 D033 D040 D040A D041 D042 D042A D043 D070 D060 D061 D063 Characteristic Input Low Voltage I/O ports with TTL buffer PIC16C923/924-04 (Commercial, Industrial) PIC16C923/924-08 (Commercial, Industrial) PIC16LC923/924-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Sym Min Typ Max Units Conditions VIL VSS VSS VSS VSS VSS with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT, HS and LP) Input High Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP) OSC1 (in RC mode) PORTB weak pull-up current Input Leakage Current (Notes 2, 3) I/O ports MCLR, RA4/T0CKI OSC1 Output Low Voltage I/O ports OSC2/CLKOUT (RC osc mode) Output High Voltage D090 I/O ports (Note 3) D092 OSC2/CLKOUT (RC osc mode) Capacitive Loading Specs on Output Pins D100* OSC2 pin D080 D083 - 0.15VDD 0.8V - 0.2VDD - 0.2VDD - 0.3VDD 2.0 0.25VDD + 0.8V 0.8VDD 0.8VDD 0.7VDD 0.9VDD IPURB 50 250 V V V V V For entire VDD range 4.5V VDD 5.5V VDD VDD V V 4.5V VDD 5.5V For entire VDD range VDD VDD VDD VDD 400 V V V Note1 V A VDD = 5V, VPIN = VSS Note1 VIH IIL - - 1.0 5 5 A Vss VPIN VDD, Pin at hi-Z A Vss VPIN VDD A Vss VPIN VDD, XT, HS and LP osc configuration VOL - - 0.6 0.6 V V IOL = 4.0 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V - V V IOH = -3.0 mA, VDD = 4.5V IOH = -1.3 mA, VDD = 4.5V 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. VOH VDD - 0.7 VDD - 0.7 - COSC2 - - D101* All I/O pins and OSC2 (in RC) CIO 50 pF D102* SCL, SDA in I2C mode 400 pF CB D150* Open -Drain High Voltage VDD 14 V RA4 pin * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C9XX be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. DS30444E - page 144 1997 Microchip Technology Inc. PIC16C9XX FIGURE 17-1: LCD VOLTAGE WAVEFORM D223 D224 VLCD3 VLCD2 VLCD1 VSS TABLE 17-2: LCD MODULE ELECTRICAL SPECIFICATIONS Parameter No. Sym D200 VLCD3 D201 Min Typ Max Units LCD Voltage on pin VLCD3 VDD - 0.3 -- Vss + 7.0 V VLCD2 LCD Voltage on pin VLCD2 -- -- VLCD3 V D202 VLCD1 LCD Voltage on pin VLCD1 -- -- VDD V D220* VOH Output High Voltage Max VLCDN 0.1 -- Max VLCDN V COM outputs IOH = 25 A SEG outputs IOH = 3 A D221* VOL Output Low Voltage Min VLCDN -- Min VLCDN + 0.1 V COM outputs IOL = 25 A SEG outputs IOL = 3 A D222* FLCDRC LCDRC Oscillator Frequency 5 15 50 kHz VDD = 5V, -40C to +85C D223* TrLCD Output Rise Time -- -- 200 s COM outputs Cload = 5,000 pF SEG outputs Cload = 500 pF VDD = 5.0V, T = 25C D224* TfLCD Output Fall Time (1) -- -- 200 s COM outputs Cload = 5,000 pF SEG outputs Cload = 500 pF VDD = 5.0V, T = 25C * (1) Characteristic Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 0 ohm source impedance at VLCD. TABLE 17-3: VLCD CHARGE PUMP ELECTRICAL SPECIFICATIONS Parameter No. Symbol D250* IVADJ D252* IVADJ/ VDD D265* VVADJ * Note Characteristic Min Typ Max Units -- 10 -- A VLCDADJ current VDD Rejection -- -- 0.1/1 A/V VLCDADJ voltage limits PIC16C92X 1.0 -- 2.3 V PIC16LC92X 1.0 VDD 0.7V V VLCDADJ regulated current output Conditions VDD < 3V These parameters are characterized but not tested. 1: For design guidance only. 1997 Microchip Technology Inc. DS30444E - page 145 PIC16C9XX 17.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance AA output access High High BUF Bus free Low Low Hold SU Setup DAT DATA input hold STO STOP condition STA START condition 2C I only TCC:ST (I2C specifications only) CC HD ST DS30444E - page 146 1997 Microchip Technology Inc. PIC16C9XX FIGURE 17-2: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin VSS CL Pin VSS RL = 464 CL = 50 pF 15 pF 1997 Microchip Technology Inc. for all pins except OSC2 unless otherwise noted. for OSC2 output DS30444E - page 147 PIC16C9XX 17.5 Timing Diagrams and Specifications FIGURE 17-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter No. Sym Characteristic Fosc External CLKIN Frequency (Note 1) Min Typ Max Units Conditions DC -- 4 MHz XT and RC osc mode DC -- 8 MHz HS osc mode DC -- 200 kHz LP osc mode Oscillator Frequency DC -- 4 MHz RC osc mode (Note 1) 0.1 -- 4 MHz XT osc mode 4 -- 8 MHz HS osc mode 5 -- 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 -- -- ns XT and RC osc mode (Note 1) 125 -- -- ns HS osc mode 5 -- -- s LP osc mode Oscillator Period 250 -- -- ns RC osc mode (Note 1) 250 -- 10,000 ns XT osc mode 125 -- 250 ns HS osc mode 5 -- -- s LP osc mode 500 -- DC ns TCY = 4/FOSC 2 TCY Instruction Cycle Time (Note 1) 3 TosL, External Clock in (OSC1) High or 50 -- -- ns XT oscillator TosH Low Time 2.5 -- -- s LP oscillator 10 -- -- ns HS oscillator 4 TosR, External Clock in (OSC1) Rise or -- -- 25 ns XT oscillator TosF Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS30444E - page 148 1997 Microchip Technology Inc. PIC16C9XX FIGURE 17-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Refer to Figure 17-2 for load conditions. TABLE 17-5: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym No. Characteristic Min Typ Max Units Conditions 10* TosH2ckL OSC1 to CLKOUT -- 75 200 ns Note 1 11* TosH2ckH OSC1 to CLKOUT -- 75 200 ns Note 1 12* TckR CLKOUT rise time -- 35 100 ns Note 1 13* TckF CLKOUT fall time -- 35 100 ns Note 1 14* TckL2ioV CLKOUT to Port out valid -- -- 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT Tosc + 200 -- -- ns Note 1 16* TckH2ioI Port in hold after CLKOUT 0 -- -- ns Note 1 17* TosH2ioV OSC1 (Q1 cycle) to Port out valid -- 50 150 ns 18* TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) PIC16C923/924 100 -- -- ns PIC16LC923/924 200 -- -- ns 19* TioV2osH Port input valid to OSC1 (I/O in setup time) 0 -- -- ns 20* TioR Port output rise time PIC16C923/924 -- 10 40 ns PIC16LC923/924 -- -- 80 ns PIC16C923/924 -- 10 40 ns PIC16LC923/924 -- -- 80 ns 21* TioF Port output fall time 22* Tinp INT pin high or low time TCY -- -- ns 23* Trbp RB7:RB4 change INT high or low time TCY -- -- ns * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. 1997 Microchip Technology Inc. DS30444E - page 149 PIC16C9XX FIGURE 17-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins Refer to Figure 17-2 for load conditions. TABLE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No. Sym 30 TmcL MCLR Pulse Width (low) 2 -- -- s 31* Twdt Watchdog Timer Time-out Period (No Prescaler) 7 18 33 ms VDD = 5V, -40C to +85C Oscillation Start-up Timer Period -- 1024TOSC -- -- TOSC = OSC1 period Power-up Timer Period 28 72 132 ms VDD = 5V, -40C to +85C I/O Hi-impedance from MCLR Low or Watchdog Timer Reset -- -- 2.1 s * 32 Tost 33* Tpwrt 34 TIOZ Characteristic Min Typ Max Units Conditions These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30444E - page 150 1997 Microchip Technology Inc. PIC16C9XX FIGURE 17-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Refer to Figure 17-2 for load conditions. TABLE 17-7: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym Characteristic 40* Tt0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 41* 42* 45* 46* 47* 48 * Tt0L Min Typ Max 0.5TCY + 20 -- -- ns 10 -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns -- -- -- -- -- -- ns ns ns 0.5TCY + 20 10 Tt0P T0CKI Period TCY + 40 No Prescaler With Prescaler Greater of: 20 or TCY + 40 N Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C923/924 15 Prescaler = PIC16LC923/924 25 2,4,8 30 Asynchronous PIC16C923/924 PIC16LC923/924 50 Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 Synchronous, PIC16C923/924 15 Prescaler = PIC16LC923/924 25 2,4,8 30 Asynchronous PIC16C923/924 PIC16LC923/924 50 Tt1P T1CKI input period Synchronous PIC16C923/924 Greater of: 30 OR TCY + 40 N PIC16LC923/924 Greater of: 50 OR TCY + 40 N Asynchronous PIC16C923/924 60 PIC16LC923/924 100 Ft1 Timer1 oscillator input frequency range DC (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc Units Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Must also meet parameter 47 N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8) -- -- -- -- -- 200 ns ns kHz -- 7Tosc -- These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30444E - page 151 PIC16C9XX FIGURE 17-7: CAPTURE/COMPARE/PWM TIMINGS RC2/CCP1 (Capture Mode) 50 51 52 RC2/CCP1 (Compare or PWM Mode) 53 54 Refer to Figure 17-2 for load conditions. TABLE 17-8: CAPTURE/COMPARE/PWM REQUIREMENTS Parameter No. Sym Characteristic 50* TccL Input Low Time Min No Prescaler With Prescaler PIC16C923/924 PIC16LC923/924 51* TccH Input High Time No Prescaler With Prescaler PIC16C923/924 PIC16LC923/924 * 52* TccP Input Period 53* TccR Output Rise Time 54* TccF Output Fall Time Typ Max Units Conditions 0.5TCY + 20 -- -- ns 10 -- -- ns 20 -- -- ns 0.5TCY + 20 -- -- ns 10 -- -- ns 20 -- -- ns 3TCY + 40 N -- -- ns PIC16C923/924 -- 10 25 ns PIC16LC923/924 -- 25 45 ns PIC16C923/924 -- 10 25 ns PIC16LC923/924 -- 25 45 ns N = prescale value (1,4 or 16) These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30444E - page 152 1997 Microchip Technology Inc. PIC16C9XX FIGURE 17-8: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Refer to Figure 17-2 for load conditions. FIGURE 17-9: SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO BIT6 - - - - - -1 MSb LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Refer to Figure 17-2 for load conditions. 1997 Microchip Technology Inc. DS30444E - page 153 PIC16C9XX FIGURE 17-10:SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Refer to Figure 17-2 for load conditions. FIGURE 17-11:SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 Refer to Figure 17-2 for load conditions. DS30444E - page 154 1997 Microchip Technology Inc. PIC16C9XX TABLE 17-9: SPI MODE REQUIREMENTS Param No. 70* 71* Sym TssL2scH, TssL2scL TscH Characteristic Min Typ Max Units SS to SCK or SCK input TCY -- -- ns 1.25TCY + 30 40 1.25TCY + 30 40 50 -- -- ns -- -- -- -- ns ns SCK input high time (slave mode) 71A* 72* 72A* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* 84* * TscL SCK input low time (slave mode) Continuous Single Byte Continuous Conditions Single Byte TdiV2scH, Setup time of SDI data input to SCK edge -- -- ns TdiV2scL TscH2diL, Hold time of SDI data input to SCK edge 50 -- -- ns TscL2diL TdoR SDO data output rise time -- 10 25 ns TdoF SDO data output fall time -- 10 25 ns TssH2doZ SS to SDO output hi-impedance 10 -- 50 ns TscR SCK output rise time (master mode) -- 10 25 ns TscF SCK output fall time (master mode) -- 10 25 ns TscH2doV, SDO data output valid after SCK edge -- -- 50 ns TscL2doV -- -- ns TdoV2scH, SDO data output setup to SCK edge TCY TdoV2scL TssL2doV SDO data output valid after SS edge -- -- 50 ns TscH2ssH, SS after SCK edge 1.5TCY + 40 -- -- ns TscL2ssH Tb2b Delay between consecutive bytes 1.5TCY + 40 -- -- ns Characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. DS30444E - page 155 PIC16C9XX FIGURE 17-12:I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA START Condition STOP Condition Refer to Figure 17-2 for load conditions. TABLE 17-10:I2C BUS START/STOP BITS REQUIREMENTS Parameter No. Sym 90* TSU:STA Characteristic START condition Setup time 91* THD:STA START condition Hold time 92* TSU:STO STOP condition Setup time 93* THD:STO STOP condition Hold time * Characterized but not tested. DS30444E - page 156 Min Typ Max 100 kHz mode 4700 -- -- 100 kHz mode 4000 -- -- 100 kHz mode 4700 -- -- 100 kHz mode 4000 -- -- Units ns ns Conditions Only relevant for repeated START condition After this period the first clock pulse is generated ns ns 1997 Microchip Technology Inc. PIC16C9XX FIGURE 17-13:I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Refer to Figure 17-2 for load conditions. TABLE 17-11:I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100* THIGH Clock high time 101* TLOW Clock low time 102* TR 103* 90* TF TSU:STA 91* THD:STA 106* 107* 92* THD:DAT TSU:DAT TSU:STO 109* TAA 110* TBUF SDA and SCL rise time SDA and SCL fall time START condition setup time START condition hold time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Min Max Units Conditions 100 kHz mode 4.0 -- s Device must operate at a minimum of 1.5 MHz SSP Module 100 kHz mode 1.5TCY 4.7 -- -- s Device must operate at a minimum of 1.5 MHz SSP Module 100 kHz mode 1.5TCY -- -- 1000 ns 100 kHz mode 100 kHz mode -- 4.7 300 -- ns s 100 kHz mode 4.0 -- s 100 kHz mode 100 kHz mode 100 kHz mode 0 250 4.7 -- -- -- ns ns s 100 kHz mode -- 3500 ns Note 1 100 kHz mode 4.7 -- s Time the bus must be free before a new transmission can start Only relevant for repeated START condition After this period the first clock pulse is generated D102* Cb Bus capacitive loading -- 400 pF * Characterized but not tested. Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 1997 Microchip Technology Inc. DS30444E - page 157 PIC16C9XX TABLE 17-12:A/D CONVERTER CHARACTERISTICS: PIC16C924-04 (COMMERCIAL, INDUSTRIAL) PIC16LC924-04 (COMMERCIAL, INDUSTRIAL) Param Sym Characteristic No. A01 NR A02 Resolution EABS Total Absolute error Typ Max Units Conditions -- -- 8-bits bit -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF A03 EIL A04 EDL Differential linearity error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A05 EFS Full scale error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF A06 EOFF Offset error -- -- <1 LSb VREF = VDD = 5.12V, VSS VAIN VREF -- guaranteed -- -- V A10 -- Integral linearity error Min Monotonicity A20 VREF Reference voltage A25 VAIN Analog input voltage A30 A40 A50 VSS VAIN VREF 3.0V -- VDD + 0.3 VSS - 0.3 -- VREF + 0.3 V ZAIN Recommended impedance of analog voltage source -- -- 10.0 k IAD PIC16C924 -- 180 -- A PIC16LC924 -- 90 -- A 10 -- 1000 A During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 12.1. -- -- 10 A During A/D Conversion cycle A/D conversion current (VDD) IREF VREF input current (Note 2) Average current consumption when A/D is on. (Note 1) * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. DS30444E - page 158 1997 Microchip Technology Inc. PIC16C9XX FIGURE 17-14:A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2) (1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-13:A/D CONVERSION REQUIREMENTS Param No. 130 Sym Characteristic TAD A/D clock period Min Typ Max PIC16C924 1.6 -- -- s TOSC based, VREF 3.0V PIC16LC924 2.0 -- -- s TOSC based, VREF full range PIC16C924 2.0 4.0 6.0 s A/D RC Mode PIC16LC924 3.0 6.0 9.0 s A/D RC Mode -- 9.5 -- TAD Note 2 20 -- s 5* -- -- s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). -- TOSC/2 -- -- If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1.5 -- -- TAD 131 TCNV Conversion time (not including S/H time) (Note 1) 132 TACQ Acquisition time 134 TGO Q4 to A/D clock start TSWC Switching from convert sample time 135 Units Conditions * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 12.1 for min conditions. 1997 Microchip Technology Inc. DS30444E - page 159 PIC16C9XX NOTES: DS30444E - page 160 1997 Microchip Technology Inc. PIC16C9XX 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. Note: The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and process characterization samples. 'Typical' represents the mean of the distribution at, 25C, while 'max' or 'min' represents (mean +3) and (mean -3) respectively where is standard deviation. FIGURE 18-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE @ 25C) FIGURE 18-3: TYPICAL IPD vs. VDD (WDT ENABLED, RC MODE @ 25C) 25.0 260 20.0 IPD(A) 280 240 IPD(nA) 220 15.0 10.0 200 180 5.0 160 0.0 2.5 3.0 3.5 140 4.0 4.5 5.0 VDD (VOLTS) 5.5 6.0 120 100 2.5 3.0 3.5 4.0 4.5 5.0 VDD (VOLTS) 5.5 6.0 FIGURE 18-4: MAXIMUM IPD vs. VDD (WDT ENABLED, RC MODE -40C TO +85C) 40.0 35.0 FIGURE 18-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE -40C TO +85C) 30.0 25.0 IPD(A) 3.5 3.0 15.0 2.5 10.0 2.0 IPD(A) 20.0 5.0 1.5 0.0 2.5 1.0 3.0 3.5 4.0 4.5 5.0 VDD (VOLTS) 5.5 6.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (VOLTS) 1997 Microchip Technology Inc. 5.5 6.0 DS30444E - page 161 PIC16C9XX FIGURE 18-7: TYPICAL IPD vs. VDD (LCD ON(1), TIMER1 (32 kHz(2)), RC MODE @ 25C) 60 90 55 80 50 70 45 60 IPD(A) IPD(A) FIGURE 18-5: TYPICAL IPD vs. VDD (LCD ON(1), INTERNAL RC(2), RC MODE @ 25C) 40 40 35 30 30 2.5 3.0 3.5 4.0 4.5 5.0 VDD (VOLTS) 5.5 6.0 20 C Spec @ 4.0V = 41 LC Spec @ 3.0V = 37 10 0 2.5 FIGURE 18-6: MAXIMUM IPD vs. VDD (LCD ON (32 kHz(1)), INTERNAL RC (32 kHz(2)), RC MODE -40C TO +85C) IPD(A) 65 60 180 55 160 50 3.5 4.0 4.5 5.0 VDD (VOLTS) 5.5 6.0 140 45 IPD(A) 120 40 100 80 35 30 2.5 3.0 FIGURE 18-8: MAXIMUM IPD vs. VDD (LCD ON(1), TIMER1(32 kHz(2)), RC MODE -40C TO +85C) 70 Data based on process characterization samples. See first page of this section for details. 50 60 3.0 3.5 4.0 4.5 5.0 C Spec @ 4.0V = 45 VDD (VOLTS) 5.5 6.0 40 LC Spec @ 3.0V = 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (VOLTS) 5.5 6.0 Note 1: The LCD module is turned on, internal charge pump enabled, 1/4 MUX, 32 Hz frame frequency and no load on LCD segments/commons. IPD will increase depending on the LCD panel connected to the PIC16C9XX. Note 2: Indicates the clock source to the LCD module. DS30444E - page 162 1997 Microchip Technology Inc. PIC16C9XX FIGURE 18-9: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD FIGURE 18-12:TYPICAL IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, RC MODE) Cext = 22 pF, T = 25C 6.0 5.5 5.0 30 R = 5k 25 4.0 3.5 20 3.0 R = 10k 2.5 IPD(A) Fosc(MHz) 4.5 2.0 10 1.5 1.0 R = 100k 5 0.5 0.0 2.5 15 3.0 3.5 4.0 4.5 VDD (VOLTS) 5.0 5.5 0 2.5 6.0 3.0 3.5 4.0 4.5 VDD (VOLTS) 5.0 5.5 6.0 Shaded area is beyond recommended range. FIGURE 18-13:MAXIMUM IPD vs. TIMER1 ENABLED (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C TO -40C, RC MODE) FIGURE 18-10:TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 100 pF, T = 25C 2.4 2.2 R = 3.3k 2.0 R = 5k 1.4 35 1.2 30 1.0 IPD(A) Fosc(MHz) 40 1.6 R = 10k 0.8 0.6 20 15 0.4 R = 100k 0.2 0.0 2.5 25 10 5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (VOLTS) 0 2.5 3.0 3.5 4.0 4.5 VDD (Volts) 5.0 5.5 6.0 FIGURE 18-11:TYPICAL RC OSCILLATOR FREQUENCY vs. VDD Cext = 300 pF, T = 25C 1000 900 Fosc(kHz) 800 R = 3.3k 700 600 R = 5k 500 400 R = 10k 300 200 R = 100k 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (VOLTS) 1997 Microchip Technology Inc. DS30444E - page 163 Data based on process characterization samples. See first page of this section for details. 45 1.8 PIC16C9XX FIGURE 18-14:TYPICAL IDD vs. FREQUENCY (RC MODE @ 20 pF, 25C) 2500 6.0V 5.5V IDD(A) 2000 5.0V 4.5V 4.0V 1500 3.5V 3.0V 1000 2.5V 500 0 0.0 1.00 3.00 4.00 5.00 Shaded area is beyond recommended range Frequency (MHz) Typical 2.7 mA @ 4 MHz, 5.5V FIGURE 18-15:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 20 pF, -40C TO +85C) 3500 6.0V 3000 5.5V 5.0V 2500 IDD(A) Data based on process characterization samples. See first page of this section for details. 2.00 4.5V 4.0V 2000 3.5V 3.0V 1500 2.5V 1000 500 0 0.0 1.00 Maximum 5.0 mA @ 4 MHz, 5.5V DS30444E - page 164 2.00 3.00 Frequency (MHz) 4.00 5.00 Shaded area is beyond recommended range 1997 Microchip Technology Inc. PIC16C9XX FIGURE 18-16:TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25C) 1400 6.0V 5.5V 1200 5.0V 4.5V 1000 4.0V IDD(A) 3.5V 800 3.0V 2.5V 600 400 200 0 600 800 1000 1200 1400 1600 Frequency (kHz) FIGURE 18-17:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40C TO +85C) 1600 6.0V 5.5V 1400 5.0V 4.5V 1200 4.0V 3.5V 1000 IDD(A) 3.0V 2.5V 800 600 400 200 0 0 200 400 Shaded area is beyond recommended range 1997 Microchip Technology Inc. 600 800 1000 1200 1400 1600 Frequency (kHz) DS30444E - page 165 Data based on process characterization samples. See first page of this section for details. 0 200 400 Shaded area is beyond recommended range PIC16C9XX FIGURE 18-18:TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25C) 1200 6.0V 5.5V 1000 5.0V 4.5V 800 4.0V IDD(A) 3.5V 600 3.0V 2.5V 400 200 0 0 100 200 300 400 500 600 700 FIGURE 18-19:MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40C TO +85C) 1400 6.0V 1200 5.5V 5.0V 4.5V 1000 4.0V 3.5V 800 IDD(A) Data based on process characterization samples. See first page of this section for details. Frequency (kHz) 3.0V 2.5V 600 400 200 0 0 100 200 300 400 500 600 700 Frequency (kHz) DS30444E - page 166 1997 Microchip Technology Inc. PIC16C9XX TABLE 18-1: RC OSCILLATOR FREQUENCIES FIGURE 18-20:TRANSCONDUCTANCE(gm) OF HS OSCILLATOR vs. VDD Average Cext Rext 4.0 Fosc @ 5V, 25C 100 pF 300 pF 5k 4.12 MHz 1.4% 10k 2.35 MHz 1.4% 3.0 100k 268 kHz 1.1% 2.5 3.3k 1.80 MHz 1.0% 5k 1.27 MHz 1.0% 10k 688 kHz 1.2% 100k 77.2 kHz 1.0% 3.3k 707 kHz 1.4% 5k 501 kHz 1.2% 10k 269 kHz 1.6% 100k 28.3 kHz 1.1% The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is 3 standard deviation from average value for VDD = 5V. gm(mA/V) 22 pF Max -40C 3.5 Typ 25C 2.0 Min 85C 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (VOLTS) Shaded area is beyond recommended range FIGURE 18-21:TRANSCONDUCTANCE(gm) OF LP OSCILLATOR vs. VDD 110 100 Max -40C 90 70 60 Typ 25C 50 40 30 20 Min 85C 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (VOLTS) Shaded areas are beyond recommended range FIGURE 18-22:TRANSCONDUCTANCE(gm) OF XT OSCILLATOR vs. VDD 1000 900 Max -40C 800 gm(A/V) 700 600 Typ 25C 500 400 300 Min 85C 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (VOLTS) Shaded areas are beyond recommended range 1997 Microchip Technology Inc. DS30444E - page 167 Data based on process characterization samples. See first page of this section for details. gm(A/V) 80 PIC16C9XX FIGURE 18-23:TYPICAL XTAL STARTUP TIME vs. VDD (LP MODE, 25C) FIGURE 18-26:TYPICAL IDD vs. VDD (LP MODE @ 25C) 3.5 140 3.0 120 100 200 kHz, 15 pF/15 pF 2.0 80 32 kHz, 33 pF/33 pF 1.5 60 IDD(A) Startup Time(Seconds) 2.5 1.0 0.5 200 kHz, 15 pF/15 pF 0.0 2.5 40 20 32 kHz, 33 pF/33 pF 3.0 3.5 4.0 4.5 5.0 5.5 0 2.5 6.0 VDD (VOLTS) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (VOLTS) FIGURE 18-24:TYPICAL XTAL STARTUP TIME vs. VDD (HS MODE, 25C) LC Spec -> Typical = 22.5 A, 32 kHz, 4.0V 7 FIGURE 18-27:MAXIMUM IDD vs. VDD (LP MODE -40C TO +85C) Startup Time(ms) 5 140 4 120 8 MHz, 33 pF/33 pF 3 8 MHz, 15 pF/15 pF 100 2 200 kHz, 15 pF/15 pF 1 4.0 80 5.0 VDD (VOLTS) 5.5 6.0 60 70 IDD(A) 4.5 FIGURE 18-25:TYPICAL XTAL STARTUP TIME vs. VDD (XT MODE, 25C) 40 20 60 32 kHz, 33 pF/33 pF 0 2.5 50 Startup Time(ms) Data based on process characterization samples. See first page of this section for details. 6 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (VOLTS) 40 200 kHz, 68 pF/68 pF LC Spec -> Maximum = 48 A, 32 kHz, 4.0V 30 200 kHz, 47 pF/47 pF 20 1 MHz, 15 pF/15 pF 10 0 2.5 4 MHz, 15 pF/15 pF 3.0 3.5 DS30444E - page 168 4.0 4.5 VDD (VOLTS) 5.0 5.5 6.0 1997 Microchip Technology Inc. PIC16C9XX FIGURE 18-28:TYPICAL IDD vs. VDD (XT MODE @ 25C) FIGURE 18-30:TYPICAL IDD vs. VDD (HS MODE @ 25C) 7 1600 1400 6 1200 5 4 MHz, 15 pF/15 pF IDD(A) 1000 800 1 MHz, 15 pF/15 pF IDD(A) 600 8 MHz, 15 pF/15 pF 3 2 400 200 1 200 kHz, 33 pF/33 pF 0 2.5 4 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 4.0 VDD (VOLTS) 4.5 5.0 5.5 6.0 VDD (VOLTS) Typical = 2.7 A, 4 MHz, 5.5V Typical = 3.5 mA, 8 MHz, 5.5V FIGURE 18-29:MAXIMUM IDD vs. VDD (XT MODE -40C TO +85C) 2500 8 2000 7 6 4 MHz, 15 pF/15 pF 1 MHz, 15 pF/15 pF 1000 5 500 4 200 kHz, 33 pF/33 pF 0 2.5 3.0 3.5 4.0 4.5 VDD (VOLTS) 5.0 5.5 6.0 IDD (MA) IDD(A) 1500 3 8 MHz, 15 pF/15 pF 2 Maximum = 5 mA, 4 MHz, 5.5V 1 0 4.0 4.5 5.0 5.5 6.0 VDD (VOLTS) Maximum = 7 mA, 8 MHz, 5.5V 1997 Microchip Technology Inc. DS30444E - page 169 Data based on process characterization samples. See first page of this section for details. FIGURE 18-31:MAXIMUM IDD vs. VDD (HS MODE -40C TO +85C) PIC16C9XX NOTES: DS30444E - page 170 1997 Microchip Technology Inc. PIC16C9XX 19.0 PACKAGING INFORMATION 19.1 64-Lead Plastic Surface Mount (TQFP 10x10x1 mm Body 1.0/0.10 mm Lead Form)) D1 D D/2 e/2 A E1 E A DETAIL A e E/2 See Detail A 8 Places 11/13 0 min. A See Detail B A2 Datum Plane 0.25 b with Lead Finish 0.09/0.20 0.08 R min. A1 0-7 Gauge Plane 0.20 min. 0.09/0.16 L 1.00 ref. b1 Base Metal DETAIL B Package Group: Plastic TQFP Millimeters Inches Symbol Min Nominal Max Min Nominal Max A A1 A2 b b1 D D1 E E1 e L N 0 0.05 0.95 0.17 0.17 0.45 64 0.10 1.00 0.22 0.20 12.00 10.00 12.00 10.00 0.50 0.60 64 7 1.20 0.15 1.05 0.27 0.23 0.75 64 0 0.002 0.037 0.007 0.007 0.018 64 0.004 0.039 0.009 0.008 0.472 0.394 0.472 0.394 0.020 0.024 64 7 0.047 0.006 0.041 0.011 0.009 0.030 64 1997 Microchip Technology Inc. DS30444E - page 171 PIC16C9XX 19.2 64-Lead Plastic Dual In-line (750 mil) N E1 E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min Max 0 A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 - 0.51 3.38 0.38 .076 0.20 57.40 55.12 19.05 16.76 1.73 19.05 19.05 3.05 64 1.19 0.686 DS30444E - page 172 Inches Notes Min Max 15 0 15 5.08 - 4.27 0.56 1.27 0.30 57.91 55.12 19.69 17.27 1.83 19.05 21.08 3.43 64 - - - 0.020 0.133 0.015 0.030 0.008 2.260 2.170 0.750 0.660 0.068 0.750 0.750 0.120 64 0.047 0.027 0.200 - 0.168 0.022 0.050 0.012 2.280 2.170 0.775 0.680 0.072 0.750 0.830 0.135 64 - - Typical Typical Reference Typical Reference Notes Typical Typical Reference Typical Reference 1997 Microchip Technology Inc. PIC16C9XX 19.3 68-Lead Plastic Leaded Chip Carrier (Square) D -A- D1 -D- 3 -F- 0.812/0.661 N Pics .032/.026 1.27 .050 2 Sides 0.177 .007 S B D-E S -HA A1 3 D3/E3 D2 0.38 .015 3 -G- 8 F-G S 0.177 .007 S B A S 2 Sides 9 0.101 Seating .004 Plane D -C- 4 E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.254 .010 Max 2 0.254 .010 Max 11 -H- 11 0.508 .020 0.508 .020 -H- 2 0.812/0.661 3 .032/.026 1.524 .060 Min 6 6 -C1.651 .065 1.651 .065 R 1.14/0.64 .045/.025 R 1.14/0.64 .045/.025 5 0.533/0.331 .021/.013 0.64 Min .025 0.177 , D-E S .007 M A F-G S Package Group: Plastic Leaded Chip Carrier (PLCC) Millimeters Symbol Min Max A 4.191 A1 D D1 D2 D3 E E1 E2 E3 N CP LT 2.286 25.019 24.130 22.860 20.320 25.019 24.130 22.860 20.320 68 0.203 1997 Microchip Technology Inc. Inches Notes Min Max 4.699 0.165 0.185 2.794 25.273 24.334 23.622 25.273 24.334 23.622 0.102 0.254 0.090 0.985 0.950 0.900 0.800 0.985 0.950 0.900 0.800 68 0.008 0.110 0.995 0.958 0.930 0.995 0.958 0.930 0.004 0.010 Reference Reference Notes Reference Reference DS30444E - page 173 PIC16C9XX 19.4 Package Marking Information 68-Lead CERQUAD Windowed MMMMMMMMMMMMMMMMM Example PIC16C924-04/CL 9650CAE AABBCDE 64-Lead TQFP Example MMMMMMMMMM MMMMMMM PIC16C923 -08I/PT AABBCDE 9712CAE 68-Lead PLCC Example MMMMMMMMMM MMMMMMM PIC16C924 -08/L AABBCDE 9648CAE 64-Lead SDIP (Shrink DIP) Example MMMMMMMMMMMMMMMMM PIC16C924-04I/SP AABBCDE 9736CAE Legend: MM...M XX...X AA BB C D1 E Note: Microchip part number information Customer specific information* Year code (last 2 digits of calender year) Week code (week of January 1 is week '01') Facility code of the plant at which wafer is manufactured. C = Chandler, Arizona, U.S.A. S = Tempe, Arizona, U.S.A. Mask revision number for microcontroller Assembly code of the plant or country of origin in which part was assembled. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask revision number, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30444E - page 174 1997 Microchip Technology Inc. PIC16C9XX APPENDIX A: APPENDIX B: COMPATIBILITY The following are the list of modifications over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (4K now as opposed to 512 before) and register file (192 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. Bits PA2, PA1, PA0 are removed from STATUS register. Data memory paging is redefined slightly. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Registers are reset differently. Wake up from SLEEP through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt on change feature. T0CKI pin is also a port pin (RA4) now. FSR is made a full eight bit register. "In-circuit programming" is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). PCON status register is added with a Power-on Reset status bit (POR). Code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. 1997 Microchip Technology Inc. 2. 3. 4. 5. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change reset vector to 0000h. DS30444E - page 175 PIC16C9XX APPENDIX C: WHAT'S NEW 18 - TosH2ioL 200 ns Min (LC devices) Figure 13-13 (Resistor Ladder and Charge Pump) in LCD Section. 30 - TmcL 2 s Min 34 - Tioz 2.1 s Max Parameter D150 - Open Drain High Voltage. Timer0 and Timer1 External Clock Timings - Various. DC and AC Characterization Graphs and Tables. 53 - TccR, 54 - TccF APPENDIX D: WHAT'S CHANGED Various descriptions for clarity. Example code for Changing prescaler assignment between Timer0 and the WDT. The A/D section has many changes that provide greater clarification of A/D operation. 73 - TdiV2scH 50 ns Min 74 - TscH2diL 50 ns Min Combined A/D specification tables for Standard and Extended Voltage devices. The Instruction Set has Q-cycle activity listings for every instruction. The following Electrical Characteristic Parameter values have changed to: D011 (Standard Voltage Devices, C) Typical 22.5 A Max 48 A D022 (Standard Voltage Devices) Typical 40 A Max 55 A D024 (Standard Voltage Devices) Typical 33 A Max 60 A D001 (Extended Voltage Devices, LC) Min 2.5 V D011 (Extended Voltage Devices, LC) Typical 13.5 A Max 30 A D022 (Extended Voltage Devices, LC) Typical 36 A Max 50 A D024 (Extended Voltage Devices, LC) Typical 15 A Max 29 A D030 (with TTL) Max 0.5VDD Max 0.8V V (ENTIRE RANGE) V (4.5V VDD 5.5V) D201, D202 Deleted D210 and D211, D251, D253, D260, D271 D222 Min Typical Max 5 15 50 kHz kHz kHz D223, D224 - units to ns. Added D265 (VLCDADJ voltage limits. Changed parameters: 12 - TckR 35 ns Typical 13 - TckF 35 ns Typical 15 - TioV2ckH Tosc + 200 ns Min DS30444E - page 176 1997 Microchip Technology Inc. PIC16C9XX INDEX A A/D Accuracy/Error ............................................................ 86 ADCON0 ............................................................... 79, 80 ADCON1 ............................................................... 79, 80 ADIF............................................................................ 80 Analog-to-Digital Converter......................................... 79 Configuring Analog Port.............................................. 83 Connection Considerations......................................... 87 Conversion time .......................................................... 85 Conversions ................................................................ 84 Converter Characteristics ......................................... 158 Faster Conversion - Lower Resolution Tradeoff ......... 85 GO/DONE ................................................................... 80 Internal Sampling Switch (Rss) Impedance ................ 82 Operation During Sleep .............................................. 86 Sampling Requirements.............................................. 82 Sampling Time ............................................................ 82 Source Impedance...................................................... 82 Transfer Function........................................................ 87 A/D Conversion Clock......................................................... 83 Registers Section ........................................................................ 19 Absolute Maximum Ratings .............................................. 141 ACK............................................................. 70, 74, 75, 76, 77 ADCON0 Register............................................................... 19 ADCON1 Register............................................................... 20 ADIE bit............................................................................... 26 ADIF bit ............................................................................... 27 ADRES............................................................ 19, 79, 80, 109 ALU ....................................................................................... 9 Application Notes AN546 ......................................................................... 79 AN552 ......................................................................... 33 AN556 ......................................................................... 29 AN578 ......................................................................... 63 AN594 ......................................................................... 57 AN607 ....................................................................... 107 Architecture Harvard ......................................................................... 9 Overview ....................................................................... 9 von Neumann................................................................ 9 Assembler MPASM Assembler................................................... 138 B BF ....................................................................................... 74 Block Diagrams A/D .............................................................................. 81 Capture Mode ............................................................. 58 Compare Mode ........................................................... 58 External Brown-out1 ................................................. 112 External Brown-out2 ................................................. 112 External Parallel Cystal Oscillator............................. 105 External Power-on Reset .......................................... 112 External Series Crystal Oscillator ............................. 105 Interrupt Logic ........................................................... 114 LCD Module ................................................................ 90 On-Chip Reset Circuit ............................................... 106 PIC16C923 ................................................................. 10 PIC16C924 ................................................................. 11 PORTC ....................................................................... 35 PORTD ................................................................. 36, 37 PORTE........................................................................ 38 1997 Microchip Technology Inc. PORTF ........................................................................39 PORTG........................................................................40 PWM............................................................................59 RA3:RA0 and RA5 Port Pins .......................................31 RA4/T0CKI Pin ............................................................31 RB3:RB0 Port Pins ......................................................33 RB7:RB4 Port Pins ......................................................33 RC Oscillator ............................................................ 105 SSP (I2C Mode)...........................................................73 SSP (SPI Mode) ..........................................................65 Timer0 .........................................................................45 Timer0/WDT Prescaler ................................................48 Timer1 .........................................................................52 Timer2 .........................................................................55 Watchdog Timer ....................................................... 116 Brown-out Protection Circuit ............................................. 112 C C bit .....................................................................................23 Capture/Compare/PWM (CCP) Capture Mode..............................................................58 CCP1 ...........................................................................57 CCP1CON ................................................................ 109 CCPR1H................................................................... 109 CCPR1L ................................................................... 109 Compare Mode............................................................58 Compare Mode Block Diagram ...................................58 Prescaler .....................................................................58 PWM Block Diagram ...................................................59 PWM Mode..................................................................59 PWM, Example Frequencies/Resolutions ...................60 Section.........................................................................57 Carry bit .................................................................................9 CCP1CON Register.............................................................19 CCP1IE bit ...........................................................................26 CCP1IF bit ...........................................................................27 CCPR1H Register ...............................................................19 CCPR1L Register ................................................................19 Clocking Scheme.................................................................15 Code Examples Call of a Subroutine in Page 1 from Page 0 ................30 Changing Between Capture Prescalers ......................58 Changing Prescaler (Timer0 to WDT) .........................49 Changing Prescaler (WDT to Timer0) .........................49 Doing an A/D Conversion ............................................84 I/O Programming .........................................................41 I2C Module Operation..................................................78 Indirect Addressing......................................................30 Initializing PORTA .......................................................31 Initializing PORTB .......................................................33 Initializing PORTC .......................................................35 Initializing PORTD .......................................................36 Initializing PORTE .......................................................38 Initializing PORTF........................................................39 Initializing PORTG .......................................................40 Loading the SSPBUF register .....................................65 Reading a 16-bit Free-running Timer ..........................53 Code Protection ........................................................ 103, 118 Computed GOTO ................................................................29 Configuration Bits ............................................................. 103 D DC bit...................................................................................23 DC Characteristics.................................................... 142, 143 Development Support ....................................................... 137 Development Tools........................................................... 137 Digit Carry bit .........................................................................9 DS30444E - page 177 PIC16C9XX Direct Addressing................................................................ 30 E Electrical Characteristics................................................... 141 External Power-on Reset Circuit ....................................... 112 F Family of Devices PIC16C9XX................................................................... 6 FSR ................................................................................... 108 FSR Register............................................... 19, 20, 21, 22, 30 Fuzzy Logic Dev. System (fuzzyTECH-MP)................... 139 G GIE .................................................................................... 113 I I/O Ports Section ........................................................................ 31 I/O Programming Considerations........................................ 41 I2C Addressing I2C Devices .............................................. 70 Arbitration.................................................................... 72 BF ......................................................................... 74, 75 CKP............................................................................. 76 Clock Synchronization ................................................ 72 Combined Format ....................................................... 71 I2C Overview............................................................... 69 Initiating and Terminating Data Transfer..................... 69 Master-Receiver Sequence ........................................ 71 Master-Transmitter Sequence .................................... 71 Multi-master ................................................................ 72 START ........................................................................ 69 STOP .................................................................... 69, 70 Transfer Acknowledge ................................................ 70 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator .......... 137 IDLE_MODE ....................................................................... 78 In-Circuit Serial Programming ................................... 103, 118 INDF.................................................................................. 108 INDF Register ............................................. 19, 20, 21, 22, 30 Indirect Addressing ............................................................. 30 Instruction Cycle.................................................................. 15 Instruction Flow/Pipelining .................................................. 15 Instruction Format ............................................................. 119 Instruction Set ADDLW ..................................................................... 121 ADDWF ..................................................................... 121 ANDLW ..................................................................... 122 ANDWF ..................................................................... 122 BCF........................................................................... 122 BSF ........................................................................... 123 BTFSC ...................................................................... 123 BTFSS ...................................................................... 124 CALL ......................................................................... 124 CLRF......................................................................... 125 CLRW ....................................................................... 125 CLRWDT................................................................... 126 COMF ....................................................................... 126 DECF ........................................................................ 126 DECFSZ.................................................................... 127 GOTO ....................................................................... 127 INCF.......................................................................... 128 INCFSZ ..................................................................... 128 IORLW ...................................................................... 129 IORWF ...................................................................... 129 MOVF........................................................................ 130 MOVLW .................................................................... 130 MOVWF .................................................................... 130 DS30444E - page 178 NOP .......................................................................... 131 OPTION .................................................................... 131 RETFIE ..................................................................... 131 RETLW ..................................................................... 132 RETURN................................................................... 132 RLF ........................................................................... 133 RRF .......................................................................... 133 SLEEP ...................................................................... 134 SUBLW ..................................................................... 134 SUBWF..................................................................... 135 SWAPF ..................................................................... 135 TRIS ......................................................................... 135 XORLW .................................................................... 136 XORWF .................................................................... 136 Section...................................................................... 119 INT Interrupt...................................................................... 115 INTCON ............................................................ 109, 113, 115 INTCON Register................................ 19, 20, 21, 22, 25, 102 INTEDG ............................................................................ 115 INTEDG bit ......................................................................... 24 Inter-Integrated Circuit (I2C) ............................................... 63 Internal Sampling Switch (Rss) Impedance........................ 82 Interrupt Flag .................................................................... 113 Interrupts................................................................... 103, 113 RB7:RB4 Port Change ............................................... 33 IRP bit ................................................................................. 23 K KeeLoq Evaluation and Programming Tools ................. 139 L Loading of PC ..................................................................... 29 M MCLR........................................................................ 106, 108 Memory Data Memory .............................................................. 17 Maps, PIC16C9XX ..................................................... 17 Program Memory ........................................................ 17 MP-DriveWayTM - Application Code Generator ................ 139 MPLAB C .......................................................................... 139 MPLAB Integrated Development Environment Software.. 138 O One-Time-Programmable Devices ....................................... 7 OPCODE .......................................................................... 119 OPTION .................................................................... 109, 115 OPTION Register.................................................... 20, 22, 24 Orthogonal ............................................................................ 9 OSC selection................................................................... 103 Oscillator HS..................................................................... 104, 107 LP ..................................................................... 104, 107 Oscillator Configurations................................................... 104 Output of TMR2 .................................................................. 55 P Paging, Program Memory................................................... 29 PC..................................................................................... 108 PCL Register .............................................. 19, 20, 21, 22, 29 PCLATH............................................................................ 109 PCLATH Register ....................................... 19, 20, 21, 22, 29 PCON ............................................................................... 109 PCON Register ................................................................... 28 PD............................................................................. 106, 108 PD bit .................................................................................. 23 PICDEM-1 Low-Cost PICmicro Demo Board ................... 138 PICDEM-2 Low-Cost PIC16CXX Demo Board................. 138 PICDEM-3 Low-Cost PIC16CXXX Demo Board .............. 138 1997 Microchip Technology Inc. PIC16C9XX PICMASTER In-Circuit Emulator ................................... 137 PICSTART Plus Entry Level Development System ....... 137 PIE1 .................................................................................. 113 PIE1 Register........................................................ 20, 26, 102 Pin Functions MCLRVPP.................................................................... 12 OSC1/CLKIN............................................................... 12 OSC2/CLKOUT........................................................... 12 RA0/AN0 ..................................................................... 12 RA1/AN1 ..................................................................... 12 RA2/AN2 ..................................................................... 12 RA3/AN3/VREF ............................................................ 12 RA4/T0CKI.................................................................. 12 RA5/AN4/SS ............................................................... 12 RB0/INT ...................................................................... 12 RB1 ............................................................................. 12 RB2 ............................................................................. 12 RB3 ............................................................................. 12 RB4 ............................................................................. 12 RB5 ............................................................................. 12 RB6 ............................................................................. 12 RB7 ............................................................................. 12 RC0/T1OSO/T1CKI .................................................... 12 RC1/T1OSI ................................................................. 12 RC2/CCP1 .................................................................. 12 RC3/SCK/SCL ............................................................ 12 RC4/SDI/SDA ............................................................. 12 RC5/SDO .................................................................... 12 RD0/SEG00 ................................................................ 13 RD1/SEG01 ................................................................ 13 RD2/SEG02 ................................................................ 13 RD3/SEG03 ................................................................ 13 RD4/SEG04 ................................................................ 13 RD5/SEG29/COM3..................................................... 13 RD6/SEG30/COM2..................................................... 13 RD7/SEG31/COM1..................................................... 13 RE0/SEG05 ................................................................ 13 RE1/SEG06 ................................................................ 13 RE2/SEG07 ................................................................ 13 RE3/SEG08 ................................................................ 13 RE4/SEG09 ................................................................ 13 RE5/SEG10 ................................................................ 13 RE6/SEG11 ................................................................ 13 RE7/SEG27 ................................................................ 13 RF0/SEG12................................................................. 13 RF1/SEG13................................................................. 13 RF2/SEG14................................................................. 13 RF3/SEG15................................................................. 13 RF4/SEG16................................................................. 13 RF5/SEG17................................................................. 13 RF6/SEG18................................................................. 13 RF7/SEG19................................................................. 13 RG0/SEG20 ................................................................ 13 RG1/SEG21 ................................................................ 13 RG2/SEG22 ................................................................ 13 RG3/SEG23 ................................................................ 13 RG4/SEG24 ................................................................ 13 RG5/SEG25 ................................................................ 13 RG6/SEG26 ................................................................ 13 RG7/SEG28 ................................................................ 13 VDD ............................................................................. 14 VSS .............................................................................. 14 PIR1 .................................................................................. 113 PIR1 Register.............................................................. 19, 102 POP .................................................................................... 29 POR .......................................................................... 107, 108 1997 Microchip Technology Inc. Oscillator Start-up Timer (OST)........................ 103, 107 Power Control Register (PCON)............................... 107 Power-on Reset (POR)............................. 103, 107, 108 Power-up Timer (PWRT) .................................. 103, 107 Power-Up-Timer (PWRT) ......................................... 107 Time-out Sequence .................................................. 107 Time-out Sequence on Power-up............................. 111 TO..................................................................... 106, 108 POR bit ................................................................................28 Port RB Interrupt............................................................... 115 PORTA Register ........................................................... 19, 31 PORTB ....................................................................... 77, 108 PORTB Register ..................................................... 19, 21, 33 PORTC ............................................................................. 108 PORTC Register........................................................... 19, 35 PORTD ............................................................................. 109 PORTD Register..................................................................36 PORTE ............................................................................. 109 PORTE Register ..................................................................38 PORTF Register ..................................................................39 PORTG Register .................................................................40 Ports PORTA ........................................................................31 PORTB ........................................................................33 PORTC ........................................................................35 PORTD ........................................................................36 PORTE ........................................................................38 PORTF ........................................................................39 PORTG........................................................................40 Power-down Mode (SLEEP)............................................. 117 PR2................................................................................... 109 PR2 Register .......................................................................20 Prescaler, Switching Between Timer0 and WDT.................49 PRO MATE II Universal Programmer ............................ 137 Program Branches.................................................................9 Program Memory Maps, PIC16C9XX..................................17 PS0 bit .................................................................................24 PS1 bit .................................................................................24 PS2 bit .................................................................................24 PSA bit.................................................................................24 PUSH...................................................................................29 Q Quick-Turnaround-Production ...............................................7 R R/W bit .............................................................. 70, 74, 75, 76 RBIF bit....................................................................... 33, 115 RBPU bit ..............................................................................24 RC Oscillator .................................................... 104, 105, 107 RCV_MODE ........................................................................78 Read-Modify-Write...............................................................41 Register File ........................................................................17 Reset ........................................................................ 103, 106 RP0 bit .......................................................................... 17, 23 RP1 bit .................................................................................23 S SCL......................................................................... 74, 76, 77 SDA .............................................................................. 76, 77 SEEVAL Evaluation and Programming System ............ 139 Serialized Quick-Turnaround-Production ..............................7 Slave Mode SCL..............................................................................74 SDA .............................................................................74 SLEEP ...................................................................... 103, 106 Software Simulator (MPLAB-SIM) .................................... 139 Special Features of the CPU ............................................ 103 DS30444E - page 179 PIC16C9XX Special Function Registers, Section ................................... 19 SPI Master Mode ............................................................... 66 Serial Clock ................................................................. 65 Serial Data In .............................................................. 65 Serial Data Out ........................................................... 65 Serial Peripheral Interface (SPI) ................................. 63 Slave Select ................................................................ 65 SPI clock ..................................................................... 66 SPI Mode .................................................................... 65 SSP SSPADD ....................................................... 73, 74, 109 SSPBUF............................................ 66, 73, 74, 76, 109 SSPCON ........................................... 64, 73, 75, 76, 109 SSPIF bit................................................... 74, 75, 76, 77 SSPOV bit................................................................... 74 SSPSR............................................................ 66, 74, 76 SSPSTAT.......................................... 63, 73, 75, 76, 109 SSP I2C Addressing .................................................................. 74 Multi-master Mode ...................................................... 77 Reception.................................................................... 75 SSP I2C Operation...................................................... 73 START ........................................................................ 76 START (S) .................................................................. 77 STOP (P) .................................................................... 77 Transmission............................................................... 76 SSPADD Register ............................................................... 20 SSPBUF Register ............................................................... 19 SSPCON Register............................................................... 19 SSPIE bit............................................................................. 26 SSPIF bit ............................................................................. 27 SSPOV................................................................................ 74 SSPSTAT Register ............................................................. 20 Stack ................................................................................... 29 Overflows .................................................................... 29 Underflow.................................................................... 29 STATUS ............................................................................ 108 STATUS Register.............................................. 19, 20, 21, 22 Interrupt Timing .................................................. 46 Overview............................................................. 43 Prescaler ............................................................ 48 Prescaler Block Diagram .................................... 48 Section................................................................ 45 Synchronization .................................................. 47 Timing................................................................. 45 Timer1 Capacitor Selection ............................................ 53 Overview............................................................. 43 Switching Prescaler Assignment ........................ 49 Timer2 Overview............................................................. 43 Timing Diagrams A/D Conversion ........................................................ 159 Timer0 ........................................................................ 45 Timer0 Interrupt Timing .............................................. 46 Timer0 with External Clock ......................................... 47 Timing Diagrams and Specifications ................................ 148 TMR0 Register.............................................................. 19, 21 TMR1H Register ................................................................. 19 TMR1IE bit.......................................................................... 26 TMR1IF bit .......................................................................... 27 TMR1L Register.................................................................. 19 TMR2 Register.................................................................... 19 TMR2IE bit.......................................................................... 26 TMR2IF bit .......................................................................... 27 TO bit .................................................................................. 23 TRISA Register....................................................... 20, 22, 31 TRISB ............................................................................... 109 TRISB Register....................................................... 20, 22, 33 TRISC ......................................................................... 77, 109 TRISC Register....................................................... 20, 35, 68 TRISD ............................................................................... 109 TRISD Register................................................................... 36 TRISE ............................................................................... 109 TRISE Register....................................................... 38, 39, 40 Two's Complement ............................................................... 9 T UV Erasable Devices............................................................ 7 T0CS bit .............................................................................. 24 T1CON Register.......................................................... 19, 102 T2CON Register.................................................................. 19 TAD ...................................................................................... 83 Timer Modules, Overview ................................................... 43 Timer0 RTCC ........................................................................ 108 T0IF........................................................................... 115 TMR0 Interrupt .......................................................... 115 Timer1 Resetting of Timer1 Registers .................................... 54 Resetting Timer1 using a CCP Trigger Output ........... 54 T1CON................................................................ 51, 109 TMR1H...................................................................... 109 TMR1L ...................................................................... 109 Timer2 T2CON................................................................ 55, 109 TIMER2 (TMR2) Module ............................................. 55 TMR2 ........................................................................ 109 Timers Timer0 Block Diagram..................................................... 45 External Clock..................................................... 47 External Clock Timing ......................................... 47 Increment Delay.................................................. 47 Interrupt............................................................... 45 W DS30444E - page 180 U W ...................................................................................... 108 W Register ALU............................................................................... 9 Wake-up from SLEEP....................................................... 117 Watchdog Timer (WDT)............................ 103, 106, 108, 116 WDT.................................................................................. 108 Period ....................................................................... 116 Programming Considerations ................................... 116 Timeout..................................................................... 108 X XMIT_MODE ...................................................................... 78 XT ............................................................................. 104, 107 Z Z bit..................................................................................... 23 Zero bit.................................................................................. 9 1997 Microchip Technology Inc. PIC16C9XX List of Equations And Examples Figure 8-1: Example 3-1: Example 4-1: Example 4-2: Example 5-1: Example 5-2: Example 5-3: Example 5-4: Example 5-5: Example 5-6: Example 5-7: Example 5-8: Figure 8-2: Figure 9-1: Figure 9-2: Instruction Pipeline Flow............................. 15 Call of a Subroutine in Page 1 from Page 0 30 Indirect Addressing ..................................... 30 Initializing PORTA....................................... 31 Initializing PORTB....................................... 33 Initializing PORTC ...................................... 35 Initializing PORTD ...................................... 36 Initializing PORTE....................................... 38 Initializing PORTF....................................... 39 Initializing PORTG ...................................... 40 Read-Modify-Write Instructions on an I/O Port ....................................................... 41 Example 7-1: Changing Prescaler (Timer0WDT).......... 49 Example 7-2: Changing Prescaler (WDTTimer0).......... 49 Example 8-1: Reading a 16-bit Free-Running Timer ........ 53 Example 10-1: Changing Between Capture Prescalers...... 58 Example 10-2: PWM Period and Duty Cycle Calculation ... 60 Example 11-1: Loading the SSPBUF (SSPSR) Register.... 65 Equation 12-1: A/D Minimum Charging Time...................... 82 Example 12-1: Calculating the Minimum Required Sample Time............................................... 82 Example 12-2: Doing an A/D Conversion ........................... 84 Example 12-3: 4-bit vs. 8-bit Conversion Times ................. 85 Example 13-1: Static MUX with 32 Segments .................. 100 Example 13-2: 1/3 MUX with 13 Segments ...................... 100 Example 14-1: Saving STATUS, W, and PCLATH Registers in RAM...................................... 115 List of Figures Figure 3-1: Figure 3-2: Figure 3-3: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: Figure 5-8: Figure 5-9: Figure 5-10: Figure 5-11: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: PIC16C923 Block Diagram......................... 10 PIC16C924 Block Diagram......................... 11 Clock/Instruction Cycle ............................... 15 Program Memory Map and Stack ............... 17 Register File Map........................................ 18 Status Register (Address 03h, 83h, 103h, 183h)........................................................... 23 OPTION Register (Address 81h, 181h) ...... 24 INTCON Register (Address 0Bh, 8Bh, 10Bh, 18Bh)................................................ 25 PIE1 Register (Address 8Ch) ..................... 26 PIR1 Register (Address 0Ch) ..................... 27 PCON Register (Address 8Eh) ................... 28 Loading of PC In Different Situations.......... 29 Direct/Indirect Addressing........................... 30 Block Diagram of pins RA3:RA0 and RA5.. 31 Block Diagram of RA4/T0CKI Pin ............... 31 Block Diagram of RB3:RB0 Pins ................ 33 Block Diagram of RB7:RB4 Pins ................ 33 PORTC Block Diagram (Peripheral Output Override)..................................................... 35 PORTD<4:0> Block Diagram...................... 36 PORTD<7:5> Block Diagram...................... 37 PORTE Block Diagram ............................... 38 PORTF Block Diagram ............................... 39 PORTG Block Diagram............................... 40 Successive I/O Operation ........................... 41 Timer0 Block Diagram ................................ 45 Timer0 Timing: Internal Clock/No Prescale 45 Timer0 Timing: Internal Clock/Prescale 1:2 46 Timer0 Interrupt Timing .............................. 46 Timer0 Timing with External Clock ............. 47 Block Diagram of the Timer0/WDT Prescaler..................................................... 48 1997 Microchip Technology Inc. Figure 10-1: Figure 10-2: Figure 10-3: Figure 10-4: Figure 10-5: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 11-8: Figure 11-9: Figure 11-10: Figure 11-11: Figure 11-12: Figure 11-13: Figure 11-14: Figure 11-15: Figure 11-16: Figure 11-17: Figure 11-18: Figure 11-19: Figure 11-20: Figure 11-21: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 13-5: Figure 13-6: Figure 13-7: Figure 13-8: Figure 13-9: Figure 13-10: Figure 13-11: Figure 13-12: Figure 13-13: Figure 14-1: Figure 14-2: Figure 14-3: T1CON: Timer1 Control Register (Address 10h) .............................................................51 Timer1 Block Diagram.................................52 Timer2 Block Diagram.................................55 T2CON: Timer2 Control Register (Address 12h) .............................................................55 CCP1CON Register (Address 17h).............57 Capture Mode Operation Block Diagram ....58 Compare Mode Operation Block Diagram ..58 Simplified PWM Block Diagram...................59 PWM Output................................................59 SSPSTAT: Sync Serial Port Status Register (Address 94h)..............................................63 SSPCON: Sync Serial Port Control Register (Address 14h)..............................................64 SSP Block Diagram (SPI Mode)..................65 SPI Master/Slave Connection .....................66 SPI Mode Timing, Master Mode..................67 SPI Mode Timing (Slave Mode With CKE = 0) ........................67 SPI Mode Timing (Slave Mode With CKE = 1) ........................68 Start and Stop Conditions ...........................69 7-bit Address Format...................................70 I2C 10-bit Address Format...........................70 Slave-receiver Acknowledge .......................70 Data Transfer Wait State.............................70 Master-transmitter Sequence ......................71 Master-receiver Sequence ..........................71 Combined Format........................................71 Multi-master Arbitration (Two Masters) .............................................72 Clock Synchronization.................................72 SSP Block Diagram (I2C Mode)...................................................73 I2C Waveforms for Reception (7-bit Address).............................................75 I2C Waveforms for Transmission (7-bit Address).............................................76 Operation of the I2C Module in IDLE_MODE, RCV_MODE or XMIT_MODE .....................78 ADCON0 Register (Address 1Fh) ...............79 ADCON1 Register (Address 9Fh) ...............80 A/D Block Diagram ......................................81 Analog Input Model .....................................82 A/D Transfer Function .................................87 Flowchart of A/D Operation .........................88 LCDCON Register (Address 10Fh) .............89 LCD Module Block Diagram ........................90 LCDPS Register (Address 10Eh) ................90 Waveforms in Static Drive ...........................91 Waveforms in 1/2 MUX, 1/3 Bias Drive .......92 Waveforms in 1/3 MUX, 1/3 Bias ................93 Waveforms in 1/4 MUX, 1/3 Bias ................94 LCD Clock Generation ................................95 Example Waveforms in 1/4 MUX Drive .......97 Generic LCDD Register Layout...................98 Sleep Entry/exit When SLPEN = 1 or CS1:CS0 = 00 .............................................99 LCDSE Register (Address 10Dh)............. 100 Charge Pump and Resistor Ladder.......... 101 Configuration Word .................................. 103 Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration)........... 104 External Clock Input Operation (HS, XT or LP OSC Configuration)........... 104 DS30444E - page 181 PIC16C9XX Figure 14-4: Figure 14-5: Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 14-11: Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 15-1: Figure 17-1: Figure 17-2: Figure 17-3: Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 17-8: Figure 17-9: Figure 17-10: Figure 17-11: Figure 17-12: Figure 17-13: Figure 17-14: Figure 18-1: Figure 18-2: Figure 18-3: Figure 18-4: Figure 18-5: Figure 18-6: Figure 18-7: Figure 18-8: Figure 18-9: Figure 18-10: Figure 18-11: Figure 18-12: Figure 18-13: External Parallel Resonant Crystal Oscillator Circuit........................................ 105 External Series Resonant Crystal Oscillator Circuit........................................ 105 RC Oscillator Mode................................... 105 Simplified Block Diagram of On-chip Reset Circuit ............................................. 106 Time-out Sequence on Power-up (MCLR not Tied to VDD): Case 1 .............. 111 Time-out Sequence on Power-up (MCLR Not Tied To VDD): Case 2............. 111 Time-out Sequence on Power-up (MCLR Tied to VDD).................................. 111 External Power-on Reset Circuit (for Slow VDD Power-up)........................... 112 External Brown-out Protection Circuit 1 .... 112 External Brown-out Protection Circuit 2 .... 112 Interrupt Logic........................................... 114 INT Pin Interrupt Timing............................ 114 Watchdog Timer Block Diagram ............... 116 Summary of Watchdog Timer Registers ... 116 Wake-up from Sleep Through Interrupt .... 118 Typical In-Circuit Serial Programming Connection................................................ 118 General Format for Instructions ................ 119 LCD Voltage Waveform ............................ 145 Load Conditions........................................ 147 External Clock Timing ............................... 148 CLKOUT and I/O Timing........................... 149 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing ........... 150 Timer0 and Timer1 External Clock Timings ..................................................... 151 Capture/Compare/PWM Timings .............. 152 SPI Master Mode Timing (CKE = 0) ......... 153 SPI Master Mode Timing (CKE = 1) ......... 153 SPI Slave Mode Timing (CKE = 0) ........... 154 SPI Slave Mode Timing (CKE = 1) ........... 154 I2C Bus Start/Stop Bits Timing.................. 156 I2C Bus Data Timing ................................. 157 A/D Conversion Timing ............................. 159 Typical IPD vs. VDD (WDT Disabled, RC Mode @ 25C).................................... 161 Maximum IPD vs. VDD (WDT Disabled, RC Mode -40C to +85C) ........................ 161 Typical IPD vs. VDD (WDT Enabled, RC Mode @ 25C).................................... 161 Maximum IPD vs. VDD (WDT Enabled, RC Mode -40C to +85C) ........................ 161 Typical IPD vs. VDD (LCD on(1), Internal RC(2), RC Mode @ 25C) ........................ 162 Maximum IPD vs. VDD (LCD on (32 kHz(1)), Internal RC (32 kHz(2)), RC Mode -40C to +85C)....................................................... 162 Typical IPD vs. VDD (LCD On(1), Timer1 (32 kHz(2)), RC Mode @ 25C)................ 162 Maximum IPD vs. VDD (LCD On(1), Timer1 (32 kHz(2)), RC Mode -40C to +85C) .... 162 Typical RC Oscillator Frequency vs. VDD . 163 Typical RC Oscillator Frequency vs. VDD . 163 Typical RC Oscillator Frequency vs. VDD . 163 Typical IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, RC Mode)......... 163 Maximum IPD vs. Timer1 Enabled (32 kHz, RC0/RC1 = 33 pF/33 pF, 85C to -40C, RC Mode) ...................................... 163 DS30444E - page 182 Figure 18-14: Typical IDD vs. Frequency (RC Mode @ 20 pF, 25C) ....................... 164 Figure 18-15: Maximum IDD vs. Frequency (RC Mode @ 20 pF, -40C to +85C)....... 164 Figure 18-16: Typical IDD vs. Frequency (RC Mode @ 100 pF, 25C) ..................... 165 Figure 18-17: Maximum IDD vs. Frequency (RC Mode @ 100 pF, -40C to +85C)..... 165 Figure 18-18: Typical IDD vs. Frequency (RC Mode @ 300 pF, 25C) ..................... 166 Figure 18-19: Maximum IDD vs. Frequency (RC Mode @ 300 pF, -40C to +85C)..... 166 Figure 18-20: Transconductance(gm) of HS Oscillator vs. VDD ..................................................... 167 Figure 18-21: Transconductance(gm) of LP Oscillator vs. VDD ..................................................... 167 Figure 18-22: Transconductance(gm) of XT Oscillator vs. VDD ..................................................... 167 Figure 18-23: Typical XTAL Startup Time vs. VDD (LP Mode, 25C)....................................... 168 Figure 18-24: Typical XTAL Startup Time vs. VDD (HS Mode, 25C) ...................................... 168 Figure 18-25: Typical XTAL Startup Time vs. VDD (XT Mode, 25C) ..................................... 168 Figure 18-26: Typical IDD vs. VDD (LP Mode @ 25C) ................................... 168 Figure 18-27: Maximum IDD vs. VDD (LP Mode -40C to +85C) ....................... 168 Figure 18-28: Typical IDD vs. VDD (XT Mode @ 25C)................................... 169 Figure 18-29: Maximum IDD vs. VDD (XT Mode -40C to +85C) ....................... 169 Figure 18-30: Typical IDD vs. VDD (HS Mode @ 25C) .................................. 169 Figure 18-31: Maximum IDD vs. VDD (HS Mode -40C to +85C)....................... 169 List of Tables Table 1-1: Table 3-1: Table 4-1: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 5-8: Table 5-9: Table 5-10: Table 5-11: Table 5-12: Table 5-13: Table 5-14: Table 7-1: Table 8-1: PIC16C9XX Family of Devices..................... 6 PIC16C9XX Pinout Description .................. 12 Special Function Register Summary .......... 19 PORTA Functions ...................................... 32 Summary of Registers Associated with PORTA ....................................................... 32 PORTB Functions ...................................... 34 Summary of Registers Associated with PORTB ....................................................... 34 PORTC Functions ...................................... 35 Summary of Registers Associated with PORTC ....................................................... 35 PORTD Functions ...................................... 37 Summary of Registers Associated with PORTD ....................................................... 37 PORTE Functions ...................................... 38 Summary of Registers Associated with PORTE ....................................................... 38 PORTF Functions....................................... 39 Summary of Registers Associated with PORTF ....................................................... 39 PORTG Functions ...................................... 40 Summary of Registers Associated with PORTG....................................................... 40 Registers Associated with Timer0 .............. 49 Capacitor Selection for the Timer1 Oscillator .................................................... 53 1997 Microchip Technology Inc. PIC16C9XX Table 8-2: Table 9-1: Table 10-1: Table 10-2: Table 10-3: Table 10-4: Table 11-1: Table 11-2: Table 11-3: Table 11-4: Table 12-1: Table 12-2: Table 13-1: Table 13-2: Table 13-3: Table 13-4: Table 14-1: Table 14-2: Table 14-3: Table 14-4: Table 14-5: Table 14-6: Table 15-1: Table 15-2: Table 16-1: Table 17-1: Table 17-2: Table 17-3: Table 17-4: Table 17-5: Table 17-6: Table 17-7: Table 17-8: Table 17-9: Table 17-10: Table 17-11: Table 17-12: Table 17-13: Table 18-1: Registers Associated with Timer1 as a Timer/counter.............................................. 54 Registers Associated with Timer2 as a Timer/Counter............................................. 56 CCP Mode - Timer Resource ..................... 57 Example PWM Frequencies and Resolutions at 8 MHz.................................. 60 Registers Associated with Timer1, Capture and Compare ................................ 61 Registers Associated with PWM and Timer2......................................................... 61 Registers Associated with SPI Operation ... 68 I2C Bus Terminology................................... 69 Data Transfer Received Byte Actions......... 74 Registers Associated with I2C Operation.... 77 TAD vs. Device Operating Frequencies ...... 83 Summary of A/D Registers ......................... 88 Frame Frequency Formulas ....................... 96 Approx. Frame Freq in Hz using Timer1 @ 32.768 kHz or Fosc @ 8 MHz..................... 96 Approx. Frame Freq in Hz using internal RC osc @ 14 kHz ....................................... 96 Summary of Registers Associated with the LCD Module........................................ 102 Ceramic Resonators ................................. 104 Capacitor Selection for Crystal Oscillator . 104 Time-out in Various Situations.................. 107 Status Bits and Their Significance ............ 108 Reset Condition for Special Registers ...... 108 Initialization Conditions for all Registers ... 108 Opcode Field Descriptions........................ 119 PIC16CXXX Instruction Set ...................... 120 development tools from microchip ............ 140 Cross Reference of Device Specs for Oscillator Configurations and Frequencies of Operation (Commercial Devices).......... 141 LCD Module Electrical Specifications ....... 145 VLCD Charge Pump Electrical Specifications............................................ 145 External Clock Timing Requirements ....... 148 CLKOUT and I/O Timing Requirements ... 149 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements ........................................... 150 Timer0 and Timer1 External Clock Requirements ........................................... 151 Capture/Compare/PWM Requirements .... 152 SPI Mode Requirements........................... 155 I2C Bus Start/Stop Bits Requirements ...... 156 I2C Bus Data Requirements ..................... 157 A/D Converter Characteristics: PIC16C924-04 (Commercial, Industrial) PIC16LC924-04 (Commercial, Industrial). 158 A/D Conversion Requirements ................. 159 RC Oscillator Frequencies........................ 167 1997 Microchip Technology Inc. DS30444E - page 183 PIC16C9XX DS30444E - page 184 1997 Microchip Technology Inc. PIC16C9XX ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts. To provide you with the most responsive service possible, the Microchip systems team monitors the BBS, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how Microchip products provide project solutions. The web site, like the BBS, is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp.mchip.com/biz/mchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Datasheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products Connecting to the Microchip BBS Connect worldwide to the Microchip BBS using either the Internet or the CompuServe communications network. Internet: You can telnet or ftp to the Microchip BBS at the address: mchipbbs.microchip.com CompuServe Communications Network: When using the BBS via the Compuserve Network, in most cases, a local call is your only expense. The Microchip BBS connection does not use CompuServe membership services, therefore you do not need CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS. 1997 Microchip Technology Inc. The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem. CompuServe service allow multiple users various baud rates depending on the local point of access. The following connect procedure applies in most locations. 1. Set your modem to 8-bit, No parity, and One stop (8N1). This is not the normal CompuServe setting which is 7E1. 2. Dial your local CompuServe access number. 3. Depress the <Enter> key and a garbage string will appear because CompuServe is expecting a 7E1 setting. 4. Type +, depress the <Enter> key and "Host Name:" will appear. 5. Type MCHIPBBS, depress the <Enter> key and you will be connected to the Microchip BBS. In the United States, to find CompuServe's phone number closest to you, set your modem to 7E1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. After the system responds with "Host Name:", type NETWORK, depress the <Enter> key and follow CompuServe's directions. For voice information (or calling from overseas), you may call (614) 723-1550 for your local CompuServe number. Microchip regularly uses the Microchip BBS to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for Microchip systems software products. For each SIG, a moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files are accepted from the user community in general to limit the spread of computer viruses. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world. Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, ICSP, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. fuzzyTECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated. All other trademarks mentioned herein are the property of their respective companies. DS30444E - page 185 PIC16C9XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16C9XX Y N Literature Number: DS30444E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30444E - page 186 1997 Microchip Technology Inc. PIC16C9XX PIC16C9XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office. Examples PART NO. -XX X /XX XXX Pattern: Package: QTP, SQTP, ROM Code or Special Requirements SP = 64-pin Shrink PDIP PT = TQFP CL = 68-pin Windowed CERQUAD L = PLCC Temperature Range: I = 0C to +70C (T for Tape/Reel) = -40C to +85C (S for Tape/Reel) Frequency Range: 04 04 08 = 200 kHz (PIC16C9XX-04) = 4 MHz = 8 MHz Device PIC16C9XX PIC16C9XXT PIC16LC9XX PIC16LC9XT :VDD range 4.0V to 6.0V :VDD range 4.0V to 6.0V (Tape/Reel) :VDD range 2.5V to 6.0V :VDD range 2.5V to 6.0V (Tape/Reel) a) PIC16C924 - 04/P 301 Commercial Temp., PDIP Package, 4 MHz, normal VDD limits, QTP pattern #301 b) PIC16LC923 - 04/PT Commercial Temp., TQFP package, 4 MHz, extended VDD limits c) PIC16C923 - 08I/CL Industrial Temp., Windowed CERQUAD package, 8 MHz, normal VDD limits * CL Devices are UV erasable and can be programmed to any device configuration. CL Devices meet the electrical requirement of each oscillator type (including LC devices). Sales and Support Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see below) 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302. 1997 Microchip Technology Inc. DS30444E - page 187 Note the following details of the code protection feature on PICmicro(R) MCUs. * * * * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product. If you have any further questions about this matter, please contact the local sales office nearest to you. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K. 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India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/01/02 2002 Microchip Technology Inc.