CY7C1399BN
256-Kbit (32 K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-06490 Rev. *I Revised January 4, 2018
256-Kbit (32 K × 8) Static RAM
Features
■Temperature Ranges
❐Industrial: –40 °C to 85 °C
❐Commercial: 0 °C to 70 °C
❐Automotive-A: –40 °C to 85 °C
■Single 3.3 V power supply
■Ideal for low-voltage cache memory applications
■High speed: 12 ns
■Low active power
❐180 mW (max)
■Low-power alpha immune 6T cell
■Available in pb-free and non pb-free plastic SOJ and TSOP- I
packages
Functional Description
The CY7C1399BN is a high-performance 3.3 V CMOS Static
RAM organized as 32,768 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE) and
active LOW Output Enable (OE) and tristate drivers. The device
has an automatic power-down feature, reducing the power
consumption by more than 95% when deselected.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location addressed
by the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins is present
on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable (WE)
is HIGH. The CY7C1399BN is available in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
For a complete list of related documentation, click here.
g
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
32K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
9
A
0
A
11
A
13
A
12
A
14
A
10
Logic Block Diagram
Document Number: 001-06490 Rev. *I Page 2 of 16
CY7C1399BN
Contents
Pin Configurations ...........................................................3
Selection Guide ................................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 5
Data Retention Waveform ................................................5
Switching Characteristics ................................................6
Switching Waveforms ...................................................... 7
Truth Table ......................................................................10
Ordering Information ...................................................... 11
Ordering Code Definitions .........................................11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products ....................................................................16
PSoC® Solutions .......................................................16
Cypress Developer Community .................................16
Technical Support ..................................................... 16
Document Number: 001-06490 Rev. *I Page 3 of 16
CY7C1399BN
Pin Configurations
Figure 1. 28-pin TSOP pinout (Top View)
Figure 2. 28-pin SOJ pinout (Top View)
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
Top View
TSOP
3
4
20
21
7
6
8
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A
7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11
A13
A12
I/O3
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
5
I/O
0
I/O
1
I/O
2
CE
OE
A
0
I/O
3
Selection Guide
Description Condition -12 -15
Maximum access time (ns) 12 15
Maximum operating current (mA) 55 50
Maximum CMOS standby current (A) Commercial 500 –
Commercial (L) 50 –
Industrial 500 500
Automotive-A – 500
Document Number: 001-06490 Rev. *I Page 4 of 16
CY7C1399BN
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Supply voltage on
VCC to relative GND [1] ................................–0.5 V to +4.6 V
DC voltage applied to outputs
in high Z State [1] ................................. –0.5 V to VCC + 0.5 V
DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Latch-up current .................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0C to +70C 3.3 V 300 mV
Industrial –40C to +85C
Automotive-A –40C to +85C
Electrical Characteristics
Over the Operating Range
Parameter [1] Description Test Conditions -12 -15 Unit
Min Max Min Max
VOH Output HIGH voltage Min VCC, IOH = –2.0 mA 2.4 – 2.4 – V
VOL Output LOW voltage Min VCC, IOL = 4.0 mA – 0.4 – 0.4 V
VIH Input HIGH voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL[1] Input LOW voltage –0.3 0.8 –0.3 0.8 V
IIX Input leakage current –1 +1 –1 +1 A
IOZ Output leakage current GND VIN VCC, Output disabled –5 +5 –5 +5 A
ICC VCC operating supply current Max VCC, IOUT = 0 mA,
f = fMAX = 1/tRC
–55–50mA
ISB1 Automatic CE power-down
current – TTL inputs
Max VCC, CE VIH,
VIN VIH, or
VIN VIL,
f = fMAX
Commercial–5––mA
Commercial (L)–4––mA
Industrial –5–5mA
Automotive-A–––5mA
ISB2 Automatic CE Power-down
current – CMOS inputs [2] Max VCC,
CE VCC – 0.3 V,
VIN VCC – 0.3 V, or
VIN 0.3 V,
WE VCC – 0.3 V or
WE 0.3 V,
f=f
MAX
Commercial – 500 – – A
Commercial (L) – 50 – – A
Industrial – 500 – 500 A
Automotive-A – – – 500 A
Notes
1. Minimum voltage is equal to –2.0 V for pulse durations of less than 20 ns.
2. Device draws low standby current regardless of switching on the addresses.
Document Number: 001-06490 Rev. *I Page 5 of 16
CY7C1399BN
Capacitance
Parameter [3] Description Test Conditions Max Unit
CIN: Addresses Input capacitance TA = 25C, f = 1 MHz, VCC = 3.3 V 5 pF
CIN: Controls 6pF
COUT Output capacitance 6pF
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [4]
3.0 V
3.3 V
OUTPUT
R1 317
R2
351
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
3ns 3ns
OUTPUT 1.73 V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
167
Data Retention Characteristics
(Over the Operating Range - L version only)
Parameter Description Conditions Min Max Unit
VDR VCC for data retention 2.0 – V
ICCDR Data retention current VCC = VDR = 2.0 V,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
020A
tCDR Chip deselect to data retention
time
0–ns
tROperation recovery time tRC –ns
Data Retention Waveform
Figure 4. Data Retention Waveform
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and capacitance CL = 30 pF.
Document Number: 001-06490 Rev. *I Page 6 of 16
CY7C1399BN
Switching Characteristics
Over the Operating Range
Parameter [5] Description -12 -15 Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 12 – 15 – ns
tAA Address to data valid – 12 – 15 ns
tOHA Data hold from address change 3 – 3–ns
tACE CE LOW to data valid – 12 – 15 ns
tDOE OE LOW to data valid – 5 – 6ns
tLZOE OE LOW to low Z [6] 0–0–ns
tHZOE OE HIGH to high Z [6, 7] –5–6ns
tLZCE CE LOW to low Z [6] 3–3–ns
tHZCE CE HIGH to high Z [6, 7] –6–7ns
tPU CE LOW to power-up 0 – 0–ns
tPD CE HIGH to power-down – 12 – 15 ns
Write Cycle [8, 9]
tWC Write cycle time 12 – 15 – ns
tSCE CE LOW to write end 8 – 10 – ns
tAW Address setup to write end 8 – 10 – ns
tHA Address hold from write end 0 – 0–ns
tSA Address setup to write start 0 – 0–ns
tPWE WE pulse width 8 – 10 – ns
tSD Data setup to write end 7 – 8–ns
tHD Data hold from write end 0 – 0–ns
tHZWE WE low to high Z[8] –7–7ns
tLZWE WE high to low Z[6] 3–3–ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and capacitance CL = 30 pF.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-06490 Rev. *I Page 7 of 16
CY7C1399BN
Switching Waveforms
Figure 5. Read Cycle No. 1 [10, 11]
Figure 6. Read Cycle No. 2 [11, 12]
ADDRESS
DATA I/O PREVIOUS DATA VALID DATA OUT VALID
tRC
tAA
tOHA
50%
50%
DATA OUT VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA I/O HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
Notes
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document Number: 001-06490 Rev. *I Page 8 of 16
CY7C1399BN
Figure 7. Write Cycle No. 1 (WE Controlled) [13, 14, 15]
Figure 8. Write Cycle No. 2 (CE Controlled) [13, 14, 15]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE
DATA IN VALID
NOTE 16
tWC
tAW
tSA
tHA
tHD
tSD
tSCE
WE
DATA I/O
ADDRESS
CE
DATA IN VALID
Notes
13. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in the output state and input signals should not be applied.
Document Number: 001-06490 Rev. *I Page 9 of 16
CY7C1399BN
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [17, 18]
Switching Waveforms (continued)
DATA I/O
ADDRESS
tHD
tSD
tLZWE
tSA
tHA
tAW
tWC
CE
WE
tHZWE
NOTE 19 DATA IN VALID
Notes
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
19. During this period, the I/Os are in the output state and input signals should not be applied.
Document Number: 001-06490 Rev. *I Page 10 of 16
CY7C1399BN
Truth Table
CE WE OE Input/Output Mode Power
H X X High Z Deselect/Power-down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High Z Deselect, Output disabled Active (ICC)
Document Number: 001-06490 Rev. *I Page 11 of 16
CY7C1399BN
Ordering Code Definitions
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
12 CY7C1399BN-12ZXC 51-85071 28-pin TSOP I (Pb-free) Commercial
CY7C1399BNL-12ZXC 28-pin TSOP I (Pb-free)
CY7C1399BN-12VXI 51-85031 28-pin molded SOJ (Pb-free) Industrial
Contact your local sales representative regarding availability of these parts.
Temperature Range: X = C or I or A
C = Commercial
I = Industrial
A = Automotive-A
X = Pb-free
Package Type: X = V or Z
V = 28-pin Molded SOJ
Z = 28-pin TSOP I
Speed: XX = 12 ns or 15 ns
L = Low power
Process Technology:
BN = 0.25 µm
399 = 256-Kb density with data width × 8 bits
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CY 1 - CXXX7399C XLBN
Document Number: 001-06490 Rev. *I Page 12 of 16
CY7C1399BN
Package Diagrams
Figure 10. 28-pin SOJ (300 Mils) V28.3 (Molded SOJ V21) Package Outline, 51-85031
51-85031 *F
Document Number: 001-06490 Rev. *I Page 13 of 16
CY7C1399BN
Figure 11. 28-pin TSOP I (8 × 13.4 × 1.2 mm) Z28 (Standard) Package Outline, 51-85071
Package Diagrams (continued)
51-85071 *J
Document Number: 001-06490 Rev. *I Page 14 of 16
CY7C1399BN
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mV millivolt
mW milliwatt
ns nanosecond
pF picofarad
Vvolt
Wwatt
Document Number: 001-06490 Rev. *I Page 15 of 16
CY7C1399BN
Document History Page
Document Title: CY7C1399BN, 256-Kbit (32 K × 8) Static RAM
Document Number: 001-06490
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 423877 NXR See ECN New data sheet.
*A 498575 NXR See ECN Added Automotive-A range related information in all instances across the
document.
Updated Electrical Characteristics:
Removed IOS parameter and its details.
Updated Ordering Information.
*B 2896382 AJU 03/19/2010 Updated Ordering Information:
Removed obsolete part numbers.
Updated Package Diagrams.
*C 3053362 PRAS 10/08/2010 Updated Ordering Information:
Removed pruned part numbers CY7C1399BNL-15VXC and
CY7C1399BNL-15VXCT.
Added Ordering Code Definitions.
*D 3383869 TAVA 09/26/2011 Rearranged sections for better clarity.
Updated Features:
Added Commercial Temperature Range related information.
Updated Functional Description:
Removed Note “For guidelines on SRAM system design, please refer to the
‘System Design Guidelines’ Cypress application note, available on the internet
at www.cypress.com website.” and its reference.
Updated Switching Waveforms:
Modified the notes in figures under Read cycle and Write cycle sections.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated to new template.
*E 4121360 VINI 09/12/2013 Updated to new template.
Completing Sunset Review.
*F 4540416 VINI 10/16/2014 Updated Switching Waveforms:
Updated Note 18.
Updated Package Diagrams:
spec 51-85071 – Changed revision from *I to *J.
Completing Sunset Review.
*G 4578447 VINI 01/16/2015 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed the prune part numbers CY7C1399BN-12VXC and
CY7C1399BN-15VXA.
Updated Package Diagrams:
spec 51-85031 – Changed revision from *E to *F.
Updated to new template.
*H 4985705 NILE 10/24/2015 No technical updates.
Completing Sunset Review.
*I 6013894 AESATMP9 01/04/2018 Updated logo and copyright.
Document Number: 001-06490 Rev. *I Revised January 4, 2018 Page 16 of 16
© Cypress Semiconductor Corporation, 2006-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
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and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
CY7C1399BN
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closest to you, visit us at Cypress Locations.
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