© Semiconductor Components Industries, LLC, 2016
April, 2019 − Rev. 8
1Publication Order Number:
NCP1252/D
NCP1252
Current Mode PWM
Controller for Forward and
Flyback Applications
The NCP1252 controller offers everything needed to build cost−
effective and reliable ac−dc switching supplies dedicated to ATX
power supplies. Thanks to the use of an internally fixed timer,
NCP1252 detects an output overload without relying on the auxiliary
Vcc. A Brown−Out input offers protection against low input voltages
and improves the converter safety. Finally a SOIC−8 package saves
PCB space and represents a solution of choice in cost sensitive project.
Features
•Peak Current Mode Control
•Adjustable Switching Frequency up to 500 kHz
•Jittering Frequency ±5% of the Switching Frequency
•Latched Primary Over Current Protection with 10 ms Fixed Delay
•Delay Extended to 150 ms in E Version
•Delayed Operation Upon Start−up via an Internal Fixed Timer
(A, B and C versions only)
•Adjustable Soft−start Timer
•Auto−recovery Brown−Out Detection
•UC384X−like UVLO Thresholds
•Vcc Range from 9 V to 28 V with Auto−recovery UVLO
•Internal 160 ns Leading Edge Blanking
•Adjustable Internal Ramp Compensation
•+500 mA / –800 mA Source / Sink Capability
•Maximum 50% Duty Cycle: A Version
•Maximum 80% Duty Cycle: B Version
•Maximum 65% Duty Cycle: C Version
•Maximum 47.5% Duty Cycle: D & E Versions
•Ready for Updated No Load Regulation Specifications
•SOIC−8 and PDIP−8 Packages
•These are Pb−Free Devices
Typical Applications
•Power Supplies for PC Silver Boxes, Games Adapter...
•Flyback and Forward Converter
SOIC−8
CASE 751
SUFFIX D
PIN CONNECTIONS
MARKING DIAGRAMS
(Top View)
OFFLINE CONTROLLER
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1
8
x = A, B, C, D or E
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
1252x
ALYWX
G
1
8
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
SS
VCC
DRV
GND
FB
BO
CS
RT
1
PDIP−8
CASE 626
SUFFIX P
1252AP
AWL
YYWWG
NCP1252
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Vout
NCP1252
Vbulk
Vcc
1
2
3
4
8
6
7
5
100 nF*
*Minimum recommended
decoupling capacitor value
Figure 1. Typical Application
Table 1. PIN FUNCTIONS
Pin No. Pin Name Function Pin Description
1 FB Feedback This pin directly connects to an optocoupler collector.
2 BO Brown−out input This pin monitors the input voltage image to offer a Brown−out protection.
3 CS Current sense Monitors the primary current and allows the selection of the ramp com-
pensation amplitude.
4 RTTiming element A resistor connected to ground fixes the switching frequency.
5 GND −The controller ground pin.
6 Drv Driver This pin connects to the MOSFET gate
7 VCC VCC This pin accepts voltage range from 8 V up to 28 V
8 SSTART Soft−start A capacitor connected to ground selects the soft−start duration. The soft
start is grounded during the delay timer
Table 2. MAXIMUM RATINGS TABLE (Notes 1 and 2)
Symbol Rating Value Unit
VCC Power Supply voltage, Vcc pin, transient voltage: 10 ms with IVcc < 20 mA 30 V
VCC Power Supply voltage, Vcc pin, continuous voltage 28 V
IVcc Maximum current injected into pin 7 20 mA
VDRV Maximum voltage on DRV pin −0.3 to VCC V
Maximum voltage on low power pins (except pin 6, 7) −0.3 to 10 V
RθJA – PDIP8 Thermal Resistance Junction−to−Air – PDIP8 131 °C/W
RθJA – SOIC8 Thermal Resistance Junction−to−Air – SOIC8 169 °C/W
TJ(MAX) Maximum Junction Temperature 150 °C
TSTG Storage Temperature Range −60 to +150 °C
ESDHBM ESD Capability, HBM model 1.8 kV
ESDMM ESD Capability, Machine Model 200 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1800 V per JEDEC Standard
JESD22−A114E. Machine Model Method 200 V per JEDEC Standard JESD22−A115A.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
NCP1252
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BO
+
−
LEB
CS
Rsense
S
R
Q
fsw
S
R
Q
Drv
Vcc
management
shutdown
(FCS)
Vbulk
15V
Boot
strap
30 V
Grand
Reset
BOK
UV LO r eset
Grand
Reset
FB
2R
R
GND
Ct Active
Clamp
15V
Buffered
Ramp
Buffered
Ramp
3.5V
0V
Rr amp
Rcomp
UVLO
+
−
VBO
Fault Timer
Count
Clock
Reset
Out
Vdd +
−
Vskip
IBO
Hyst.
Jittering
UV LO
Grand Reset
SST ART
Iss
Vdd
Fixed
Delay
120 ms
Soft start
RT
Fsw
selection
+
−
1V
+
−
Fswing
Soft Start
Status
S
R
Q
Reset
End
Set
10 kHz
clk 2 bits counter
MaxDC
Note:
MaxDC = 50% with A version
MaxDC = 80% with B version
Figure 2. Internal Circuit Architecture
RT
Vcc
UVLO
Q
Q
Q
reset
MaxDC = 65% with C version
MaxDC = 47.5% with D & E versions
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Table 3. ELECTRICAL CHARATERISTICS
(VCC = 15 V, RT = 43 kW, CDRV = 1 nF. For typical values TJ = 25°C, for min/max values TJ = –25°C to +125°C, unless otherwise noted)
Characteristics Test Condition Symbol Min Typ Max Unit
SUPPLY SECTION AND VCC MANAGEMENT
Startup threshold at which driving pulses
are authorized
VCC increasing
A, B, C versions
D & E versions
VCC(on) 9.4
13.1
10
14
10.6
14.9
V
Minimum Operating voltage at which driving pulses
are stopped
VCC decreasing VCC(off) 8.4 9 9.6 V
Hysteresis between VCC(on) and VCC(min) A, B and C versions
D & E versions
VCC(HYS) 0.9
4.5
1.0
5.0
−
−
V
Start−up current, controller disabled VCC < VCC(on) & VCC increasing
from zero
ICC1 − − 100 mA
Internal IC consumption, controller switching Fsw =100 kHz, DRV = open ICC2 0.5 1.4 2.2 mA
Internal IC consumption, controller switching Fsw =100 kHz, CDRV = 1 nF ICC3 2.0 2.7 3.5 mA
CURRENT COMPARATOR
Current Sense Voltage Threshold VILIM 0.92 1 1.08 V
Leading Edge Blanking Duration tLEB −160 −ns
Input Bias Current (Note 3) Ibias −0.02 −mA
Propagation delay From CS detected to gate
turned off
tILIM −70 150 ns
Internal Ramp Compensation Voltage level @ 25°C (Note 4) Vramp 3.15 3.5 3.85 V
Internal Ramp Compensation resistance to CS pin @ 25°C (Note 4) Rramp −26.5 −kW
INTERNAL OSCILLATOR
Oscillator Frequency RT = 43 kW & DRV pin = 47 kWfOSC 92 100 108 kHz
Oscillator Frequency RT = 8.5 kW & DRV pin = 47 kWfOSC 425 500 550 kHz
Frequency Modulation in percentage of fOSC (Note 3) fjitter −±5−%
Frequency modulation Period (Note 3) Tswing −3.33 −ms
Maximum operating frequency (Note 3) fMAX 500 − − kHz
Maximum duty−cycle – A version DCmaxA 45.6 48 49.6 %
Maximum duty−cycle – B version DCmaxB 76 80 84 %
Maximum duty−cycle – C version DCmaxC 61 65 69 %
Maximum duty−cycle – D & E versions DCmaxD 44.2 45.6 47.2 %
FEEDBACK SECTION
Internal voltage division from FB to CS setpoint FBdiv −3− −
Internal pull−up resistor Rpull−up −3.5 −kW
FB pin maximum current FB pin = GND IFB 1.5 − − mA
Internal feedback impedance from FB to GND ZFB −40 −kW
Open loop feedback voltage FB pin = open VFBOL −6.0 −V
Internal Diode forward voltage (Note 3) Vf−0.75 −V
DRIVE OUTPUT
DRV Source resistance RSRC −10 30 W
DRV Sink resistance RSINK −6 19 W
Output voltage rise−time VCC = 15 V, CDRV = 1 nF,
10 to 90%
tr−26 −ns
3. Guaranteed by design
4. Vramp, Rramp Guaranteed by design
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Table 3. ELECTRICAL CHARATERISTICS
(VCC = 15 V, RT = 43 kW, CDRV = 1 nF. For typical values TJ = 25°C, for min/max values TJ = –25°C to +125°C, unless otherwise noted)
Characteristics UnitMaxTypMinSymbolTest Condition
DRIVE OUTPUT
Output voltage fall−time VCC = 15 V, CDRV = 1 nF,
90 to 10%
tf−22 −ns
Clamping voltage (maximum gate voltage) VCC = 25 V
RDRV = 47 kW, CDRV = 1 nF
VCL −15 18 V
High−state voltage drop VCC = VCC(min) + 100 mV, RDRV
= 47 kW, CDRV = 1 nF
VDRV(clamp) −50 500 mV
CYCLE SKIP
Skip cycle level Vskip 0.2 0.3 0.4 V
Skip threshold Reset Vskip(reset) −Vskip+
Vskip(HY
S)
−V
Skip threshold Hysteresis Vskip(HYS) −25 −mV
SOFT START
Soft−start charge current SS pin = GND ISS 8.8 10 11 mA
Soft start completion voltage threshold VSS 3.5 4.0 4.5 V
Internal delay before starting the Soft start when
VCC(on) is reached
For A, B and C versions only
− No delay for D & E versions
SSdelay 100 120 155 ms
PROTECTION
Current sense fault voltage level triggering the
timer
FCS 0.9 1 1.1 V
Timer delay before latching a fault (overload or
short circuit) − A/B/C/D versions
When CS pin > FCS Tfault 10 15 20 ms
Timer delay before latching a fault (overload or
short circuit) − E version
When CS pin > FCS Tfault 120 155 200 ms
Brown−out voltage VBO 0.974 1 1.026 V
Internal current source generating the Brown−out
hysteresis
−5°C ≤ TJ ≤ +125°C
−25°C ≤ TJ ≤ +125°C
IBO 8.8
8.6
10
10
11.2
11.2
mA
3. Guaranteed by design
4. Vramp, Rramp Guaranteed by design
Table 4. SELECTION TABLE
NCP1252 Start−up Delay Duty Ratio Max VCC Start (Typ.) Fault Timer (Typ.) Fault
AYes 50% 10 V 15 ms Latched
BYes 80% 10 V 15 ms Latched
CYes 65% 10 V 15 ms Latched
D No 47.5% 14 V 15 ms Latched
E No 47.5% 14 V 150 ms Latched
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TYPICAL CHARACTERISTICS
Figure 3. Supply Voltage Threshold vs.
Junction Temperature (A, B and C Versions)
Figure 4. Supply Voltage Hysteresis vs.
Junction Temperature (A, B and C Versions)
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
8.8
9.0
9.2
9.4
9.6
9.8
10.0
10.2
100806040200−20−40
0.90
0.95
1.00
1.05
1.10
1.15
1.20
UNDER VOLTAGE LOCK OUT LEVEL (V)
SUPPLY VOLTAGE HYSTERESIS LEVEL (V)
120
VCC(on)
VCC(off)
120
Figure 5. Supply Voltage VCC(ON) Threshold vs.
Junction Temperature (D Version)
Figure 6. Supply Voltage Hysteresis vs.
Junction Temperature (D Version)
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
13.0
13.5
14.0
14.5
15.0
100806040200−20−40
4.0
4.5
5.0
5.5
6.0
UNDER VOLTAGE LOCK OUT LEVEL (V)
SUPPLY VOLTAGE HYSTERESIS LEVEL (V)
120 120
Figure 7. Start−up Current (ICC1) vs. Junction
Temperature
Figure 8. Supply Current (ICC3) vs. Junction
Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
100806040200−20−40
0
10
20
30
40
50
100806040200−20−40
0
1
2
3
4
5
STARTUP CURRENT ICC1 (mA)
SUPPLY CURRENT ICC3 (mA)
120 120
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TYPICAL CHARACTERISTICS
Figure 9. Supply Current (ICC3) vs. Supply
Voltage
Figure 10. Current Sense Voltage Threshold
vs. Junction Temperature
SUPPLY VOLTAGE Vcc (V) TEMPERATURE (°C)
3025201510
0
1
2
3
4
120806040200−20−40
0.92
0.94
0.96
0.98
1.00
1.04
1.06
1.08
Figure 11. Leading Edge Blanking Time vs.
Junction Temperature
Figure 12. Leading Edge Blanking Time vs.
Supply Voltage
TEMPERATURE (°C) SUPPLY VOLTAGE Vcc (V)
100806040200−20−40
0
50
100
150
200
250
300
3025201510
0
50
100
150
200
250
300
SUPPLY CURRENT ICC3 (mA)
CURRENT SENSE VOLTAGE
THRESHOLD (V)
LEADING EDGE BLANKING TIME (ns)
LEADING EDGE BLANKING TIME (ns)
100
1.02
120
Figure 13. Propagation Delay from CS to DRV
vs. Junction Temperature
Figure 14. Propagation Delay from CS to DRV
vs. Supply Voltage
TEMPERATURE (°C) SUPPLY VOLTAGE Vcc (V)
1201008060200−20−40
0
20
40
60
80
100
140
160
3025201510
0
20
40
60
80
120
140
160
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
120
40
100
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TYPICAL CHARACTERISTICS
Figure 15. Oscillator Frequency vs. Junction
Temperature
Figure 16. Oscillator Frequency vs. Supply
Voltage
TEMPERATURE (°C) SUPPLY VOLTAGE Vcc (V)
120806040200−20−40
92
94
96
98
100
104
106
108
3025201510
92
94
96
98
100
104
106
108
Figure 17. Oscillator Frequency vs. Oscillator
Resistor
Rt RESISTOR (kW)
TEMPERATURE (°C)
100806040200
0
50
150
200
300
350
400
500
100806040200−20−40
45
46
48
49
OSCILLATOR FREQUENCY @ Rt = 43 kW (kHz)
SWITCHING FREQUENCY, FSW (kHz)
MAXIMUM DUTY CYCLE (%)
102
100
102
OSCILLATOR FREQUENCY @ Rt = 43 kW (kHz)
100
250
450
47
120
Figure 18. Maximum Duty−cycle, A Version vs.
Junction Temperature
Figure 19. Maximum Duty−cycle, B Version vs.
Junction Temperature
TEMPERATURE (°C)
100806040200−20−40
76
77
78
79
80
82
83
84
MAXIMUM DUTY CYCLE (%)
120
81
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TYPICAL CHARACTERISTICS
Figure 20. Maximum Duty−cycle, C Version vs.
Junction Temperature
TEMPERATURE (°C)
100806040200−20−40
0
2
4
6
8
10
12
14
TEMPERATURE (°C)
SUPPLY VOLTAGE Vcc (V)
100806040200−20−40
10
12
14
16
20
3025201510
10
12
14
16
18
20
TEMPERATURE (°C)
100806040200−20−40
0
0.1
0.2
0.4
0.5
0.7
0.9
1.0
DRIVE SINK AND SOURCE RESIST-
ANCE (W)
DRIVE CLAMPING VOLTAGE (V)
DRIVE CLAMPING VOLTAGE (V)
SKIP CYCLE THRESHOLD (V)
120
ROH
ROL
120
18
0.3
0.6
0.8
120
TEMPERATURE (°C)
100806040200−20−40
44.0
44.5
45.0
45.5
46.0
47.0
MAXIMUM DUTY CYCLE (%)
120
46.5
Figure 21. Maximum Duty−cycle, D Version vs.
Junction Temperature
Figure 22. Drive Sink and Source Resistances
vs. Junction Temperature
Figure 23. Drive Clamping Voltage vs.
Junction Temperature
Figure 24. Drive Clamping Voltage vs. Supply
Voltage
Figure 25. Skip Cycle Threshold vs. Junction
Temperature
TEMPERATURE (°C)
100806040200−20−40
61
62
63
64
65
67
68
69
MAXIMUM DUTY CYCLE (%)
120
66
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TYPICAL CHARACTERISTICS
Figure 26. Soft Start Current vs. Junction
Temperature
Figure 27. Soft Start Completion Voltage
Threshold vs. Junction Temperature
TEMPERATURE (°C)
TEMPERATURE (°C)
120806040200−20−40
3.0
3.5
4.0
4.5
5.0
100806040200−20−40
0.90
0.92
0.96
0.98
1.02
1.04
1.08
1.10
Figure 28. Brown Out Voltage Threshold vs.
Junction Temperature
Figure 29. Brown Out Voltage Threshold vs.
Supply Voltage
SUPPLY VOLTAGE Vcc (V)
TEMPERATURE (°C)
3025201510
0.90
0.92
0.94
0.98
1.02
1.04
1.08
1.10
100806040200−20−40
8.0
8.5
9.0
9.5
10.0
11.0
11.5
12.0
Figure 30. Internal Brown Out Current Source
vs. Junction Temperature
SUPPLY VOLTAGE Vcc (V)
3025201510
8.0
8.5
9.0
9.5
10.5
11.0
11.5
12.0
SOFT START COMPLETION VOLT-
AGE THRESHOLD (V)
BROWN OUT VOLTAGE THRESHOLD (V)
BROWN OUT VOLTAGE THRESHOLD (V)
INTERNAL BROWN OUT CURRENT SOURCE (mA)
100
0.94
1.00
1.06
120
0.96
1.00
1.06
120
10.5
INTERNAL BROWN OUT CURRENT SOURCE (mA)
10.0
Figure 31. Internal Brown Out Current Source
vs. Supply Voltage
TEMPERATURE (°C)
120806040200−20−40
8
9
10
11
SOFT START CURRENT (mA)
100
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Application Information
Introduction
The NCP1252 hosts a high−performance current−mode
controller specifically developed to drive power supplies
designed for the ATX and the adapter market:
•Current Mode operation: implementing peak
current−mode control topology, the circuit offers
UC384X−like features to build rugged power supplies.
•Adjustable switching frequency: a resistor to ground
precisely sets the switching frequency between 50 kHz
and a maximum of 500 kHz. There is no
synchronization capability.
•Internal frequency jittering: Frequency jittering
softens the EMI signature by spreading out peak energy
within a band ±5% from the center frequency.
•Wide Vcc excursion: the controller allows operation
up to 28 V continuously and accepts transient voltage
up to 30 V during 10 ms with IVCC < 20 mA
•Gate drive clamping: a lot of power MOSFETs do not
allow their driving voltage to exceed 20 V. The
controller includes a low−loss clamping voltage which
prevents the gate from going beyond 15 V typical.
•Low startup−current: reaching a low no−load standby
power represents a difficult exercise when the
controller requires an external, lossy, resistor connected
to the bulk capacitor. The start−up current is guaranteed
to be less than 100 mA maximum, helping the designer
to reach a low standby power level.
•Short−circuit protection: by monitoring the CS pin
voltage when it exceeds 1 V (maximum peak current),
the controller detects a fault and starts an internal
digital timer. On the condition that the digital timer
elapses, the controller will permanently latch−off. This
allows accurate overload or short−circuit detection
which is not dependant on the auxiliary winding. Reset
occurs when: a) a BO reset is sensed, b) VCC is cycled
down to VCC(min) level. If the short circuit or the fault
disappear before the fault timer ends, the fault timer is
reset only if the CS pin voltage level is below 1 V at
least during 3 switching frequency periods. This delay
before resetting the fault timer prevents any false or
missing fault or over load detection.
•Adjustable soft−start: the soft−start is activated upon
a start−up sequence (VCC going−up and crossing
VCC(on)) after a minimum internal time delay of 120 ms
(SSdelay). But also when the brown−out pin is reset
without in that case timer delay. This internal time
delay gives extra time to the PFC to be sure that the
output PFC voltage is in regulation. The soft start pin is
grounded until the internal delay is ended. Please note
that SSdelay is present only for A, B and C versions.
•Shutdown: if an external transistor brings the BO pin
down, the controller is shut down, but all internal
biasing circuits are alive. When the pin is released, a
new soft−start sequence takes place.
•Brown−Out protection: BO pin permanently monitors
a fraction of the input voltage. When this image is
below the VBO threshold, the circuit stays off and does
not switch. As soon the voltage image comes back
within safe limits, the pulses are re−started via a
start−up sequence including soft−start. The hysteresis is
implemented via a current source connected to the BO
pin; this current source sinks a current (IBO) from the
pin to the ground. As the current source status depends
on the brown−out comparator, it can easily be used for
hysteresis purposes. A transistor pulling down the BO
pin to ground will shut−off the controller. Upon release,
a new soft−start sequence takes place.
•Internal ramp compensation: a simple resistor
connected from the CS pin to the sense resistor allows
the designer to inject ramp compensation inside his
design.
•Skip cycle feature: When the power supply loads are
decreasing to a low level, the duty cycle also decreases
to the minimum value the controller can offer. If the
output loads disappear, the converter runs at the
minimum duty cycle fixed by the propagation delay and
driving blocks. It often delivers too much energy to the
secondary side and it trips the voltage supervisor. To
avoid this problem, the FB is allowed to impose the min
tON down to ~ Vf and it further decreases down to
Vskip, zero duty cycle is imposed. This mode helps to
ensure no−load outputs conditions as requested by
recently updated ATX specifications. Please note that
the converter first goes to min tON before going to zero
duty cycle: normal operation is thus not disturbed. The
following figure illustrates the different mode of
operation versus the FB pin level.
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FB level
Time
Normal Operation:
Skip: DC = 0%
Figure 32. Mode of Operation versus the FB Pin Level
DCmin < DC < DCmaxA/B/C
VFBOL = 6.0 V
Vf = 0.75 V
Vskip = 0.3 V
Operation @ Ton_min
DC = DCmin
Startup Sequence:
The startup sequence is activated when Vcc pin reaches
VCC(on) level. Once the startup sequence has been activated
the internal delay timer (SSdelay) runs (except D version).
Only when the internal delay elapses the soft start can be
allowed if the BO pin level is above VBO level. If the BO pin
threshold is reached or as soon as this level will be reached
the soft start is allowed. When the soft start is allowed the SS
pin is released from the ground and the current source
connected to this pin sources its current to the external
capacitor connected on SS pin. The voltage variation of the
SS pin divided by 4 gives the same peak current variation on
the CS pin.
The following figures illustrate the different startup cases.
Time
BO pin
Time
SS pin
Time
DRV pin
Time
120 ms: Internal
delay
Time
BO pin
Time
SS pin
Time
DRV pin
Time
120 ms: Internal
delay
CASE #1 CASE #2
Soft start Soft start
No
pulse
Figure 33. Different Startup Sequence Case #1 & #2 − (For A, B and C versions)
VBO
VCC(on)
VCC pin VCC pin
VBO
VCC(on)
With the Case #1, when the VCC pin reaches the VCC(on)
level, the internal timer starts. As the BO pin level is above
the VBO threshold at the end of the internal delay, a soft start
sequence is started.
With the Case #2, at the end of the internal delay, the BO
pin level is below the VBO threshold thus the soft start
sequence can not start. A new soft start sequence will start
only when the BO pin reaches the VBO threshold.
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Time
Time
Time
Time
Time
BO pin
Time
SS pin
Time
DRV pin
Time
CASE #3 CASE #4
SS capacitor is
discharged
Soft start
Figure 34. Controller Shuts Down with the Brown Out Pin
VBO
VCC(on)
VCC pin
BO pin
SS pin
DRV pin
VBO
VCC(on)
VCC pin
When the BO pin is grounded, the controller is shut down
and the SS pin is internally grounded in order to discharge
the soft start capacitor connected to this pin (Case #3). If the
BO pin is released, when its level reaches the VBO level a
new soft start sequence happens.
Soft Start:
As illustrated by the following figure, the rising voltage on
the SS pin voltage divided by 4 controls the peak current
sensed on the CS pin. Thus as soon as the CS pin voltage
becomes higher than the SS pin voltage divided by 4 the
driver latch is reset.
LEB
CS
Rse nse
S
R
Q
Rcomp
Clock
UVLO
Grand Reset
SS
Iss
Vdd
Fixe d
Delay
120 ms
Soft start
+
−
Soft Start
Status
DRV
1/4
Figure 35. Soft Start Principle
Q
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The following figure illustrates a soft start sequence.
Soft Start pin
(2 V/div)
CS pin
(0.5 V/div)
Time
(4 ms/div)
Figure 36. Soft Start Example
VSS = 4 V
TSS = 13 ms
Brown−Out Protection
By monitoring the level on BO pin, the controller protects
the forward converter against low input voltage conditions.
When the BO pin level falls below the VBO level, the
controllers stops pulsing until the input level goes back to
normal and resumes the operation via a new soft start sequence.
The brown−out comparator features a fixed voltage
reference level (VBO). The hysteresis is implemented by
using the internal current connected between the BO pin and
the ground when the BO pin is below the internal voltage
reference (VBO).
BO
S
R
Q
shutdown
Vbulk
BOK
UVLO r eset
Grand
Reset
+
−
VBO
IBO
RB O u p
RB Olo
Figure 37. BO Pin Setup
Q
The following equations show how to calculate the
resistors for BO pin.
First of all, select the bulk voltage value at which the
controller must start switching (Vbulkon) and the bulk
voltage for shutdown (Vbulkoff) the controller.
Where:
•Vbulkon = 370 V
•Vbulkoff = 350 V
•VBO = 1 V
•IBO = 10 mA
When BO pin voltage is below VBO (internal voltage
reference), the internal current source (IBO) is activated. The
following equation can be written:
VbulkON +RBOupǒIBO )VBO
RBOloǓ)VBO (eq. 1)
When BO pin voltage is higher than VBO, the internal
current source is now disabled. The following equation can
be written:
VBO +VbulkoffRBOlo
RBOlo )RBOup
(eq. 2)
From Equation 2 it can be extracted the RBOup:
RBOup +ǒVbulkoff *VBO
VBO ǓRBOlo (eq. 3)
Equation 3 is substituted in Equation 1 and solved for
RBOlo, yields:
NCP1252
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15
RBOlo +VBO
IBO ǒVbulkon *VBO
Vbulkoff *VBO *1Ǔ(eq. 4)
RBOup can be also written independently of RBOlo by
substituting Equation 4 into Equation 3 as follow:
RBOup +Vbulkon *Vbulkoff
IBO
(eq. 5)
From Equation 4 and Equation 5, the resistor divider value
can be calculated:
RBOlo +1
10 mǒ370 *1
350 *1*1Ǔ+5731 W
RBOup +370 *350
10 m+2.0 MW
Short Circuit or Over Load Protection:
A short circuit or an overload situation is detected when
the CS pin level reaching its maximum level at 1 V. In that
case the fault status is stored in the latch and allows the
digital timer count. If the digital timer ends then the fault is
latched and the controller permanently stops the pulses on
the driver pin.
If the fault is gone before ending the digital timer, the
timer is reset only after 3 switching controller periods
without fault detection (or when the CS pin < 1 V during at
least 3 switching periods).
If the fault is latched the controller can be reset if a BO
reset is sensed or if VCC is cycled down to VCC(off). The fault
timer is typically set to 15 ms for A/B/C and D versions but
is extended to 150 ms for the E version.
CS pin
(500 mV/div)
12 Vout
(5 V/div)
Time
(4 ms/div)
Short Circuit
Figure 38. Short Circuit Detection Example
Fault timer: 15 ms
Shut Down
There is one possibility to shut down the controller; this
possibility consists of grounding the BO pin as illustrated in
Figure 37.
Slope Compensation
Slope compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half of the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a duty−cycle
close to and above 50%. To lower the current loop gain, one
usually injects between 50 and 100% of the inductor
downslope. Figure 39 depicts how internally the ramp is
generated:
The compensation is derived from the oscillator via a
buffer. A switch placed between the buffered internal
oscillator ramp and Rramp disconnects the compensation
ramp during the OFF time DRV signal.
NCP1252
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16
LEB
CS
Rsense
S
R
Q
FB 2R
R
Buffered
Ramp
Rramp
Rcomp
Clock
Vdd
+
−
DRV
path
Ccs
Figure 39. Ramp Compensation Setup
Q
In the NCP1252, the internal ramp swings with a slope of:
Sint +Vramp
DCmax
FSW (eq. 6)
In a forward application the secondary−side downslope
viewed on a primary side requires a projection over the sense
resistor Rsense. Thus:
Ssense +(Vout )Vf)
Lout
Ns
Np
Rsense (eq. 7)
where:
•Vout is output voltage level
•Vf the freewheel diode forward drop
•Lout, the secondary inductor value
•Ns/Np the transformer turn ratio
•Rsense: the sense resistor on the primary side
Assuming the selected amount of ramp compensation to
be applied is δcomp, then we must calculate the division ratio
to scale down Sint accordingly:
Ratio +Rsensedcomp
Sint
(eq. 8)
A few line of algebra determined Rcomp:
Rcomp +Rramp Ratio
1*Ratio (eq. 9)
The previous ramp compensation calculation does not
take into account the natural primary ramp created by the
transformer magnetizing inductance. In some case
illustrated here after the power supply does not need
additional ramp compensation due to the high level of the
natural primary ramp.
The natural primary ramp is extracted from the following
formula:
Snatural +Vbulk
Lmag
Rsense (eq. 10)
Then the natural ramp compensation will be:
dnatural_comp +Snatural
Ssense
(eq. 11)
If the natural ramp compensation (δnatural_comp) is higher
than the ramp compensation needed (δcomp), the power
supply does not need additional ramp compensation. If not,
only the difference (δcomp−δnatural_comp) should be used to
calculate the accurate compensation value.
Thus the new division ratio is:
(eq. 12)
if dnatural_comp tdcomp åRatio +Ssense(dcomp *dnatural_comp)
Sint
Then Rcomp can be calculated with the same equation used
when the natural ramp is neglected (Equation 9).
Ramp Compensation Design Example:
2 switch−Forward Power supply specification:
•Regulated output: 12 V
•Lout = 27 mH
•Vf = 0.7 V (drop voltage on the regulated output)
•Current sense resistor : 0.75 W
•Switching frequency : 125 kHz
•Vbulk = 350 V, minimum input voltage at which the
power supply works.
•Duty cycle max: DCmax = 84%
•Vramp = 3.5 V, Internal ramp level.
•Rramp = 26.5 kW, Internal pull−up resistance
•Targeted ramp compensation level: 100%
•Transformer specification:
− Lmag = 13 mH
− Ns/Np = 0.085
NCP1252
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17
Internal ramp compensation level
Sint +Vramp
DCmax
Fsw åSint +3.5
0.84 125 kHz +520 mV ńms
Secondary−side downslope projected over the sense resistor is:
Ssense +(Vout )Vf)
Lout
Ns
Np
Rsense åSsense +(12 )0.7)
27 @10−60.085 0.75 +29.99 mV ńms
Natural primary ramp:
Snatural +Vbulk
Lmag
Rsense åSnatural +350
13 @10−30.75 +20.19 mV ńms
Thus the natural ramp compensation is:
dnatural_comp +Snatural
Ssense ådnatural_comp +20.19
29.99 +67.3%
Here the natural ramp compensation is lower than the desired ramp compensation, so an external compensation should be
added to prevent sub−harmonics oscillation.
Ratio +Ssense(dcomp *dnatural_comp)
Sint åRatio +29.99 @(1.00 *0.67)
520 +0.019
We can know calculate external resistor (Rcomp) to reach the correct compensation level.
Rcomp +Rramp Ratio
1*Ratio åRcomp +26.5 @1030.019
1*0.019 +509 W
Thus with Rcomp = 510 W, 100% compensation ramp is applied on the CS pin.
The following example illustrates a power supply where the natural ramp offers enough ramp compensation to avoid external
ramp compensation.
2 switch−Forward Power supply specification:
•Regulated output: 12 V
•Lout = 27 mH
•Vf = 0.7 V (drop voltage on the regulated output)
•Current sense resistor: 0.75 W
•Switching frequency: 125 kHz
•Vbulk = 350 V, minimum input voltage at which the
power supply works.
•Duty cycle max: DCmax = 84%
•Vramp = 3.5 V, Internal ramp level.
•Rramp = 26.5 kW, Internal pull−up resistance
•Targeted ramp compensation level: 100%
•Transformer specification:
− Lmag = 7 mH
− Ns/Np = 0.085
Secondary−side downslope projected over the sense resistor is:
Ssense +(Vout )Vf)
Lout
Ns
Np
Rsense åSsense +(12 )0.7)
27 @10−60.085 0.75 +29.99 mV ńms
The natural primary ramp is:
Snatural +Vbulk
Lmag
Rsense åSnatural +350
7@10−30.75 +37.5 mV ńms
And the natural ramp compensation will be:
dnatural_comp +Snatural
Ssense ådnatural_comp +37.5
29.99 +125%
So in that case the natural ramp compensation due to the magnetizing inductance of the transformer will be enough to prevent
any sub−harmonics oscillation in case of duty cycle above 50%.
NCP1252
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18
Table 5. ORDERING INFORMATION
Device Version Marking Shipping†
NCP1252APG A 1252AP 50 Units / Rail
NCP1252ADR2G A 1252A 2500 / Tape & Reel
NCP1252BDR2G B 1252B 2500 / Tape & Reel
NCP1252CDR2G C 1252C 2500 / Tape & Reel
NCP1252DDR2G D 1252D 2500 / Tape & Reel
NCP1252EDR2G E 1252E 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
NCP1252
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19
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE P
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
DIM MIN MAX
INCHES
A−−−− 0.210
A1 0.015 −−−−
b0.014 0.022
C0.008 0.014
D0.355 0.400
D1 0.005 −−−−
e0.100 BSC
E0.300 0.325
M−−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
E1
M
8X
c
D1
B
A2 0.115 0.195 2.92 4.95
L0.115 0.150 2.92 3.81
°°
H
NOTE 5
e
e/2 A2
NOTE 3
MBMNOTE 6
M
NCP1252
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20
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NCP1252/D
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