LT4180IGN#PBF - Linear Technology

LT4180

4180fa

TYPICAL APPLICATION

FEATURES DESCRIPTION

Virtual Remote Sense

Controller

The LT

4180 solves the problem of providing tight load

regulation over long, highly resistive cables without

requiring an additional pair of remote sense wires. This

Virtual Remote Sense™ device continuously interrogates

the line impedance and corrects the power supply output

voltage via its feedback loop to maintain a steady voltage

at the load regardless of current changes.

The LT4180 is a full-featured controller with 5mA opto-

isolator sink capability, under/overvoltage lockout,

soft-start and a ±1% internal voltage reference. The

Virtual Remote Sense feature set includes user-program-

mable dither frequency and optional spread spectrum

dither.

The LT4180 works with any topology and type of isolated

or nonisolated power supply, including DC/DC converters

and adjustable linear regulators.

The LT4180 is available in a 24-pin, SSOP package.

Isolated Power Supply with Virtual Remote Sense

APPLICATIONS

n Tight Load Regulation with Highly Resistive Cables

without Requiring Remote Sense Wiring

n Compatible with Isolated and Nonisolated Power

Supplies

n ±1% Internal Voltage Reference

n 5mA Sink Current Capability

n Soft-Correct Reduces Turn-On Transients

n Undervoltage and Overvoltage Protection

n Pin-Programmable Dither Frequency

n Optional Spread Spectrum Dither

n Wide VIN Range: 3.1V to 50V

n 24-Pin SSOP Package

n 12V High Intensity Lamps

n 28V Industrial Systems

n High Power (>40 Watts) CAT5 Cable Systems

n Wiring Drop Cancellation for Notebook Computer

Battery Charging

n AC and DC Adaptors

n Well-Logging and Other Remote Instrumentation

n Surveillance Equipment

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

Virtual Remote Sense is a trademark of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

VLOAD vs VWIRE

CAT5E CABLE

LINE

DIV0 DIV1VIN

COSC

COMP

DRAIN

SENSE DIV2 SPREAD CHOLD1 CHOLD2 CHOLD3 CHOLD4

4180 TA01a

RUN

ROSC

SWITCHING

REGULATOR

–LT4180

VIRTUAL REMOTE SENSE

CLRL

RSENSE

VWIRING (V)

VLOAD (V)

4.97

4.98

4.99

4.96

4.95

0.5 1.51 2 2.5 3

4.92

4.91

4.94

5.00

4.93

4180 TAO1b

LT4180

4180fa

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

VIN ............................................................. –0.3V to 52V

SENSE.......................................................VIN – 0.3V to VIN

INTVCC, RUN, FB, OV, ROSC, OSC,

DIV0, DIV1, DIV2, SPREAD, CHOLD1,

CHOLD2, CHOLD3, CHOLD4, DRAIN, COMP,

GUARD2, GUARD3, GUARD4, VPP ............ –0.3V to 5.5V

VIN Pin Current .......................................................10mA

INTVCC Pin Current .............................................–10mA

COSC Pin Current ..................................................3.3mA

Maximum Junction Temperature .......................... 125°C

Operating Junction Temperature Range (Note 2)

E-, I-Grades ....................................... –40°C to 125°C

MP-Grade .......................................... –55°C to 125°C

Storage Temperature Range .................. –65°C to 125°C

(Note 1)

TOP VIEW

GN PACKAGE

24-LEAD NARROW PLASTIC SSOP

INTVCC

DRAIN

COMP

CHOLD1

GUARD2

CHOLD2

GUARD3

CHOLD3

GUARD4

CHOLD4

GND

VIN

VPP

SENSE

RUN

SPREAD

DIV0

DIV1

DIV2

OSC

ROSC

COSC

TJMAX = 150°C, θJA = 85°C/W

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT4180EGN#PBF LT4180EGN#TRPBF LT4180GN 24-Lead Narrow Plastic SSOP –40°C to 125°C

LT4180IGN#PBF LT4180IGN#TRPBF LT4180GN 24-Lead Narrow Plastic SSOP –40°C to 125°C

LT4180MPGN#PBF LT4180MPGN#TRPBF LT4180GN 24-Lead Narrow Plastic SSOP –55°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ

cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Operating Supply Voltage l3.10 50 V

IVIN Input Quiescent Current ROSC Open, COSC Open, SENSE = VIN l12 mA

VREF Reference Voltage VCHOLD2 = VCHOLD3 = 1.2V, Measured at CHOLD4

During Track ∆VOUT Clock Phase l

1.209

1.197

1.221

1.233

1.245

ILIM Open-Drain Current Limit With FB = VREF + 200mV, OSC Stopped with Voltage

Feedback Loop Closed

51217 mA

VOL DRAIN Low Voltage VIN = 3V 0.3 V

VINTVCC LDO Regulator Output Voltage VIN = 5V 3.15 V

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C, VIN = SENSE = 5V, unless otherwise noted.

LT4180

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ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. The LT4180E is guaranteed to meet performance speciﬁ cations

from 0°C to 125°C junction temperature. Speciﬁ cations over the –40°C

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C, VIN = SENSE = 5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VINTVCC LDO Regulator Output Voltage in

Dropout

VIN = 2.5V 2.2 V

VOV Overvoltage Threshold Rising 1.21 V

VOHYST Overvoltage Input Hysteresis VRISING – VFALLING 15 80 mV

VRUN Run Threshold Falling 1.21 V

VRHYST Run Input Hysteresis VRISING – VFALLING 15 80 mV

IFB Input Bias Current –0.2 0.2 µA

AV(RATIO) Current Ampliﬁ er Gain Ratio AVL/AVH, AV Measured in V/V 0.891 0.9 0.909

ISENSE Current Ampliﬁ er Input Bias Current Measured at SENSE with SENSE = VIN –1 1 µA

AV∆VFB Ampliﬁ er Gain 9.7 10 10.3 V/V

ICHOLD1 Track/Hold Charging Current Measured at CHOLD1 with VCHOLD1 = 1.2V ±60 µA

ICHOLD2 Track/Hold Charging Current Measured at CHOLD2 with VCHOLD2 = 1.2V ±25 µA

ICHOLD3 Track/Hold Charging Current Measured at CHOLD3 with VCHOLD3 = 1.2V ±25 µA

ICHOLD4 Track/Hold Charging Current Measured at CHOLD4 with VCHOLD4 = 1.5V,

VCHOLD2 = 1V, VCHOLD3 = 1.2V

10 µA

Measured at CHOLD4 with VCHOLD4 = 1.5V,

VCHOLD2 = 1.4V, VCHOLD3 = 1.2V

–200 µA

ISC Soft-Correct Current Measured at CHOLD4 ±1.5 µA

ILKG1 Track/Hold Leakage Current Measured at CHOLD1 with VCHOLD1 = 1.2V ±1 µA

ILKG2 Track/Hold Leakage Current Measured at CHOLD2 with VCHOLD2 = 1.2V ±1 µA

ILKG3 Track/Hold Leakage Current Measured at CHOLD3 with VCHOLD3 = 1.2V ±1 µA

ILKG4 Track/Hold Leakage Current Measured at CHOLD4 with VCHOLD4 = 1.2V ±1 µA

fOSC Oscillator Frequency ROSC = 20k, COSC = 1nF 170 200 230 kHz

gmFB Voltage Error Ampliﬁ er

Transconductance

Measured from FB to COMP, VCOMP = 2V,

OSC Stopped with Voltage Feedback Loop Closed

120 µmho

gmIAMP Current Ampliﬁ er Transconductance Measured from SENSE to COMP, VCOMP = 2V,

OSC Stopped with Current Feedback Loop Closed

700 µmho

to 125°C operating junction temperature range are assured by design

characterization and correlation with statistical process controls. The

LT4180I is guaranteed over the full –40°C to 125°C operating junction

temperature range. The LT4180MP is guaranteed over the full –55°C to

125°C operating junction temperature range.

Note 3. Positive current is deﬁ ned as ﬂ owing into a pin.

LT4180

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TYPICAL PERFORMANCE CHARACTERISTICS

IDRAIN vs VDRAIN Normal Timing Spread Spectrum Timing

VLOAD vs VWIRE

Load Step in

12V Linear Application Load Step in Buck Application

VREF vs Temperature INTVCC vs Temperature

Oscillator Frequency

vs Temperature

VWIRING (V)

VLOAD (V)

4.97

4.98

4.99

4.96

4.95

0.5 1.51 2 2.5 3

4.92

4.91

4.94

5.00

4.93

4180 G07

5ms/DIV

500mA

200mA

200mA TO 500mA LOAD TRANSIENT

100µF LOAD CAP

VSENSE

2V/DIV

VLOAD

2V/DIV

ILOAD

200mA/DIV

4180 G08

RWIRE = 8

5µs/DIV

TRIGGERED ON CHOLD1

500mV/DIV

CHOLD1

WITH 15k

PULL-DOWN

2V/DIV

OSC

4180 G05 1µs/DIV

TRIGGERED ON OSC

500mV/DIV

CHOLD1

WITH 15k

PULL-DOWN

2V/DIV

OSC

4180 G06

10ms/DIV

VSENSE

2V/DIV

VLOAD

2V/DIV

4180 G09

ILOAD

500mA/DIV 500mA

1.5A

RWIRE = 2.5

500mA TO 1.5A LOAD TRANSIENT

470µF LOAD CAP

TEMPERATURE (°C)

–55

VREF (V)

1.2205

1.2210

1.2215

105

1.2200

1.2195

1.2190 –35 –15 5 25 45 65 85 125

4108 G01 TEMPERATURE (°C)

–55

INTVCC (V)

3.150

3.160

3.155

3.165

105

3.145

3.140

3.135 –35 –15 5 25 45 65 85 125

4108 G02

TEMPERATURE (°C)

–55

FREQUENCY (kHz)

203.0

203.5

204.0

105

202.5

202.0

201.5 –35 –15 5 25 45 65 85 125

4108 G03

ROSC = 20k

COSC = 1nF

VDRAIN (V)

IDRAIN (mA)

0.7

0.2 0.4

0.1 0.9

0.3 0.5 0.8

0.6 1

4180 G04

LT4180

4180fa

PIN FUNCTIONS

INTVCC (Pin 1): The LDO Output. A low ESR ceramic

capacitor provides decoupling and output compensation.

1µF or more should be used.

DRAIN (Pin 2): Open-Drain of the Output Transistor. This

pin drives either the LED in an opto-isolator, or pulls down

on the regulator control pin.

COMP (Pin 3): Gate of the Output Transistor. This pin allows

additional compensation. It must be left open if unused.

CHOLD1 (Pin 4): Connects to track/hold ampliﬁ er hold

capacitor. The other end of this capacitor should be Kelvin

connected to GND.

GUARD2 (Pin 5): Guard Ring Drive for CHOLD2.

CHOLD2 (Pin 6): Connects to track/hold ampliﬁ er hold

capacitor. The other end of this capacitor should be Kelvin

connected to GND.

GUARD3 (Pin 7): Guard Ring Drive for CHOLD3.

CHOLD3 (Pin 8): Connects to track/hold ampliﬁ er hold

capacitor. The other end of this capacitor should be Kelvin

connected to GND.

GUARD4 (Pin 9): Guard Ring Drive for CHOLD4.

CHOLD4 (Pin 10): Connects to track/hold ampliﬁ er hold

capacitor. The other end of this capacitor should be Kelvin

connected to GND.

FB (Pin 11): Receives the feedback voltage from an exter-

nal resistor divider across the main output. An (optional)

capacitor to ground may be added to eliminate high

frequency noise. The time constant for this RC network

should be no greater than 0.1 times the dither frequency.

For example, with fDITHER = 1kHz,

= 0.1ms.

GND (Pin 12): Ground.

COSC (Pin 13): Oscillator Timing Capacitor. Oscillator fre-

quency is set by this capacitor and ROSC. For best accuracy,

the minimum recommended capacitance is 100pF.

ROSC (Pin 14): Oscillator Timing Resistor. Oscillator

frequency is set by this resistor and COSC.

OSC (Pin 15): Oscillator Output. This output may be

used to synchronize the switching regulator to the

Virtual Remote Sense. This is a high current output capable

of driving opto-isolators. Other isolation methods may

also be used with this output.

DIV2 (Pin 16): Dither Division Ratio Programming Pin.

DIV1 (Pin 17): Dither Division Ratio Programming Pin.

DIV0 (Pin 18): Dither Division Ratio Programming Pin.

Use the following table to program the dither division

ratio (fOSC/fDITHER)

Table 1. Programming the Dither Division Ratio (fOSC/fDITHER)

DIV2 DIV1 DIV0 DIVISION RATIO

0008

00116

01032

01164

100128

101256

110512

1 1 1 1024

For example, fDITHER = fOSC /128 with DIV2 = 1 and DIV1

= DIV0 = 0.

SPREAD (Pin 19): Spread Spectrum Enable Input. Dither

phasing is pseudo-randomly adjusted when SPREAD is

tied high.

OV (Pin 20): Overvoltage Comparator Input. This prevents

line drop correction when wiring drops would cause ex-

cessive switching power supply output voltage. Set OV

so VREG(MAX) ≤ 1.50VLOAD.

RUN (Pin 21): The RUN pin provides the user with an accu-

rate means for sensing the input voltage and programming

the start-up threshold for the line drop corrector.

SENSE (Pin 22): Current Sense Input. This input connects

to the current sense resistor. Kelvin connect to RSENSE.

VPP (Pin 23): Connect this pin to INTVCC.

VIN (Pin 24): Main Supply Pin. VIN

must be locally bypassed

to ground. Kelvin connect the current sense resistor to

this pin and minimize interconnect resistance.

LT4180

4180fa

BLOCK DIAGRAM

4180 BD

CORRECTED _REF

–

GM2

–

+–

GM1

TRACK/

HOLD

+–

IAMP

TRACK/

HOLD

–

INST

AMP

TRACK/

HOLD

TRACK/

HOLD

TRACK_HI_FB TRACK_LOW_FB TRACK_DELTA_FB

REF

REF_OK

CHOLD2

5GUARD2

7GUARD3

9GUARD4

12 GND

4CHOLD1

CHOLD3

CHOLD4

3COMP

2DRAIN

21 RUN

ROSC

COSC

20 OV

TRACK_HI_I

FB_SELECT

OVERVOLTAGE

UNDERVOLTAGE

BANDGAP

SENSE

INTVCC

24 VIN

LDO

VPP

TRIM

CIRCUIT

HI_GAIN

RLIM

SPREAD

DIV0

DIV1

DIV2

OSC

SPREAD

SPECTRUM

CLOCK

GENERATOR

OSC

MOD

CLK

LT4180

4180fa

OPERATION

Voltage drops in wiring can produce considerable load

regulation errors in electrical systems (Figure 1). As

load current, IL, increases the voltage drop in the wiring

(IL • RW) increases and the voltage delivered to the system

(VL) drops. The traditional approach to solving this problem,

remote sensing, regulates the voltage at the load, increas-

ing the power supply voltage (VOUT) to compensate for

voltage drops in the wiring. While remote sensing works

well, it does require an additional pair of wires to measure

at the load, which may not always be practical.

The LT4180 eliminates the need for a pair of remote sense

wires by creating a Virtual Remote Sense. Virtual remote

sensing is achieved by measuring the incremental change

in voltage that occurs with an incremental change in current

in the wiring (Figure 2). This measurement can then be

used to infer the total DC voltage drop in the wiring, which

can then be compensated for. The Virtual Remote Sense

takes over control of the power supply via the feedback

pin (VFB) of the power supply maintaining tight regulation

of load voltage, VL.

The LT4180 operates by modulating the output current of

the regulator and looking at the resulting voltage change.

A large output capacitor is placed across the load so the

AC impedance at the load is low.

[Normally, a capacitor

appears across the load in remote sensing situations to

keep the impedance low at that point].

This capacitor is

large enough that the AC impedance at the load is very low

compared to the line resistance. When the output current

is modulated, any voltage change that appears across the

terminals of the LT4180 is due to the resistance in the line

since the AC resistance at the load is very low.

There are four sample-and-hold capacitors in the LT4180.

The operation cycles through several stages to obtain the

correction voltage. First, the output voltage is regulated

and the control point is sampled and held. The control

loop is then switched to a current regulating control loop

and the output current is changed by 10%. Two sample-

and-hold currents store the voltage at the high current and

low current level of the modulation. This voltage change

is the result of a 10% change in current, making the volt-

age change 10% of the total drop in the line. The voltage

change is ampliﬁ ed by a factor of 10.

The ampliﬁ ed voltage change that occurs with the current

is again sampled and held and is used as the correction

voltage. The correction voltage is summed into the output

and this corrects for the line drop. Since this correction

is actually open-loop, the actual voltage at the load is not

measured. The ability of the LT4180 to correct for line drops

is dependent upon the accuracy of the computations.

The LT4180 can correct better than 50 to 1 for line drops.

For example, a 10V drop in the line becomes a 200mV

change at the load.

The frequency of the correction cycle can be set from over

32kHz down to less than 250Hz, depending on the size of

the capacitors in the system. For very large capacitors in

high current systems, the dither correction clock would be

run more slowly. In simpler systems with smaller output

capacitors, the dither can be run at a higher frequency. If

the load contains frequencies similar to the dither, beat

notes can result between the load and the LT4180. A

spread spectrum option on the LT4180 allows the device

to change phasing during the correction cycle so that it

will not interfere with load pulses.

Finally, the LT4180 takes into account all resistances be-

tween the LT4180 and the load capacitor. It can correct for

cable connections, line resistances and varying contact

resistances. By measuring the peak change at the output

of the LT4180 one can monitor the impedance between the

LT4180 and the load, and detect increasing impedances

Figure 1. Traditional Remote Sensing Figure 2. Virtual Remote Sensing

4180 F02

POWER WIRING

VIRTUAL REMOTE

SENSE

POWER SUPPLY +

–

VOUT

VFB

SYSTEM

–

4180 F01

POWER WIRING

REMOTE SENSE WIRING

POWER SUPPLY +

–

VOUT

SYSTEM

–

LT4180

4180fa

INTRODUCTION

The LT4180 is designed to interface with a variety of power

supplies and regulators having either an external feedback

or control pin. In Figure 4, the regulator error ampliﬁ er

(which is a gm ampliﬁ er) is disabled by tying its inverting

input to ground. This converts the error ampliﬁ er into a

constant-current source which is then controlled by the

drain pin of the LT4180. This is the preferred method of

interfacing because it eliminates the regulator error ampli-

ﬁ er from the control loop which simpliﬁ es compensation

and provides best control loop response.

APPLICATIONS INFORMATION

Figure 4. Nonisolated Regulator Interface

For proper operation, increasing control voltage should

correspond to increasing regulator output. For example,

in the case of a current mode switching power supply, the

control pin ITH should produce higher peak currents as

the ITH pin voltage is made more positive.

Figure 5. Isolated Power Supply Interface

Figure 6. Cascoded DRAIN Pin for Isolated Supplies

DRAIN

4180 F04

LT4180

ITH OR

REGULATOR

–

DRAIN

4180 F05

LT4180

INTVCC

REGULATOR

OPTO-COUPLER

–

DRAIN

4180 F06

INTVCC

LT4180

TO VC > 5V

COMP

from degrading contacts. Making the capacitor larger can

minimize the voltage ripple at the load due to a combination

of load regulation and the dither frequency of the LT4180.

Figure 3 shows the timing diagram for Virtual Remote

Sense. A new cycle begins when the power supply and

Virtual Remote Sense close the loop around VOUT (regulate

VOUT = H). Both VOUT and IOUT slew and settle to a new

value, and these values are stored in the Virtual Remote

Sense (track VOUT high = L and track IOUT = L). The VOUT

feedback loop is opened and a new feedback loop is set

up commanding the power supply to deliver 90% of the

previously measured current (0.9IOUT). VOUT drops to a new

value as the power supply reaches a new steady state, and

this information is also stored in the Virtual Remote Sense.

At this point, the change in output voltage (∆VOUT) for a Figure 3. Simpliﬁ ed Timing Diagram, Virtual Remote Sense

VOUT

TRACK ∆VOUT

REGULATE VOUT

TRACK VOUT HIGH

TRACK IOUT

REGULATE IOUT LOW

TRACK VOUT LOW

4180 F03

Isolated power supplies and regulators may also be used

by adding an opto-coupler (Figure 5). LT4180 output volt-

age INTVCC supplies power to the opto-coupler LED. In

situations where the control pin VC of the regulator may

exceed 5V, a cascode may be added to keep the DRAIN

pin of the LT4180 below 5V (Figure 6). Use a low VT

MOSFET for the cascode transistor.

–10% change in output current has been measured and

is stored in the Virtual Remote Sense. This voltage is used

during the next Virtual Remote Sense cycle to compensate

for voltage drops due to wiring resistance.

OPERATION

LT4180

4180fa

APPLICATIONS INFORMATION

DESIGN PROCEDURE

The ﬁ rst step in the design procedure is to determine

whether the LT4180 will control a linear or switching sup-

ply/regulator. If using a switching power supply or regulator,

it is recommended that the supply be synchronized to the

LT4180 by connecting the OSC pin to the SYNC pin (or

equivalent) of the supply.

If the power supply is synchronized to the LT4180, the

power supply switching frequency is determined by:

fOSC=4

ROSC •C

OSC

Recommended values for ROSC are between 20k and 100k

(with 30.1k the optimum for best accuracy) and greater

than 100pF for COSC. COSC may be reduced to as low as

50pF, but oscillator frequency accuracy will be somewhat

degraded.

The following example synchronizes a 250kHz switching

power supply to the LT4180. In this example, start with

ROSC = 30.1k:

COSC =4

250kHz • 30.1k =531pF

This example uses 470pF. For 250kHz:

ROSC =4

250kHz • 470pF =34.04k

The closest standard 1% value is 34k.

The next step is to determine the highest practical dither

frequency. This may be limited either by the response

time of the power supply or regulator, or by the propaga-

tion time of the wiring connecting the load to the power

supply or regulator.

First determine the settling time (to 1% of ﬁ nal value)

of the power supply. The settling time should be the

worst-case value (over the whole operating envelope: VIN,

ILOAD, etc.).

F1 =1

2•t

SETTLING

For example, if the power supply takes 1ms to settle

(worst-case) to within 1% of ﬁ nal value:

F1 =1

2•1e–3=500Hz

Next, determine the propagation time of the wiring. In

order to ignore transmission line effects, the dither period

should be approximately twenty times longer than this.

This will limit dither frequency to:

F2 =V

20 • 1.017ns/ft • L Hz

Where VF is the velocity factor (or velocity of propagation),

and L is the length of the wiring (in feet).

For example, assume the load is connected to a power

supply with 1000ft of CAT5 cable. Nominal velocity of

propagation is approximately 70%.

F2 =0.7

20 • 1.017e–9 • 1000 =34.4kHz

The maximum dither frequency should not exceed F1 or

F2 (whichever is less):

DITHER < min (F1, F2).

Continuing this example, the dither frequency should be

less than 500Hz (limited by the power supply).

With the dither frequency known, the division ratio can

be determined:

DRATIO =fOSC

fDITHER

=250,000

500 =500

The nearest division ratio is 512 (set DIV0 = L, DIV1 =

DIV2 = H). Based on this division ratio, nominal dither

frequency will be:

fDITHER =fOSC

DRATIO

=250,000

512 =488Hz

After the dither frequency is determined, the minimum

load decoupling capacitor can be determined. This load

capacitor must be sufﬁ ciently large to ﬁ lter out the dither

signal at the load.

LT4180

4180fa

APPLICATIONS INFORMATION

CLOAD =2.2

RWIRE •2• f

DITHER

Where CLOAD is the minimum load decoupling capacitance,

RWIRE is the minimum wiring resistance of one conduc-

tor of the wiring pair, and fDITHER is the minimum dither

frequency.

Continuing the example, our CAT5 cable has a maximum

9.38Ω/100m conductor resistance.

Maximum wiring resistance is:

WIRE = 2 • 1000ft • 0.305m/ft • 0.0938Ω/m

WIRE = 57.2Ω

With an oscillator tolerance of ±15%, the minimum

dither frequency is 414.8Hz, so the minimum decoupling

capacitance is:

CLOAD =2.2

57.2Ω• 2 • 414.8Hz =46.36µF

This is the minimum value. Select a nominal value to ac-

count for all factors which could reduce the nominal, such

as initial tolerance, voltage and temperature coefﬁ cients

and aging.

CHOLD Capacitor Selection and Compensation

CHOLD1

A 47nF capacitor will sufﬁ ce for most applications. A

smaller value might allow faster recovery from a sudden

load change, but care must be taken to ensure full load

p-p ripple at this node is kept within 5mV:

CHOLD2 =CHOLD3 =2.5nF

fDITHER(kHz)

For a dither frequency of 488Hz:

CHOLD2 =CHOLD3 =2.5nF

0.488(kHz) =5.12nF

NPO ceramic or other capacitors with low leakage and di-

electric absorption should be used for all HOLD capacitors.

Set CHOLD4 to 1µF. This value will be adjusted later.

Compensation

Start with a 47pF capacitor between the COMP and DRAIN

pins of the LT4180. Add an RC network in parallel with the

47pF capacitor, 10k and 10nF are good starting values.

Once the output voltage has been conﬁ rmed to regulate

at the desired level at no load, increase the load current

to the100% level and monitor the wire current (Dither

Current) with a current probe. Verify the Dither Current

resembles a square-wave with the desired dither frequency.

If the output voltage is too low, increase the value of the

10k resistor until some overshoot is observed at the leading

edge of the dither current waveform. If the output voltage

is still too low, decrease the value of the 10nF capacitor

and repeat the previous step. Repeat this process until the

full load output voltage increases to within 1% below the

no load level. Refer to Figures 7a, 7b and 7c, which show

compensation of the 12V 1.5A Buck Regulator Application

on the datasheet. Check for proper voltage drop correction

over the load range. The “Dither Current” should have

good half-wave symmetry. Namely, waveform should have

similar rise and fall times, enough settling time at top and

bottom and minimum to no over/undershoot.

20µs/DIV

VLOAD

11.2V

IDITHER

50mA/DIV

4180 F07a

Figure 7a. Dither Current and VOUT with

10nF, 10k Compensation 1.5A Load

LT4180

4180fa

APPLICATIONS INFORMATION

20µs/DIV

VLOAD

11.9V

4180 F07b

IDITHER

500mA/DIV

Figure 7b. Dither Current and VOUT with

10nF, 37k Compensation 1.5A Load

Figure 8a. 500mA to 1A Transient Response

Test with CHOLD4 = 25nF CHOLD4 Too Small

Figure 7c. Dither Current and VOUT with

3.3nF, 28k Compensation 1.5A Load

Figure 8b. 500mA to 1A Transient Response Test

with CHOLD4 = 47nF Nicely Damped Behavior

20µs/DIV

VLOAD

11.9V

4180 F07c

IDITHER

50mA/DIV

Set Final Value of CHOLD4

Set the minimum value for CHOLD4, by performing a

transient load test of 30% to 60% of the load and set the

value of CHOLD4 to where a nicely damped waveform is

observed. Refer to Figures 8a and 8b for an illustration.

10ms/DIV

VLOAD

1V/DIV

4180 F08a

IDITHER

500mA/DIV

VLOAD

1V/DIV

4180 F08b

IDITHER

500mA/DIV

After all the CHOLD values have been ﬁ nalized, check for

proper voltage drop correction and converter behavior

(start-up, regulation etc.), over the load and input volt-

age ranges.

Setting Output Voltage, Undervoltage and Overvoltage

Thresholds

The RUN pin has accurate rising and falling thresholds

which may be used to determine when Virtual Remote Sense

operation begins. Undervoltage threshold should never

be set lower than the minimum operating voltage of the

LT4180 (3.1V).

The overvoltage threshold should be set slightly greater

than the highest voltage which will be produced by the

power supply or regulator:

OUT(MAX) = VLOAD(MAX) + VWIRE(MAX)

VOUT(MAX) should never exceed 1.5 • VLOAD

Since the RUN and OV pins connect to MOSFET input

comparators, input bias currents are negligible and a com-

mon voltage divider can be used to set both thresholds

(Figure 9).

LT4180

4180fa

APPLICATIONS INFORMATION

Figure 9. Voltage Divider for Output Voltage, UVL and OVL

The voltage divider resistors can be calculated from the

following equations:

RT=VOV

200µA ,R4=1.22V

200µA

Where RT is the total divider resistance and VOV is the

overvoltage set point.

Find the equivalent series resistance for R2 and R3 (RSERIES).

This resistance will determine the RUN voltage level.

RSERIES =1.22 • RT

UVL

⎛

⎝

⎜⎞

⎠

⎟−R4

R1=RT−RSERIES −R4

R3 =

1.22V −VOUT(NOM) •R4

⎛

⎝

⎜⎞

⎠

⎟

VOUT(NOM)

R2 =RSERIES −R3

Where VUVL is the RUN voltage and VOUT(NOM) is the

nominal output voltage desired.

For example, with VUVL = 4V, VOV = 7.5V and VOUT(NOM) = 5V,

RT=7.5V

200µA =37.5k

R4 =1.22V

200µA =6.1k

RSERIES =1.22V • 37.5k

⎛

⎝

⎜⎞

⎠

⎟−6.1k =5.34k

R1 =37.5k −5.34k −6.1k =26.06k

R3 =

1.22V −5V • 6.1k

37.5k

⎛

⎝

⎜⎞

⎠

⎟

37.5k

=3.05k

R2 =RSERIES −R3 =2.29k

RSENSE SELECTION

Select the value of RSENSE so that it produces a 100mV

voltage drop at maximum load current. For best accuracy,

VIN and SENSE should be Kelvin connected to this resistor.

Figure 10. Soft-Correct Operation, CHOLD4 = 1μF

4180 F09

RUN

LT4180

VIN

200ms/DIV 4180 F08

POWER SUPPLY

OUTPUT VOLTAGE

10Vw

POWER SUPPLY

INPUT VOLTAGE

Soft-Correct Operation

The LT4180 has a soft-correct function which insures

orderly start-up. When the RUN pin rising threshold is

ﬁ rst exceeded (indicating VIN has crossed its undervoltage

lockout threshold), power supply output voltage is set to

a value corresponding to zero wiring voltage drop (no

correction for wiring). Over a period of time (determined

by CHOLD4), the power supply output voltage ramps up to

account for wiring voltage drops, providing best load-end

voltage regulation. A new soft-correct cycle is also initiated

whenever an overvoltage condition occurs.

LT4180

4180fa

APPLICATIONS INFORMATION

Using Guard Rings

The LT4180 includes a total of four track/holds in the

Virtual Remote Sense path. For best accuracy, all leakage

sources on the CHOLD pins should be minimized.

At very low dither frequencies, the circuit board layout

may include guard rings which should be tied to their

respective guard ring drivers.

To better understand the purpose of guard rings, a simpliﬁ ed

model of hold capacitor leakage (with and without guard

rings) is shown in Figure 11. Without guard rings, a large

difference voltage may exist between the hold capacitor

(Pin 1) node and adjacent conductors (Pin 2) producing

substantial leakage current through the leakage resistance

(RLKG). By adding a guard ring driver with approximately

the same voltage as the voltage on the hold capacitor node,

the difference voltage across RLKG1 is reduced substantially

thereby reducing leakage current on the hold capacitor.

Figure 12. Clock Interface for Synchronization

OSCSYNC

4180 F12

LT4180

REGULATOR

Figure 11. Simpliﬁ ed Leakage Models

(with and without Guard Rings)

4180 F11

RLKG

WITH

GUARD RING

WITHOUT

GUARD RING

RLKG1 RLKG2

Spread Spectrum Operation

Virtual Remote Sense functionality relies on sampling

techniques. Because switching power supplies are

commonly used, the LT4180 uses a variety of techniques

to minimize potential interference (in the form of beat

notes which may occur between the dither frequency and

power supply switching frequency). Besides several types

of internal ﬁ ltering, and the option for Virtual Remote

Sense/power supply synchronization, the LT4180 also

provides spread spectrum operation.

By enabling spread spectrum operation, low modula-

tion index pseudo-random phasing is applied to

Virtual Remote Sense timing. This has the effect of

converting any remaining narrow-band interference into

broadband noise, reducing its effect.

Increasing Voltage Correction Range

Correction range may be slightly improved by regulating

INTVCC to 5V. This may be done by placing an LDO between

VIN and INTVCC. Contact Linear Technology Applications

for more information.

Synchronization

Linear and switching power supplies and regulators may

be used with the LT4180. In most applications regulator

interference should be negligible. For those applications

where accurate control of interference spectrum is de-

sirable, an oscillator output has been provided so that

switching supplies may be synchronized to the LT4180

(Figure 12). The OSC pin was designed so that it may

directly connect to most regulators, or drive opto-isolators

(for isolated power supplies).

LT4180

4180fa

TYPICAL APPLICATIONS

12V, 500mA Linear Regulator

12V, 500mA Boost Regulator

R11

15k 1%

5.36k

FB DIV0DIV1

VIN INTVCC

INTVCC

VPP

COMP GND

DRAIN

DIV2

CHOLD1 CHOLD2GUARD2 GUARD3 GUARD4CHOLD3 CHOLD4

C12

47nF

4180 TA03

RUN

ROSC

COSC

SENSE

SPREAD

LT4180EGN

C13

470pF

C11

470pF

C10

470pF

47nF

47pF

DFLS220

4.7µH OUTPUT TO WIRING AND LOAD

(100mA MINIMUM)

500mA, 6 MAX RWIRE

100µF LOAD CAPACITANCE

VISHAY

IHLP2525CZ-11

1µF

R12

41.7k

10nF

3.65k

61.9k

R13

1.5k

1µF

0.2

OSC

GND

VIN

0.1µF

R10

84.5k

FAULT

SHDN

VCC

SYNC RT SS CLKOUT GND

GATE SW1 SW1 SW1 SW2 SW2 SW2

LT3581EMSE

191k

24.3k

10k

100k

10µF

25V

4.7µF

16V

200k

FB DIV0DIV1

VIN INTVCC

INTVCC

VPP

COMP GND

DRAIN

DIV2

CHOLD1 CHOLD2GUARD2 GUARD3 GUARD4CHOLD3 CHOLD4

C10

33nF

4180 TA02

RUN

ROSC

COSC

2.2k

SENSE

SPREAD

LT4180EGN

C11

470pF

47nF

IRLZ440 OUTPUT TO WIRING AND LOAD

500mA

8 MAX RWIRE

100µF LOAD CAPACITANCE

1µF

41.7k

3.74k

63.4k

1% C3

1µF

0.2

OSC

GND

VIN

20V

27k

10µF

25V

4.7µF

25V

5.36k

INTVCC

330pF

VN2222

10k

LT4180

4180fa

TYPICAL APPLICATIONS

3.3V Isolated Flyback Regulator

R17

10.7k

R13

5.36k

FB DIV0DIV1

VIN

VOUT

SS VIN

VIN

INTVCC

INTVCC2

VPP

COMP GND

DRAIN

DIV2

PULSE ENGINEERING PA1277NL

PA1277NL

CHOLD1 CHOLD2GUARD2 GUARD3 GUARD4CHOLD3 CHOLD4

C15

0.1µF

4180 TA04

RUN

ROSC

COSC

R10

2.74k

SENSE

SPREAD

LT4180EGN

C16

470pF

C14

470pF

C13

470pF

C12

47nF

C11

47pF

BAV21W

BAS516

Si4848DY

PS2801-1

OUTPUT TO WIRING AND LOAD

3.3V, 3A

0.4 MAX RWIRE

4 × 470µF, AUX TPSE 477M010R0050

LOAD CAPACITANCE

1µF

R15

41.2k

C17

15nF

523

13.3k

1µF

0.033

SHDN/

UVLO SYNC

GND

GATEVC

SENSE

0.1µF

R16

36.5k

105k

INTVCC2

INTVCC

R14

8.66k

OSC OSC

VIN

18V TO 72V

GND

123

5678

78 32

UPS840

100µF

10V

100µF

10V

10k

4700pF

CIN2

1µF

100V

CIN1

1µF

100V

9.1k

LT3758

EMSE

R12

100

4.7µF

50V

C18

2200pF

250V

VIN

51.1 1%

R7, 1

0.01µF

R11

1.3k

C10

(OPT.)

RCS1

0.033

LT4180

4180fa

PACKAGE DESCRIPTION

GN Package

24-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.337 – .344*

(8.560 – 8.738)

GN24 (SSOP) 0204

345678 9 10 11 12

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

161718192021222324 15 14 13

.016 – .050

(0.406 – 1.270)

.015 .004

(0.38 0.10) × 45°

0 – 8 TYP

.0075 – .0098

(0.19 – 0.25)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.033

(0.838)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 .0015

.045 .005

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LT4180

4180fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 6/11 Revised Typical Applications drawings

Revised Electrical Characteristics

Replaced curves G08 and G09 in Typical Performance Characteristics

Replaced text for CHOLD Capacitor Selection and Compensation section and deleted Power Supply Current Limiting

paragraph in Applications Information section

1, 13, 14, 18

2, 3

10, 11

LT4180

4180fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0611 REV A • PRINTED IN USA

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