ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 1 -
GENERAL DESCRIPTION
The AK4112B is a digital audio receiver (DIR) compatible with 96kHz, 24bits. The channel status
decoding supports both consumer and professional modes. The AK4112B can automatically detect a
Non-PCM bit stream. When combined with an AK4527B multi channel codec, the two chips provide a
system solution for AC-3 applications. The dedicated pins or a serial µP I/F can control the mode setting.
The small package, 28pin VSOP saves the board space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
o Supports AES/EBU, IEC958, S/PDIF, EIAJ CP1201
o Low jitter Analog PLL
o PLL Lock Range: 22k~108kHz
o Clock Source: PLL or X'tal
o 4 channel Receivers input and 1 through transmission output
o Auxiliary digital input
o De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
o Dedicated Detect Pins
- Non-PCM Bit Stream Detect Pin
- Validity Flag Detect Pin
- 96kHz Sampling Detect Pin
- Unlock & Parity Error Detect Pin
o Supports up to 24bit Audio Data Format
o Audio I/F: Master or Slave Mode
o 32bits Channel Status Buffer
o Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream
o Serial µP I/F
o Two Master Clock Outputs: 128fs/256fs/512fs
o Operating Voltage: 2.7 to 3.6V with 5V tolerance
o Small Package: 28pin VSOP
o Ta: -40~85°C
High Feature 96kHz 24bit DIR
AK4112B
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 2 -
Input
Selector
System
Control
Clock
Recovery
Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect
Error
Detect
DEM
µp I/F
Audio
I/F
96kHz
Detect
X'tal
Oscillator
RX1
RX2
RX3
RX4
V/TX
DVDD
DVSS
PDN
AUTO
ERF
TVDD
LRCK
BICK
SDTO
DAUX
FS96
XTO
XTI
MCKO2
MCKO1
R
AVDD
AVSS
CDTI
CDTO
CCLK
CSN
Serial Control Mode
System
Control
Clock
Recovery
Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect
Error
Detect
DEM
Audio
I/F
96kHz
Detect
X'tal
Oscillator
RX1
V
DVDD
DVSS
AUTO
ERF
TVDD
LRCK
BICK
SDTO
DAUX
FS96
XTO
XTI
MCKO2
MCKO1
R
AVDD
AVSS
CM1
CM0
OCKS1
OCKS0
OCKS0
PDN
OCKS1
CM0
CM1
DIF0
DIF1
DIF2
4
Parallel Control Mode
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 3 -
n Ordering Guide
AK4112BVF -40 ~ +85 °C 28pin VSOP (0.65mm pitch)
n
Pin Layout
6
5
4
3
2
1
DVDD
DVSS
V/TX
TVDD
XTI
XTO
PDN 7
R8
Top
View
10
9
AVDD
AVSS
RX1 11
RX2/DIF0 12
13
14
RX3/DIF1
RX4/DIF2
CM0/CDTO
CM1/CDTI
OCKS1/CCLK
OCKS0/CSN
MCKO1
MCKO2
DAUX
BICK
SDTO
LRCK
ERF
FS96
23
24
25
26
27
28
22
21
19
20
18
17
16
15
P/SN
AUTO
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 4 -
PIN/FUNCTION
No. Pin Name I/O Function
1 DVDD - Digital Power Supply Pin, 3.3V
2 DVSS - Digital Ground Pin
3 TVDD - Input Buffer Power Supply Pin, 3.3V or 5V
V O Validity Flag Output Pin in Parallel Mode
4 TX O Transmit channel (through data) Output Pin in Serial Mode
5 XTI I X'tal Input Pin
6 XTO O X'tal Output Pin
7 PDN I Power-Down Mode Pin
When “L”, the AK4112B is powered-down and reset.
8 R - External Resistor Pin
18kΩ +/-1% resistor to AVSS externally.
9 AVDD - Analog Power Supply Pin
10 AVSS - Analog Ground Pin
11 RX1 I Receiver Channel 1
This channel is selected in Parallel Mode or default of Serial Mode.
DIF0 I Audio Data Interface Format 0 Pin in Parallel Mode
12 RX2 I Receiver Channel 2 in Serial Mode
DIF1 I Audio Data Interface Format 1 Pin in Parallel Mode
13 RX3 I Receiver Channel 3 in Serial Mode
DIF2 I Audio Data Interface Format 2 Pin in Parallel Mode
14 RX4 I Receiver Channel 4 in Serial Mode
15 AUTO O Non-PCM Detect Pin
“L”: No detect, “H” : Detect
16 P/S I Parallel/Serial Select Pin
“L”: Serial Mode, “H”: Parallel Mode
17 FS96 O 96kHz Sampling Detect Pin
(RX Mode) “H” : fs=88.2kHz or more, “L” fs=54kHz or less.
(X’tal Mode) “H” : XFS96=1, “L” : XFS96=0.
18 ERF O Unlock & Parity Error Output Pin
“L”: No Error, “H”: Error
19 LRCK I/O Output Channel Clock Pin
20 SDTO O Audio Serial Data Output Pin
21 BICK I/O Audio Serial Data Clock Pin
22 DAUX I Auxiliary Audio Data Input Pin
23 MCK02 O Master Clock #2 Output Pin
24 MCK01 O Master Clock #1 Output Pin
OCKS0 I Output Clock Select 0 Pin in Parallel Mode
25 CSN I Chip Select Pin in Serial Mode
OCKS1 I Output Clock Select 1 Pin in Parallel Mode
26 CCLK I Control Data Clock Pin in Serial Mode
CM1 I Master Clock Operation Mode Pin0 in Parallel Mode
27 CDTI I Control Data Input Pin in Serial Mode
CM0 I Master Clock Operation Mode Pin1 in Parallel Mode
28 CDTO O Control Data Output Pin in Serial Mode
Note 1: All input pins except internal pull-down pins should not be left floating.
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 5 -
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2)
Parameter Symbol min max Units
Power Supplies:
Analog
Digital
Input Buffer
|AVSS-DVSS| (Note 3)
AVDD
DVDD
TVDD
∆ GND
-0.3
-0.3
-0.3
4.6
4.6
6.0
0.3
V
V
V
V
Input Current , Any Pin Except Supplies IIN - ±10 mA
Input Voltage (Except XTI pin)
Input Voltage (XTI pin) VIN
VINX -0.3
-0.3 TVDD+0.3
DVDD+0.3 V
V
Ambient Temperature (power applied) Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Note 2: All voltages with respect to ground.
Note 3: AVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V;Note 2)
Parameter Symbol min typ max Units
Power Supplies:
Analog
Digital
Input Buffer
AVDD
DVDD
TVDD
2.7
2.7
DVDD
3.3
3.3
3.3
3.6
AVDD
5.5
V
V
V
Note 2: All voltages with respect to ground.
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V)
Parameter Symbol min typ max Units
Input Resistance Zin 10 kΩ
Input Voltage VTH 350 mVpp
Input Hysteresis VHY - 130 mV
Input Sample Frequency fs 22 - 108 kHz
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified)
Parameter Symbol min typ max Units
Power Supply Current
Normal operation : PDN = “H” (Note 4)
Power down: PDN = “L” (Note 5)
20
10
40
100
mA
µA
High-Level Input Voltage (Except XTI pin)
High-Level Input Voltage (XTI pin)
Low-Level Input Voltage
VIH
VIH
VIL
70%DVDD
70%DVDD
DVSS-0.3
-
-
-
TVDD
DVDD
30%DVDD
V
V
V
High-Level Output Voltage (Iout=-400µA)
Low-Level Output Voltage (Iout=400µA) VOH
VOL DVDD-0.4
- -
- -
0.4 V
V
Input Leakage Current Iin - - ± 10 µA
Note 4: AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=96kHz, X'tal=12.288MHz,
Clock Operation Mode 2, OCKS1=1, OCKS0=0.
AVDD=8mA(typ), DVDD=12mA(typ), TVDD=10µA(typ)
Note 5: RX inputs are open and all digital input pins are held DVDD or DVSS.
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 6 -
SWITCHING CHARACTERISTICS
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz
External Clock Frequency
Duty fECLK
dECLK 11.2896
40
50 24.576
60 MHz
%
MCKO1 Output Frequency
Duty fMCK1
dMCK1 5.632
40
50 27.648
60 MHz
%
MCKO2 output Frequency
Duty fMCK2
dMCK2 2.816
40
50 27.648
60 MHz
%
PLL Clock Recover Frequency (RX1-4) fpll 22 - 108 kHz
LRCK Frequency
Duty Cycle fs
dLCK 22
45 48
108
55 kHz
%
Audio Interface Timing
Slave Mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (Note 6)
BICK “↑” to LRCK Edge (Note 6)
LRCK to SDTO (MSB)
BICK “↓” to SDTO
DAUX Hold Time
DAUX Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRM
tBSD
tDXH
tDXS
140
60
60
30
30
20
20
35
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
Master Mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
DAUX Hold Time
DAUX Setup Time
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
-20
20
20
64fs
50
20
40
Hz
%
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK "↑" to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
200
80
80
50
50
150
50
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN
Pulse Width
tPW
150
ns
Note 6: BICK rising edge must not occur at the same time as LRCK edge.
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 7 -
n Timing Diagram
tLRB
LRCK
BICK
SDTO
tBSD
tBLR tBCKL tBCKH
tLRM
50%DVDD
50%DVDD
50%DVDD
DAUX 50%DVDD
tDXS tDXH
Serial Interface Timing (Slave Mode)
LRCK
BICK
SDATA
tBSD
tMBLR
50%DVDD
50%DVDD
50%DVDD
DAUX
tDXH
50%DVDD
tDXS
Serial Interface Timing (Master Mode)
tCCKL
CSN
CCLK
tCDS
CDTI
tCDH
tCSS
C0
A4
tCCKH
CDTO Hi-Z
R/W
C0
50%DVDD
50%DVDD
50%DVDD
WRITE/READ Command Input Timing
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 8 -
tCSW
CSN
CCLK
CDTI D2 D0
tCSH
CDTO Hi-Z
D1D3
50%DVDD
50%DVDD
50%DVDD
WRITE Data Input Timing
CSN
CCLK
tDCD
CDTO D7 D6
CDTI A1 A0
D5
Hi-Z
50%DVDD
50%DVDD
50%DVDD
50%DVDD
READ Data Output Timing 1
CSN
CCLK
tCCZ
CDTO D2 D1
CDTI
D0
D3
tCSW
tCSH
50%DVDD
50%DVDD
50%DVDD
50%DVDD
READ Data Input Timing 2
tPW
PDN 30%DVDD
Power Down & Reset Timing
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 9 -
OPERATION OVERVIEW
n Non-PCM (AC-3, MPEG, etc.) Stream Detect
The AK4112B has a Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC958 Interface” is detected, the AUTO goes “H”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “H”. Once the AUTO is set
“H”, it will remain “H” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers
0DH-10H.
n Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 22kHz to 108kHz and the lock time is less than 20ms. The 96kHz
detect output pin FS96 goes “H” when the sampling rate is 88.2kHz or more and “L” at 54kHz or less. In X’tal Mode, the
FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect.
n Master Clock
The AK4112B has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2.
No. OCKS1 OCKS0 MCKO1 MCKO2 X’tal fs (kHz)
0 0 0 256fs 256fs 256fs 32, 44.1, 48, 96 Default
1 0 1 256fs 128fs 256fs 32, 44.1, 48, 96
2 1 0 512fs 256fs 512fs 32, 44.1, 48
3 1 1 Test Mode
Table 1. Master clock frequencies select
n Clock Operation Mode
The CM0 and CM1 select the clock source of MCKO1/2 and the data source of SDTO via the dedicated pins or the
control register. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the
clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored.
Mode CM1 CM0 UNLOCK PLL X'tal Clock source FS96 SDTO
0 0 0 - ON OFF PLL RFS96 RX Default
1 0 1 - OFF ON X'tal XFS96 DAUX
0 ON ON PLL RFS96 RX
2 1 0 1 ON ON X'tal XFS96 DAUX
3 1 1 - ON ON X'tal XFS96 DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Table 2. Clock Operation Mode select
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 10 -
n Clock Source
The following circuits are available to feed the clock to XTI pin (#5 pin) of AK4112B.
1) X’tal
XTI
XTO AK4112B
Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF)
2) External clock
XTI
XTO AK4112B
External Clock
Note: Input clock must not exceed DVDD.
3) Fixed to the Clock Operation Mode 0
XTI
XTO AK4112B
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 11 -
n Sampling Frequency and Pre-emphasis Detect
The AK4112B outputs the encoded information of sampling frequency and pre-emphasis in channel status to FS0, FS1
and PEM bits in control register. These information are output from channel 1 at default. It can be switched to channel 2
by CS12 bit in control register.
FS1 FS0 fs Byte 3
Bits 0-3
0 0 44.1kHz 0000
0 1 Reserved all others
1 0 48kHz 0100
1 1 32kHz 1100
Table 3. fs information in Consumer Mode
FS1 FS0 fs Byte 0
Bits 6-7
0 0 44.1kHz 10
0 1 Reserved 00
1 0 48kHz 01
1 1 32kHz 11
Table 4. fs information in Profession Mode
PEM Pre-emphasis Byte 0
Bits 3-5
0 OFF ≠ 0X100
1 ON 0X100
Table 5. PEM in Consumer Mode
PEM Pre-emphasis Byte 0
Bits 2-4
0 OFF ≠110
1 ON 110
Table 6. PEM in professional Mode
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
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n De-emphasis Filter Control
The AK4112B includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to four sampling
frequencies (32kHz, 44.1kHz, 48kHz and 96kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically
by sampling frequency and pre-emphasis information in the channel status. The AK4112B goes this mode at default.
Therefore, in Parallel Mode, the AK4112B is always placed in this mode and the de-emphasis filter is controlled by the
status bits in channel 1. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU is “0”.
When the “0” data is input to the de-emphasis filter, the output data will be “0” or “-1”. The internal de-empahsis filter is
bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis Mode is OFF.
FS96 FS1 FS0 Mode
0 0 0 44.1kHz
0 0 1 OFF
0 1 0 48kHz
0 1 1 32kHz
1 0 0 OFF
1 0 1 OFF
1 1 0 96kHz
1 1 1 OFF
Table 7. De-emphasis Auto Control at DEAU=“1” and PEM=“1”
DFS DEM1 DEM0 Mode
0 0 0 44.1kHz
0 0 1 OFF Default
0 1 0 48kHz
0 1 1 32kHz
1 0 0 OFF
1 0 1 OFF
1 1 0 96kHz
1 1 1 OFF
Table 8. De-emphasis Manual Control at DEAU=“0” and PEM=“1”
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 13 -
n System Reset and Power-Down
The AK4112B has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The
RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled.
The AK4112B should be reset once by bringing PDN pin = “L” upon power-up.
PDN Pin (Pin #7):
All analog and digital circuit are placed in the power-down and reset mode by bringing PDN= “L”. All the
registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled.
RSTN Bit (Address 00H; D0):
All the registers except PWN and RSTN are initialized by bringing RSTN bit = “0”. The internal timings are
also initialized. Witting to the register is not available except PWN and RSTN. Reading to the register is
disabled.
PWN Bit (Address 00H; D1):
The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks are stopped. The registers
are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled.
n Biphase Input and Through Output
Four receiver inputs (RX1-4) are available in Serial Control Mode. Each input includes amplifier corresponding to
unbalance mode and can accept the signal of 350mV or more. IPS0-1 selects the receiver channel, and OPS0-1 selects the
source of the bit stream driving the transmit channel (TX). The TX output can be stopped by setting TXE bit “0”.
IPS1 IPS0 INPUT Data
0 0 RX1 Default
0 1 RX2
1 0 RX3
1 1 RX4
Table 9. Recovery data select
OPS1 OPS0 INPUT Data
0 0 RX1 Default
0 1 RX2
1 0 RX3
1 1 RX4
Table 10. Output data select
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 14 -
RX
AK4112B
0.1uF
75
Ω
Coax
75Ω
0.47nF
Note
Figure 1. Consumer Input Circuit (Coaxial Input)
Note: In case of coaxial input, if a coupling level to this input from the next RX input line
pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is
possible to lower the coupling level by adding this decoupling capacitor.
RX
AK4112B
470
O/E
Optical Receiver
Optical
Fiber
Figure 2. Consumer Input Circuit (Optical Input)
In case of coaxial input, as the input level of RX line is small, in Serial Mode, be careful not to crosstalk among RX input
lines. For example, by inserting the shield pattern among them. In Parallel Mode, only one channel input (RX1) is
available and RX2-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”.
The AK4112B includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor
network. The T1 in Figure 3 is a transformer of 1:1.
TX
DVSS
R2
T1
75
Ω
cable
R1
Vdd R1 R2
3.3V 240Ω 150Ω
3.0V 220Ω 150Ω
Figure 3. TX External Resistor Network
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 15 -
n Error Handling
There are the following five factors which ERF pin goes “H”. ERF pin shows the status of the internal PLL operation and
it is “L” when the PLL is OFF (Clock Operation Mode 1).
1. Unlock Error : “H” when the PLL goes UNLOCK state.
2. Parity Error : Updated every sub-frame cycle.
3. Biphase Error : Updated every sub-frame cycle
4. Frame length Error : Updated every sub-frame cycle
5. STC (Status Change) flag=“1” : Holds “1” until reading 03H.
In Parallel Mode, ERF pin outputs the ORed signal including the factors of 1,2,3 and 4. Once ERF pin goes ”H”, it
maintains “H” for 1024/fs cycles after the all error factors are removed. Table 11 shows the state of each output pins
when the ERF pin is “H”. The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect.
When unlock state, the channel status bits are not updated and the previous data is maintained.
Error AUTO SDTO V
Unlock Error “L” “L” “L”
Parity Error Output Previous Data Output
Biphase Error Output Previous Data Output
Frame Length Error Output Previous Data Output
Table 11. Error handling (Parallel Mode)
In Serial Mode, ERF pin outputs the ORed signal including the factors of 1,2,3,4 and 5. However, Parity, Biphase and
Frame Length Error can be masked by MPAR bit, and the STC flag can be masked by MSTC bit. When those are masked
by each bit, the error factor does not affect ERF pin operation. The STC flag is set whenever a comparison between the
last sample of bits D5-0 of the receiver status 1 register (03H) and the new sample are different This comparison is made
every fs cycle. The STC flag is reset by reading the register 03H. This flag is also disabled during the first block after
reset.
Once ERF pin goes ”H”, it maintains “H” for 1024/fs cycles (can be changed by ERFH0-1 bits) after the all error factors
(In case of STC, from STC flag “1” to reading 03H) are removed. Once PAR, BIP, FRERR, V or UNLOCK bit goes “1”,
it returns “0” by reading Receiver Status 2 (04H). When unlock state, the channel status bits are not updated and the
previous data is maintained.
Register Pin Error
& Status UNLOCK PAR BIP FRERR STC AUTO SDTO V TX
Unlock Error 1 0 0 0 0 “L” “L” “L” Output
Parity Error 0 1 0 0 0 Output Previous Data Output Output
Biphase Error 0 0 1 0 0 Output Previous Data Output Output
Frame Length Error 0 0 0 1 0 Output Previous Data Output Output
Status change 0 0 0 0 1 Output Output Output Output
Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 16 -
Command
ERF
MCKO, BICK,
LRCK
SDTO
STC bit
V
READ 03H
Reset
(ch. status ) (state B)(state A )
(status change )
ERF Hold Time
Hold “1”
ERF pin timing at Status Change
error(UNLOCK,
PAR, BIP, FRERR)
ERF
SDTO(UNLOCK)
Vpin (UNLOCK)
MCKO,BICK,LRCK
(UNLOCK)
Vpin
(except UNLOCK)
Previous Data
register (UNOCK,
PAR, BIP, FRERR) Hold ”1”
Command READ 04H
MCKO,BICK,LRCK
(except UNLOCK)
(fs: around 20kHz)
SDTO
(except UNLOCK)
ERF Hold Time
Reset
(error)
Free Run
ERF pin timing at UNLOCK, PAR, BIP, FRERR error
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 17 -
PD pin ="L" to "H"
Read 03H
STC is reset, ERF pin ="L"
Read 04H
Mute = "H"
ERF pin ="H"
Read 03H
STC is reset, ERF pin ="L"
Read 04H
ERF pin ="H"
Mute="L"
NO
YES
YES
Initialize
Figure 4. Error handling sequence Example
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 18 -
n Audio Serial Interface Format
The DIF0, DIF1 and DIF2 pins as shown in Table 13 can select eight serial data formats. In all formats the serial data is
MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on
the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to
128fs at fs=48kHz. In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the
last 4LSBs are auxiliary data (see Figure 5).
When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4112B continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4112B
output “0” from SDTO. In case of using DAUX pin, the data is transformed and output from SDTO. DAUX pin is used
in Clock Operation Mode 1, 3 and unlock state of Mode 2.
The input data format to DAUX should be left justified except in Mode5 and 7(Table 13). In Mode5 or 7, both the input
data format of DAUX and output data format of SDTO are I2S. Mode6 and 7 are Slave Mode that is corresponding to the
Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2.
The initial state of the audio format is the Master Mode upon the power-up. Therefore, if the audio format is changed to
the Slave Mode after power-up, the setting of the external clocks should be careful until completing to set the control
registers.
0 3 4 7 8 11 12 27 28 29 30 31
preamble Aux.
LSB MSB
VU C P
sub-frame of IEC958
023
AK4112B Audio Data (MSB First)
LSBMSB
Figure 5. Bit configuration
LRCK BICK
Mode DIF2 DIF1 DIF0 DAUX SDTO I/O I/O
0 0 0 0 24bit, Left justified 16bit, Right justified H/L O 64fs O
1 0 0 1 24bit, Left justified 18bit, Right justified H/L O 64fs O
2 0 1 0 24bit, Left justified 20bit, Right justified H/L O 64fs O
3 0 1 1 24bit, Left justified 24bit, Right justified H/L O 64fs O
4 1 0 0 24bit, Left justified 24bit, Left justified H/L O 64fs O Default
5 1 0 1 24bit, I2S 24bit, I2S L/H O 64fs O
6 1 1 0 24bit, Left justified 24bit, Left justified H/L I 64-128fs I
7 1 1 1 24bit, I2S 24bit, I2S L/H I 64-128fs I
Table 13. Audio data format
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 19 -
LRCK(0)
BICK
(0:64fs)
SDTO(0)
012 31 0 1
15:MSB, 0:LSB
Lch Data Rch Data
15 1716 1531 0 1 2 1716
0 1 01 15 141415
Figure 5. Mode 0 Timing
LRCK(0)
BICK
(0:64fs)
SDTO(0)
0 1 2 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
91110 931 0 1 2 1110
0 1 01
12
21 202021
12
2223 2223
Figure 6. Mode 3 Timing
LRCK
BICK
(64fs)
SDTO(0)
0 1 2 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
21 2322 2131 0 1 2 2322
23 222
24
1 001
24
212223 3 2 23 22
Figure 7. Mode 4, 6 Timing Mode 4: LRCK, BICK: Output
Mode 6: LRCK, BICK: Input
LRCK
BICK
(64fs)
SDTO(0)
0 1 2 31 0 1
23:MSB, 0:LSB
Lch Data Rch Data
2322 2131 0 1 2 2322
23 22
24
1 0
24
3 2 23
25
2 01212223
25
Figure 8. Mode 5, 7 Timing Mode 5: LRCK, BICK: Output
Mode 7: LRCK, BICK: Input
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 20 -
n Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C0/1 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. When the state of
P/S pin is changed, the AK4112B should be reset by PDN= “L”.
CDTI
CCLK
CSN
C1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO Hi-Z
WRITE
CDTI
C1
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CDTO Hi-Z
READ
D4
D5
D6
D7
D0
D1
D2
D3
Hi-Z
C1-C0: Chip Address (Fixed to “00”)
R/W: READ/WRITE (0:READ, 1:WRITE)
A4-A0: Register Address
D7-D0: Control Data
Figure 10. Control I/F Timing
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 21 -
n Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Clock & Power down Control 0 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN
01H Input/Output Control MPAR MSTC CS12 TXE IPS1 IPS0 OPS1 OPS0
02H Format & De-emphasis Control V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS
03H Receiver status 1 ERF 0 AUDION AUTO PEM FS1 FS0 RFS96
04H Receiver status 2 CV STC CRC UNLOCK V FRERR BIP PAR
05H Channel A Status Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
06H Channel A Status Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8
07H Channel A Status Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16
08H Channel A Status Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24
09H Channel B Status Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
0AH Channel B Status Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8
0BH Channel B Status Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16
0CH Channel B Status Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24
0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
11H Count Control 0 0 0 0 0 EFH1 EFH0 XFS96
Notes:
For addresses from 12H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 22 -
n Register Definitions
Reset & Initialize
Addr
Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Clock & Power down Control 0 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN
R/W RD R/W R/W R/W R/W R/W R/W R/W
default 0 0 0 0 0 0 1 1
RSTN: Timing Reset & Register Initialize
0: Reset & Initialize
1: Normal Operation
PWN: Power Down
0: Power down
1: Normal Operation
OCKS1-0: Master Clock frequency Select
CM1-0: Master Clock Operation Mode Select
BCU: Block start & C/U output Mode
When BCU=1, the 3 output pins change another function.
MCKO2 pin→ B; block start signal
AUTO pin→ C bit
FS96 pin→ U bit
The block signal goes high at the start of frame 0 and remains high until the end of frame 31.
(B, C, U, V output timing at RX mode, Master mode)
B
C (or U,V)
LRCK
C(L0) C(R0) C(L1) C(R31)C(L31) C(L32)C(R191)
1/4fs
SDTO
(except I2S)
L191 R191 L0 R30 R31
L31
SDTO
(I2S)
L191 R191 L30 L31
R30
L0
R190
R0
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 23 -
Input/Output Control
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Input/Output Control MPAR MSTC CS12 TXE IPS1 IPS0 OPS1 OPS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
default 1 0 0 1 0 0 0 0
OPS1-0: Output Through Data Select
IPS1-0: Input Recovery Data Select
TXE: TX Output Enable
0: Disable. TX output pin is placed in a high impedance state.
1: Enable
CS12: Channel Status Select
0: Channel 1
1: Channel 2
Selects which channel status is used to derive AUDION, PEM, FS1 and FS0.
The de-emphasis filter, however, is always controlled by channel 1 in the Parallel Mode.
MSTC: Status change flag mask bit
This bit is low to mask status change from being reported by ERF.
MPAR: Parity mask bit
This bit is low to mask Parity Error, Biphase Error and Frame Length Error from being reported by
ERF.
Format & De-emphasis Control
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Format & De-emphasis Control V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS
R/W R/W R/W R/W R/W R/W R/W R/W R/W
default 0 1 0 0 1 0 1 0
V/TX: V/TX Output Select
0: Validity Flag Output. This output is updated every fs cycle.
1: TX
DFS: 96kHz De-emphasis Control
DEM1-0: 32, 44.1, 48kHz De-emphasis Control
DEAU: De-emphasis Auto Detect Enable
0: Disable
1: Enable
DIF2-0: Audio Data Format Control
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 24 -
Receiver Status 1
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Receiver status 1 ERF 0 AUDION AUTO PEM FS1 FS0 RFS96
R/W RD RD RD RD RD RD RD RD
default 0 0 0 0 0 0 0 0
RFS96: 96kHz Sampling Detect at Recovery Mode.
0: fs=54kHz or less.
1: fs=88.2kHz or more
FS1-0: Sampling Frequency Output
PEM: Pre-emphasis Output
0: OFF
1: ON
This bit is made by encoding channel status bits.
AUTO: Non-PCM Auto Detect
0: No detect
1: Detect
This function is the same as AUTO pin.
AUDION: Audio bit Output
0: Audio
1: Non Audio
ERF: Unlock or Parity Error or Status change
0: No Error or No change
1: Error or Change
This function is the same as ERF pin. This bit goes “1” when Unlock Error, Parity Error, Biphase
Error, Frame Length Error or Status Change occurs. If MPAR=0 & MSTC=0, only an unlock error
is reported.
Receiver Status 2
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H Receiver status 2 CV STC CRC UNLOCK V FRERR BIP PAR
R/W RD RD RD RD RD RD RD RD
default 0 0 0 0 0 0 0 0
PAR: Parity Status (0:No Error, 1:Error)
It is high if Parity Error is detected in the sub-frame. PAR is unaffected by the state of MPAR.
BIP: Biphase Status (0:No Error, 1:Error)
FRERR: Frame Error Status (0:No Error, 1:Error)
V: Validity bit (0:No Error, 1:Error)
UNLOCK: PLL Lock status (0:Lock, 1:Unlock)
CRC: Cyclic Redundancy Check (0:No Error, 1:Error on either channel)
STC: Status change flag of Receiver status 1 (0:No change, 1:change)
This flag goes “H” when the latest value of D5-0 in Receiver Status 1(03H) is different from the
previous value. This comparison is made at every fs cycle. This bit returns to “L” by reading
Receiver Status 1(03H). The flag is disabled during the first block after Reset.
CV: Channel Status Validity (0:Valid, 1:Not Valid, data is updating)
This signal goes “H” at the start of frame 0 and maintains “H” until the end of frame 31.
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 25 -
Channel Status
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
05H Channel A Status Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
06H Channel A Status Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8
07H Channel A Status Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16
08H Channel A Status Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24
09H Channel B Status Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
0AH Channel B Status Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8
0BH Channel B Status Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16
0CH Channel B Status Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24
R/W RD
default Not initialized
CA31-0: Channel A Status Byte 4-1
CB31-0: Channel B Status Byte 4-1
Bit definition changes depending upon PRO bit setting. When CV=1, these bits are updating and
may be invalid.
Burst Preamble Pc/Pd in non-PCM encoded Audio bitstreams
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8
0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8
R/W RD
default Not initialized
PC15-0: Burst Preamble Pc Byte 1, 0
PD15-0: Burst Preamble Pd Byte 1, 0
Count Control
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
11H Count Control 0 0 0 0 0 EFH1 EFH0 XFS96
R/W RD RD RD RD RD R/W R/W R/W
default 0 0 0 0 0 0 1 0
XFS96: FS96 output select at X’tal Mode (clock Operation Mode1, Mode3 and Unlock state of Mode2)
1: FS96pin=“H”
0: FS96pin=“L”
EFH1-0: Error Flag Hold Count Select
00: 512 LRCK
01: 1024 LRCK
10: 2048 LRCK
11: 4096 LRCK
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 26 -
n Burst preambles in non-PCM bitstreams
0
16 bits of bitstream
3 4 7 8 11 12 27 28 29 30 31
preamble Aux. LSB MSB VU C P
sub-frame of IEC958
015
Pa Pb Pc Pd Burst_payload stuffing
repetition time of the burst
Preamble word Length of field Contents value
Pa 16 bits sync word 1 0xF872
Pb 16 bits sync word 2 0x4E1F
Pc 16 bits Burst info see Table 15.
Pd 16 bits Length code numbers of bits
Table 14. Burst preamble words
Bits of Pc value contents repetition time of burst
in IEC958 frames
0-4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14-26
27
28
29-31
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
reserved
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
reserved
(reserved for MPEG-4 AAC data)
MPEG-2 AAC data
reserved
≤4096
1536
384
1152
1152
384
1152
512
1024
2048
512
1024
5, 6 0 reserved, shall be set to “0”
7 0
1 Error-flag indicating a valid burst_payload
Error-flag indicating that the burst_payload may contain
Errors
8-12 data type dependent info
13-15 0 bit stream number, shall be set to “0”
Table 15. Fields of burst info Pc
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 27 -
n Non-PCM Bitstream timing
1) When Non-PCM preamble is not coming within 4096 frames,
Pa Pc1Pd1Pb Pa Pc2Pd2Pb Pa Pc3Pd3Pb
“0”Pc1Pc2
“0”Pd1Pd2Pd3
Pc3
PDN pin
Bit stream
AUTO
Pc Register
Pd Register
Repetition time >4096 frames
2) When Non-PCM bitstream stops
Pa Pc1Pd1Pb Stop Pa PcnPdnPb
Pc0Pc1
Pd0Pd1Pdn
Pcn
ERF pin
Bit stream
AUTO
Pc Register
Pd Register
ERF hold time
2~3 Syncs (B,M or W)
<20mS (Lock time)
<Repetition time
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 28 -
SYSTEM DESIGN
Figure 11 shows the example of system connection diagram for Serial Mode.
DVDD
1
DVSS
2
TVDD
3
V/TX
4
XTI
5
XTO
6
PDN
7
R
8
AVDD
9
AVSS
10
RX1
11
RX2
12
CDTO 28
CDTI 27
CCLK
26
CSN 25
MCKO1 24
MCKO2
23
DAUX
22
BICK 21
SDTO
20
LRCK 19
ERF
18
FS96 17
0.1u
10u
+
AK4112B
13
14
16
15
RX3
RX4
P/SN
AUTO
3.3V Supply
0.1u
10u
+
18k
(see Figure 1,2) DSP
and
AD/DA
Micro-
controller
3.3~5V Supply
(Note 8)
C
10u
+
0.1u
3.3V Supply
C
Figure 11. Typical Connection Diagram (Serial Mode)
Notes:
- “C” depends on the crystal oscillator (Typ. 10-40pF)
- AVSS and DVSS must be connected the same ground plane
- Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock
jitter performance.
.
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 29 -
PACKAGE
0.1±0.1
0-10°
Detail A
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0.10
0.15-0.05
0.22±0.1
0.65
*9.8±0.2
1.25±0.2
A
1
14
15
28
28pin VSOP (Unit: mm)
*5.6±0.2
7.6±0.2
0.5±0.2
+0.1
0.675
n
Material & Lead finish
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
ASAHI KASEI [AK4112B]
MS0078-E-01 2002/7
- 30 -
MARKING
AKM
AK4112BVF
XXXBYYYYC
XXXXBYYYYC: Date code identifier
XXXB: Lot number (X : Digit number, B : Alpha character )
YYYYC: Assembly date (Y : Digit number C : Alpha character)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.