Product Brief
August 2000
TADM04622 SONET/SDH 155/622 Mbits/s Interface
Features
■Transmission convergence and SONET/SDH ter-
minal/ADM functionality for linear and ring net-
works.
■Versatile IC supports 155/622 Mbits/s SONET/
SDH interface solutions for packet over SONET
(POS), frame relay (FR), or asynchronous transfer
mode (ATM) applications.
■Low-power 2.5 V/3.3 V operation.
■–40 °C to +85 °C temperature range.
SONET/SDH Interface
■Termination of quad STS-3/STM-1 or STS-12/
STM-4.
■Supports overhead processing for transport and
path overhead bytes.
■Optional insertion and extraction of overhead bytes
via serial overhead interface.
■STS pointer processing to align the receive frame
to the system frame.
■STS-1 granularity cross connect between receive,
mate, STM, and data payloads.
■Support for 1+1 and 1:1 linear networks; UPSR
and BLSR ring networks.
■Full path termination and SPE extraction/insertion.
■SONET/SDH compliant condition and alarm
reporting.
■Handles all concatenation levels of STS-1 to
STS-12c (in multiples of 1: e.g., 2c, 3c, 4c, etc.).
■Built-in diagnostic loopback modes.
■Compliant with
Telcordia Technologies
®,
ANSI
®,
and ITU standards.
Data Processing
■Provisionable data engine supports payload inser-
tion/extraction for PPP, ATM, or HDLC streams.
■Extraction and insertion of DS3 frames containing
HDLC or ATM data streams for up to 16 channels.
■Integrated UTOPIA Level 2 and Level 3 compatible
physical layer interface for packets or ATM cells.
■Insertion and extraction of up to 16 separate data
channels.
■Maintains counts for cell/packet traffic (e.g., total
number of cells, number of discarded cells).
■Direct cell/packet over fiber interface device.
■Compliant with ATM forum, ITU standards, and
IETF standards.
Interfaces
■Enhanced UTOPIA interface for cell and packet
transfer (PLATO).
■Built-in redundant STS/STM backplane interface
using 622 MHz LVDS technology.
■Mate-to-mate backplane interface using 622 MHz
LVDS technology for 1+1, 1:1, BLSR, and UPSR
network support.
■Optional 78 MHz bus (32-bit) for STS/STM inter-
face.
Microprocessor Interface
■Up to 66 MHz synchronous.
■16-bit address and 16-bit data interface.
■Synchronous or asynchronous modes available.