Product Brief
August 2000
TADM04622 SONET/SDH 155/622 Mbits/s Interface
Features
Transmission convergence and SONET/SDH ter-
minal/ADM functionality for linear and ring net-
works.
Versatile IC supports 155/622 Mbits/s SONET/
SDH interface solutions for packet over SONET
(POS), frame relay (FR), or asynchronous transfer
mode (ATM) applications.
Low-power 2.5 V/3.3 V operation.
–40 °C to +85 °C temperature range.
SONET/SDH Interface
Termination of quad STS-3/STM-1 or STS-12/
STM-4.
Supports overhead processing for transport and
path overhead bytes.
Optional insertion and extraction of overhead bytes
via serial overhead interface.
STS pointer processing to align the receive frame
to the system frame.
STS-1 granularity cross connect between receive,
mate, STM, and data payloads.
Support for 1+1 and 1:1 linear networks; UPSR
and BLSR ring networks.
Full path termination and SPE extraction/insertion.
SONET/SDH compliant condition and alarm
reporting.
Handles all concatenation levels of STS-1 to
STS-12c (in multiples of 1: e.g., 2c, 3c, 4c, etc.).
Built-in diagnostic loopback modes.
Compliant with
Telcordia Technologies
®,
ANSI
®,
and ITU standards.
Data Processing
Provisionable data engine supports payload inser-
tion/extraction for PPP, ATM, or HDLC streams.
Extraction and insertion of DS3 frames containing
HDLC or ATM data streams for up to 16 channels.
Integrated UTOPIA Level 2 and Level 3 compatible
physical layer interface for packets or ATM cells.
Insertion and extraction of up to 16 separate data
channels.
Maintains counts for cell/packet traffic (e.g., total
number of cells, number of discarded cells).
Direct cell/packet over fiber interface device.
Compliant with ATM forum, ITU standards, and
IETF standards.
Interfaces
Enhanced UTOPIA interface for cell and packet
transfer (PLATO).
Built-in redundant STS/STM backplane interface
using 622 MHz LVDS technology.
Mate-to-mate backplane interface using 622 MHz
LVDS technology for 1+1, 1:1, BLSR, and UPSR
network support.
Optional 78 MHz bus (32-bit) for STS/STM inter-
face.
Microprocessor Interface
Up to 66 MHz synchronous.
16-bit address and 16-bit data interface.
Synchronous or asynchronous modes available.
22 Agere Systems Inc.
Product Brief
August 2000
TADM04622 SONET/SDH 155/622 Mbits/s Interface
Description*
The TADM04622 SONET/SDH interface device pro-
vides a versatile solution for OC-3/OC-12 linear and
ring datacom/telecom applications. Constructed using
Agere’s state-of-the-art CMOS technology, this device
incorporates integrated SONET/SDH framing, section/
line/path termination, pointer processing, cross con-
nect, and data engine blocks.
The device provides complete encapsulation and de-
encapsulation for packet and ATM streams into and out
of SONET/SDH payloads.
Communication with the TADM device is accomplished
through a generic microprocessor interface. The device
supports separate address and data buses.
With the TADM device, construction of all types of inter-
faces for OC-3/OC-12 data equipment is simplified and
cost reduced allowing extremely competitive solutions
to be constructed.
This device integrates the SONET/SDH network termi-
nation functions with a generic cell/packet delineation
circuit. It supports STS-12/STM-4 and quad STS-3/
STM-1 interface rates. Up to 16 data channels trans-
ported within an STS-N payload are processed and
handed off over an enhanced UTOPIA interface. The
concatenation levels supported by this device are STS-
1,STS-2c,STS-3c,STS-4c,...,STS12c.Thedata
formats processed by this device are ATM cells or
HDLC framed packets such as PPP or SDL (SDL is
planned for future releases of the device) framed pack-
ets. Future plans for the TADM04622 also call for a vir-
tual concatenation feature allowing all nontraditional
concatenation modes like STS-5c, STS-7c, etc.,
enabling service providers flexibility to adjust their
bandwidth on demand.
* Therelevantdocumentation forthe TADM04622 device is found in
the
TADM042G5
Advance Data Sheet and the
TADM SONET/
SDH 155/622/2488 Mbits/s Add/Drop Data Interface
Data Adden-
dum.
5-7393(F).a
Figure 1. Block Diagram
PACKET/CELL
OVERHEAD PROCESSOR:
•DELINEATION
•DESCRAMBLING
•DECAPSULATION
PROCESSOR
MONITOR
OVERHEAD
PROCESSOR
INSERT
TRANSPORT
OVERHEAD
INTERFACE BLOCK
POINTER
PROCESSOR
CONNECTION
MEMORY
PTR
INTER
AND
DS3/
MPR
PACKET/CELL
FIFOs
CONTROL
DS3/
MPR
AND
SPE
MPR
PACKET/CELL
PROCESSOR:
•ENCAPSULATION
•SCRAMBLING
PAYLOAD
TERMINATION
TSI STM INTERFACE
MATE
INTERFACE
SWITCHING
UTOPIA
INTERFACE
STM_B
STM_A
MPU INTERFACE
DIRECT CELL/PACKET OVER FIBER
DIRECT CELL/PACKET OVER FIBER
STM-4/STS-12
OR QUAD
STM-1/STS-3
STM-4/STS-12
OR QUAD
STM-1/STS-3
MISCELLANEOUS
GPIO/STMDCCTO GO INTERFACE
TERMINATION
TXCLK
PATH
SWITCH
LINE
SWITCH
Agere Systems Inc. 3
Product Brief
August 2000 TADM04622 SONET/SDH 155/622 Mbits/s Interface
Notes
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
August 2000
PB00-121SONT (Replaces PN00-008SONT)
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@agere.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Product Brief
August 2000
in PCI Bus Master (with Target) Applications
TADM04622 SONET/SDH 155/622
Telcordia Technologies
is a registered trademark of Bell Communications Research, Inc.
ANSI
is a registered trademark of American National Standards Institute, Inc.