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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD75P3018A 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD75P3018A replaces the PD753017A's internal mask ROM with a one-time PROM, and features expanded ROM capacity. The PD75P3018A inherits the function of the PD75P3018, and enables high-speed operation at a low supply voltage of 1.8 V. Because the PD75P3018A supports programming by users, it is suitable for use in evaluation of systems in development stages using the PD753012A, 753016A, or 753017A, and for use in small-scale production. The following document describes further details of the functions. Please make sure to read this document before starting design. PD753017 User's Manual : U11282E FEATURES Compatible with PD753017A Memory capacity: * PROM : 32768 x 8 bits * RAM : 1024 x 4 bits Can operate in the same power supply voltage as the mask version PD753017A * VDD = 1.8 to 5.5 V LCD controller/driver ORDERING INFORMATION Part Number Package PD75P3018AGC-3B9 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) PD75P3018AGC-3B9-A 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) PD75P3018AGC-8BT 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) PD75P3018AGC-8BT-A 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) PD75P3018AGK-BE9 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) PD75P3018AGK-9EU 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) PD75P3018AGK-9EU-A 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) Caution Mask-option pull-up resistors are not provided in this device. Remark Products with "-A" at the end of the part number are lead-free products. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U11917EJ2V1DS00 (2nd edition) Date Published August 2005 N CP (K) Printed in Japan The mark shows major revised points. PD75P3018A FUNCTION OUTLINE Item Function Instruction execution time * 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) Internal memory PROM 32768 x 8 bits RAM 1024 x 4 bits General-purpose register * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks Input/output port CMOS input 8 CMOS input/output 16 CMOS output 8 On-chip pull-up resistor connection can be specified by using software: 23 Also used for segment pins N-ch open-drain input/output 8 Total 2 13 V breakdown voltage 40 LCD controller/driver * Segment number selection : 24/28/32 segments (can be changed to CMOS output port in unit of 4; max. 8) * Display mode selection : Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias) 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) Timer 5 channels: * 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, timer with gate) * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel Serial interface * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode * SBI mode Bit sequential buffer (BSB) 16 bits Clock output (PCL) * , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) Buzzer output (BUZ) * 2, 4, 32 kHz Vectored interrupt * External : 3 * Internal : 5 Test input * External : 1 * Internal : 1 System clock oscillator * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode Power supply voltage VDD = 1.8 to 5.5 V Package * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) Data Sheet U11917EJ2V1DS PD75P3018A CONTENTS 1. PIN CONFIGURATION (Top View) ................................................................................................ 4 2. BLOCK DIAGRAM ........................................................................................................................... 5 3. PIN FUNCTIONS .............................................................................................................................. 6 3.1 Port Pins ................................................................................................................................................... 6 3.2 Non-port Pins ........................................................................................................................................... 8 3.3 Pin Input/Output Circuits ......................................................................................................................... 10 3.4 Recommended Connection for Unused Pins ........................................................................................ 12 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 13 4.1 Difference between Mk I Mode and Mk II Mode ..................................................................................... 13 4.2 Setting of Stack Bank Selection Register (SBS) ................................................................................... 14 5. DIFFERENCES BETWEEN PD75P3018A AND PD753012A, 753016A, AND 753017A ....... 15 6. MEMORY CONFIGURATION .......................................................................................................... 16 6.1 Program Counter (PC) ............................................................................................................................. 16 6.2 Program Memory (PROM) ....................................................................................................................... 16 6.3 Data Memory (RAM) ................................................................................................................................. 19 7. INSTRUCTION SET ......................................................................................................................... 20 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ............................................. 30 8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 30 8.2 Program Memory Write Procedure ......................................................................................................... 31 8.3 Program Memory Read Procedure ......................................................................................................... 32 8.4 One-time PROM Screening ..................................................................................................................... 33 9. ELECTRICAL SPECIFICATIONS .................................................................................................... 34 10. PACKAGE DRAWINGS ................................................................................................................... 48 11. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 52 APPENDIX A. PD75316B, 753017A AND 75P3018A FUNCTION LIST .......................................... 55 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 57 APPENDIX C. RELATED DOCUMENTS ............................................................................................... 61 Data Sheet U11917EJ2V1DS 3 PD75P3018A 1. PIN CONFIGURATION (Top View) * 80-pin plastic QFP (14 x 14 mm) PD75P3018AGC-3B9, 75P3018AGC-3B9-A, 75P3018AGC-8BT, 75P3018AGC-8BT-A * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 PD75P3018AGK-BE9, 75P3018AGK-9EU, 75P3018AGK-9EU-A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 45 16 44 17 18 43 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P60/KR0 X2 X1 VPPNote XT2 XT1 VDD P33/MD3 P32/MD2 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2/TI1/TI2 P11/INT1 P10/INT0 P03/SI/SB1 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P40/D0 P41/D1 P42/D2 P43/D3 Vss P50/D4 P51/D5 P52/D6 P53/D7 P00/INT4 P01/SCK P02/SO/SB0 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 Note Connect the VPP directly to VDD during normal operation. PIN IDENTIFICATIONS 4 BIAS : LCD Power Supply Bias Control P70-P73 : Port7 BP0-BP7 : Bit Port 0-7 PCL : Programmable Clock BUZ : Buzzer Clock PTO0-PTO2 : Programmable Timer Output 0-2 COM0-COM3 : Common Output 0-3 RESET : Reset D0-D7 : Data Bus 0-7 S0-S31 : Segment Output 0-31 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 SB0, SB1 : Serial Bus 0,1 INT2 : External Test Input 2 SCK : Serial Clock KR0-KR7 : Key Return 0-7 SI : Serial Input LCDCL : LCD Clock SO : Serial Output MD0-MD3 : Mode Selection 0-3 SYNC : LCD Synchronization P00-P03 : Port0 TI0-TI2 : Timer Input 0-2 P10-P13 : Port1 VDD : Positive Power Supply P20-P23 : Port2 VLC0-VLC2 : LCD Power Supply 0-2 P30-P33 : Port3 VPP : Programming Power Supply P40-P43 : Port4 Vss : Ground P50-P53 : Port5 X1, X2 : Main System Clock Oscillation 1, 2 P60-P63 : Port6 XT1, XT2 : Subsystem Clock Oscillation 1, 2 Data Sheet U11917EJ2V1DS PD75P3018A 2. BLOCK DIAGRAM TIMER/EVENT COUNTER #1 PTO1/P21 INTT1 TI1/TI2/ P12/INT2 TIMER/EVENT COUNTER #2 PTO2/P22/PCL PROGRAM COUNTER (15) SP (8) CY ALU BASIC INTERVAL TIMER/ WATCHDOG TIMER GENERAL REG. INTBT TI0/P13 TIMER/EVENT COUNTER #0 INTT0 TOUT0 PROM PROGRAM MEMORY 32768 x 8 BITS DECODE AND CONTROL RAM DATA MEMORY 1024 x 4 BITS WATCH TIMER BUZ/P23 4 P00 to P03 PORT1 4 P10 to P13 PORT2 4 P20 to P23 PORT3 4 P30/MD0 to P33/MD3 PORT4 4 P40/D0 to P43/D3 PORT5 4 P50/D4 to P53/D7 PORT6 4 P60 to P63 PORT7 4 P70 to P73 BANK INTT2 TOUT0 PTO0/P20 SBS PORT0 INTW fLCD SI/SB1/P03 SO/SB0/P02 SCK/P01 LCD CONTROLLER /DRIVER CLOCKED SERIAL INTERFACE INTCSI TOUT0 INT0/P10 INT1/P11 INT2/P12/TI1/TI2 INT4/P00 KR0/P60 to KR7/P73 INTERRUPT CONTROL 24 S0 to S23 8 S24/BP0 to S31/BP7 4 COM0 to COM3 3 8 fLCD fx/2 N BIT SEQ. BUFFER (16) BIAS CPU CLOCK LCDCL/P30/MD0 SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER CONTROL CONTROL SUB MAIN PCL/PTO2/P22 XT1 XT2 X1 X2 Data Sheet U11917EJ2V1DS VLC0 to VLC2 SYNC/P31/MD1 VDD VSS RESET VPP 5 PD75P3018A 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name P00 I/O Input Alternate Function INT4 Function This is a 4-bit input port (PORT0). P01 to P03 are 3-bit pins for which an internal pull-up resistor connection can be specified by software. 8-bit I/O -- After Reset I/O Circuit TypeNote 1 Input <B> P01 SCK P02 SO/SB0 <F>-B P03 SI/SB1 <M>-C P10 Input INT0 P11 INT1 P12 TI1/TI2/INT2 P13 TI0 P20 I/O PTO0 P21 PTO1 P22 PCL/PTO2 P23 BUZ P30 I/O LCDCL/MD0 P31 SYNC/MD1 P32 MD2 P33 MD3 P40Note 2 I/O D0 P41Note 2 D1 P42Note 2 D2 P43Note 2 D3 P50Note 2 I/O D4 P51Note 2 D5 P52Note 2 D6 P53Note 2 D7 <F>-A This is a 4-bit input port (PORT1). These are 4-bit pins for which an internal pull-up resistor connection can be specified by software. P10/INT0 can select noise elimination circuit. -- Input <B>-C This is a 4-bit I/O port (PORT2). These are 4-bit pins for which an internal pull-up resistor connection can be specified by software. -- Input E-B This is a programmable 4-bit I/O port (PORT3). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor connection can be specified by software. -- Input E-B This is an N-ch open-drain 4-bit I/O port (PORT4). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (low-order 4 bits) for program memory (PROM) write/verify. High impedance M-E High impedance M-E This is an N-ch open-drain 4-bit I/O port (PORT5). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (high-order 4 bits) for program memory (PROM) write/verify. Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed. 6 Data Sheet U11917EJ2V1DS PD75P3018A 3.1 Port Pins (2/2) Pin Name P60 I/O Alternate Function I/O KR0 P61 KR1 P62 KR2 P63 KR3 P70 I/O KR4 P71 KR5 P72 KR6 P73 KR7 BP0 Output S24 BP1 S25 BP2 S26 BP3 S27 BP4 Output S28 BP5 S29 BP6 S30 BP7 S31 Function 8-bit I/O This is a programmable 4-bit I/O port (PORT6). Input and output in single-bit units can be specified. When set for 4-bit units, an internal pull-up resistor connection can be specified by software. This is a 4-bit I/O port (PORT7). When set for 4-bit units, an internal pull-up resistor connection can be specified by software. 1-bit output port (BIT PORT). These pins are also used as segment output pin. -- After Reset I/O Circuit TypeNote 1 Input <F>-A Input <F>-A Note 2 H-A Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. VLC1 is selected as the input source for BP0 to BP7. The output level varies depending on the external circuit for BP0 to BP7 and VLC1. Example: As shown below, BP0 to BP7 are mutually connected via the PD75P3018A, so the output levels of BP0 to BP7 are determined by the sizes of R1, R2, and R3. VDD R2 BP0 ON VLC1 BP1 R1 ON R3 PD75P3018A Data Sheet U11917EJ2V1DS 7 PD75P3018A 3.2 Non-port Pins (1/2) Pin Name TI0 I/O Input TI1, TI2 Alternate Function P13 Function After Reset I/O Circuit TypeNote 1 External event pulse input to timer/event counter Input <B>-C Timer/event counter output Input E-B Input <F>-A P12/INT2 PTO0 Output P20 PTO1 P21 PTO2 P22 PCL P22 Clock output BUZ P23 Optional frequency output (for buzzer or system clock trimming) P01 Serial clock I/O SO/SB0 P02 Serial data output Serial data bus I/O <F>-B SI/SB1 P03 Serial data input Serial data bus I/O <M>-C SCK I/O INT4 Input P00 Edge detection vectored interrupt input (both rising and falling edges detection) <B> INT0 Input P10 Edge detection vectored interrupt input Noise elimination circuit/ (detected edge is selectable) asynchronous is selectable INT1 P11 INT0/P10 can select noise elimination circuit. Asynchronous INT2 P12/TI1/TI2 Rising edge detection testable input Input <B>-C Falling edge detection testable input Input <F>-A Falling edge detection testable input Asynchronous KR0-KR3 Input P60-P63 KR4-KR7 Input P70-P73 Input <F>-A X1 Input -- -- -- X2 -- Ceramic/crystal oscillation circuit connection for main system clock. If using an external clock, input to X1 and input inverted phase to X2. -- Crystal oscillation circuit connection for subsystem clock. If using an external clock, input to XT1 and input inverted phase to XT2. XT1 can be used as a 1-bit (test) input. -- -- -- System reset input (low level active) -- <B> Mode selection for program memory (PROM) write/verify Input E-B Data bus for program memory (PROM) write/verify Input M-E XT1 Input XT2 -- RESET Input MD0 Input P30/LCDCL MD1 P31/SYNC MD2, MD3 P32, P33 D0-D3 I/O D4-D7 VPP P40-P43 P50-P53 Note 2 -- -- Program power supply voltage for program memory (PROM) write/verify. For normal operation, connect directly to VDD. Apply +12.5 V for PROM write/verify. -- -- VDD -- -- Positive power supply -- -- Vss -- -- Ground -- -- Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. The VPP pin does not operate correctly during normal operation unless connected to the VDD pin. 8 Data Sheet U11917EJ2V1DS PD75P3018A 3.2 Non-port Pins (2/2) Pin Name I/O Alternate Function S0-S23 Output -- Segment signal output Note 1 G-A S24-S31 Output BP0-BP7 Segment signal output Note 1 H-A Common signal output Note 1 G-B COM0-COM3 Output VLC0-VLC2 BIAS LCDCLNote 2 Note 2 SYNC -- Function -- -- Power source for LCD driver Output -- Output for external split resistor cut After Reset I/O Circuit Type -- -- High impedance -- I/O P30/MD0 Clock output for driving external expansion driver Input E-B I/O P31/MD1 Clock output for synchronization of external expansion driver Input E-B Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs. S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0 2. These pins are provided for future system expansion. Currently, only P30 and P31 are used. Data Sheet U11917EJ2V1DS 9 PD75P3018A 3.3 Pin Input/Output Circuits The input/output circuits for the PD75P3018A's pins are shown in abbreviated form below. (1/2) TYPE A TYPE D VDD VDD Data P-ch OUT P-ch IN Output disable N-ch N-ch Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF). CMOS standard input buffer TYPE B TYPE E-B VDD P.U.R. P.U.R. enable P-ch IN Data IN/OUT Type D Output disable Type A Schmitt trigger input with hysteresis characteristics. P.U.R. : Pull-Up Resistor TYPE B-C TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch Data IN/OUT Type D Output disable IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor 10 Data Sheet U11917EJ2V1DS PD75P3018A (2/2) TYPE F-B TYPE H-A VDD P.U.R. P.U.R. enable P-ch Output disable (P) VDD SEG data Type G-A IN P-ch IN/OUT Data Output disable N-ch Bit Port data Output disable Output disable (N) Type D P.U.R. : Pull-Up Resistor TYPE G-A TYPE M-C VDD VLC0 P.U.R. VLC1 P.U.R. enable P-ch N-ch P-ch IN/OUT OUT SEG data N-ch Data N-ch Output disable VLC2 N-ch P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-E IN/OUT Data VLC0 N-ch (+13 V withstand voltage) Output disable VLC1 VDD P-ch N-ch Input instruction P-ch Note P.U.R. OUT COM data N-ch P-ch Voltage controller VLC2 N-ch (+13 V withstand voltage) Note Pull-up resistor operated only when executing input instructions (when pins are low level, current flows from VDD to pins). Data Sheet U11917EJ2V1DS 11 PD75P3018A 3.4 Recommended Connection for Unused Pins Pin Recommended Connection P00/INT4 Connect to VSS or VDD P01/SCK Connect to VSS or VDD via a resistor individually P02/SO/SB0 P03/SI/SB1 Connect to VSS P10/INT0, P11/INT1 Connect to VSS or VDD P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 Input : Connect to VSS or VDD via a resistor individually P21/PTO1 Output : Leave open P22/PTO2/PCL P23/BUZ P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2, P33/MD3 P40/D0-P43/D3 Connect to VSS P50/D4-P53/D7 P60/KR0-P63/KR3 Input : Connect to VSS or VDD via a resistor individually P70/KR4-P73/KR7 Output : Leave open S0-S23 Leave open S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 Connect to VSS BIAS Connect to VSS only when VLC0 to VLC2 are all not used. In other cases, leave open. XT1Note Connect to VSS Note XT2 Leave open Note When subsystem clock is not used, specify SOS.0 = 1 (indicates that internal feedback resistor is disconnected). 12 Data Sheet U11917EJ2V1DS PD75P3018A 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE Setting a stack bank selection (SBS) register for the PD75P3018A enables the program memory to be switched between Mk I mode and Mk II mode. This function is applicable when using the PD75P3018A to evaluate the PD753012A, 753016A, or 753017A. When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for PD753012A, 753016A, and 753017A) When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for PD753012A, 753016A, and 753017A) 4.1 Difference between Mk I Mode and Mk II Mode Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the PD75P3018A. Table 4-1. Difference between Mk I Mode and Mk II Mode Item Mk I Mode Mk II Mode Program counter PC13-0 PC14 is fixed at 0 PC14-0 Program memory (bytes) 16384 32768 Data memory (bits) 1024 x 4 Stack Stack bank Selectable via memory banks 0 to 3 No. of stack bytes 2 bytes 3 bytes BRA !addr1 instruction Not available Available 3 machine cycles 4 machine cycles execution time CALLF !faddr instruction 2 machine cycles 3 machine cycles Supported mask ROMs When set to Mk I mode: PD753012A, 753016A, and 753017A When set to Mk II mode: PD753012A, 753016A, and 753017A Instruction CALLA !addr1 instruction Instruction CALL !addr instruction Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. With regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used. Data Sheet U11917EJ2V1DS 13 PD75P3018A 4.2 Setting of Stack Bank Selection Register (SBS) Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 10XXBNote at the beginning of the program. When using the Mk II mode, be sure to initialize it to 00XXBNote. Note Set the desired value for XX. Figure 4-1. Format of Stack Bank Selection Register Address F84H 3 2 1 0 SBS3 SBS2 SBS1 SBS0 Symbol SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 1 0 Memory bank 2 1 1 Memory bank 3 0 Be sure to set bit 2 to 0. Mode selection specification 0 Mk II mode 1 Mk I mode Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in Mk I mode. When using instructions for Mk II mode, set SBS3 to "0" and set Mk II mode before using the instructions. 2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register. 14 Data Sheet U11917EJ2V1DS PD75P3018A 5. DIFFERENCES BETWEEN PD75P3018A AND PD753012A, 753016A, AND 753017A The PD75P3018A replaces the internal mask ROM in the PD753012A, 753016A, and 753017A with a one-time PROM and features expanded ROM capacity. The PD75P3018A's Mk I mode supports the Mk I mode in the PD753012A, 753016A, and 753017A and the PD75P3018A's Mk II mode supports the Mk II mode in the PD753012A, 753016A, and 753017A. Table 5-1 lists differences among the PD75P3018A and the PD753012A, 753016A, and 753017A. Be sure to check the differences among these products before using them with PROMs for debugging or prototype testing of application systems or, later, when using them with a mask ROM for full-scale production. For the CPU functions and internal hardwares, refer to PD753017 User's Manual (U11282E). Table 5-1. Differences between PD75P3018A and PD753012A, 753016A, and 753017A PD753012A Item Program counter 14 bits Program memory (bytes) Mask ROM PD753016A PD753017A PD75P3018A 15 bits One-time PROM During Mk I mode 12288 16384 16384 16384 During Mk II mode 12288 16384 24576 32768 Data memory (x 4 bits) 1024 Mask options Yes (Can be specified whether to incorporate or not) No (Cannot incorporate) Feedback resistor for subsystem clock Yes (Can be specified whether to use or not) No (used) Wait time during RESET Yes (Can be specified either 217/fX or 215/fX)Note No (Fixed at 215/fX)Note Pin Nos. 29 to 32 P40 to P43 P40/D0 to P43/D3 Pin Nos. 34 to 37 P50 to P53 P50/D4 to P53/D7 Pin No. 50 P30/LCDCL P30/LCDCL/MD0 Pin No. 51 P31/SYNC P31/SYNC/MD1 Pin Nos. 52 and 53 P32, P33 P32/MD2, P33/MD3 Pin No. 57 IC VPP Pull-up resistor for PORT4 and PORT5 LCD split resistor Pin configuration Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. Note For 217/fX, during 6.0 MHz operation is 21.8 ms, and during 4.19 MHz operation is 31.3 ms. For 215/fX, during 6.0 MHz operation is 5.46 ms, and during 4.19 MHz operation is 7.81 ms. Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask ROM version from the PROM version in a process between prototype development and full production, be sure to fully evaluate the mask ROM version's CS (not ES). Data Sheet U11917EJ2V1DS 15 PD75P3018A 6. MEMORY CONFIGURATION 6.1 Program Counter (PC) ... 15 bits This is a 15-bit binary counter that stores program memory address data. Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid. Figure 6-1. Configuration of Program Counter PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC Fixed at zero during Mk I mode 6.2 Program Memory (PROM) ... 32768 x 8 bits The program memory consists of 32768 x 8-bit one-time PROM. The program memory address can be selected as shown below by setting the stack bank selection (SBS) register. Mk I Mode Usable address 0000H to 3FFFH Mk II Mode 0000H to 7FFFH Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call instruction, during Mk I and Mk II modes. 16 Data Sheet U11917EJ2V1DS PD75P3018A Figure 6-2. Program Memory Map (Mk I mode) 0000H 7 6 MBE RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (low-order 8 bits) 0004H MBE RBE INT0 start address (high-order 6 bits) CALLF !faddr instruction entry address INT0 start address (low-order 8 bits) 0006H MBE RBE INT1 start address (high-order 6 bits) INT1 start address (low-order 8 bits) 0008H MBE RBE INTCSI start address (high-order 6 bits) BRCB !caddr instruction branch address INTCSI start address (low-order 8 bits) 000AH MBE RBE INTT0 start address (high-order 6 bits) INTT0 start address (low-order 8 bits) 000CH MBE RBE INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (low-order 8 bits) Branch addresses for the following instructions * BR BCDE * BR BCXA * BR !addr * CALL !addr Branch/call address by GETI 0020H Reference table for GETI instruction 007FH 0080H BR $addr instruction relative branch address (-15 to -1, +2 to +16) 07FFH 0800H 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3FFFH Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's low-order 8 bits only. Data Sheet U11917EJ2V1DS 17 PD75P3018A Figure 6-3. Program Memory Map (Mk II mode) 0000H 7 6 MBE RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (low-order 8 bits) 0002H MBE RBE INTBT/INT4 start address (high-order 6 bits) INTBT/INT4 start address (low-order 8 bits) 0004H MBE RBE INT0 start address (high-order 6 bits) CALLF !faddr instruction entry address Branch addresses for the following instructions * BR BCDE * BR BCXA * BRA !addr1 * CALLA !addr1 INT0 start address (low-order 8 bits) 0006H MBE RBE INT1 start address (high-order 6 bits) INT1 start address (low-order 8 bits) 0008H MBE RBE INTCSI start address (high-order 6 bits) BR $addr1 instruction relative branch address (-15 to -1, +2 to +16) INTCSI start address (low-order 8 bits) 000AH MBE RBE INTT0 start address (high-order 6 bits) INTT0 start address (low-order 8 bits) 000CH MBE RBE INTT1, INTT2 start address (high-order 6 bits) BRCB !caddr instruction branch address INTT1, INTT2 start address (low-order 8 bits) 0020H Reference table for GETI instruction 007FH 0080H BR !addr instruction branch address CALL !addr instruction branch address 07FFH 0800H Branch/call address by GETI 0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2FFFH 3000H BRCB !caddr instruction branch address 3FFFH 4000H BRCB !caddr instruction branch address 4FFFH 5000H BRCB !caddr instruction branch address 5FFFH 6000H BRCB !caddr instruction branch address 6FFFH 7000H BRCB !caddr instruction branch address 7FFFH Caution To allow the vectored interrupt's 14-bit start address (noted above), set the address within a 16K area (0000H to 3FFFH). Remark 18 For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's low-order 8 bits only. Data Sheet U11917EJ2V1DS PD75P3018A 6.3 Data Memory (RAM) ... 1024 x 4 bits Figure 6-4 shows the data memory configuration. Data memory consists of a data area and a peripheral hardware area. The data area consists of 1024 x 4-bit static RAM. Figure 6-4. Data Memory Map Data memory Memory bank 000H (32 x 4) General-purpose register area 01FH 020H 0 256 x 4 (224 x 4) 0FFH 100H 256 x 4 (224 x 4) 1 1DFH 1E0H Display data memory (32 x 4) 1FFH 200H Data area static RAM (1024 x 4) Stack area Note 256 x 4 2 256 x 4 3 2FFH 300H 3FFH Not incorporated F80H 128 x 4 Peripheral hardware area 15 FFFH Note Memory bank 0, 1, 2, or 3 can be selected as the stack area. Data Sheet U11917EJ2V1DS 19 PD75P3018A 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, see the RA75X Assembler Package User's Manual Language (U12385E)). When there are several codes, select and use just one. Codes that consist of uppercase letters and + or - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (For details, refer to the PD753017 User's Manual (U11282E)). The number of labels that can be entered for fmem and pmem are restricted. Representation Coding Format reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp' XA, BC, DE, HL, XA', BC', DE', HL' rp'1 BC, DE, HL, XA', BC', DE', HL' rpa HL, HL+, HL-, DE, DL rpa1 DE, DL n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or labelNote bit 2-bit immediate data or label fmem FB0H-FBFH, FF0H-FFFH immediate data or label pmem FC0H-FFFH immediate data or label addr 0000H-3FFFH immediate data or label addr1 0000H-7FFFH immediate data or label (Mk II mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H-7FH immediate data (however, bit0 = 0) or label PORTn PORT0-PORT7 IEXXX IEBT, IECSI, IET0, IET1, IET2, IE0-IE2, IE4, IEW RBn RB0-RB3 MBn MB0-MB3, MB15 Note When processing 8-bit data, only even-numbered addresses can be specified. 20 Data Sheet U11917EJ2V1DS PD75P3018A (2) Operation legend A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC) DE : Register pair (DE) HL : Register pair (HL) XA' : Expansion register pair (XA') BC' : Expansion register pair (BC') DE' : Expansion register pair (DE') HL' : Expansion register pair (HL') PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 7) IME : Interrupt master enable flag IPS : Interrupt priority selection register IEXXX : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Delimiter for address and bit (XX) : Addressed data XXH : Hexadecimal data Data Sheet U11917EJ2V1DS 21 PD75P3018A (3) Description of symbols used in addressing area MB = MBE * MBS *1 MBS = 0-3, 15 *2 MB = 0 *3 MBE = 0 : MB = 0 (000H-07FH) Data memory addressing MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS MBS = 0-3, 15 *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 addr = 0000H-3FFFH *7 addr, addr1 = (Current PC) -15 to (Current PC) -1 (Current PC) +2 to (Current PC) +16 *8 caddr = 0000H-0FFFH (PC14, 13, 12 = 000B) or 1000H-1FFFH (PC14, 13, 12 = 001B) or 2000H-2FFFH (PC14, 13, 12 = 010B) or 3000H-3FFFH (PC14, 13, 12 = 011B) or 4000H-4FFFH (PC14, 13, 12 = 100B: Mk II mode only) or 5000H-5FFFH (PC14, 13, 12 = 101B: Mk II mode only) or 6000H-6FFFH (PC14, 13, 12 = 110B: Mk II mode only) or 7000H-7F7FH (PC14, 13, 12 = 111B: Mk II mode only) *9 faddr = 0000H-07FFH *10 taddr = 0020H-007FH *11 addr1 = 0000H-7FFFH (Mk II mode only) Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. 22 Data Sheet U11917EJ2V1DS Program memory addressing PD75P3018A (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip ..................................................................... S = 0 * Skipped instruction is 1-byte or 2-byte instruction .... S = 1 * Skipped instruction is 3-byte instructionNote .............. S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock . Use the PCC setting to select among four cycle times. Data Sheet U11917EJ2V1DS 23 PD75P3018A Instruction Group Transfer Mnemonic MOV XCH Operand Operation A, #n4 1 1 A n4 reg1, #n4 2 2 reg1 n4 Addressing Area Skip Condition String-effect A XA, #n8 2 2 XA n8 String-effect A HL, #n8 2 2 HL n8 String-effect B rp2, #n8 2 2 rp2 n8 A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL- 1 2+S A (HL), then L L-1 *1 L=FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 @HL, A 1 1 (HL) A *1 @HL, XA 2 2 (HL) XA *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 mem, A 2 2 (mem) A *3 mem, XA 2 2 (mem) XA *3 A, reg 2 2 A reg XA, rp' 2 2 XA rp' reg1, A 2 2 reg1 A rp'1, XA 2 2 rp'1 XA A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL- 1 2+S A (HL), then L L-1 *1 L=FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 A, reg1 1 1 A reg1 XA, rp' 2 2 XA rp' 1 3 XA (PC13-8+DE)ROM MOVTNote 1 XA, @PCDE Table No. of Machine Bytes Cycle XA (PC14-8+DE)ROM reference XA, @PCXA 1 3 XA (PC13-8+XA)ROM XA (PC14-8+XA)ROM XA, @BCDE XA, @BCXA 1 1 3 3 XA (BCDE)ROMNote 2 *6 Note 2 XA (BCDE)ROM *11 XA (BCXA)ROM Note 2 *6 XA (BCXA)ROM Note 2 *11 Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 2. Only the low-order 3 bits in the B register are valid. 24 Data Sheet U11917EJ2V1DS PD75P3018A ADDC SUBS SUBC AND OR XOR Operation Addressing Area Skip Condition CY, fmem.bit 2 2 CY (fmem.bit) *4 CY, pmem.@L 2 2 CY (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY (H+mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) CY *4 pmem.@L, CY 2 2 (pmem7-2+L3-2.bit(L1-0)) CY *5 @H+mem.bit, CY 2 2 (H+mem3-0.bit) CY *1 A, #n4 1 1+S A A+n4 carry XA, #n8 2 2+S XA XA+n8 carry A, @HL 1 1+S A A+(HL) XA, rp' 2 2+S XA XA+rp' carry rp'1, XA 2 2+S rp'1 rp'1+XA carry A, @HL 1 1 A, CY A+(HL)+CY XA, rp' 2 2 XA, CY XA+rp'+CY rp'1, XA 2 2 rp'1, CY rp'1+XA+CY A, @HL 1 1+S A A-(HL) XA, rp' 2 2+S XA XA-rp' borrow rp'1, XA 2 2+S rp'1 rp'1-XA borrow A, @HL 1 1 A, CY A-(HL)-CY XA, rp' 2 2 XA, CY XA-rp'-CY rp'1, XA 2 2 rp'1, CY rp'1-XA-CY A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA *1 carry *1 *1 borrow *1 *1 ADDS No. of Machine Bytes Cycle Arithmetic MOV1 Operand Bit transfer Mnemonic Instruction Group *1 *1 Accumulator RORC A 1 1 CY A0, A3 CY, An-1 An manipulation NOT A 2 2 AA Increment/ INCS reg 1 1+S reg reg+1 reg=0 rp1 1 1+S rp1 rp1+1 rp1=00H @HL 2 2+S (HL) (HL)+1 *1 (HL)=0 mem 2 2+S (mem) (mem)+1 *3 (mem)=0 reg 1 1+S reg reg-1 reg=FH rp' 2 2+S rp' rp'-1 rp'=FFH decrement DECS Data Sheet U11917EJ2V1DS 25 PD75P3018A Instruction Group Comparison Mnemonic SKE Operand No. of Machine Bytes Cycle Operation Addressing Area Skip Condition reg, #n4 2 2+S Skip if reg=n4 reg=n4 @HL, #n4 2 2+S Skip if (HL)=n4 *1 (HL)=n4 A, @HL 1 1+S Skip if A=(HL) *1 A=(HL) XA, @HL 2 2+S Skip if XA=(HL) *1 XA=(HL) A, reg 2 2+S Skip if A=reg A=reg XA, rp' 2 2+S Skip if XA=rp' XA=rp' Carry flag SET1 CY 1 1 CY 1 manipulation CLR1 CY 1 1 CY 0 SKT CY 1 1+S NOT1 CY 1 1 CY CY SET1 mem.bit 2 2 (mem.bit) 1 *3 fmem.bit 2 2 (fmem.bit) 1 *4 pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0)) 1 *5 @H+mem.bit 2 2 (H+mem3-0.bit) 1 *1 mem.bit 2 2 (mem.bit) 0 *3 fmem.bit 2 2 (fmem.bit) 0 *4 pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0)) 0 *5 @H+mem.bit 2 2 (H+mem3-0.bit) 0 *1 mem.bit 2 2+S Skip if(mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if(fmem.bit)=1 *4 (fmem.bit)=1 SKT SKF SKTCLR AND1 OR1 XOR1 26 CY=1 pmem.@L 2 2+S Skip if(pmem7-2+L3-2.bit(L1-0))=1 *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if(mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+S Skip if(fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if(pmem7-2+L3-2.bit(L1-0))=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=0 *1 (@H+mem.bit)=0 fmem.bit 2 2+S Skip if(fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY C (H+mem3-0.bit) *1 CLR1 manipulation Memory bit Skip if CY=1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3-0.bit) *1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7-2+L3-2.bit(L1-0)) *5 CY, @H+mem.bit 2 2 CY C (H+mem3-0.bit) *1 Data Sheet U11917EJ2V1DS PD75P3018A Instruction Group Branch Mnemonic BRNote 1 Operand No. of Machine Bytes Cycle Operation Addressing Area addr -- -- PC14 0, PC13-0 addr Use the assembler to select the most appropriate instruction among the following. * BR !addr * BRCB !caddr * BR $addr *6 addr1 -- -- PC14-0 addr1 Use the assembler to select the most appropriate instruction among the following. * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 *11 !addr 3 3 PC14 0, PC13-0 addr *6 $addr 1 2 PC14 0, PC13-0 addr *7 $addr1 1 2 PC14-0 addr1 PCDE 2 3 PC14 0, PC13-0 PC13-8+DE Skip Condition PC14-0 PC14-8+DE PCXA 2 3 PC14 0, PC13-0 PC13-8+XA PC14-0 PC14-8+XA BCDE 2 3 PC14 0, PC13-0 BCDENote 2 *6 PC14-0 BCDE *11 Note 2 BCXA 2 3 PC14 0, PC13-0 BCXA PC14-0 BCXA Note 1 BRA Note 1 BRCB !addr !caddr Note 2 Note 2 *6 *11 3 3 PC14 0, PC13-0 addr *6 3 3 PC14-0 addr1 *11 2 2 PC14 0, PC13-0 PC13, 12+caddr11-0 *8 PC14-0 PC14, 13, 12+caddr11-0 Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 2. The only following bits are valid in the B register. For Mk I mode : Low-order 2 bits For Mk II mode : Low-order 3 bits Data Sheet U11917EJ2V1DS 27 PD75P3018A Instruction Group Subroutine Mnemonic CALLANote Operand !addr1 No. of Machine Bytes Cycle 3 3 Operation (SP-5) 0, PC14-12 Addressing Area Skip Condition *11 (SP-6)(SP-3)(SP-4) PC11-0 stack control (SP-2) X, X, MBE, RBE PC14-0 addr1, SP SP-6 Note CALL !addr 3 3 (SP-4)(SP-1)(SP-2) PC11-0 *6 (SP-3) MBE, RBE, PC13, 12 PC14 0, PC13-0 addr, SP SP-4 4 (SP-5) 0, PC14-12 (SP-6)(SP-3)(SP-4) PC11-0 (SP-2) X, X, MBE, RBE PC14 0, PC13-0 addr, SP SP-6 CALLFNote !faddr 2 2 (SP-4)(SP-1)(SP-2) PC11-0 *9 (SP-3) MBE, RBE, PC13, 12 PC14 0, PC13-0 000+faddr, SP SP-4 3 (SP-5) 0, PC14-12 (SP-6)(SP-3)(SP-4) PC11-0 (SP-2) X, X, MBE, RBE PC14-0 0000+faddr, SP SP-6 Note RET 1 3 MBE, RBE, PC13, 12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PC14 0, SP SP+4 X, X, MBE, RBE (SP+4) 0, PC14-12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+6 Note RETS 1 3+S MBE, RBE, PC13, 12 (SP+1) Unconditional PC11-0 (SP)(SP+3)(SP+2) PC14 0, SP SP+4 then skip unconditionally X, X, MBE, RBE (SP+4) 0, PC14-12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+6 then skip unconditionally RETINote 1 3 MBE, RBE, PC13, 12 (SP+1), PC14 0 PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 0, PC14-12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. 28 Data Sheet U11917EJ2V1DS PD75P3018A Instruction Group Subroutine Mnemonic 1 (SP-1)(SP-2) rp, SP SP-2 BS 2 2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp 1 1 rp (SP+1)(SP), SP SP+2 BS 2 2 MBS (SP+1), RBS (SP), SP SP+2 2 2 IME(IPS.3) 1 2 2 IEXXX 1 2 2 IME(IPS.3) 0 IEXXX 2 2 IEXXX 0 A, PORTn 2 2 A PORTn XA, PORTn 2 2 XA PORTn+1, PORTn (n=4, 6) PORTn, A 2 2 PORTn A PORTn, XA 2 2 PORTn+1, PORTn XA (n=4, 6) HALT 2 2 Set HALT Mode(PCC.2 1) STOP 2 2 Set STOP Mode(PCC.3 1) NOP 1 1 No Operation RBn 2 2 RBS n (n=0-3) MBn 2 2 MBS n (n=0-3, 15) taddr 1 3 * When using TBR instruction EI control IEXXX DI Note 1 IN OUTNote 1 CPU control Special Operation 1 POP I/O No. of Machine Bytes Cycle rp PUSH stack control Interrupt Operand SEL Note 2, 3 GETI Addressing Area Skip Condition (n=0-7) (n=2-7) *10 PC13-0 (taddr)5-0+(taddr+1), PC14 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - * When using TCALL instruction (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, 12, PC14 0 PC13-0 (taddr)5-0+(taddr+1) SP SP-4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions 1 3 * When using TBR instruction Determined by referenced instruction *10 PC13-0 (taddr)5-0+(taddr+1), PC14 0 -- - - - - - - -- -- -- -- -- -- -- -- -- -- -- ------- -- -- -- -- -- -- -- -- -- -- -- 4 - - - - - - - - - - - - * When using TCALL instruction (SP-5) 0, PC14-12 (SP-6)(SP-3)(SP-4) PC11-0 (SP-2) X, X, MBE, RBE, PC14 0 PC13-0 (taddr)5-0+(taddr+1) SP SP-6 - - - - -- -- -- -- -- -- -- -- -- -- -- -- ----- -- -- -- -- -- -- -- -- -- -- -- -- - - 3 * When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instructions - - - - - - - - - - - - Determined by referenced instruction Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction's table definitions. 3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only. Data Sheet U11917EJ2V1DS 29 PD75P3018A 8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY The program memory contained in the PD75P3018A is a 32768 x 8-bit one-time PROM that can be electrically written one time only. The pins listed in the table below are used for this one-time PROM's write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses. Pin Function VPP Pin where program voltage is applied during program memory write/verify (usually VDD potential) X1, X2 Clock input pins for address updating during program memory write/verify. Input the X1 pin's inverted signal to the X2 pin. MD0-MD3 Operation mode selection pin for program memory write/verify D0/P40 to D3/P43 (low-order 4 bits) D4/P50 to D7/P53 (high-order 4 bits) 8-bit data I/O pins for program memory write/verify VDD Pin where power supply voltage is applied. Applies VDD = 1.8 to 5.5 V in normal operation mode and +6 V for program memory write/verify. Caution Pins not used for program memory write/verify should be connected to VSS via a resistor individually. 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD75P3018A enters the program memory write/verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation Mode Specification Operation Mode VPP VDD MD0 MD1 MD2 MD3 +12.5 V +6 V H L H L Zero-clear program memory address L H H H Write mode L L H H Verify mode H X H H Program inhibit mode X: L or H 30 Data Sheet U11917EJ2V1DS PD75P3018A 8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Write data in the 1 ms write mode. (7) Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7). (8) (X : number of write operations from steps (6) and (7)) x 1 ms additional write. (9) Apply four pulses to the X1 pin to increment the program memory address by one. (10) Repeat steps (6) to (9) until the end address is reached. (11) Select the zero-clear program memory address mode. (12) Return the VDD and VPP pins back to 5 V. (13) Turn off the power. The following figure shows steps (2) to (9). X repetitions Write VPP Verify Additional write Address increment VPP VDD VDD + 1 VDD VDD X1 D0/P40 to D3/P43 D4/P50 to D7/P53 Data input Data output Data input MD0/P30 MD1/P31 MD2/P32 MD3/P33 Data Sheet U11917EJ2V1DS 31 PD75P3018A 8.3 Program Memory Read Procedure The PD75P3018A can read program memory contents using the following procedure. (1) Pull unused pins to Vss through resistors. Set the X1 pin low. (2) Supply 5 V to the VDD and VPP pins. (3) Wait 10 s. (4) Select the zero-clear program memory address mode. (5) Supply 6 V to the VDD and 12.5 V to the VPP pins. (6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one address. (7) Select the zero-clear program memory address mode. (8) Return the VDD and VPP pins back to 5 V. (9) Turn off the power. The following figure shows steps (2) to (7). VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40 to D3/P43 D4/P50 to D7/P53 Data output Data output MD0/P30 MD1/P31 "L" MD2/P32 MD3/P33 32 Data Sheet U11917EJ2V1DS PD75P3018A 8.4 One-time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC Electronics. Therefore, NEC Electronics recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening. Storage Temperature Storage Time 125C 24 hours Data Sheet U11917EJ2V1DS 33 PD75P3018A 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Symbol Conditions Ratings Unit Supply voltage VDD -0.3 to +7.0 V PROM supply voltage VPP -0.3 to +13.5 V Input voltage VI1 Other than ports 4 and 5 -0.3 to VDD + 0.3 V VI2 Ports 4 and 5 (During N-ch open drain) -0.3 to +14 V -0.3 to VDD + 0.3 V Per pin -10 mA Total of all pins -30 mA Per pin 30 mA Output voltage VO High-level output current IOH Low-level output current IOL 220 mA Operating ambient temperature TA -40 to +85Note C Storage temperature Tstg -65 to +150 C Total of all pins Note To drive LCD in normal mode, TA = -10 to +85C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25C, VDD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO 15 pF 34 Data Sheet U11917EJ2V1DS PD75P3018A Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Ceramic resonator Parameter Conditions Oscillation frequency (fX)Note 1 X1 TYP. 1.0 C2 Oscillation stabilization timeNote 3 VDD Crystal resonator After VDD has reached MIN. value of oscillation voltage range Oscillation frequency (fX)Note 1 Unit 6.0Note 2 MHz 4 ms 1.0 6.0Note 2 MHz 10 ms X2 C1 C2 Oscillation stabilization timeNote 3 VDD = 4.5 to 5.5 V 30 VDD External clock X1 MAX. X2 C1 X1 MIN. X1 input frequency (fX)Note 1 1.0 6.0Note 2 MHz X1 input high-/ low-level width (tXH, tXL) 83.3 500 ns X2 Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, do not select processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than 0.95 s, falling short of the rated value of 0.95 s. 3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillator, wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U11917EJ2V1DS 35 PD75P3018A Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Crystal resonator Parameter Conditions Oscillation frequency (fXT)Note 1 XT1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.0 2 s XT2 R C3 C4 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V 10 VDD External clock XT1 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high-/ low-level width (tXTH, tXTL) 5 15 s XT2 Notes 1. The oscillation frequency and XT1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillator , wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillator. The subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 36 Data Sheet U11917EJ2V1DS PD75P3018A DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Low-level output Symbol IOL current High-level input VIH1 Conditions MAX. Unit Per pin 15 mA Total of all pins 150 mA VIH3 Low-level input 0.7VDD VDD V 1.8 V VDD < 2.7 V 0.9VDD VDD V 2.7 V VDD 5.5 V 0.8VDD VDD V 1.8 V VDD < 2.7 V 0.9VDD VDD V Ports 4, 5 2.7 V VDD 5.5 V 0.7VDD 13 V (N-ch open-drain) 1.8 V VDD < 2.7 V 0.9VDD 13 V VDD - 0.1 VDD V 2.7 V VDD 5.5 V 0 0.3VDD V 1.8 V VDD < 2.7 V 0 0.1VDD V 2.7 V VDD 5.5 V 0 0.2VDD V 1.8 V VDD < 2.7 V 0 0.1VDD V 0 0.1 V Ports 0, 1, 6, 7, RESET VIH4 X1, XT1 VIL1 Ports 2 to 5 voltage VIL2 High-level output Low-level output Ports 0, 1, 6, 7, RESET VIL3 X1, XT1 VOH SCK, SO, Ports 2, 3, 6, 7, BP0 to BP7 voltage TYP. 2.7 V VDD 5.5 V Ports 2, 3 voltage VIH2 MIN. VDD - 0.5 V IOH = -1.0 mA VOL1 voltage SCK, SO, Ports 2 to 7, IOL = 15 mA BP0 to BP7 VDD = 4.5 to 5.5 V 0.2 2.0 V 0.4 V 0.2VDD V Pins other than X1, XT1 3 A X1, XT1 20 A IOL = 1.6 mA VOL2 SB0, SB1 High-level input ILIH1 VIN = VDD leakage current ILIH2 N-ch open-drain Pull-up resistor 1 k ILIH3 VIN = 13 V Ports 4, 5 (N-ch open-drain) 20 A Low-level input ILIL1 VIN = 0 V Pins other than X1, XT1, Ports 4, 5 -3 A leakage current ILIL2 X1, XT1 -20 A ILIL3 Ports 4, 5 (N-ch open-drain) -3 A -30 A When input instruction is not executed Ports 4, 5 (N-ch opendrain). When input VDD = 5.0 V -10 -27 A instruction is executed VDD = 3.0 V -3 -8 A ILOH1 VOUT = VDD SCK, SO/SB0, SB1, Ports 2, 3, 6, 7 3 A leakage current ILOH2 VOUT = 13 V Ports 4, 5 (N-ch open-drain) 20 A Low-level output ILOL VOUT = 0 V -3 A RL VIN = 0 V 200 k High-level output leakage current Internal pull-up Ports 0 to 3, 6, 7 (except P00 pin) 50 100 resistor Data Sheet U11917EJ2V1DS 37 PD75P3018A DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol LCD drive voltage VLCD Conditions VAC0 = 0 MIN. VAC current IVAC LCD output voltage VODC deviation Unit 2.7 VDD V TA = -10 to +85C 2.2 VDD V 1.8 VDD V 4 A 0 0.2 V 0 0.2 V VAC0 = 1, VDD = 2.0 V 10% 1 IO = 1.0 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 Note 2 VLCD2 = VLCD x 1/3 (common) LCD output voltage VODS deviation MAX. TA = -40 to +85C VAC0 = 1 Note 1 TYP. IO = 0.5 A 1.8 V VLCD VDD Note 2 (segment) Supply currentNote 3 IDD1 IDD2 6.0 MHzNote 4 VDD = 5.0 V 10%Note 5 3.7 11.0 mA crystal VDD = 3.0 V 10%Note 6 0.73 2.2 mA oscillation HALT VDD = 5.0 V 10% 0.92 2.6 mA VDD = 3.0 V 10% C1 = C2 = 22 pF mode IDD1 IDD2 IDD3 0.3 0.9 mA VDD = 5.0 V 10% Note 5 2.7 8.0 mA crystal VDD = 3.0 V 10% Note 6 0.57 1.7 mA oscillation HALT VDD = 5.0 V 10% 0.90 2.5 mA C1 = C2 = 22 pF mode VDD = 3.0 V 10% 0.28 0.8 mA 32.768 VDD = 3.0 V 10% 42 126 A voltage VDD = 2.0 V 10% 37 110 A 42 84 A 39 117 A 39 78 A VDD = 3.0 V 10% 8.5 25 A voltage VDD = 2.0 V 10% 5.8 17 A 8.5 17 A 3.5 12 A 3.5 7 A XT1 = 0 VNote 10 VDD = 5.0 V 10% 0.05 10 A STOP mode VDD = 3.0 V 10% 0.02 5 A 0.02 3 A 4.19 MHz kHz IDD4 Note 4 Note 7 Low- Note 8 crystal mode oscillation VDD = 3.0 V, TA = 25C Low current VDD = 3.0 V 10% consumption VDD = 3.0 V, TA = 25C modeNote 9 HALT Lowmode mode Note 8 VDD = 3.0 V, TA = 25C Low current VDD = 3.0 V 10% consumption VDD = 3.0 V, TA = 25C modeNote 9 IDD5 TA = 25C Notes 1. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 A. 2. Voltage deviation is the difference between the ideal values (VLCDn ; n = 0, 1, 2) of the segment and common outputs and the output voltage. 3. The current flowing through the internal pull-up resistor is not included. 4. Including the case when the subsystem clock oscillates. 5. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 6. When the device operates in low-speed mode with PCC set to 0000. 7. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 8. When the sub-oscillation circuit control register (SOS) is set to 0000. 9. When the SOS is set to 0010. 10. When the SOS is set to 00x1, and the feedback resistor of the sub-oscillator is cut (x: don't care). 38 Data Sheet U11917EJ2V1DS PD75P3018A AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol CPU clock cycle time Note 1 tCY Conditions Operation with MIN. VDD = 2.7 to 5.5 V MAX. Unit 0.67 64 s 64 s 125 s 0 1.0 MHz 0 275 kHz (minimum instruction execution main system clock 0.95 time = 1 machine cycle) Operation with subsystem clock 114 TI0, TI1, TI2 input frequency TI0, TI1, TI2 input high-/ fTI tTIH, tTIL VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V low-level width TYP. 122 0.48 s 1.8 s Interrupt input high-/low-level tINTH, tINTL INT0 IM02 = 0 Note 2 s width IM02 = 1 10 s INT1, 2, 4 10 s KR0-7 10 s 10 s RESET low-level width tRSL Notes 1. The cycle time (minimum instruction execution time) of the CPU tCY vs VDD clock () is determined by the (with main system clock) oscillation frequency of the connected resonator 64 60 (and external clock), the system clock control register (SCC), and 6 processor clock control register 5 (PCC). supply voltage VDD vs. cycle time t CY characteristics when the device operates with the main system clock. Cycle time tCY [s] The figure on the right shows the Operation guaranteed range 4 3 2 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0). 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] Data Sheet U11917EJ2V1DS 39 PD75P3018A Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ... internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time tKCY1 SCK high-/low-level width SI SI Note 1 Note 1 Symbol tKL1, tKH1 setup time (to SCK ) tSIK1 hold time (from SCK ) tKSI1 SCK SO Note 1 output tKSO1 delay time Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V RL = 1 k, Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY1/2-50 ns tKCY1/2-150 ns 150 ns 500 ns 400 ns 600 ns 0 250 ns 0 1000 ns Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK ... external clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time tKCY2 SCK high-/low-level width SI Note 1 Symbol tKL2, tKH2 setup time (to SCK ) tSIK2 SINote 1 hold time (from SCK ) tKSI2 SCK SO Note 1 delay time output tKSO2 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V RL = 1 k, Note 2 VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns 400 ns 600 ns 0 300 ns 0 1000 ns Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead. 2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 40 Data Sheet U11917EJ2V1DS Unit PD75P3018A SBI mode (SCK ... internal clock output (master)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high-/low-level width SB0, 1 setup time Symbol tKCY3 tKL3, tKH3 tSIK3 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V (to SCK ) SB0, 1 hold time (from SCK ) tKSI3 SCK SB0, 1 output tKSO3 delay time RL = 1 k, Note VDD = 2.7 to 5.5 V CL = 100 pF MIN. TYP. MAX. Unit 1300 ns 3800 ns tKCY3/2-50 ns tKCY3/2-150 ns 150 ns 500 ns tKCY3/2 ns 0 250 ns 0 1000 ns SCK SB0, 1 tKSB tKCY3 ns SB0, 1 SCK tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line. SBI mode (SCK ... external clock input (slave)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time SCK high-/low-level width SB0, 1 setup time Symbol tKCY4 tKL4, tKH4 tSIK4 Conditions VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V (to SCK ) SB0, 1 hold time (from SCK ) tKSI4 SCK SB0, 1 output tKSO4 delay time MIN. TYP. MAX. 800 ns 3200 ns 400 ns 1600 ns 100 ns 150 ns tKCY4/2 RL = 1 k, Note VDD = 2.7 to 5.5 V CL = 100 pF Unit ns 0 300 ns 0 1000 ns SCK SB0, 1 tKSB tKCY4 ns SB0, 1 SCK tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line. Data Sheet U11917EJ2V1DS 41 PD75P3018A AC Timing Test Points (except X1 and XT1 inputs) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock Timing 1/fX tXL tXH VDD-0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD-0.1 V XT1 input 0.1 V TI0, TI1, TI2 Timing 1/fTI tTIL TI0, TI1, TI2 42 Data Sheet U11917EJ2V1DS tTIH PD75P3018A Serial Transfer Timing 3-wire Serial I/O Mode tKCY1,2 tKL1,2 tKH1,2 SCK tSIK1,2 SI tKSI1,2 Input data tKSO1,2 Output data SO 2-wire Serial I/O Mode tKCY1,2 tKL1,2 tKH1,2 SCK tSIK1,2 tKSI1,2 SB0, 1 tKSO1,2 Data Sheet U11917EJ2V1DS 43 PD75P3018A Serial Transfer Timing Bus Release Signal Transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSIK3, 4 tSBK SB0, 1 tKSO3, 4 Command Signal Transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSIK3, 4 tSBK SB0, 1 tKSO3, 4 Interrupt Input Timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET Input Timing tRSL RESET 44 Data Sheet U11917EJ2V1DS tKSI3, 4 tKSI3, 4 PD75P3018A Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85C) Parameter Symbol Data retention power Conditions MIN. VDDDR 1.8 tSREL 0 TYP. MAX. Unit 5.5 V supply voltage Release signal setup time Oscillation stabilization tWAIT wait timeNote 1 s 15 Released by RESET Released by interrupt request 2 /fX ms Note 2 ms Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Set by the basic interval timer mode register (BTM). (Refer to the table below.) Wait Time BTM3 BTM2 BTM1 BTM0 fX = 4.19 MHz fX = 6.0 MHz 20 20 - 0 0 0 2 /fX (approx. 250 ms) 2 /fX (approx. 175 ms) - 0 1 1 217/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms) - 1 0 1 215/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms) - 1 1 1 213/fX (approx. 1.95 ms) 213/fX (approx. 1.37 ms) Data Retention Timing (when STOP mode released by RESET) Internal reset operation HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (standby release signal: when STOP mode released by interrupt signal) HALT mode STOP mode Operation mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U11917EJ2V1DS 45 PD75P3018A DC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter Symbol High-level input voltage Conditions MIN. TYP. MAX. Unit 0.7VDD VDD V VDD - 0.5 VDD V VIH1 Pins other than X1, X2 VIH2 X1, X2 VIL1 Pins other than X1, X2 0 0.3VDD V VIL2 X1, X2 0 0.4 V Input leakage current ILI VIN = VIL or VIH 10 A High-level output voltage VOH IOH = -1 mA Low-level output voltage VOL IOL = 1.6 mA VDD supply current IDD VPP supply current IPP Low-level input voltage VDD - 1.0 V 0.4 V 30 mA 30 mA MAX. Unit MD0 = VIL, MD1 = VIH Cautions 1. Ensure that VPP does not exceed +13.5 V including overshoot. 2. VDD must be applied before VPP, and cut after VPP. AC Programming Characteristics (TA = 25 5C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter Symbol Note 1 Conditions MIN. TYP. tAS tAS 2 s MD1 setup time (to MD0) tM1S tOES 2 s Data setup time (to MD0) tDS tDS 2 s tAH tAH 2 s Data hold time (from MD0) tDH tDH 2 s Address setup time Address hold time Note 2 Note 2 (to MD0) (from MD0) MD0Data output float delay time tDF tDF 0 VPP setup time (to MD3) tVPS tVPS 2 130 s VDD setup time (to MD3) tVDS tVCS 2 s Initial program pulse width tPW tPW 0.95 Additional program pulse width tOPW tOPW 0.95 MD0 setup time (to MD1) tM0S tCES 2 MD0Data output delay time tDV tDV MD0 = MD1 = VIL MD1 hold time (from MD0) tM1H tOEH tM1H + tM1R 50 s MD1 recovery time (from MD0) tM1R tOR Program counter reset time tPCR X1 input high-/low-level widths 1.0 ns 1.05 ms 21.0 ms s 1 s 2 s 2 s -- 10 s tXH, tXL -- 0.125 s X1 input frequency fX -- Initial mode setting time tI -- 2 s MD3 setup time (to MD1) tM3S -- 2 s MD3 hold time (from MD1) tM3H -- 2 s tM3SR -- 2 s MD3 setup time (to MD0) 4.19 Program memory read Note 2 tDAD tACC Program memory read Note 2 Data output hold time from address tHAD tOH Program memory read 0 MD3 hold time (from MD0) tM3HR -- Program memory read 2 MD3Data output float delay time tDFR -- Program memory read Data output delay time from address MHz 2 s 130 s s 2 s Notes 1. Symbol of corresponding PD27C256A 2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin. 46 Data Sheet U11917EJ2V1DS PD75P3018A Program Memory Write Timing tVPS VPP VPP VDD VDD VDD+1 VDD tVDS tXH X1 tXL D0/P40-D3/P43 D4/P50-D7/P53 Data Output Data Input Data Input tDS tI tDS tDH tDV Data Input tDH tDF tAH tAS MD0/P30 tPW tM1R tM0S tOPW MD1/P31 tPCR tM1S tM1H MD2/P32 tM3S tM3H MD3/P33 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD tXH VDD X1 tXL tDAD tHAD D0/P40-D3/P43 D4/P50-D7/P53 Data Output Data Output tDV tI tDFR tM3HR MD0/P30 MD1/P31 tPCR MD2/P32 tM3SR MD3/P33 Data Sheet U11917EJ2V1DS 47 PD75P3018A 10. PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) A B 41 40 60 61 detail of lead end S C D Q R 21 20 80 1 F G J H I M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.20.4 B 14.00.2 C 14.00.2 D 17.20.4 F 0.825 G 0.825 H I 0.300.10 0.13 J 0.65 (T.P.) K 1.60.2 0.80.2 L M 0.15 +0.10 -0.05 N 0.10 P 2.70.1 Q 0.10.1 R 55 S 3.0 MAX. S80GC-65-3B9-6 48 Data Sheet U11917EJ2V1DS PD75P3018A 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G H I M P K S N S L M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 17.200.20 B 14.000.20 C 14.000.20 D 17.200.20 F 0.825 G 0.825 H I 0.320.06 0.13 J 0.65 (T.P.) K 1.600.20 L 0.800.20 M 0.17 +0.03 -0.07 N P Q R S 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1 Data Sheet U11917EJ2V1DS 49 PD75P3018A 80 PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 41 61 40 detail of lead end S C D Q R 21 80 1 20 F G H I J M K P M N S L NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. S ITEM MILLIMETERS A 14.000.20 B 12.000.20 C 12.000.20 D F 14.000.20 1.25 G 1.25 H 0.22 +0.05 -0.04 I 0.10 J 0.50 (T.P.) K 1.000.20 L 0.500.20 M 0.145 +0.055 -0.045 N 0.10 P 1.050.07 Q 0.100.05 R 55 S 1.27 MAX. P80GK-50-BE9-6 50 Data Sheet U11917EJ2V1DS PD75P3018A 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 41 61 40 detail of lead end S C D P T 80 R 21 1 20 U Q F G L H I J M K S N M S NOTE ITEM Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A B 14.00.2 12.00.2 C 12.00.2 D F 14.00.2 1.25 G 1.25 H 0.220.05 I 0.08 J 0.5 (T.P.) K L 1.00.2 0.5 M 0.1450.05 N 0.08 P 1.0 Q 0.10.05 R +4 3 -3 S 1.10.1 T 0.25 U 0.60.15 P80GK-50-9EU-1 Data Sheet U11917EJ2V1DS 51 PD75P3018A 11. RECOMMENDED SOLDERING CONDITIONS The PD75P3018A should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 11-1. Surface Mounting Type Soldering Conditions (1/3) (1) PD75P3018AGC-3B9: 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once WS60-00-1 Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) -- Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. (2) PD75P3018AGC-8BT: 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less IR35-00-2 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less VP15-00-2 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once WS60-00-1 Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) -- Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. 52 Data Sheet U11917EJ2V1DS PD75P3018A Table 11-1. Surface Mounting Type Soldering Conditions (2/3) (3) PD75P3018AGK-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) IR35-107-3 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) VP15-107-3 Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note -- After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. (4) PD75P3018AGK-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) IR35-107-2 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 to 72 hours) VP15-107-2 Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note -- After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. Data Sheet U11917EJ2V1DS 53 PD75P3018A Table 11-1. Surface Mounting Type Soldering Conditions (3/3) (5) PD75P3018AGC-3B9-A: 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) PD75P3018AGC-8BT-A: 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 to 72 hours) Wave soldering For details, contact an NEC Electronics sales representative. -- Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) -- Note IR60-207-3 After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with "-A" at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. (6) PD75P3018AGK-9EU-A: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 to 72 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note Recommended Condition Symbol IR60-207-3 -- After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with "-A" at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics sales representative. 54 Data Sheet U11917EJ2V1DS PD75P3018A APPENDIX A. PD75316B, 753017A AND 75P3018A FUNCTION LIST PD75316B PD753017A PD75P3018A Mask ROM 0000H-3F7FH (16256 x 8 bits) Mask ROM 0000H-5FFFH (24576 x 8 bits) One-time PROM 0000H-7FFFH (32768 x 8 bits) Parameter Program memory Data memory 000H-3FFH (1024 x 4 bits) CPU 75X Standard 75XL CPU When main system clock is selected 0.95, 1.91, or 15.3 s (at 4.19 MHz operation) * 0.95, 1.91, 3.81, or 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, or 10.7 s (at 6.0 MHz operation) When subsystem clock is selected 122 s (at 32.768 kHz operation) 29 to 32 P40 to P43 P40/D0 to P43/D3 34 to 37 P50 to P53 P50/D4 to P53/D7 44 P12/INT2 P12/INT2/TI1/TI2 47 P21 P21/PTO1 48 P22/PCL P22/PCL/PTO2 50 to 53 P30 to P33 P30/MD0 to P33/MD3 57 IC VPP SBS register None SBS.3 = 1; Mk I mode selection SBS.3 = 0; Mk II mode selection Stack area 000H-0FFH n00H-nFFH (n = 0-3) Subroutine call instruction stack operation 2-byte stack Mk I mode: 2-byte stack Mk II mode: 3-byte stack BRA !addr1 CALLA !addr1 Unavailable Mk I mode: unavailable Mk II mode: available Instruction execution time Pin connection Stack Instruction MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA Available CALL !addr 3 machine cycles Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles Mask option Yes None Timer 3 channels: * Basic interval timer : 1 channel * 8-bit timer/event counter : 1 channel * Watch timer: 1 channel 5 channels: * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter, carrier generator, timer with gate) * Watch timer: 1 channel Data Sheet U11917EJ2V1DS 55 PD75P3018A PD75316B Parameter PD753017A PD75P3018A Clock output (PCL) , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) * , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) BUZ output (BUZ) 2 kHz (Main system clock: at 4.19 MHz operation) * 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: at 6.0 MHz operation) Serial interface 3 modes are available * 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode * SBI mode SOS register Feedback resistor cut flag (SOS.0) None Provided Sub-oscillator current cut flag (SOS.1) None Provided Register bank selection register (RBS) None Yes Standby release by INT0 Unavailable Available Interrupt priority selection register (IPS) None Yes Vectored interrupt External: 3, Internal: 3 External: 3, Internal: 5 Supply voltage VDD = 2.0 to 6.0 V VDD = 1.8 to 5.5 V Operating ambient temperature TA = -40 to +85C Package * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 80-pin plastic QFP (14 x 14 mm) 56 Data Sheet U11917EJ2V1DS PD75P3018A APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PD75P3018A. In the 75XL Series, the relocatable assembler common to series is used in combination with the device file of each type. RA75X relocatable assembler Host machine Part No. (name) OS PC-9800 Series Supply medium TM MS-DOS 3.5" 2HD S5A13RA75X 3.5" 2HC S7B13RA75X Ver.3.30 to Ver.6.2Note Device file IBM PC/ATTM Refer to "OS for or compatible IBM PCs" Host machine Part No. (name) PC-9800 Series OS Supply medium MS-DOS 3.5" 2HD S5A13DF753017 3.5" 2HC S7B13DF753017 Ver.3.30 to Ver.6.2Note IBM PC/AT Refer to "OS for or compatible IBM PCs" Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described above. Data Sheet U11917EJ2V1DS 57 PD75P3018A PROM Write Tools Hardware Software PG-1500 This is a PROM programmer that can program single-chip microcontroller with PROM in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 K to 4 M bits. PA-75P316BGC This is a PROM programmer adapter for the PD75P3018AGC-3B9. It can be used when connected to a PG-1500. PA-75P316BGK This is a PROM programmer adapter for the PD75P3018AGK-BE9. It can be used when connected to a PG-1500. PA-75P3018AGC-8BT This is a PROM programmer adapter for the PD75P3018AGC-8BT. It can be used when connected to a PG-1500. PA-75P3018AGK-9EU This is a PROM programmer adapter for the PD75P3018AGK-9EU. It can be used when connected to a PG-1500. PG-1500 controller Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on host machine. Host machine Part No. (name) PC-9800 Series OS Supply medium MS-DOS 3.5" 2HD S5A13PG1500 3.5" 2HD S7B13PG1500 Ver.3.30 to Ver.6.2Note IBM PC/AT Refer to "OS for or compatible IBM PCs" Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark 58 Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above. Data Sheet U11917EJ2V1DS PD75P3018A Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P3018A. Various system configurations using these in-circuit emulators are listed below. Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. For development of the PD75P3018A, the IE-75000-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. The IE-75000-R includes a connected emulation board (IE-75000-R-EM). IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. IE-75300-R-EM This is an emulation board for evaluating application systems using the PD75P3018A. It is used in combination with the IE-75000-R or IE-75001-R. EP-753018GC-R This is an emulation probe for the PD75P3018AGC. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. EV-9200GC-80 EP-753018GK-R It includes a 80-pin conversion socket (EV-9200GC-80) to facilitate connections with target system. This is an emulation probe for the PD75P3018AGK. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. TGK-080SDWNote 2 It includes a 80-pin conversion adapter (TGK-080SDW) to facilitate connections with target system. Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface. Host machine Part No. (name) PC-9800 Series OS Supply medium MS-DOS 3.5" 2HD S5A13IE75X 5" 2HD S5A10IE75X Ver.3.30 to Ver.6.2Note 3 IBM PC/AT Refer to "OS for 3.5" 2HC S7B13IE75X or compatible IBM PCs" 5" 2HC S7B10IE75X Notes 1. This is a maintenance product. 2. This is a product of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics 2nd Department (TEL +81-6-6244-6672) 3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the IE control program is guaranteed only when using the host machine and OS described above. Data Sheet U11917EJ2V1DS 59 PD75P3018A OS for IBM PCs The following operating systems for the IBM PC are supported. OS TM PC DOS Version Ver.5.02 to Ver.6.3 J6.1/V to J6.3/V MS-DOS Ver.5.0 to Ver.6.22 5.0/V to 6.2/V IBM DOSTM J5.02/V Caution Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. 60 Data Sheet U11917EJ2V1DS PD75P3018A APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents Document No. Document Name Japanese English PD753012A, 753016A, 753017A Data Sheet U11662J U11662E PD75P3018A Data Sheet U11917J U11917E PD753017 User's Manual U11282J U11282E PD753017 Instruction Table IEM-5598 -- 75XL Series Selection Guide U10453J U10453E (This document) Development Tool Related Documents Document No. Document Name Hardware Software Japanese English IE-75000-R/IE-75001-R User's Manual EEU-846 EEU-1416 IE-75300-R-EM User's Manual U11354J U11354E EP-753017GC/GK-R User's Manual EEU-967 EEU-1495 PG-1500 User's Manual U11940E U11940E RA75X Assembler Package Operation U12622J U12622E User's Manual Language U12385J U12385E PG-1500 Controller User's Manual PC-9800 Series (MS-DOS) base EEU-704 EEU-1291 IBM PC Series (PC DOS) base EEU-5008 U10540E Other Related Documents Document No. Document Name Japanese SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) English X13769X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices Electrostatic Discharge (ESD) C11892J C11892E Guide to Microcontroller-Related Products by Third Parties U11416J -- Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents. Data Sheet U11917EJ2V1DS 61 PD75P3018A NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. 62 Data Sheet U11917EJ2V1DS PD75P3018A Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 Data Sheet U11917EJ2V1DS 63 PD75P3018A MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of August, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1