UPD75P3018AGC-8BT-A - RENESAS TECHNOLOGY

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DESCRIPTION

The

PD75P3018A replaces the

PD753017A’s internal mask ROM with a one-time PROM, and features expanded

ROM capacity. The

PD75P3018A inherits the function of the

PD75P3018, and enables high-speed operation at

a low supply voltage of 1.8 V.

Because the

PD75P3018A supports programming by users, it is suitable for use in evaluation of systems in

development stages using the

PD753012A, 753016A, or 753017A, and for use in small-scale production.

The following document describes further details of the functions. Please make sure to read this document

before starting design.

PD753017 User’s Manual : U11282E

FEATURES

Compatible with

PD753017A

Memory capacity:

• PROM : 32768 × 8 bits

• RAM : 1024 × 4 bits

Can operate in the same power supply voltage as the mask version

PD753017A

• VDD = 1.8 to 5.5 V

LCD controller/driver

ORDERING INFORMATION

Part Number Package

PD75P3018AGC-3B9 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

PD75P3018AGC-3B9-A 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

PD75P3018AGC-8BT 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

PD75P3018AGC-8BT-A 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

PD75P3018AGK-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

PD75P3018AGK-9EU 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

PD75P3018AGK-9EU-A 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

Caution Mask-option pull-up resistors are not provided in this device.

Remark Products with "-A" at the end of the part number are lead-free products.

PD75P3018A

MOS INTEGRATED CIRCUIT

4-BIT SINGLE-CHIP MICROCONTROLLER

The mark shows major revised points.

Document No. U11917EJ2V1DS00 (2nd edition)

Date Published August 2005 N CP (K)

Printed in Japan

DATA SHEET

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

PD75P3018A

2Data Sheet U11917EJ2V1DS

FUNCTION OUTLINE

Item Function

Instruction execution time • 0.95, 1.91, 3.81, 15.3

s (main system clock: at 4.19 MHz operation)

• 0.67, 1.33, 2.67, 10.7

s (main system clock: at 6.0 MHz operation)

• 122

s (subsystem clock: at 32.768 kHz operation)

Internal memory PROM 32768 × 8 bits

RAM 1024 × 4 bits

General-purpose register • 4-bit operation: 8 × 4 banks

• 8-bit operation: 4 × 4 banks

Input/output port CMOS input 8 On-chip pull-up resistor connection can be specified by using software: 23

CMOS input/output 16

CMOS output 8 Also used for segment pins

N-ch open-drain input/output

813 V breakdown voltage

Total 40

LCD controller/driver • Segment number selection : 24/28/32 segments (can be changed to CMOS

output port in unit of 4; max. 8)

• Display mode selection : Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias)

1/3 duty (1/3 bias), 1/4 duty (1/3 bias)

Timer 5 channels:

• 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter,

carrier generator, timer with gate)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit

• 2-wire serial I/O mode

• SBI mode

Bit sequential buffer (BSB) 16 bits

Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)

• Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)

Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation

or subsystem clock: at 32.768 kHz operation)

• 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation)

Vectored interrupt • External : 3

• Internal : 5

Test input • External : 1

• Internal : 1

System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation

• Crystal oscillator for subsystem clock oscillation

Standby function STOP/HALT mode

Power supply voltage VDD = 1.8 to 5.5 V

Package • 80-pin plastic QFP (14 × 14 mm)

• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

PD75P3018A

Data Sheet U11917EJ2V1DS

CONTENTS

1. PIN CONFIGURATION (Top View) ................................................................................................4

2. BLOCK DIAGRAM ........................................................................................................................... 5

3. PIN FUNCTIONS .............................................................................................................................. 6

3.1 Port Pins ................................................................................................................................................... 6

3.2 Non-port Pins ........................................................................................................................................... 8

3.3 Pin Input/Output Circuits ......................................................................................................................... 10

3.4 Recommended Connection for Unused Pins ........................................................................................ 12

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 13

4.1 Difference between Mk I Mode and Mk II Mode ..................................................................................... 13

4.2 Setting of Stack Bank Selection Register (SBS) ................................................................................... 14

5. DIFFERENCES BETWEEN

PD75P3018A AND

PD753012A, 753016A, AND 753017A ....... 15

6. MEMORY CONFIGURATION .......................................................................................................... 16

6.1 Program Counter (PC) ............................................................................................................................. 16

6.2 Program Memory (PROM) ....................................................................................................................... 16

6.3 Data Memory (RAM) ................................................................................................................................. 19

7. INSTRUCTION SET ......................................................................................................................... 20

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ............................................. 30

8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 30

8.2 Program Memory Write Procedure ......................................................................................................... 31

8.3 Program Memory Read Procedure ......................................................................................................... 32

8.4 One-time PROM Screening ..................................................................................................................... 33

9. ELECTRICAL SPECIFICATIONS ....................................................................................................34

10. PACKAGE DRAWINGS ................................................................................................................... 48

11. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 52

APPENDIX A.

PD75316B, 753017A AND 75P3018A FUNCTION LIST .......................................... 55

APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 57

APPENDIX C. RELATED DOCUMENTS ............................................................................................... 61

PD75P3018A

4Data Sheet U11917EJ2V1DS

1. PIN CONFIGURATION (Top View)

•80-pin plastic QFP (14 × 14 mm)

PD75P3018AGC-3B9, 75P3018AGC-3B9-A, 75P3018AGC-8BT, 75P3018AGC-8BT-A

•80-pin plastic TQFP (fine pitch) (12 × 12 mm)

PD75P3018AGK-BE9, 75P3018AGK-9EU, 75P3018AGK-9EU-A

Note Connect the VPP directly to VDD during normal operation.

PIN IDENTIFICATIONS

BIAS : LCD Power Supply Bias Control P70-P73 : Port7

BP0-BP7 : Bit Port 0-7 PCL : Programmable Clock

BUZ : Buzzer Clock PTO0-PTO2 : Programmable Timer Output 0-2

COM0-COM3 : Common Output 0-3 RESET : Reset

D0-D7 : Data Bus 0-7 S0-S31 : Segment Output 0-31

INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 SB0, SB1 : Serial Bus 0,1

INT2 : External Test Input 2 SCK : Serial Clock

KR0-KR7 : Key Return 0-7 SI : Serial Input

LCDCL : LCD Clock SO : Serial Output

MD0-MD3 : Mode Selection 0-3 SYNC : LCD Synchronization

P00-P03 : Port0 TI0-TI2 : Timer Input 0-2

P10-P13 : Port1 VDD : Positive Power Supply

P20-P23 : Port2 VLC0-VLC2 : LCD Power Supply 0-2

P30-P33 : Port3 VPP : Programming Power Supply

P40-P43 : Port4 Vss : Ground

P50-P53 : Port5 X1, X2 : Main System Clock Oscillation 1, 2

P60-P63 : Port6 XT1, XT2 : Subsystem Clock Oscillation 1, 2

S11

S10

RESET

P73/KR7

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24/BP0

S25/BP1

S26/BP2

S27/BP3

S28/BP4

S29/BP5

S30/BP6

S31/BP7

COM0

COM1

COM2

COM3

BIAS

LC0

LC1

LC2

P40/D0

P41/D1

P42/D2

P43/D3

Vss

P50/D4

P51/D5

P52/D6

P53/D7

P00/INT4

P01/SCK

P02/SO/SB0

P60/KR0

PPNote

XT2

XT1

P33/MD3

P32/MD2

P31/SYNC/MD1

P30/LCDCL/MD0

P23/BUZ

P22/PCL/PTO2

P21/PTO1

P20/PTO0

P13/TI0

P12/INT2/TI1/TI2

P11/INT1

P10/INT0

P03/SI/SB1

PD75P3018A

Data Sheet U11917EJ2V1DS

2. BLOCK DIAGRAM

PORT0 P00 to P034

PORT1 P10 to P134

PORT2 P20 to P234

PORT3 P30/MD0 to

P33/MD3

PORT4 P40/D0 to

P43/D3

PORT5 P50/D4 to

P53/D7

PORT6 P60 to P634

PORT7 P70 to P734

LCD

CONTROLLER

/DRIVER

S0 to S2324

S24/BP0 to

S31/BP7

COM0 to

COM3

LC0

to V

LC2

BIAS

LCDCL/P30/MD0

SYNC/P31/MD1

LCD

RESETV

CPU CLOCK Φ

STAND BY

CONTROL

X2X1XT2XT1

SYSTEM CLOCK

GENERATOR

MAINSUB

CLOCK

DIVIDER

CLOCK

OUTPUT

CONTROL

fx/2

PCL/PTO2/P22

GENERAL

REG.

RAM

DATA

MEMORY

1024 x 4 BITS

BANK

SBS

SP (8)

ALU

DECODE

AND

CONTROL

TIMER/EVENT

COUNTER

PTO1/P21

INTT1

TIMER/EVENT

COUNTER

PTO2/P22/PCL

INTT2

BASIC

INTERVAL

TIMER/

WATCHDOG

TIMER

INTBT

TIMER/EVENT

COUNTER

TI0/P13

INTT0

CLOCKED

SERIAL

INTERFACE

SI/SB1/P03

INTCSI

INTERRUPT

CONTROL

INT0/P10

TI1/TI2/

P12/INT2

PTO0/P20

TOUT0

WATCH

TIMER

INTW

BUZ/P23

LCD

SO/SB0/P02

SCK/P01

TOUT0

INT1/P11

INT2/P12/TI1/TI2

INT4/P00

KR0/P60 to

KR7/P73

BIT SEQ.

BUFFER (16)

PROGRAM

COUNTER

(15)

PROM

PROGRAM

MEMORY

32768 x 8 BITS

TOUT0

PD75P3018A

6Data Sheet U11917EJ2V1DS

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin Name I/O Alternate Function Function 8-bit After Reset I/O Circuit

I/O TypeNote 1

P00 Input INT4 This is a 4-bit input port (PORT0). — Input

P01 to P03 are 3-bit pins for which an internal

P01 SCK pull-up resistor connection can be specified <F>-A

by software.

P02 SO/SB0 <F>-B

P03 SI/SB1 <M>-C

P10 Input INT0 This is a 4-bit input port (PORT1). — Input -C

These are 4-bit pins for which an internal pull-up

P11 INT1 resistor connection can be specified by software.

P10/INT0 can select noise elimination circuit.

P12 TI1/TI2/INT2

P13 TI0

P20 I/O PTO0 This is a 4-bit I/O port (PORT2). — Input E-B

These are 4-bit pins for which an internal pull-up

P21 PTO1 resistor connection can be specified by software.

P22 PCL/PTO2

P23 BUZ

P30 I/O LCDCL/MD0 This is a programmable 4-bit I/O port (PORT3). — Input E-B

Input and output in single-bit units can be specified.

P31 SYNC/MD1 When set for 4-bit units, an internal pull-up resistor

connection can be specified by software.

P32 MD2

P33 MD3

P40Note 2 I/O D0 This is an N-ch open-drain 4-bit I/O port (PORT4). √High M-E

When set to open-drain, voltage is 13 V. impedance

P41Note 2 D1 Also functions as data I/O pin (low-order 4 bits)

for program memory (PROM) write/verify.

P42Note 2 D2

P43Note 2 D3

P50Note 2 I/O D4 This is an N-ch open-drain 4-bit I/O port (PORT5). High M-E

When set to open-drain, voltage is 13 V. impedance

P51Note 2 D5 Also functions as data I/O pin (high-order 4 bits)

for program memory (PROM) write/verify.

P52Note 2 D6

P53Note 2 D7

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.

2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.

PD75P3018A

Data Sheet U11917EJ2V1DS

3.1 Port Pins (2/2)

Pin Name I/O Alternate Function Function 8-bit After Reset I/O Circuit

I/O TypeNote 1

P60 I/O KR0 This is a programmable 4-bit I/O port (PORT6). √Input <F>-A

Input and output in single-bit units can be specified.

P61 KR1 When set for 4-bit units, an internal pull-up resistor

connection can be specified by software.

P62 KR2

P63 KR3

P70 I/O KR4 This is a 4-bit I/O port (PORT7). Input <F>-A

When set for 4-bit units, an internal pull-up resistor

P71 KR5 connection can be specified by software.

P72 KR6

P73 KR7

BP0 Output S24 1-bit output port (BIT PORT). These pins are also — Note 2 H-A

used as segment output pin.

BP1 S25

BP2 S26

BP3 S27

BP4 Output S28

BP5 S29

BP6 S30

BP7 S31

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.

2. VLC1 is selected as the input source for BP0 to BP7. The output level varies depending on the external circuit

for BP0 to BP7 and VLC1.

Example: As shown below, BP0 to BP7 are mutually connected via the

PD75P3018A, so the output levels of BP0 to BP7

are determined by the sizes of R1, R2, and R3.

LC1

BP0

BP1

PD75P3018A

8Data Sheet U11917EJ2V1DS

3.2 Non-port Pins (1/2)

Pin Name I/O Alternate Function Function After Reset I/O Circuit

TypeNote 1

TI0 Input P13 External event pulse input to timer/event counter Input -C

TI1, TI2 P12/INT2

PTO0 Output P20 Timer/event counter output Input E-B

PTO1 P21

PTO2 P22

PCL P22 Clock output

BUZ P23

Optional frequency output (for buzzer or system clock trimming)

SCK I/O P01 Serial clock I/O Input <F>-A

SO/SB0 P02 Serial data output <F>-B

Serial data bus I/O

SI/SB1 P03 Serial data input <M>-C

Serial data bus I/O

INT4 Input P00 Edge detection vectored interrupt input

(both rising and falling edges detection)

INT0 Input P10 Edge detection vectored interrupt input

Noise elimination circuit/

Input -C

(detected edge is selectable)

asynchronous is selectable

INT1 P11

INT0/P10 can select noise elimination circuit.

Asynchronous

INT2 P12/TI1/TI2 Rising edge detection testable input Asynchronous

KR0-KR3 Input P60-P63 Falling edge detection testable input Input <F>-A

KR4-KR7 Input P70-P73 Falling edge detection testable input Input <F>-A

X1 Input — Ceramic/crystal oscillation circuit connection for main system — —

clock. If using an external clock, input to X1 and input

X2 — inverted phase to X2.

XT1 Input — Crystal oscillation circuit connection for subsystem clock. — —

If using an external clock, input to XT1 and input inverted

XT2 — phase to XT2. XT1 can be used as a 1-bit (test) input.

RESET Input — System reset input (low level active) —

MD0 Input P30/LCDCL Mode selection for program memory (PROM) write/verify Input E-B

MD1 P31/SYNC

MD2, MD3 P32, P33

D0-D3 I/O P40-P43 Data bus for program memory (PROM) write/verify Input M-E

D4-D7 P50-P53

VPPNote 2 ——Program power supply voltage for program memory — —

(PROM) write/verify.

For normal operation, connect directly to VDD.

Apply +12.5 V for PROM write/verify.

VDD ——Positive power supply — —

Vss — — Ground — —

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.

2. The VPP pin does not operate correctly during normal operation unless connected to the VDD pin.

PD75P3018A

Data Sheet U11917EJ2V1DS

3.2 Non-port Pins (2/2)

Pin Name I/O Alternate Function Function After Reset I/O Circuit

Type

S0-S23 Output — Segment signal output Note 1 G-A

S24-S31 Output BP0-BP7 Segment signal output Note 1 H-A

COM0-COM3 Output — Common signal output Note 1 G-B

VLC0-VLC2 ——Power source for LCD driver — —

BIAS Output — Output for external split resistor cut High —

impedance

LCDCLNote 2 I/O P30/MD0 Clock output for driving external expansion driver Input E-B

SYNCNote 2 I/O P31/MD1 Clock output for synchronization of external expansion driver Input E-B

Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.

S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0

2. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

PD75P3018A

10 Data Sheet U11917EJ2V1DS

3.3 Pin Input/Output Circuits

The input/output circuits for the

PD75P3018A’s pins are shown in abbreviated form below.

(1/2)

P-ch

N-ch

P-ch

N-ch

OUT

Data

Output

disable

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R. : Pull-Up Resistor

Type A

P-ch P.U.R.

enable

P.U.R.

P.U.R. : Pull-Up Resistor

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R. : Pull-Up Resistor

Type B

CMOS standard input buffer Push-pull output that can be set to high impedance output

(with both P-ch and N-ch OFF).

Schmitt trigger input with hysteresis characteristics.

TYPE A TYPE D

TYPE E-BTYPE B

TYPE B-C TYPE F-A

PD75P3018A

Data Sheet U11917EJ2V1DS

(2/2)

TYPE F-B TYPE H-A

TYPE M-CTYPE G-A

TYPE G-B TYPE M-E

Output

disable

P-ch

N-ch

IN/OUT

Data

P-ch

P.U.R.

enable

P.U.R.

Output

disable

(N)

Output

disable

(P)

P.U.R. : Pull-Up Resistor

Type G-A

Voltage

controller

Type D

SEG

data

Output

disable

Bit Port

data

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Output

disable

P.U.R. : Pull-Up Resistor

N-ch

P-ch

OUT

N-ch

LC0

LC1

COM

data

LC2

N-ch

P-ch

Pull-up resistor operated only when executing input instructions

(when pins are low level, current flows from V

to pins).

Output

disable

Data N-ch

IN/OUT

(+13 V

withstand

voltage)

Note

P-ch

Input instruction

Note

P.U.R.

N-ch

VLC2

N-chP-ch

OUT

VLC0

VLC1

SEG

data

(+13 V

withstand

voltage)

PD75P3018A

12 Data Sheet U11917EJ2V1DS

3.4 Recommended Connection for Unused Pins

Pin Recommended Connection

P00/INT4 Connect to VSS or VDD

P01/SCK Connect to VSS or VDD via a resistor individually

P02/SO/SB0

P03/SI/SB1 Connect to VSS

P10/INT0, P11/INT1 Connect to VSS or VDD

P12/TI1/TI2/INT2

P13/TI0

P20/PTO0 Input : Connect to VSS or VDD via a resistor individually

P21/PTO1 Output : Leave open

P22/PTO2/PCL

P23/BUZ

P30/LCDCL/MD0

P31/SYNC/MD1

P32/MD2, P33/MD3

P40/D0-P43/D3 Connect to VSS

P50/D4-P53/D7

P60/KR0-P63/KR3

Input : Connect to VSS or VDD via a resistor individually

P70/KR4-P73/KR7 Output : Leave open

S0-S23 Leave open

S24/BP0-S31/BP7

COM0-COM3

VLC0-VLC2 Connect to VSS

BIAS Connect to VSS only when VLC0 to VLC2 are all not used.

In other cases, leave open.

XT1Note Connect to VSS

XT2Note Leave open

Note When subsystem clock is not used, specify SOS.0 = 1 (indicates that

internal feedback resistor is disconnected).

PD75P3018A

Data Sheet U11917EJ2V1DS

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

Setting a stack bank selection (SBS) register for the

PD75P3018A enables the program memory to be switched between

Mk I mode and Mk II mode. This function is applicable when using the

PD75P3018A to evaluate the

PD753012A,

753016A, or 753017A.

When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for

PD753012A, 753016A, and 753017A)

When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for

PD753012A, 753016A, and 753017A)

4.1 Difference between Mk I Mode and Mk II Mode

Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the

PD75P3018A.

Table 4-1. Difference between Mk I Mode and Mk II Mode

Item Mk I Mode Mk II Mode

Program counter PC13-0 PC14-0

PC14 is fixed at 0

Program memory (bytes) 16384 32768

Data memory (bits) 1024 × 4

Stack Stack bank Selectable via memory banks 0 to 3

No. of stack bytes 2 bytes 3 bytes

Instruction BRA !addr1 instruction Not available Available

CALLA !addr1 instruction

Instruction CALL !addr instruction 3 machine cycles 4 machine cycles

execution time CALLF !faddr instruction 2 machine cycles 3 machine cycles

Supported mask ROMs When set to Mk I mode: When set to Mk II mode:

PD753012A, 753016A, and 753017A

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore,

this mode is effective for enhancing software compatibility with products that have a program area of

more than 16 Kbytes.

With regard to the number of stack bytes during execution of subroutine call instructions, the usable

area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.

However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes

longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and

processing performance than on software compatibility, the Mk I mode should be used.

PD75P3018A

14 Data Sheet U11917EJ2V1DS

4.2 Setting of Stack Bank Selection Register (SBS)

Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing

this.

The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be

sure to initialize the stack bank selection register to 10XXBNote at the beginning of the program. When using the Mk II mode,

be sure to initialize it to 00XXBNote.

Note Set the desired value for XX.

Figure 4-1. Format of Stack Bank Selection Register

Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in Mk I mode. When using

instructions for Mk II mode, set SBS3 to “0” and set Mk II mode before using the instructions.

2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after

RESET input and after setting the stack bank selection register.

SBS3 SBS2 SBS1 SBS0F84H

Address 3 2 1 0

SBS

Symbol

Stack area specification

Memory bank 0

Memory bank 1

Memory bank 2

Memory bank 3

0 Be sure to set bit 2 to 0.

Mk II mode

Mk I mode

Mode selection specification

PD75P3018A

Data Sheet U11917EJ2V1DS

5. DIFFERENCES BETWEEN

PD75P3018A AND

PD753012A, 753016A, AND 753017A

The

PD75P3018A replaces the internal mask ROM in the

PD753012A, 753016A, and 753017A with a one-time PROM

and features expanded ROM capacity. The

PD75P3018A’s Mk I mode supports the Mk I mode in the

PD753012A,

753016A, and 753017A and the

PD75P3018A’s Mk II mode supports the Mk II mode in the

PD753012A, 753016A, and

753017A.

Table 5-1 lists differences among the

PD75P3018A and the

PD753012A, 753016A, and 753017A. Be sure to check

the differences among these products before using them with PROMs for debugging or prototype testing of application

systems or, later, when using them with a mask ROM for full-scale production.

For the CPU functions and internal hardwares, refer to

PD753017 User's Manual (U11282E).

Table 5-1. Differences between

PD75P3018A and

PD753012A, 753016A, and 753017A

Item

PD753012A

PD753016A

PD753017A

PD75P3018A

Program counter 14 bits 15 bits

Program memory (bytes) Mask ROM One-time PROM

During 12288 16384 16384 16384

Mk I mode

During 12288 16384 24576 32768

Mk II mode

Data memory (× 4 bits) 1024

Mask options Pull-up resistor for Yes (Can be specified whether to incorporate or not)

No (Cannot incorporate)

PORT4 and PORT5

LCD split resistor

Feedback resistor Yes (Can be specified whether to use or not)

No (used)

for subsystem clock

Wait time Yes (Can be specified either 217/fX or 215/fX)Note

No (Fixed at 2

/fX)

Note

during RESET

Pin configuration Pin Nos. 29 to 32 P40 to P43 P40/D0 to P43/D3

Pin Nos. 34 to 37 P50 to P53 P50/D4 to P53/D7

Pin No. 50 P30/LCDCL P30/LCDCL/MD0

Pin No. 51 P31/SYNC P31/SYNC/MD1

Pin Nos. 52 and 53 P32, P33 P32/MD2, P33/MD3

Pin No. 57 IC VPP

Other Noise resistance and noise radiation may differ due to the different circuit sizes and mask

layouts.

Note For 217/fX, during 6.0 MHz operation is 21.8 ms, and during 4.19 MHz operation is 31.3 ms.

For 215/fX, during 6.0 MHz operation is 5.46 ms, and during 4.19 MHz operation is 7.81 ms.

Caution Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask

ROM version from the PROM version in a process between prototype development and full production,

be sure to fully evaluate the mask ROM version’s CS (not ES).

PD75P3018A

16 Data Sheet U11917EJ2V1DS

6. MEMORY CONFIGURATION

6.1 Program Counter (PC) ... 15 bits

This is a 15-bit binary counter that stores program memory address data.

Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid.

Figure 6-1. Configuration of Program Counter

6.2 Program Memory (PROM) ... 32768 × 8 bits

The program memory consists of 32768 × 8-bit one-time PROM. The program memory address can be selected as shown

below by setting the stack bank selection (SBS) register.

Mk I Mode Mk II Mode

Usable address 0000H to 3FFFH 0000H to 7FFFH

Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call

instruction, during Mk I and Mk II modes.

PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC

Fixed at zero during

Mk I mode

PD75P3018A

Data Sheet U11917EJ2V1DS

Figure 6-2. Program Memory Map (Mk I mode)

Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch

to addresses with changes in the PC’s low-order 8 bits only.

MBE

RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

INT0 start address (high-order 6 bits)

INT0 start address (low-order 8 bits)

INT1 start address (high-order 6 bits)

INT1 start address (low-order 8 bits)

INTCSI start address (high-order 6 bits)

INTCSI start address (low-order 8 bits)

INTT0 start address (high-order 6 bits)

INTT0 start address (low-order 8 bits)

INTT1, INTT2 start address (high-order 6 bits)

INTT1, INTT2 start address (low-order 8 bits)

Reference table for GETI instruction

0000H

0002H

0004H

0006H

0008H

000AH

000CH

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

CALLF

!faddr instruction

entry address

Branch addresses for

the following instructions

• BR BCDE

• BR BCXA

• BR !addr

• CALL !addr

Branch/call

address

by GETI

BR $addr instruction

relative branch address

(–15 to –1,

+2 to +16)

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

765 0

0020H

PD75P3018A

18 Data Sheet U11917EJ2V1DS

Figure 6-3. Program Memory Map (Mk II mode)

Caution To allow the vectored interrupt’s 14-bit start address (noted above), set the address within a 16K area

(0000H to 3FFFH).

Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch

to addresses with changes in the PC’s low-order 8 bits only.

MBE

RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

INT0 start address (high-order 6 bits)

INT0 start address (low-order 8 bits)

INT1 start address (high-order 6 bits)

INT1 start address (low-order 8 bits)

INTCSI start address (high-order 6 bits)

INTCSI start address (low-order 8 bits)

INTT0 start address (high-order 6 bits)

INTT0 start address (low-order 8 bits)

INTT1, INTT2 start address (high-order 6 bits)

INTT1, INTT2 start address (low-order 8 bits)

Reference table for GETI instruction

0000H

0002H

0004H

0006H

0008H

000AH

000CH

1FFFH

2000H

2FFFH

3000H

3FFFH

4000H

4FFFH

5000H

5FFFH

6000H

6FFFH

7000H

7FFFH

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

CALLF

!faddr instruction

entry address

!addr instruction

branch address

CALL

!addr instruction

branch address

Branch/call

address

by GETI

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

765 0

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

Branch addresses for

the following instructions

• BR BCDE

• BR BCXA

• BRA !addr1

• CALLA !addr1

BR $addr1 instruction

relative branch address

(–15 to –1,

+2 to +16)

PD75P3018A

Data Sheet U11917EJ2V1DS

6.3 Data Memory (RAM) ... 1024 × 4 bits

Figure 6-4 shows the data memory configuration.

Data memory consists of a data area and a peripheral hardware area. The data area consists of 1024 × 4-bit static RAM.

Figure 6-4. Data Memory Map

Note Memory bank 0, 1, 2, or 3 can be selected as the stack area.

(32 × 4)

256 × 4

(224 × 4)

256 × 4

(224 × 4)

(32 × 4)

256 × 4

128 × 4

000H

01FH

020H

0FFH

100H

1DFH

1E0H

1FFH

200H

2FFH

300H

3FFH

F80H

FFFH

General-purpose register area

Display data memory

Data area

static RAM

(1024 × 4)

Stack area

Note

Peripheral hardware area

Data memory Memory bank

Not incorporated

PD75P3018A

20 Data Sheet U11917EJ2V1DS

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s

operand representations (for further description, see the RA75X Assembler Package User’s Manual Language

(U12385E)). When there are several codes, select and use just one. Codes that consist of uppercase letters and + or

– symbols are key words that should be entered as they are.

For immediate data, enter an appropriate numerical value or label.

Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (For details, refer to the

PD753017

User’s Manual (U11282E)). The number of labels that can be entered for fmem and pmem are restricted.

Representation Coding Format

reg X, A, B, C, D, E, H, L

reg1 X, B, C, D, E, H, L

rp XA, BC, DE, HL

rp1 BC, DE, HL

rp2 BC, DE

rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’

rp’1 BC, DE, HL, XA’, BC’, DE’, HL’

rpa HL, HL+, HL–, DE, DL

rpa1 DE, DL

n4 4-bit immediate data or label

n8 8-bit immediate data or label

mem 8-bit immediate data or labelNote

bit 2-bit immediate data or label

fmem FB0H-FBFH, FF0H-FFFH immediate data or label

pmem FC0H-FFFH immediate data or label

addr 0000H-3FFFH immediate data or label

addr1 0000H-7FFFH immediate data or label (Mk II mode only)

caddr 12-bit immediate data or label

faddr 11-bit immediate data or label

taddr 20H-7FH immediate data (however, bit0 = 0) or label

PORTn PORT0-PORT7

IEXXX IEBT, IECSI, IET0, IET1, IET2, IE0-IE2, IE4, IEW

RBn RB0-RB3

MBn MB0-MB3, MB15

Note When processing 8-bit data, only even-numbered addresses can be specified.

PD75P3018A

Data Sheet U11917EJ2V1DS

(2) Operation legend

A: A register; 4-bit accumulator

B: B register

C: C register

D: D register

E: E register

H: H register

L: L register

X: X register

XA : Register pair (XA); 8-bit accumulator

BC : Register pair (BC)

DE : Register pair (DE)

HL : Register pair (HL)

XA’ : Expansion register pair (XA’)

BC’ : Expansion register pair (BC’)

DE’ : Expansion register pair (DE’)

HL’ : Expansion register pair (HL’)

PC : Program counter

SP : Stack pointer

CY : Carry flag; bit accumulator

PSW : Program status word

MBE : Memory bank enable flag

RBE : Register bank enable flag

PORTn : Port n (n = 0 to 7)

IME : Interrupt master enable flag

IPS : Interrupt priority selection register

IEXXX : Interrupt enable flag

RBS : Register bank selection register

MBS : Memory bank selection register

PCC : Processor clock control register

.: Delimiter for address and bit

(XX) : Addressed data

XXH : Hexadecimal data

PD75P3018A

22 Data Sheet U11917EJ2V1DS

(3) Description of symbols used in addressing area

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

MB = 0 (000H-07FH)

MB = 15 (F80H-FFFH)

MB = MBS

MBS = 0-3, 15

MB = MBE • MBS

MBS = 0-3, 15

MB = 0

MBE = 1 :

MBE = 0 :

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

addr = 0000H-3FFFH

addr, addr1 =

*7 (Current PC) –15 to (Current PC) –1

(Current PC) +2 to (Current PC) +16

*8 caddr = 0000H-0FFFH (PC

= 000B) or

1000H-1FFFH (PC

= 001B) or

2000H-2FFFH (PC

= 010B) or

3000H-3FFFH (PC

= 011B) or

4000H-4FFFH (PC

= 100B: Mk II mode only) or

5000H-5FFFH (PC

= 101B: Mk II mode only) or

6000H-6FFFH (PC

= 110B: Mk II mode only) or

7000H-7F7FH (PC

= 111B: Mk II mode only)

faddr = 0000H-07FFH

taddr = 0020H-007FH

addr1 = 0000H-7FFFH (Mk II mode only)

*10

*11

Program memory

addressing

Data memory

addressing

PD75P3018A

Data Sheet U11917EJ2V1DS

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as

shown below.

• No skip ..................................................................... S = 0

• Skipped instruction is 1-byte or 2-byte instruction .... S = 1

• Skipped instruction is 3-byte instructionNote .............. S = 2

Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

One machine cycle equals one cycle (= tCY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.

PD75P3018A

24 Data Sheet U11917EJ2V1DS

Instruction Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

Group

Bytes Cycle Area

Condition

Transfer MOV A, #n4 1 1 A ← n4 String-effect A

reg1, #n4 2 2 reg1← n4

XA, #n8 2 2 XA ← n8 String-effect A

HL, #n8 2 2 HL ← n8 String-effect B

rp2, #n8 2 2 rp2 ← n8

A, @HL 1 1 A ← (HL) *1

A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L=0

A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L=FH

A, @rpa1 1 1 A ← (rpa1) *2

XA, @HL 2 2 XA ← (HL) *1

@HL, A 1 1 (HL) ← A*1

@HL, XA 2 2 (HL) ← XA *1

A, mem 2 2 A ← (mem) *3

XA, mem 2 2 XA ← (mem) *3

mem, A 2 2 (mem) ← A*3

mem, XA 2 2 (mem) ← XA *3

A, reg 2 2 A ← reg

XA, rp’ 2 2 XA ← rp’

reg1, A 2 2 reg1 ← A

rp’1, XA 2 2 rp’1 ← XA

XCH A, @HL 1 1 A ↔ (HL) *1

A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L=0

A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L=FH

A, @rpa1 1 1 A ↔ (rpa1) *2

XA, @HL 2 2 XA ↔ (HL) *1

A, mem 2 2 A ↔ (mem) *3

XA, mem 2 2 XA ↔ (mem) *3

A, reg1 1 1 A ↔ reg1

XA, rp’ 2 2 XA ↔ rp’

Table MOVTNote 1 XA, @PCDE 1 3 XA ← (PC13-8+DE)ROM

reference XA ← (PC14-8+DE)ROM

XA, @PCXA 1 3 XA ← (PC13-8+XA)ROM

XA ← (PC14-8+XA)ROM

XA, @BCDE 1 3 XA ← (BCDE)ROMNote 2 *6

XA ← (BCDE)ROMNote 2 *11

XA, @BCXA 1 3 XA ← (BCXA)ROMNote 2 *6

XA ← (BCXA)ROMNote 2 *11

Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

2. Only the low-order 3 bits in the B register are valid.

PD75P3018A

Data Sheet U11917EJ2V1DS

Instruction Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

Group

Bytes Cycle Area

Condition

Bit transfer MOV1 CY, fmem.bit 2 2 CY← (fmem.bit) *4

CY, pmem.@L 2 2 CY ← (pmem7-2+L3-2.bit(L1-0)) *5

CY, @H+mem.bit 2 2 CY ← (H+mem3-0.bit) *1

fmem.bit, CY 2 2 (fmem.bit) ← CY *4

pmem.@L, CY 2 2 (pmem7-2+L3-2.bit(L1-0)) ← CY *5

@H+mem.bit, CY 2 2 (H+mem3-0.bit) ← CY *1

Arithmetic ADDS A, #n4 1 1+S A ← A+n4 carry

XA, #n8 2 2+S XA ← XA+n8 carry

A, @HL 1 1+S A ← A+(HL) *1 carry

XA, rp’ 2 2+S XA ← XA+rp’ carry

rp’1, XA 2 2+S rp’1 ← rp’1+XA carry

ADDC A, @HL 1 1 A, CY ← A+(HL)+CY *1

XA, rp’ 2 2 XA, CY ← XA+rp’+CY

rp’1, XA 2 2 rp’1, CY ← rp’1+XA+CY

SUBS A, @HL 1 1+S A ← A–(HL) *1 borrow

XA, rp’ 2 2+S XA ← XA–rp’ borrow

rp’1, XA 2 2+S rp’1 ← rp’1–XA borrow

SUBC A, @HL 1 1 A, CY ← A–(HL)–CY *1

XA, rp’ 2 2 XA, CY ← XA–rp’–CY

rp’1, XA 2 2 rp’1, CY ← rp’1–XA–CY

AND A, #n4 2 2 A ← A n4

A, @HL 1 1 A ← A (HL) *1

XA, rp’ 2 2 XA ← XA rp’

rp’1, XA 2 2 rp’1 ← rp’1 XA

OR A, #n4 2 2 A ← A ∨ n4

A, @HL 1 1 A ← A ∨ (HL) *1

XA, rp’ 2 2 XA ← XA ∨ rp’

rp’1, XA 2 2 rp’1 ← rp’1 ∨ XA

XOR A, #n4 2 2 A ← A ∨ n4

A, @HL 1 1 A ← A ∨ (HL) *1

XA, rp’ 2 2 XA ← XA ∨ rp’

rp’1, XA 2 2 rp’1 ← rp’1 ∨ XA

Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An

manipulation NOT A 2 2 A ← A

Increment/ INCS reg 1 1+S reg ← reg+1 reg=0

decrement rp1 1 1+S rp1 ← rp1+1 rp1=00H

@HL 2 2+S (HL) ← (HL)+1 *1 (HL)=0

mem 2 2+S (mem) ← (mem)+1 *3 (mem)=0

DECS reg 1 1+S reg ← reg–1 reg=FH

rp’ 2 2+S rp’ ← rp’–1 rp’=FFH

∨

PD75P3018A

26 Data Sheet U11917EJ2V1DS

Instruction Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

Group

Bytes Cycle Area

Condition

Comparison SKE reg, #n4 2 2+S Skip if reg=n4 reg=n4

@HL, #n4 2 2+S Skip if (HL)=n4 *1 (HL)=n4

A, @HL 1 1+S Skip if A=(HL) *1 A=(HL)

XA, @HL 2 2+S Skip if XA=(HL) *1 XA=(HL)

A, reg 2 2+S Skip if A=reg A=reg

XA, rp’ 2 2+S Skip if XA=rp’ XA=rp’

Carry flag SET1 CY 1 1 CY ← 1

manipulation CLR1 CY 1 1 CY ← 0

SKT CY 1 1+S Skip if CY=1 CY=1

NOT1 CY 1 1 CY ← CY

Memory bit SET1 mem.bit 2 2 (mem.bit) ← 1*3

manipulation fmem.bit 2 2 (fmem.bit) 1 *4

pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0)) 1*5

@H+mem.bit 2 2 (H+mem3-0.bit) 1*1

CLR1 mem.bit 2 2 (mem.bit) 0*3

fmem.bit 2 2 (fmem.bit) 0*4

pmem.@L 2 2 (pmem7-2+L3-2.bit(L1-0)) 0*5

@H+mem.bit 2 2 (H+mem3-0.bit) 0*1

SKT mem.bit 2 2+S Skip if(mem.bit)=1 *3 (mem.bit)=1

fmem.bit 2 2+S Skip if(fmem.bit)=1 *4 (fmem.bit)=1

pmem.@L 2 2+S Skip if(pmem7-2+L3-2.bit(L1-0))=1 *5 (pmem.@L)=1

@H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=1 *1

(@H+mem.bit)=1

SKF mem.bit 2 2+S Skip if(mem.bit)=0 *3 (mem.bit)=0

fmem.bit 2 2+S Skip if(fmem.bit)=0 *4 (fmem.bit)=0

pmem.@L 2 2+S Skip if(pmem7-2+L3-2.bit(L1-0))=0 *5 (pmem.@L)=0

@H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=0 *1

(@H+mem.bit)=0

SKTCLR fmem.bit 2 2+S Skip if(fmem.bit)=1 and clear *4 (fmem.bit)=1

pmem.@L 2 2+S

Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear

*5 (pmem.@L)=1

@H+mem.bit 2 2+S Skip if(H+mem3-0.bit)=1 and clear *1

(@H+mem.bit)=1

AND1 CY, fmem.bit 2 2 CY ← CY (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY (pmem7-2+L3-2.bit(L1-0)) *5

CY, @H+mem.bit 2 2 CY ← C (H+mem3-0.bit) *1

OR1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L3-2.bit(L1-0)) *5

CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem3-0.bit) *1

XOR1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L3-2.bit(L1-0)) *5

CY, @H+mem.bit 2 2 CY ← C ∨ (H+mem3-0.bit) *1

∨

←

PD75P3018A

Data Sheet U11917EJ2V1DS

Instruction Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

Group

Bytes Cycle Area

Condition

Branch BRNote 1 addr — — PC14 ← 0, PC13-0 ← addr *6

Use the assembler to select the

most appropriate instruction

among the following.

• BR !addr

• BRCB !caddr

• BR $addr

addr1 — — PC14-0 ← addr1 *11

Use the assembler to select

the most appropriate instruction

among the following.

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

!addr 3 3 PC14 ← 0, PC13-0 ← addr *6

$addr 1 2 PC14 ← 0, PC13-0 ← addr *7

$addr1 1 2 PC14-0 ← addr1

PCDE 2 3 PC14 ← 0, PC13-0 ← PC13-8+DE

PC14-0 ← PC14-8+DE

PCXA 2 3 PC14 ← 0, PC13-0 ← PC13-8+XA

PC14-0 ← PC14-8+XA

BCDE 2 3 PC14 ← 0, PC13-0 ← BCDENote 2 *6

PC14-0 ← BCDENote 2 *11

BCXA 2 3 PC14 ← 0, PC13-0 ← BCXANote 2 *6

PC14-0 ← BCXANote 2 *11

BRANote 1 !addr 3 3 PC14 ← 0, PC13-0 ← addr *6

33PC14-0 ← addr1 *11

BRCBNote 1 !caddr 2 2 PC14 ← 0, PC13-0 ← PC13, 12+caddr11-0 *8

PC14-0 ← PC14, 13, 12+caddr11-0

Notes 1. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

2. The only following bits are valid in the B register.

For Mk I mode : Low-order 2 bits

For Mk II mode : Low-order 3 bits

PD75P3018A

28 Data Sheet U11917EJ2V1DS

Instruction Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

Group

Bytes Cycle Area

Condition

Subroutine CALLANote !addr1 3 3 (SP–5) ← 0, PC14-12 *11

stack control (SP–6)(SP–3)(SP–4) ← PC11-0

(SP–2) ← X, X, MBE, RBE

PC14–0 ← addr1, SP ← SP–6

CALLNote !addr 3 3 (SP–4)(SP–1)(SP–2) ← PC11-0 *6

(SP–3) ← MBE, RBE, PC13, 12

PC14 ← 0, PC13–0 ← addr, SP ← SP–4

4 (SP–5) ← 0, PC14-12

(SP–6)(SP–3)(SP–4) ← PC11-0

(SP–2)← X, X, MBE, RBE

PC14 ← 0, PC13-0 ← addr, SP ← SP–6

CALLFNote !faddr 2 2 (SP–4)(SP–1)(SP–2) ← PC11-0 *9

(SP–3) ← MBE, RBE, PC13, 12

PC14 ← 0, PC13-0 ← 000+faddr, SP ← SP–4

3 (SP–5) ← 0, PC14-12

(SP–6)(SP–3)(SP–4) ← PC11-0

(SP–2) ← X, X, MBE, RBE

PC14-0 ← 0000+faddr, SP ← SP–6

RETNote 13MBE, RBE, PC13, 12 ← (SP+1)

PC11-0 ← (SP)(SP+3)(SP+2)

PC14 ← 0, SP ← SP+4

X, X, MBE, RBE ← (SP+4)

0, PC14-12 ← (SP+1)

PC11-0 ← (SP)(SP+3)(SP+2)

SP ← SP+6

RETSNote 13+S MBE, RBE, PC13, 12 ← (SP+1) Unconditional

PC11-0 ← (SP)(SP+3)(SP+2)

PC14 ← 0, SP ← SP+4

then skip unconditionally

X, X, MBE, RBE ← (SP+4)

0, PC14-12 ← (SP+1)

PC11-0 ← (SP)(SP+3)(SP+2)

SP ← SP+6

then skip unconditionally

RETINote 13

MBE, RBE, PC

13, 12

← (SP+1), PC

← 0

PC11-0 ← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

0, PC14-12 ← (SP+1)

PC11-0 ← (SP)(SP+3)(SP+2)

PSW ← (SP+4)(SP+5), SP ← SP+6

Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

PD75P3018A

Data Sheet U11917EJ2V1DS

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - -

Instruction Mnemonic Operand

No. of Machine

Operation

Addressing

Skip

Group

Bytes Cycle Area

Condition

Subroutine PUSH rp 1 1 (SP–1)(SP–2) ← rp, SP ← SP–2

stack control BS 2 2

(SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2

POP rp 1 1 rp ← (SP+1)(SP), SP ← SP+2

BS 2 2

MBS ← (SP+1), RBS ← (SP), SP ← SP+2

Interrupt EI 2 2 IME(IPS.3) ← 1

control IEXXX 2 2 IEXXX ← 1

DI 2 2 IME(IPS.3) ← 0

IEXXX 2 2 IEXXX ← 0

I/O INNote 1 A, PORTn 2 2 A ← PORTn (n=0-7)

XA, PORTn 2 2

XA ← PORTn+1, PORTn

(n=4, 6)

OUTNote 1 PORTn, A 2 2 PORTn

←

A (n=2-7)

PORTn, XA 2 2

PORTn+1, PORTn ← XA

(n=4, 6)

CPU control HALT 2 2 Set HALT Mode(PCC.2

←

STOP 2 2 Set STOP Mode(PCC.3

←

NOP 1 1 No Operation

Special SEL RBn 2 2 RBS

←

n (n=0-3)

MBn 2 2 MBS

←

n (n=0-3, 15)

GETINote 2, 3 taddr 1 3 • When using TBR instruction *10

PC13-0 ← (taddr)5-0+(taddr+1), PC14 ← 0

• When using TCALL instruction

(SP–4)(SP–1)(SP–2)

←

PC11-0

(SP–3) ← MBE, RBE, PC

13, 12

, PC

← 0

PC13-0

←

(taddr)5-0+(taddr+1)

←

SP–4

• When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr+1) instructions instruction

13• When using TBR instruction *10

PC13-0 ← (taddr)5-0+(taddr+1), PC14 ← 0

4• When using TCALL instruction

(SP–5)

←

0, PC14-12

(SP–6)(SP–3)(SP–4)

←

PC11-0

(SP–2)

←

X, X, MBE, RBE, PC14

←

PC13-0

←

(taddr)5-0+(taddr+1)

←

SP–6

3• When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr+1) instructions instruction

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.

2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction’s table definitions.

3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

- - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PD75P3018A

30 Data Sheet U11917EJ2V1DS

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory contained in the

PD75P3018A is a 32768 × 8-bit one-time PROM that can be electrically written

one time only. The pins listed in the table below are used for this one-time PROM’s write/verify operations. Clock input

from the X1 pin is used instead of address input as a method for updating addresses.

Pin Function

VPP Pin where program voltage is applied during program memory

write/verify (usually VDD potential)

X1, X2 Clock input pins for address updating during program memory

write/verify. Input the X1 pin’s inverted signal to the

X2 pin.

MD0-MD3 Operation mode selection pin for program memory write/verify

D0/P40 to D3/P43 8-bit data I/O pins for program memory write/verify

(low-order 4 bits)

D4/P50 to D7/P53

(high-order 4 bits)

VDD Pin where power supply voltage is applied.

Applies VDD = 1.8 to 5.5 V in normal operation mode and +6 V

for program memory write/verify.

Caution Pins not used for program memory write/verify should be connected to VSS via a resistor individually.

8.1 Operation Modes for Program Memory Write/Verify

When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the

PD75P3018A enters the program memory write/verify

mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.

Operation Mode Specification Operation Mode

VPP VDD MD0 MD1 MD2 MD3

+12.5 V +6 V H L H L Zero-clear program memory address

LHHHWrite mode

LLHHVerify mode

HXHHProgram inhibit mode

X: L or H

PD75P3018A

Data Sheet U11917EJ2V1DS

8.2 Program Memory Write Procedure

Program memory can be written at high speed using the following procedure.

(1) Pull unused pins to Vss through resistors. Set the X1 pin low.

(2) Supply 5 V to the VDD and VPP pins.

(3) Wait 10

(4) Select the zero-clear program memory address mode.

(5) Supply 6 V to the VDD and 12.5 V to the VPP pins.

(6) Write data in the 1 ms write mode.

(7) Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7).

(8) (X : number of write operations from steps (6) and (7)) × 1 ms additional write.

(9) Apply four pulses to the X1 pin to increment the program memory address by one.

(10) Repeat steps (6) to (9) until the end address is reached.

(11) Select the zero-clear program memory address mode.

(12) Return the VDD and VPP pins back to 5 V.

(13) Turn off the power.

The following figure shows steps (2) to (9).

VPP

VDD

VDD + 1

VDD

VPP

VDD

D0/P40 to D3/P43

D4/P50 to D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

X repetitions

Write Verify

Additional

write

Address

increment

Data input

Data

output

Data input

PD75P3018A

32 Data Sheet U11917EJ2V1DS

8.3 Program Memory Read Procedure

The

PD75P3018A can read program memory contents using the following procedure.

(1) Pull unused pins to Vss through resistors. Set the X1 pin low.

(2) Supply 5 V to the VDD and VPP pins.

(3) Wait 10

(4) Select the zero-clear program memory address mode.

(5) Supply 6 V to the VDD and 12.5 V to the VPP pins.

(6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one

address.

(7) Select the zero-clear program memory address mode.

(8) Return the VDD and VPP pins back to 5 V.

(9) Turn off the power.

The following figure shows steps (2) to (7).

+ 1

D0/P40 to D3/P43

D4/P50 to D7/P53

MD0/P30

MD2/P32

MD3/P33

MD1/P31

“L”

Data output Data output

PD75P3018A

Data Sheet U11917EJ2V1DS

8.4 One-time PROM Screening

Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC Electronics. Therefore, NEC

Electronics recommends that after the required data is written and the PROM is stored under the temperature and time

conditions shown below, the PROM should be verified via a screening.

Storage Temperature Storage Time

125°C24 hours

PD75P3018A

34 Data Sheet U11917EJ2V1DS

9. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter Symbol Conditions Ratings Unit

Supply voltage VDD –0.3 to +7.0 V

PROM supply voltage VPP –0.3 to +13.5 V

Input voltage VI1 Other than ports 4 and 5 –0.3 to VDD + 0.3 V

VI2

Ports 4 and 5 (During N-ch open drain)

–0.3 to +14 V

Output voltage VO–0.3 to VDD + 0.3 V

High-level output current IOH Per pin –10 mA

Total of all pins –30 mA

Low-level output current IOL Per pin 30 mA

Total of all pins 220 mA

Operating ambient TA–40 to +85Note °C

temperature

Storage temperature Tstg –65 to +150 °C

Note To drive LCD in normal mode, TA = –10 to +85°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge

of suffering physical damage, and therefore the product must be used under conditions that ensure

that the absolute maximum ratings are not exceeded.

Capacitance (TA = 25°C, VDD = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input capacitance CIN f = 1 MHz 15 pF

Output capacitance COUT Unmeasured pins returned to 0 V 15 pF

I/O capacitance CIO 15 pF

PD75P3018A

Data Sheet U11917EJ2V1DS

Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Ceramic Oscillation frequency 1.0 6.0Note 2 MHz

resonator (fX)Note 1

Oscillation After VDD has 4 ms

stabilization timeNote 3 reached MIN. value

of oscillation voltage

range

Crystal Oscillation frequency 1.0 6.0Note 2 MHz

resonator (fX)Note 1

Oscillation VDD = 4.5 to 5.5 V 10 ms

stabilization timeNote 3

External X1 input frequency 1.0 6.0Note 2 MHz

clock (fX)Note 1

X1 input high-/ 83.3 500 ns

low-level width

(tXH, tXL)

Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only.

For the instruction execution time, refer to AC Characteristics.

2. If the oscillation frequency is 4.19 MHz < fX ≤ 6.0 MHz at 1.8 V ≤ V DD < 2.7 V, do not select processor clock control

s, falling short of the rated value

of 0.95

3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied

or STOP mode has been released.

Caution When using the main system clock oscillator, wire the portion enclosed in the broken line in the above

figure as follows to prevent adverse influence due to wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring in the vicinity of a line through which a high alternating current flows.

• Always keep the ground point of the capacitor of the oscillator at the same potential as VDD.

• Do not ground to a power supply pattern through which a high current flows.

• Do not extract signals from the oscillator.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

X1 X2

C1 C2

VDD

X1 X2

C1 C2

X1 X2

PD75P3018A

36 Data Sheet U11917EJ2V1DS

Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit

Crystal Oscillation frequency 32 32.768 35 kHz

resonator (fXT)Note 1

Oscillation VDD = 4.5 to 5.5 V 1.0 2 s

stabilization timeNote 2

External XT1 input frequency 32 100 kHz

clock (fXT)Note 1

XT1 input high-/ 5 15

low-level width

(tXTH, tXTL)

Notes 1. The oscillation frequency and XT1 input frequency shown above indicate characteristics of the oscillator only.

For the instruction execution time, refer to AC Characteristics.

2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied.

Caution When using the subsystem clock oscillator , wire the portion enclosed in the broken line in the above

figure as follows to prevent adverse influence due to wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring with other signal lines.

• Do not route the wiring in the vicinity of a line through which a high alternating current flows.

• Always keep the ground point of the capacitor of the oscillator at the same potential as VDD.

• Do not ground to a power supply pattern through which a high current flows.

• Do not extract signals from the oscillator.

The subsystem clock oscillator has a low amplification factor to reduce current consumption and is

more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in

wiring the subsystem clock oscillator.

Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

XT1 XT2

C3 C4

VDD

XT1 XT2

PD75P3018A

Data Sheet U11917EJ2V1DS

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Low-level output IOL Per pin 15 mA

current Total of all pins 150 mA

High-level input VIH1 Ports 2, 3 2.7 V ≤ VDD ≤ 5.5 V 0.7VDD VDD V

voltage 1.8 V ≤ VDD < 2.7 V 0.9VDD VDD V

VIH2 Ports 0, 1, 6, 7, RESET 2.7 V ≤ VDD ≤ 5.5 V 0.8VDD VDD V

1.8 V ≤ VDD < 2.7 V 0.9VDD VDD V

VIH3 Ports 4, 5 2.7 V ≤ VDD ≤ 5.5 V 0.7VDD 13 V

(N-ch open-drain) 1.8 V ≤ VDD < 2.7 V 0.9VDD 13 V

VIH4 X1, XT1 VDD – 0.1 VDD V

Low-level input VIL1 Ports 2 to 5 2.7 V ≤ VDD ≤ 5.5 V 0 0.3VDD V

voltage 1.8 V ≤ VDD < 2.7 V 0 0.1VDD V

VIL2 Ports 0, 1, 6, 7, RESET 2.7 V ≤ VDD ≤ 5.5 V 0 0.2VDD V

1.8 V ≤ VDD < 2.7 V 0 0.1VDD V

VIL3 X1, XT1 0 0.1 V

High-level output VOH SCK, SO, Ports 2, 3, 6, 7, BP0 to BP7 VDD – 0.5 V

voltage IOH = –1.0 mA

Low-level output VOL1 SCK, SO, Ports 2 to 7, IOL = 15 mA 0.2 2.0 V

voltage BP0 to BP7 VDD = 4.5 to 5.5 V

IOL = 1.6 mA 0.4 V

VOL2 SB0, SB1 N-ch open-drain 0.2VDD V

Pull-up resistor ≥ 1 kΩ

High-level input ILIH1 VIN = VDD Pins other than X1, XT1 3

leakage current ILIH2 X1, XT1 20

ILIH3 VIN = 13 V Ports 4, 5 (N-ch open-drain) 20

Low-level input ILIL1 VIN = 0 V Pins other than X1, XT1, Ports 4, 5 –3

leakage current ILIL2 X1, XT1 –20

ILIL3 Ports 4, 5 (N-ch open-drain) –3

When input instruction is not executed

Ports 4, 5 (N-ch open- –30

drain). When input VDD = 5.0 V –10 –27

instruction is executed VDD = 3.0 V –3 –8

High-level output ILOH1 VOUT = VDD SCK, SO/SB0, SB1, Ports 2, 3, 6, 7 3

leakage current ILOH2 VOUT = 13 V Ports 4, 5 (N-ch open-drain) 20

Low-level output ILOL VOUT = 0 V –3

leakage current

Internal pull-up RLVIN = 0 V Ports 0 to 3, 6, 7 (except P00 pin) 50 100 200 kΩ

resistor

PD75P3018A

38 Data Sheet U11917EJ2V1DS

VDD = 3.0 V ±10% 3.5 12

VDD = 3.0 V, TA = 25°C3.5 7

VDD = 3.0 V ±10% 39 117

VDD = 3.0 V, TA = 25°C3978

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

LCD drive voltage VLCD VAC0 = 0 TA = –40 to +85°C2.7 VDD V

= –10 to +85°C2.2 V

VAC0 = 1 1.8 V

VAC current

Note 1

IVAC

VAC0 = 1, V

= 2.0 V ±10% 1 4

LCD output voltage

VODC IO = ±1.0

AVLCD0 = VLCD 0±0.2 V

deviationNote 2 VLCD1 = VLCD × 2/3

(common) VLCD2 = VLCD × 1/3

LCD output voltage

VODS IO = ±0.5

A1.8 V ≤ VLCD ≤ VDD 0±0.2 V

deviationNote 2

(segment)

Supply current

Note 3

IDD1 6.0 MHzNote 4 VDD = 5.0 V ±10%Note 5 3.7 11.0 mA

crystal VDD = 3.0 V ±10%Note 6 0.73 2.2 mA

IDD2 oscillation HALT VDD = 5.0 V ±10% 0.92 2.6 mA

C1 = C2 = 22 pF

mode VDD = 3.0 V ±10% 0.3 0.9 mA

IDD1

4.19 MHz

Note 4

VDD = 5.0 V ±10%Note 5 2.7 8.0 mA

crystal VDD = 3.0 V ±10%Note 6 0.57 1.7 mA

IDD2 oscillation HALT VDD = 5.0 V ±10% 0.90 2.5 mA

C1 = C2 = 22 pF

mode VDD = 3.0 V ±10% 0.28 0.8 mA

IDD3 32.768 Low- VDD = 3.0 V ±10% 42 126

kHzNote 7 voltage VDD = 2.0 V ±10% 37 110

crystal

mode

Note 8

VDD = 3.0 V, TA = 25°C4284

oscillation

IDD4 HALT Low- VDD = 3.0 V ±10% 8.5 25

mode voltage VDD = 2.0 V ±10% 5.8 17

mode

Note 8

VDD = 3.0 V, TA = 25°C8.5 17

IDD5

XT1 = 0 V

Note 10

VDD = 5.0 V ±10% 0.05 10

STOP mode VDD = 3.0 V ±10% 0.02 5

TA = 25°C0.02 3

Notes 1. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the current

increases by about 1

2. Voltage deviation is the difference between the ideal values (VLCDn ; n = 0, 1, 2) of the segment and common

outputs and the output voltage.

3. The current flowing through the internal pull-up resistor is not included.

4. Including the case when the subsystem clock oscillates.

5. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011.

6. When the device operates in low-speed mode with PCC set to 0000.

7. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001

and oscillation of the main system clock stopped.

8. When the sub-oscillation circuit control register (SOS) is set to 0000.

9. When the SOS is set to 0010.

10. When the SOS is set to 00x1, and the feedback resistor of the sub-oscillator is cut (x: don’t care).

Low current

consump-

tion

mode

Note 9

Low current

consump-

tion

mode

Note 9

PD75P3018A

Data Sheet U11917EJ2V1DS

AC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

CPU clock cycle time Note 1 tCY Operation with

VDD = 2.7 to 5.5 V

0.67 64

(minimum instruction execution

main system clock 0.95 64

time = 1 machine cycle) Operation with subsystem clock 114 122 125

TI0, TI1, TI2 input frequency

fTI VDD = 2.7 to 5.5 V 0 1.0 MHz

0275 kHz

TI0, TI1, TI2 input high-/

tTIH

tTIL VDD = 2.7 to 5.5 V 0.48

low-level

width 1.8

Interrupt input high-/low-level

tINTH

tINTL INT0 IM02 = 0 Note 2

width IM02 = 1 10

INT1, 2, 4 10

KR0-7 10

RESET low-level

width tRSL 10

Notes 1. The cycle time (minimum instruc-

tion execution time) of the CPU

clock (Φ) is determined by the

oscillation frequency of the

connected resonator (and

external clock), the system clock

control register (SCC), and

processor clock control register

(PCC).

The figure on the right shows the

supply voltage VDD vs. cycle time

tCY characteristics when the

device operates with the main

system clock.

2. 2tCY or 128/fX depending on the

setting of the interrupt mode

Operation

guaranteed range

Supply voltage

VDD

[V]

0123456

0.5

Cycle time t

[µs]

tCY vs VDD

(with main system clock)

PD75P3018A

40 Data Sheet U11917EJ2V1DS

Serial transfer operation

2-wire and 3-wire serial I/O modes (SCK ... internal clock output): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY1 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-/low-level width tKL1

tKH1 VDD = 2.7 to 5.5 V

KCY1

/2–50

KCY1

/2–150

Note 1

setup time (to SCK ↑)

tSIK1 VDD = 2.7 to 5.5 V 150 ns

500 ns

Note 1

hold time (from SCK ↑)

tKSI1 VDD = 2.7 to 5.5 V 400 ns

600 ns

SCK ↓ → SO

Note 1

output

tKSO1 RL = 1 kΩ, Note 2 VDD = 2.7 to 5.5 V 0 250 ns

delay

time CL = 100 pF 0 1000 ns

Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

2-wire and 3-wire serial I/O modes (SCK ... external clock input): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY2 VDD = 2.7 to 5.5 V 800 ns

3200 ns

SCK high-/low-level width tKL2

tKH2 VDD = 2.7 to 5.5 V 400 ns

1600 ns

Note 1

setup time (to SCK ↑)

tSIK2 VDD = 2.7 to 5.5 V 100 ns

150 ns

Note 1

hold time (from SCK ↑)

tKSI2 VDD = 2.7 to 5.5 V 400 ns

600 ns

SCK ↓ → SO

Note 1

output

tKSO2 RL = 1 kΩ, Note 2 VDD = 2.7 to 5.5 V 0 300 ns

delay

time CL = 100 pF 0 1000 ns

Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

PD75P3018A

Data Sheet U11917EJ2V1DS

SBI mode (SCK ... internal clock output (master)): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY3 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-/low-level width tKL3

tKH3 VDD = 2.7 to 5.5 V

KCY3

/2–50

KCY3

/2–150

SB0, 1 setup time

tSIK3 VDD = 2.7 to 5.5 V 150 ns

(to SCK ↑)

500 ns

SB0, 1 hold time (from SCK ↑)

tKSI3 tKCY3/2 ns

SCK ↓ → SB0, 1 output

tKSO3 RL = 1 kΩ, Note VDD = 2.7 to 5.5 V 0 250 ns

delay

time CL = 100 pF 0 1000 ns

SCK ↑ → SB0, 1 ↓

tKSB tKCY3 ns

SB0, 1 ↓ → SCK ↓

tSBK tKCY3 ns

SB0, 1 low-level width tSBL tKCY3 ns

SB0, 1 high-level width tSBH tKCY3 ns

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.

SBI mode (SCK ... external clock input (slave)): (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY4 VDD = 2.7 to 5.5 V 800 ns

3200 ns

SCK high-/low-level width tKL4

tKH4 VDD = 2.7 to 5.5 V 400 ns

1600 ns

SB0, 1 setup time

tSIK4 VDD = 2.7 to 5.5 V 100 ns

(to SCK ↑)

150 ns

SB0, 1 hold time (from SCK ↑)

tKSI4 tKCY4/2 ns

SCK ↓ → SB0, 1 output

tKSO4 RL = 1 kΩ, Note VDD = 2.7 to 5.5 V 0 300 ns

delay

time CL = 100 pF 0 1000 ns

SCK ↑ → SB0, 1 ↓

tKSB tKCY4 ns

SB0, 1 ↓ → SCK ↓

tSBK tKCY4 ns

SB0, 1 low-level width tSBL tKCY4 ns

SB0, 1 high-level width tSBH tKCY4 ns

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.

PD75P3018A

42 Data Sheet U11917EJ2V1DS

AC Timing Test Points (except X1 and XT1 inputs)

Clock Timing

TI0, TI1, TI2 Timing

(MIN.)

(MAX.)

(MIN.)

(MAX.)

(MIN.)

(MAX.)

(MIN.)

(MAX.)

XT1 input

1/fXT

tXTL tXTH

VDD–0.1 V

0.1 V

X1 input

1/fX

tXL tXH

VDD–0.1 V

0.1 V

TI0, TI1, TI2

1/fTI

tTIL tTIH

PD75P3018A

Data Sheet U11917EJ2V1DS

Serial Transfer Timing

3-wire Serial I/O Mode

2-wire Serial I/O Mode

SCK

KCY1,2

KL1,2

KH1,2

SIK1,2

KSI1,2

KSO1,2

Input data

Output data

SCK

KCY1,2

KL1,2

KH1,2

SIK1,2

KSI1,2

KSO1,2

SB0, 1

PD75P3018A

44 Data Sheet U11917EJ2V1DS

Serial Transfer Timing

Bus Release Signal Transfer

Command Signal Transfer

Interrupt Input Timing

RESET Input Timing

KSB

SBL

SBH

SBK

KCY3, 4

KL3, 4

KH3, 4

SIK3, 4

KSI3, 4

KSO3, 4

SCK

SB0, 1

KCY3, 4

KL3, 4

KH3, 4

KSB

SBK

SIK3, 4

KSO3, 4

SB0, 1

SCK

KSI3, 4

INTL

INTH

INT0, 1, 2, 4

KR0-7

RSL

RESET

PD75P3018A

Data Sheet U11917EJ2V1DS

Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = –40 to +85°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retention power VDDDR 1.8 5.5 V

supply voltage

Release signal setup time tSREL 0

Oscillation stabilization tWAIT Released by RESET 215/fXms

wait timeNote 1 Released by interrupt request Note 2 ms

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable

operation when oscillation is started.

2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

Wait Time

BTM3 BTM2 BTM1 BTM0

fX = 4.19 MHz fX = 6.0 MHz

–0002

20/fX (approx. 250 ms) 220/fX (approx. 175 ms)

–0112

17/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms)

–1012

15/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms)

–1112

13/fX (approx. 1.95 ms) 213/fX (approx. 1.37 ms)

Data Retention Timing (standby release signal: when STOP mode released by interrupt signal)

STOP mode

Operation mode

Internal reset operation

HALT mode

Data retention mode

SREL

WAIT

STOP instruction execution

RESET

DDDR

STOP mode

Operation mode

HALT mode

Data retention mode

SREL

WAIT

STOP instruction execution

Standby release signal

(interrupt request)

DDDR

Data Retention Timing (when STOP mode released by RESET)

PD75P3018A

46 Data Sheet U11917EJ2V1DS

DC Programming Characteristics (TA = 25 ±5°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

High-level input voltage VIH1 Pins other than X1, X2 0.7VDD VDD V

VIH2 X1, X2 VDD – 0.5 VDD V

Low-level input voltage VIL1 Pins other than X1, X2 0 0.3VDD V

VIL2 X1, X2 0 0.4 V

Input leakage current ILI VIN = VIL or VIH 10

High-level output voltage VOH IOH = –1 mA VDD – 1.0 V

Low-level output voltage VOL IOL = 1.6 mA 0.4 V

VDD supply current IDD 30 mA

VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA

Cautions 1. Ensure that VPP does not exceed +13.5 V including overshoot.

2. VDD must be applied before VPP, and cut after VPP.

AC Programming Characteristics (TA = 25 ±5°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V, VSS = 0 V)

Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit

Address setup timeNote 2 (to MD0↓)tAS tAS 2

MD1 setup time (to MD0↓)tM1S tOES 2

Data setup time (to MD0↓)tDS tDS 2

Address hold timeNote 2 (from MD0↑)tAH tAH 2

Data hold time (from MD0↑)tDH tDH 2

MD0↑→Data output float delay time

tDF tDF 0130 ns

VPP setup time (to MD3↑)tVPS tVPS 2

VDD setup time (to MD3↑)tVDS tVCS 2

Initial program pulse width tPW tPW 0.95 1.0 1.05 ms

Additional program pulse width tOPW tOPW 0.95 21.0 ms

MD0 setup time (to MD1↑)tM0S tCES 2

MD0

↓

→Data output delay time

tDV tDV MD0 = MD1 = VIL 1

MD1 hold time (from MD0↑)tM1H tOEH tM1H + tM1R ≥ 50

MD1 recovery time (from MD0↓)tM1R tOR 2

Program counter reset time tPCR —10

X1 input high-/low-level widths tXH, tXL —0.125

X1 input frequency fX— 4.19 MHz

Initial mode setting time tI—2

MD3 setup time (to MD1↑)tM3S —2

MD3 hold time (from MD1↓)tM3H —2

MD3 setup time (to MD0↓)tM3SR —Program memory read 2

Data output delay time from address

Note 2

tDAD tACC Program memory read 2

Data output hold time from address

Note 2

tHAD tOH Program memory read 0 130

MD3 hold time (from MD0↑)tM3HR —Program memory read 2

MD3

↓

→Data output float delay time

tDFR —Program memory read 2

Notes 1. Symbol of corresponding

PD27C256A

2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin.

PD75P3018A

Data Sheet U11917EJ2V1DS

Program Memory Write Timing

Program Memory Read Timing

VPP

VDD

VDD+1

VDD

D0/P40-D3/P43

D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

VPP

VDD

Data Input

Data Output

Data Input Data Input

tVPS

tVDS

tXH

tXL

tDS

tDH

tPW

tDV tDF

tM1R

tM0S

tDS tDH

tOPW

tAH tAS

tM1S tM1H

tPCR

tM3S

tM3H

VPP

VDD

VDD+1

VDD

D0/P40-D3/P43

D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

VDD

VPP

Data Output Data Output

tVPS

tVDS

tXH

tXL tDAD

tHAD

tDV tDFR

tM3HR

tPCR

tM3SR

PD75P3018A

48 Data Sheet U11917EJ2V1DS

10. PACKAGE DRAWINGS

80-PIN PLASTIC QFP (14x14)

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

17.2±0.4

14.0±0.2

0.13

0.825

17.2±0.4

C14.0±0.2

H0.30±0.10

0.65 (T.P.)

K1.6±0.2

L0.8±0.2

F0.825

S80GC-65-3B9-6

0.10

2.7±0.1

0.1±0.1

5°±5°

3.0 MAX.

M0.15+0.10

−0.05

61 40

121

detail of lead end

C D

PD75P3018A

Data Sheet U11917EJ2V1DS

80-PIN PLASTIC QFP (14x14)

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

17.20±0.20

14.00±0.20

0.13

0.825

17.20±0.20

C14.00±0.20

H 0.32±0.06

0.65 (T.P.)

K1.60±0.20

P1.40±0.10

Q0.125±0.075

L0.80±0.20

F0.825

N 0.10

M 0.17

+0.03

−0.07

P80GC-65-8BT-1

S1.70 MAX.

R3°+7°

−3°

4160 4061

2180 201

detail of lead end

C D

PD75P3018A

50 Data Sheet U11917EJ2V1DS

80 PIN PLASTIC TQFP (FINE PITCH) (12x12)

ITEM MILLIMETERS

J0.50 (T.P.)

0.10

A14.00±0.20

B12.00±0.20

C12.00±0.20

D14.00±0.20

G1.25

1.25

H0.22

P80GK-50-BE9-6

S1.27 MAX.

K1.00±0.20

L0.50±0.20

M0.145

N0.10

P1.05±0.07

Q0.10±0.05

R5°±5°

+0.05

–0.04

+0.055

–0.045

NS L

detail of lead end

60 41

C D

NOTE

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

PD75P3018A

Data Sheet U11917EJ2V1DS

80-PIN PLASTIC TQFP (FINE PITCH) (12x12)

ITEM MILLIMETERS

H0.22±0.05

1.25

A14.0±0.2

C12.0±0.2

F1.25

14.0±0.2

B12.0±0.2

N0.08

0.145±0.05

Q0.1±0.05

1.0

J0.5 (T.P.)

L0.5

1.0±0.2

I0.08

S1.1±0.1

R3°+4°

−3°

detail of lead end

NOTE

Each lead centerline is located within 0.08 mm of

its true position (T.P.) at maximum material condition.

60 41

120

P80GK-50-9EU-1

T0.25

U0.6±0.15

PD75P3018A

52 Data Sheet U11917EJ2V1DS

11. RECOMMENDED SOLDERING CONDITIONS

The

PD75P3018A should be soldered and mounted under the following recommended conditions.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Table 11-1. Surface Mounting Type Soldering Conditions (1/3)

(1)

PD75P3018AGC-3B9: 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. IR35-00-3

(at 210˚C or higher), Count: Three times or less

VPS Package peak temperature: 215˚C, Time: 40 seconds max. VP15-00-3

(at 200˚C or higher), Count: Three times or less

Wave soldering Solder bath temperature: 260˚C max., Time: 10 seconds max., Count: Once WS60-00-1

Preheating temperature: 120˚C max. (package surface temperature)

Partial heating

Pin temperature: 350

˚C

max., Time: 3 seconds max. (per pin row)

—

Caution Do not use different soldering methods together (except for partial heating).

Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

(2)

PD75P3018AGC-8BT: 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. IR35-00-2

(at 210˚C or higher), Count: Twice or less

VPS Package peak temperature: 215˚C, Time: 40 seconds max. VP15-00-2

(at 200˚C or higher), Count: Twice or less

Wave soldering Solder bath temperature: 260˚C max., Time: 10 seconds max., Count: Once WS60-00-1

Preheating temperature: 120˚C max. (package surface temperature)

Partial heating

Pin temperature: 350

˚C

max., Time: 3 seconds max. (per pin row)

—

Caution Do not use different soldering methods together (except for partial heating).

Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

PD75P3018A

Data Sheet U11917EJ2V1DS

Table 11-1. Surface Mounting Type Soldering Conditions (2/3)

(3)

PD75P3018AGK-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. IR35-107-3

(at 210˚C or higher), Count: Three times or less,

Exposure limit: 7 daysNote (after that, prebake at 125˚C for 10 to 72 hours)

VPS Package peak temperature: 215˚C, Time: 40 seconds max. VP15-107-3

(at 200˚C or higher), Count: Three times or less,

Exposure limit: 7 daysNote (after that, prebake at 125˚C for 10 to 72 hours)

Partial heating

Pin temperature: 350

˚C

max., Time: 3 seconds max. (per pin row)

—

Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

(4)

PD75P3018AGK-9EU: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. IR35-107-2

(at 210˚C or higher), Count: Twice or less,

Exposure limit: 7 daysNote (after that, prebake at 125˚C for 10 to 72 hours)

VPS Package peak temperature: 215˚C, Time: 40 seconds max. VP15-107-2

(at 200˚C or higher), Count: Twice or less,

Exposure limit: 7 daysNote (after that, prebake at 125˚C for 10 to 72 hours)

Partial heating

Pin temperature: 350

˚C

max., Time: 3 seconds max. (per pin row)

—

Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

PD75P3018A

54 Data Sheet U11917EJ2V1DS

Table 11-1. Surface Mounting Type Soldering Conditions (3/3)

(5)

PD75P3018AGC-3B9-A: 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm)

PD75P3018AGC-8BT-A: 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 260˚C, Time: 60 seconds max. IR60-207-3

(at 220˚C or higher), Count: Three times or less,

Exposure limit: 7 daysNote (after that, prebake at 125˚C for 20 to 72 hours)

Wave soldering For details, contact an NEC Electronics sales representative. —

Partial heating

Pin temperature: 350

˚C

max., Time: 3 seconds max. (per pin row)

—

Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remarks 1. Products with “-A” at the end of the part number are lead-free products.

2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

(6)

PD75P3018AGK-9EU-A: 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm)

Soldering Method Soldering Conditions Recommended

Condition Symbol

Infrared reflow Package peak temperature: 260˚C, Time: 60 seconds max. IR60-207-3

(at 220˚C or higher), Count: Three times or less,

Exposure limit: 7 daysNote (after that, prebake at 125˚C for 20 to 72 hours)

Partial heating

Pin temperature: 350

˚C

max., Time: 3 seconds max. (per pin row)

—

Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remarks 1. Products with “-A” at the end of the part number are lead-free products.

2. For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

PD75P3018A

Data Sheet U11917EJ2V1DS

APPENDIX A.

PD75316B, 753017A AND 75P3018A FUNCTION LIST

Parameter

PD75316B

PD753017A

PD75P3018A

Program memory Mask ROM Mask ROM One-time PROM

0000H-3F7FH 0000H-5FFFH 0000H-7FFFH

(16256 × 8 bits) (24576 × 8 bits) (32768 × 8 bits)

Data memory 000H-3FFH (1024 × 4 bits)

CPU 75X Standard 75XL CPU

Instruction When main system 0.95, 1.91, or 15.3

s• 0.95, 1.91, 3.81, or 15.3

s (at 4.19 MHz operation)

execution time clock is selected (at 4.19 MHz operation) • 0.67, 1.33, 2.67, or 10.7

s (at 6.0 MHz operation)

When subsystem 122

s (at 32.768 kHz operation)

clock is selected

Pin connection 29 to 32 P40 to P43 P40/D0 to P43/D3

34 to 37 P50 to P53 P50/D4 to P53/D7

44 P12/INT2 P12/INT2/TI1/TI2

47 P21 P21/PTO1

48 P22/PCL P22/PCL/PTO2

50 to 53 P30 to P33 P30/MD0 to P33/MD3

57 IC VPP

Stack SBS register None SBS.3 = 1; Mk I mode selection

SBS.3 = 0; Mk II mode selection

Stack area 000H-0FFH n00H-nFFH (n = 0-3)

Subroutine call instruction

2-byte stack Mk I mode: 2-byte stack

stack operation Mk II mode: 3-byte stack

Instruction BRA !addr1 Unavailable Mk I mode: unavailable

CALLA !addr1 Mk II mode: available

MOVT XA, @BCDE Available

MOVT XA, @BCXA

BR BCDE

BR BCXA

CALL !addr 3 machine cycles

Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles

CALLF !faddr 2 machine cycles

Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles

Mask option Yes None

Timer 3 channels: 5 channels:

• Basic interval timer • Basic interval timer/watchdog timer: 1 channel

: 1 channel • 8-bit timer/event counter: 3 channels

• 8-bit timer/event counter

(can be used as 16-bit timer/event counter, carrier generator,

: 1 channel timer with gate)

• Watch timer: 1 channel • Watch timer: 1 channel

PD75P3018A

56 Data Sheet U11917EJ2V1DS

Parameter

PD75316B

PD753017A

PD75P3018A

Clock output (PCL) Φ, 524, 262, 65.5 kHz • Φ, 524, 262, 65.5 kHz

(Main system clock: (Main system clock: at 4.19 MHz operation)

at 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz

(Main system clock: at 6.0 MHz operation)

BUZ output (BUZ) 2 kHz • 2, 4, 32 kHz

(Main system clock: (Main system clock: at 4.19 MHz operation or

at 4.19 MHz operation) subsystem clock: at 32.768 kHz operation)

• 2.93, 5.86, 46.9 kHz

(Main system clock: at 6.0 MHz operation)

Serial interface 3 modes are available

• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit

• 2-wire serial I/O mode

• SBI mode

SOS register

Feedback resistor cut flag

None Provided

(SOS.0)

Sub-oscillator current None Provided

cut flag

(SOS.1)

Standby release by INT0 Unavailable Available

Interrupt priority selection register (IPS) None Yes

Vectored interrupt External: 3, Internal: 3 External: 3, Internal: 5

Supply voltage VDD = 2.0 to 6.0 V VDD = 1.8 to 5.5 V

Operating ambient temperature TA = –40 to +85°C

Package • 80-pin plastic TQFP (fine pitch) (12 × 12 mm)

• 80-pin plastic QFP (14 × 14 mm)

PD75P3018A

Data Sheet U11917EJ2V1DS

APPENDIX B. DEVELOPMENT TOOLS

The following development tools have been provided for system development using the

PD75P3018A. In the 75XL

Series, the relocatable assembler common to series is used in combination with the device file of each type.

RA75X relocatable assembler Host machine Part No. (name)

OS Supply medium

PC-9800 Series MS-DOSTM 3.5" 2HD

S5A13RA75X

Ver.3.30 to

Ver.6.2Note

IBM PC/ATTM Refer to "OS for 3.5" 2HC

S7B13RA75X

or compatible IBM PCs"

Device file Host machine Part No. (name)

OS Supply medium

PC-9800 Series MS-DOS 3.5" 2HD

S5A13DF753017

Ver.3.30 to

Ver.6.2Note

IBM PC/AT Refer to "OS for 3.5" 2HC

S7B13DF753017

or compatible IBM PCs"

Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described

above.

PD75P3018A

58 Data Sheet U11917EJ2V1DS

PROM Write Tools

Hardware PG-1500 This is a PROM programmer that can program single-chip microcontroller with PROM in stand

alone mode or under control of host machine when connected with supplied accessory board

and optional programmer adapter.

It can also program typical PROMs in capacities ranging from 256 K to 4 M bits.

PA-75P316BGC This is a PROM programmer adapter for the

PD75P3018AGC-3B9.

It can be used when connected to a PG-1500.

PA-75P316BGK This is a PROM programmer adapter for the

PD75P3018AGK-BE9.

It can be used when connected to a PG-1500.

PA-75P3018AGC-8BT

This is a PROM programmer adapter for the

PD75P3018AGC-8BT.

It can be used when connected to a PG-1500.

PA-75P3018AGK-9EU

This is a PROM programmer adapter for the

PD75P3018AGK-9EU.

It can be used when connected to a PG-1500.

Software PG-1500 controller Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on

host machine.

Host machine Part No. (name)

OS Supply medium

PC-9800 Series MS-DOS 3.5" 2HD

S5A13PG1500

Ver.3.30 to

Ver.6.2Note

IBM PC/AT Refer to "OS for 3.5" 2HD

S7B13PG1500

or compatible IBM PCs"

Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.

PD75P3018A

Data Sheet U11917EJ2V1DS

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the

PD75P3018A.

Various system configurations using these in-circuit emulators are listed below.

Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during

development of application systems using the 75X or 75XL Series products.

For development of the

PD75P3018A, the IE-75000-R is used with optional emulation board

(IE-75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R).

Highly efficient debugging can be performed when connected to host machine and PROM

programmer.

The IE-75000-R includes a connected emulation board (IE-75000-R-EM).

IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during

development of application systems using the 75X or 75XL Series products.

The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe

(EP-753018GC-R or EP-753018GK-R).

Highly efficient debugging can be performed when connected to host machine and PROM

programmer.

IE-75300-R-EM This is an emulation board for evaluating application systems using the

PD75P3018A.

It is used in combination with the IE-75000-R or IE-75001-R.

EP-753018GC-R This is an emulation probe for the

PD75P3018AGC.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

EV-9200GC-80 It includes a 80-pin conversion socket (EV-9200GC-80) to facilitate connections with target

system.

EP-753018GK-R This is an emulation probe for the

PD75P3018AGK.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

TGK-080SDW

Note 2

It includes a 80-pin conversion adapter (TGK-080SDW) to facilitate connections with target

system.

Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to

the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.

Host machine Part No. (name)

OS Supply medium

PC-9800 Series MS-DOS 3.5" 2HD

S5A13IE75X

Ver.3.30 to 5" 2HD

S5A10IE75X

Ver.6.2Note 3

IBM PC/AT Refer to "OS for 3.5" 2HC

S7B13IE75X

or compatible IBM PCs" 5" 2HC

S7B10IE75X

Notes 1. This is a maintenance product.

2. This is a product of TOKYO ELETECH CORPORATION.

For further information, contact: Daimaru Kogyo, Ltd.

Tokyo Electronics Department (TEL +81-3-3820-7112)

Osaka Electronics 2nd Department (TEL +81-6-6244-6672)

3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark Operation of the IE control program is guaranteed only when using the host machine and OS described above.

PD75P3018A

60 Data Sheet U11917EJ2V1DS

OS for IBM PCs

The following operating systems for the IBM PC are supported.

OS Version

PC DOSTM Ver.5.02 to Ver.6.3

J6.1/V to J6.3/V

MS-DOS Ver.5.0 to Ver.6.22

5.0/V to 6.2/V

IBM DOSTM J5.02/V

Caution Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function.

PD75P3018A

Data Sheet U11917EJ2V1DS

APPENDIX C. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary versions are

not marked as such.

Device Related Documents

Document No.

Document Name

Japanese English

PD753012A, 753016A, 753017A Data Sheet U11662J U11662E

PD75P3018A Data Sheet U11917J U11917E

(This document)

PD753017 User's Manual U11282J U11282E

PD753017 Instruction Table IEM-5598 —

75XL Series Selection Guide U10453J U10453E

Development Tool Related Documents

Document No.

Document Name

Japanese English

Hardware IE-75000-R/IE-75001-R User's Manual EEU-846 EEU-1416

IE-75300-R-EM User's Manual U11354J U11354E

EP-753017GC/GK-R User's Manual EEU-967 EEU-1495

PG-1500 User's Manual U11940E U11940E

Software RA75X Assembler Package Operation U12622J U12622E

User's Manual Language U12385J U12385E

PG-1500 Controller User's Manual PC-9800 Series EEU-704 EEU-1291

(MS-DOS) base

IBM PC Series EEU-5008 U10540E

(PC DOS) base