Features
• Low-voltage and standard-voltage operation
VCC = 1.7V to 5.5V
• Internally organized as 32,768 x 8
• Two-wire serial interface
• Schmitt Trigger, filtered inputs for noise suppression
• Bidirectional data transfe r protoc ol
• 1MHz (5.0V, 2.7V, 2.5V), and 400kHz (1.7V) compatibility
• Write protect pi n for hardware and software data protecti on
• 64-byte page w rite mode (parti al page writes allowed)
• Self-timed write cycle (5ms max)
• High reliability
Endurance: one million write cycles
Data retenti o n: 40 years
• Lead-free/Halogen-free devices availab le
• 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN and 8-ball VFBGA packages
• Die sales: wafer form , waffle pack and b umped wafers
Description
The Atmel® AT24C256C provides 262,144-bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of eight
bits each. The device’s cascading feature allows up to eight devices to share a
common two-wire bus. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operation are essential.
The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead UDFN, and 8-ball VFBGA packages. In addition, this device operates from
1.7V to 5.5V.
Table 1. Pin Configurations
Pin Name
Function
V
CC
WP
SCL
SDA
A0
A1
A2
GND
4
3
2
1
5
6
7
8
8-lead UDFN
Bottom View
V
CC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-ball VFBGA
Bottom View
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-lead SOIC V
CC
WP
SCL
SDA
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
V
CC
WP
SCL
SDA
A0 – A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP Write Protect
GND Ground
Two-wire
Serial EEPROM
256K (32,768 x 8)
Atmel AT24C256C
8568D–SEEPR–9/11
2 Atmel AT24C256C
8568D–SEEPR–9/11
1. Absolute Maximum Ratings*
Operating temperature ........................... −55°C to +125°C
Storage temperature ............................ −65°C to + 150°C
Voltage on any pin
with respect to ground .................................. − 1.0 V +7.0V
Maximum operating voltage ..................................... 6.25V
DC output current .................................................... 5.0mA
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the dev ice. This is a stres s rating only
and functio nal operation of the devic e at these or
any other conditions beyond those indicated in
the operational sections of this specification are
not
implied. Exposure to absolute maximum
rating condit ions for extended per iods may affect
device reliability.
Figure 1-1. Block Diagram
START
STOP
LOGIC
V
CC
GND
WP
SCL
SDA
A
2
A
1
A
0
SERIAL
CONTROL
LOGIC
EN H.V. PUMP/TIMING
EEPROM
DATA RECOVERY
SERIAL MUX
X DEC
D
OUT
/ACK
LOGIC
COMP
LOAD INC
DATA WORD
ADDR/COUNTER
Y DEC
R/W
D
OUT
D
IN
LOAD
DEVICE
ADDRESS
COMPARATOR
Atmel AT24C256C
3
8568D–SEEPR–9/11
2. Pin Descriptions
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and
negative-edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may
be wire-ORed wit h any number of other open-drain or open-collector de vices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are
hardwired (directly to GND or to VCC) for compatibility with other Atmel AT24Cxx devices. When the pins are
hardwired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is
discussed in detail under “Device Addressing”) A device is selected when a corresponding hardw are and software
match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND.
However, due to capacitive coupling that may appear during customer applications, Atmel recommends always
connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or
less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When
WP is connected directly to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP
pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer
applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resis tor,
Atmel recommends using 10kΩ or less.
4 Atmel AT24C256C
8568D–SEEPR–9/11
3. Memory Organization
Atmel AT24C256C, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64-bytes each.
Random word add ressing requires a 15-bit data word address.
Table 3-1. Pin Capacitance(1)
Applicable over recommended operating range f rom: TA = 25°C, f = 1.0MHz, VCC = +1.7V
Symbol Test Condition Max Units Conditions
C
I/O
Input/Output Capacitance (SDA)
8
pF
V
I/O
= 0V
C
IN
Input Capacitance (A0, A1, SCL)
6
pF
V
IN
= 0V
Note: 1. This parameter is characterized and is not 100% tested
Table 3-2. DC Cha ra cteristics
Applicable over recommended operating range f rom: TAI = − 40°C to +85°C, VCC = +1.7V to +5.5V (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
VCC1 Supply Voltage 1.7 5.5 V
I
CC1
Supply Current
V
CC
= 5.0V
Read at 400kHz
1.0
2.0
mA
I
CC2
Supply Current
V
CC
= 5.0V
Write at 400kHz
2.0
3.0
mA
ISB1 Standby Current
(1.7V option)
VCC = 1.7V VIN = VCC or VSS 1.0 µA
VCC = 5.0V 6.0 µA
ILI Input Leakage
Currentt VCC = 5.0V VIN = VCC or VSS 0.10 3.0 µA
ILO
Output Leakage
Currentt VCC = 5.0V VOUT = VCC or VSS 0.05 3.0 µA
V
IL
Input Low Level(1)
-0.6
V
CC
x 0.3
V
V
IH
Input High Level(1)
V
CC
x 0.7
V
CC
+ 0.5
V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1mA 0.4 V
VOL1 Output Low Level VCC = 1.7V IOL = 0.15mA 0.2 V
Note: 1. VIL min and VIH max are reference onl y and are not tested
Atmel AT24C256C
5
8568D–SEEPR–9/11
Table 3-3. AC Characteristics (Industrial Tem perature)
Applicable over recommended operating range f rom :
TAI = − 40°C to +85°C, VCC = +1.7V to +5.5V, CL = 100 pF (unless ot h e r w i se noted). Test conditions are listed in Note 2.
Symbol Parameter 1.7V 2.5, 5.0V Units
Min Max Min Max
f
SCL
Clock Frequency, SCL
400
1000
kHz
tLOW Clock Pulse Width Low 1.3 0.4 µs
tHIGH Clock Pulse Width High 0.6 0.4 µs
tI Noise Suppression Time(1) 100 50 ns
t
AA
Clock Low to Data Out Valid
0.05
0.9
0.05
0.55
µs
tBUF Time the bus must be free before a new transmission can start(1) 1.3 0.5 µs
tHD.STA Start Hold Time 0.6 0.25 µs
tSU.STA Start Set-up Tim e 0.6 0.25 µs
tHD.DAT Data In Hold Time 0 0 µs
tSU.DAT Data In Set-up Time 100 100 ns
t
R
Inputs Rise Time(1)
0.3
0.3
µs
tF Inputs Fall Time(1) 300 100 ns
t
SU.STO
Stop Set-up Time
0.6
0.25
µs
t
DH
Data Out Hold Time
50
50
ns
t
WR
Write Cycle Time
5
5
ms
Endurance(1)
25°C, Page Mode, 3.3V
1,000,000
Write Cycles
Note: 1. This parameter is ens ured by characterization and is not 100% tested
2. AC measurement conditions:
- RL (connects to VCC): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V)
- Input pulse volt ages: 0.3VCC to 0.7VCC
- Input rise and fall times: ≤ 50ns
- Input and output timing reference voltages: 0. 5VCC
6 Atmel AT24C256C
8568D–SEEPR–9/11
4. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (refer to Figure 4-1). Data changes during SCL high
periods will indi cat e a start or stop condition as d efined below.
Figure 4-1. Data Validity
SDA
SCL
DATA ST
ABLE DATA STABLE
DATA
CHANGE
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any
other command (refer to Figure 4-2).
Figure 4-2. Start and Stop Definition
SDA
SCL
POTSTRATS
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command wil l pl ace the EEPROM in a standby power mode (refer to Figure 4-2).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words .
The EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The Atmel® AT24C256C features a low-power standby mode that is enabled upon power-up
and after the re ceipt of the stop bit and the completion of any internal operations.
Atmel AT24C256C
7
8568D–SEEPR–9/11
SOFTWARE RESET: After an interruption in protocol, power loss or system res et, any 2-wire part can be protocol
reset by following t hese steps:
a) Create a start bi t condition,
b) Clock nine cycles,
c) Create another start bit followed by stop bit condition as shown below.
The device is ready f or next communication after abov e st eps has been completed.
Figure 4-3. Soft ware Res et
Start bit Stop bitStart bitDummy Clock Cycles
SCL
SDA
98321
Figure 4-4. Bus Timing
SCL
SDA IN
SDA OUT
t
F
t
HIGH
t
LOW
t
LOW
t
R
t
AA
t
DH
t
BUF
t
SU.STO
t
SU.DAT
t
HD.DAT
t
HD.STA
t
SU.STA
8 Atmel AT24C256C
8568D–SEEPR–9/11
Figure 4-5. Write Cycle Timing
twr
(1)
STOP
CONDITION START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
Note: 1. The write cycle time tWR is the time from a valid stop condition of a writ e sequence to the end of
the internal clear/write cycle
Figure 4-6. Output Acknowledge
SCL
DATA IN
DATA OUT
EGDELWONKCATRATS
9
8
1
Atmel AT24C256C
9
8568D–SEEPR–9/11
5. Device Addressing
The 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read
or write operation (refer to Figure 5-1). The device address word consists of a mandatory “1”, “0” sequence for the
first four most significant bits as shown. This is common to all two-wire EEPROM devices.
Figure 5-1. Device A ddressing
1 0 1 0 A2 A1 A0 R/W
MSB
LSB
The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on the same bus.
These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal
proprietary cir cuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will
return to a standby state.
DATA SECURITY: The Atmel® AT24C256C has a hardware data protec tion scheme that allows the user to write
protect the whole memory when the WP pin is at VCC.
10 Atmel AT24C256C
8568D–SEEPR–9/11
6. Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the
first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing
device, such as a microcontroller, must then terminate the write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cy cle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle an d the EEPROM will not respond unt il the write is complete (refer to Figure 6-1).
Figure 6-1. Byte Write
Note: * = DON’T CARE bi t
PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word
received. The mi crocontroller mu st terminate the page write sequ ence with a stop condition (refer to Figure 6-2).
Figure 6-2. Page W rite
Note: * = DON’T CARE bi t
The data word address lower six bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
same page. If more than 64 data words are transmitted to the EEPROM, the data w ord address will “roll over” and
previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to
the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a “0”, allowing the read or write sequence t o continue.
Atmel AT24C256C
11
8568D–SEEPR–9/11
7. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in
the device address word is set to “1”. There are three read operations: current address read, random address
read, and sequent i al read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed
during the last read or write operation, incremented by one. This address stays valid between operations as long
as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page,
to the first byt e of the first page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but
does generate a f ol l owing stop condition (refer to Figure 7-1).
Figure 7-1. Curre nt Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address read by
sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and
serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following
stop condition. (Refer to Figure 7-2)
Figure 7-2. Random Rea d
Note: * = DON’T CARE bi t
12 Atmel AT24C256C
8568D–SEEPR–9/11
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read.
After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM
receives an acknowledge, it will continue to increment the data word address and serially clock out sequential
data words. When the memory address limit is reached, the data word address will “roll over” and the sequential
read will continue. The sequential read operation is terminated when the microc ontroller does not respond with a
“0” but does generate a following stop condition (refer to Figure 7-3).
Figure 7-3. Seque ntial Read
Atmel AT24C256C
13
8568D–SEEPR–9/11
8. Ordering Code Detail
Atmel Designator
Product Family
Device Density
Device Revision
Shipping Carrier Option
Operating Voltage
Package Option
256 = 256K
B or blank = Bulk (tubes)
T = Tape and re
el
L = 1.7V to 5.5V
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
C = VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu lead finish,
Industrial Temperature Range
(-40°C to +85°C)
U = Green, matte Sn lead finish,
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil wafer thickness
AT24C256C-SSHL-B
14 Atmel AT24C256C
8568D–SEEPR–9/11
9. Part Markings
Package M ar k Con tact:
DL-CSO-Assy_eng@atmel.com
DRAWING NO. REV.
TITLE
Lot Number
AAAAAAA = ATMEL Wafer Lot Number
Voltages
L: 1.8v min
Grade/Lead Finish Material
U: Industrial/MattTin
H: Industrial/NiPdAu
ATMEL Truncation
AT: ATMEL
ATM: ATMEL
ATML: ATMEL
Catalog Number: AT24C256C Catalog Truncation: 2EC
3 Rows of 8 Characters
AAAAAAAA
2ECL @
ATMLHYWW
8 lead SOIC
3 Rows
8 lead TSSOP
AAAAAAA
2ECL @
ATHYWW
2 Rows
2ECU
@YMXX
2.35x3.73mm
8-ball VFBGA
- 8 lead DFN -
3 Rows of 3 Characters
2EC
HL@
YXX
2.0x3.0mm
Date Codes
Y = Year M = Month WW = Work Week ofAssembly
0: 2010 4: 2014 A: January 02: Week 2
1: 2011 5: 2015 B: February 04: Week 4
2: 2012 6: 2016 “ ” “ ” “ ”
3: 2013 7: 2017 L: December 52: Week 52
Location ofAssembly
@ = Location ofAssembly
Trace Code
XX = Trace Code (ATMEL Lot Numbers to Correspond Code)
(e.g. XX: AA, AB...YZ, ZZ)
PIN 1
PIN 1
2 of 6 and 1 of 7 Characters
1 of 4 and 1 of 5 Characters
24C256CSM B
3/28/11
Note: Packages are not to scale in comparison to each other
.
24C256CSM, AT24C256C Standard Marking Information
for Package Offering
Atmel AT24C256C
15
8568D–SEEPR–9/11
10. Ordering Codes
Atmel AT24C256C Ordering Information
Ordering Code Voltage Package Operating Range
AT24C256C-SSHL-B(1)
AT24C256C-SSHL-T(2)
AT24C256C-XHL-B(1)
AT24C256C-XHL-T(2)
AT24C256C-MAHL-T(2)
AT24C256C-CUL-T(2)
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
8S1
8S1
8X
8X
8MA2
8U2-1
Lead-free/Halogen-free
Industrial Temperature (−40°C to 85°C)
AT24C256C-WWU11L(3)
1.7V to 5.5V
Die Sale
Industrial Temperature (−40°C to 85°C)
Note: 1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel deli ver y (SOIC 4k/reel, TSSOP, UDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Package Type
8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8X
8-lead, 4.40mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Dual No Lead Package (UDFN)
8U2-1
8-ball, die Ball Grid Array Package (VFBGA)
16 Atmel AT24C256C
8568D–SEEPR–9/11
11. Packaging Information
8S1 – JEDEC SOIC
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV.TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 –0.25
A1.35 –1.75
b0.31 –0.51
C0.17 –0.25
D4.80 –5.05
E1 3.81 –3.99
E5.79 –6.20
e1.27 BSC
L0.40 –1.27
0° –8°
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
8S1 G
6/22/11
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC) SWB
Atmel AT24C256C
17
8568D–SEEPR–9/11
8X – TSSOP
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV.TITLE GPC
COMM ON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 -0.15
A2 0.80 1.00 1.05
D2.90 3.00 3.10 2, 5
E6.40 BSC
E1 4.30 4.40 4.50 3, 5
b0.19 –0.30 4
e0.65 BSC
L0.45 0.60 0.75
L1 1.00 REF
C0.09 -0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this c or ner
E
e
Notes: 1. This drawing is for gener al information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion an d adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8X D
6/22/11
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
C
A1
18 Atmel AT24C256C
8568D–SEEPR–9/11
8MA2 – UDFN
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8MA2YNZ B
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
COMM ON DIMENSIONS
(Unit of Measure = mm)
SYMBOLMIN NOM MAX NOTE
D2.00 BSC
E3.00 BSC
D2 1.40 1.50 1.60
E2 1.20 1.30 1.40
A 0.50 0.55 0.60
A1 0.0 0.02 0.05
A2 – – 0.55
C 0.152 REF
L0.30 0.35 0.40
e 0.50 BSC
b0.18 0.25 0.30 3
K0.20 – –
7/15/11
D2
E2
E
e (6x)
L (8x)
b (8x)
Pin#1 ID
A
A1
A2
Pin 1 ID
D
C
K
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
Atmel AT24C256C
19
8568D–SEEPR–9/11
8U2-1 – VFBGA
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV.TITLE GPC
8U2-1 D
07/14/10
8U2-1, 8-ball, 2.35 x 3.73 mm Body,
0.75 mm pitch, VFBGA Package (dBGA2) GWW
COMM ON DIMENSIONS
(Unit of Measure = mm)
SYMBOLMIN NOM MAX NOTE
A0.81 0.91 1.00
A
1
0.15 0.20 0.25
A
2
0.40 0.45 0.50
b0.25 0.30 0.35
D 2.35 BSC
E 3.73 BSC
e
0.75 BSC
e1
0.74 REF
d 0.75 BSC
d1
0.80 REF
2. Dimension 'b' is measured at the maximum solder ball d iameter.
1. This drawing is for general information.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
Notes:
A
0.08 C
C
// 0.10 C
A1
A2
Øb
Ø0.15 mC A B
Ø0.08 mC
A
(4X)0.10
B
A1 BALLPA D CORNER D
e
SIDE VIEWTOP VIEW
e
(e1)
d
2 1
D
C
B
A
A1 BALLPA D CORNER
(d1)
8 SOL DER BALL S
BOTTOM VIEW
20 Atmel AT24C256C
8568D–SEEPR–9/11
Appendix A. Revision History
Doc. Rev.
Date
Comments
8568D 09/2011 Atmel global device marking alignment
Update 8S1, 8A2 to 8X, 8MA2, and 8U2-1 package drawings
8568C
05/2010
Update 8S1 and 8A2 package drawings.
8568B
03/2010
Part Markings and ordering detail/codes updated.
8568A
09/2009
Initial document release
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