PACDN009MR - California Micro Devices

09/21/04 430 N. McCarthy Blvd., Milpitas, CA 95035-51 12 ●Tel: 408.263.3214 ●Fax: 408.263.7846 ●www.calmicro.com 1

PACDN009

5 Channel ESD Protection Array

Features

• Five channels of ESD protection

•±8 kV contact, ±15 kV air ESD protection per

channel (IEC 61000-4-2 standard)

•±15 kV of ESD protection per channel (HBM)

• Low loading capacitance (3pF typical)

• Low leakage current is ideal for battery-powered

devices

• Available in miniature 8-lead MSOP package

• Lead-free version available

Applications

• Consumer electronic products

• Cellular phones

•PDAs

• Notebook computers

• Desktop PCs

• Digital cameras and camcorders

• VGA (video) port protection for desktop

and portable PCs

Product Description

The PACDN009 is a diode array designed to provide 5

channels of ESD protection for electronic components

or sub-systems. Each channel consists of a pair of

diodes which steers an ESD current pulse to either the

positive (VP) or negative (VN) supply. The PACDN009

protects against ESD pulses up to ±15kV Human Body

Model (100 pF capacitor discharging through a 1.5KΩ

resistor), and ±8kV contact discharge, per International

Standard IEC 61000-4-2.

This device is particularly well-suited for portable elec-

tronics (e.g., cellular phones, PDAs, notebook comput-

ers) because of its small package footprint, high ESD

protection level, and low loading capacitance. It is also

suitable for protecting video output lines and I/O ports

in computers and peripherals and is ideal for a wide

range of consumer electronics products.

The PACDN009 is supplied in an 8-lead MSOP pack-

age and is available with optional lead-free finishing.

Electrical Schematic

Typical Application Circuit

PACDN009

I/O Port

Buffers Connector

Expansion

Handheld/PDA ESD Protection

14568

0.22

* Capacitor should be placed

as close as possible to Pin7

1234

N.C.

2430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ●Tel: 408.263.3214 ●Fax: 408.263.7846 ●www.calmicro.com 09/21/04

PACDN009

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.

PIN DESCRIPTIONS

PIN NAME TYPE DESCRIPTION

1 CH 1 I/O ESD Channel

2 N.C. - No connect

NGND Negative voltage supply rail or ground reference rail

4 CH 2 I/O ESD Channel

5 CH 3 I/O ESD Channel

6 CH 4 I/O ESD Channel

PSupply Positive voltage supply rail

8 CH 5 I/O ESD Channel

PACKAGE / PINOUT DIAGRAMS

PACDN009

CH 1

N.C.

CH 2

CH 5

CH 4

CH 3

TOP VIEW

Note: This drawing is not to scale.

8-lead MSOP Package

PART NUMBERING INFORMATION

Leads Package

Standard Finish Lead-free Finish

Ordering Part

Number1Part Marking

Ordering Part

Number1Part Marking

8 MSOP PACDN009M D009 PACDN009MR 009R

09/21/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ●Tel: 408.263.3214 ●Fax: 408.263.7846 ●www.calmicro.com 3

PACDN009

Specifications

Note 1: Only one diode conducting at a time.

Note 1: All parameters specified at TA=25°C unless otherwise noted. VP = 5V, VN = 0V unless noted.

Note 2: These parameters guaranteed by design and characterization.

Note 3: From I/O pins to VP or VN only. VP bypassed to VN with a 0.22µF ceramic capacitor (see Application Information for more

details).

Note 4: Human Body Model per MIL-STD-883, Method 3015, CDischarge = 100pF, RDischarge = 1.5KΩ, VP = 5.0V, VN grounded.

Note 5: Standard IEC 61000-4-2 with CDischarge = 150pF, RDischarge = 330Ω, VP = 5.0V, VN grounded.

ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING UNITS

Supply Voltage (VP - VN)6.0V

Diode Forward DC Current (Note 1) 20 mA

Operating Temperature Range -40 to +85 °C

Storage Temperature Range -65 to +150 °C

DC Voltage at any channel input (VN - 0.5) to (VP + 0.5) V

Package Power Rating

MSOP Package 200 mW

STANDARD OPERATING CONDITIONS

PARAMETER RATING UNITS

Operating Temperature Range -40 to +85 °C

Operating Supply Voltage (VP - VN) 0 to 5.5 V

ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IPSupply Current (VP-VN)=5.5V 10 µA

VF Diode Forward Voltage IF = 20mA 0.65 0.95 V

VESD ESD Protection

Peak Discharge Voltage at any channel

input, in system

a) Human Body Model, MIL-STD-883,

Method 3015

b) Contact Discharge per IEC 61000-4-2

c) Air Discharge per IEC 61000-4-2

Note 3

Notes 2,4

Note 5

±15

±8

±15

VCL Channel Clamp Voltage

Positive Transients

Negative Transients

@15kV ESD HBM

VP + 13.0

VN - 13.0

ILEAK Channel Leakage Current ±0.1 ±1.0 µA

CIN Channel Input Capacitance @ 1 MHz, VP=5V, VN=0V,

VIN=2.5V; Note 2 applies

35pF

4430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ●Tel: 408.263.3214 ●Fax: 408.263.7846 ●www.calmicro.com 09/21/04

PACDN009

Performance Information

Input Capacitance vs. Input Voltage

012345

VIN

CIN (pF)

Typical Variation of C

vs. V

= 5V, V

= 0V, 0.1

F chip capacitor between V

and V

)

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PACDN009

Application Information

Design Considerations

In order to realize the maximum protection against

ESD pulses, care must be taken in the PCB layout to

minimize parasitic series inductances on the Supply/

Ground rails as well as the signal trace segment

between the signal input (typically a connector) and the

ESD protection device. Refer to Figure 1, which illus-

trates an example of a positive ESD pulse striking an

input channel. The parasitic series inductances back to

the power supply are represented by L1 and L2. The

voltage VCL on the line being protected is:

VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt

+ L2 x d(IESD ) / dt

where IESD is the ESD current pulse, and VSUPPLY is

the positive supply voltage.

An ESD current pulse can rise from zero to its peak

value in a very short time. As an example, a level 4

contact discharge per the IEC61000-4-2 standard

results in a current pulse that rises from zero to 30

Amps in 1ns. Here d(IESD)/dt can be approximated by

∆IESD/∆t, or 30/(1x10-9). So just 10nH of series induc-

tance (L1 and L2 combined) will lead to a 300V incre-

ment in VCL!

Similarly for negative ESD pulses, parasitic series

inductance from the VN pin to the ground rail will lead

to drastically increased negative voltage on the line

being protected.

Another consideration is the output impedance of the

power supply for fast transient currents. Most power

supplies exhibit a much higher output impedance to

fast transient current spikes. In the VCL equation

above, the VSUPPLY term, in reality, is given by (VDC +

IESD x ROUT), where VDC and ROUT are the nominal

supply DC output voltage and effective output imped-

ance of the power supply respectively. For example,

with ROUT equal to 1 ohm, we would see a 10V incre-

ment in VCL for a peak IESD of 10A.

If the inductances and resistance described above are

close to zero, the rail-clamp ESD protection diodes will

do a good job of protection. However, since this is not

possible in practical situations, a bypass capacitor

must be used to absorb the very high frequency ESD

energy. So for any brand of rail-clamp ESD protection

diodes, a bypass capacitor should be connected

between the VP pin of the diodes and the ground plane

(VN pin of the diodes) as shown in the Application Cir-

cuit diagram below. A value of 0.22µF is adequate for

IEC-61000-4-2 level 4 contact discharge protection

(±8kV). Ceramic chip capacitors mounted with short

printed circuit board traces are good choices for this

application. Electrolytic capacitors should be avoided

as they have poor high frequency characteristics. For

extra protection, connect a zener diode in parallel with

the bypass capacitor to mitigate the effects of the para-

sitic series inductance inherent in the capacitor. The

breakdown voltage of the zener diode should be

slightly higher than the maximum supply voltage.

As a general rule, the ESD Protection Array should be

located as close as possible to the point of entry of

expected electrostatic discharges. The power supply

bypass capacitor mentioned above should be as close

to the VP pin of the Protection Array as possible, with

minimum PCB trace lengths to the power supply,

ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also California Micro Devices Application Notes

AP209, “Design Considerations for ESD Protection”

and AP219, "ESD Protection for USB 2.0 Systems"”

Figure 1. Application of Positive ESD Pulse between Input Channel and Ground

PATH OF ESD CURRENT PULSE I

ONE

CHANNEL

PAC DN009

CHANNEL

INPUT

GROUND RAIL

CHASSIS GROUND

POSITIVE SUPPLY RAIL

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

LINE BEING

PROTECTED

ESD

20A

VCL

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PACDN009

Application Information (cont’d)

Implementation Examples

ESD events are very high-speed pulses with rise times

in the range of 1ns or less. To effectively use the

PACDN009, the following design guidelines must be

observed (as discussed in the application section):

1) The inductance from the VN and VP connections of

the PACDN009 to ground must be very low. This

includes the path through the VP decoupling capacitor

to ground and the path to the power supply (as dis-

cussed above).

2) The inductance between the connector pin to be

protected and the PACDN009 channel input pin must

be kept to a minimum. If there is a large inductance

here, the ESD event will find a lower impedance path

which will more likely be through the device to be pro-

tected. Figure 2 shows the implementation schematic

and Figure 3 shows a possible layout for the

PACDN009. In figure 3, notice the large VCC and

ground areas with multiple via connections to the

underlying reference planes and the positioning of the

bypass capacitor. Note how the signal lines to be pro-

tected flow from the connector to the PACDN009 and

then out to the device to be protected (Figure 3). This

daisy chaining provides a low impedance path from the

connector to the PACDN009 and a higher impedance

path from the PACDN009 to the protected device.

Figure 2. Typical ESD protection implementation

ONE

CHANNEL

PAC DN009

GROUND RAIL

POSITIVE SUPPLY RAIL

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

POWER SUPPLY

OPTIONAL

ZENER DIODE

FOR EXTRA

PROTECTION

CHANNEL

INPUT

DECOUPLING

CAPCITOR

0.22µF

LINE BEING

PROTECTED

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PACDN009

Application Information (cont’d)

Figure 3. PCB Layout Recomendation

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PACDN009

Mechanical Details

MSOP Mechanical Specifications

The PACDN009 is supplied in an 8-lead MSOP pack-

age. Dimensions are presented below.

For complete information on the MSOP-8 package,

see the specific California Micro Devices Package

Information document.

* This is an approximate number which may vary.

Package Dimensions for MSOP-8

PACKAGE DIMENSIONS

Package MSOP

Leads 8

Dimensions Millimeters Inches

Min Max Min Max

A0.87 1.17 0.034 0.046

A1 0.05 0.25 0.002 0.010

B0.30 (typ) 0.012 (typ)

C0.18 0.007

D2.90 3.10 0.114 0.122

E2.90 3.10 0.114 0.122

e0.65 BSC 0.025 BSC

H4.78 4.98 0.188 0.196

L0.52 0.54 0.017 0.025

# per tube 80 pieces*

# per tape

and reel

4000 pieces

Controlling dimension: inches

Mechanical Package Diagrams

1234

8765

END VIEW

SEATING

PLANE

SIDE VIEW

TOP VIEW

Pin 1

Marking