Advance information SD116U256 SD116U256L Ultra Low Power 256K x 16 CMOS SRAM Features Functional Description * Low-power consumption - Active: 25mA ICC at 70ns - Stand-by: 15 A (CMOS input/output) 4 A (CMOS input/output, L version) The SD116U256 is a Low Power CMOS Static RAM organized as 262,144 words by 16 bits. Easy memory expansion is provided by an active LOW (CE1) and (OE) pin and active HIGH (CE2). * 70/85/100/120 ns access time This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16. * Equal access and cycle time * Single +1.6V to 2.2V Power Supply * Tri-state output Writing to these devices is performed by taking Chip Enable (CE1) with Write Enable (WE) and Byte Enable (BLE/BHE) LOW while (CE2) remains HIGH. * Automatic power-down when deselected * Multiple center power and ground pins for improved noise immunity Reading from the device is performed by taking Chip Enable (CE1) with Output Enable (OE) and Byte Enable (BLE/BHE) LOW while Write Enable (WE) and (CE2) are held HIGH. * Individual byte controls for both Read and Write cycles * Available in 48-fpBGA/ 44L TSOPII * CE2 pin available for fpBGA only Logic Block Diagram TSOPII - Pin Description Pre-Charge Circuit A0 A1 Row Select A2 A3 A4 A5 A6 A7 Vcc Vss Memory Array 2048 X 2048 A8 A9 I/O1 - I/O8 Data Cont I/O Circuit I/O9 - I/O16 Data Cont Column Select A10 A11 A12 A13 A14 A15 A16 A17 WE OE BHE Control Logic BLE A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 CE Rev.8/19/99 20410 TOWN CENTER LANE, STE 270 s CUPERTINO, CA 95014 s TEL (408) 255-1262 s FAX (408) 255-1359 SD116U256/SD116U256L PACKAGE DIMENSION Soft Device, Inc. SD116U256 fpBGA 1 2 3 4 5 6 1 2 3 4 5 6 A BLE OE A0 A1 A2 CE2 B I/O9 BHE A3 A4 CE1 I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC Note: NC means no Ball. Top View Top View 48 Ball - 9x12 fpBGA (Ultra Low Power) A1 C PACKAGE OUTLINE DWG. SYMBOL UNIT:MM A 1.05+0.15 A1 0.25+0.05 A aaa SIDE VIEW E E1 b 0.35+.05 c 0.30(TYP) D 12.00+0.10 D1 5.25 E 9.00+0.10 e H G F D D1 E D C B A 1 2 3 4 BOTTOM VIEW 5 6 b SOLDER BALL 2 E1 3.75 e 0.75TYP aaa 0.10 SD116U256/SD116U256L PAD Descriptions PAD Name CE1, CE2 Descriptions I/O Chip selects I OE Output enable I WE Write enable I BLE Lower Byte selection I BHE Upper Byte selection I Address Inputs I A0 ~ A17 I/O1 ~ I/O16 Data Inputs/Outputs I/O VCC Power Supply - VSS Ground - NC No Connection - Absolute Maximum Ratings * Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 +3.3 V Power Dissipation PT - 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0C Temperature Under Bias Tbias -40 +85 0C * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 SD116U256/SD116U256L Truth Table CE1 H X X L L L L CE2 X L X H H H H OE X X X H H L L WE X X X H H H H BLE X X H L X L H BHE X X H X L H L L L L L H H H H L X X X H L L L L L H L L H L L Note: I/O1-8 I/O9-16 Power Mode High-Z High-Z Standby Deselected High-Z High-Z Standby Deselected High-Z High-Z Standby Deselected High-Z High-Z Active Output Disabled High-Z High-Z Active Output Disabled Data Out High-Z Active Lower Byte Read High-Z Data Out Active Upper Byte Read Data Out Data Out Active Word Read Data In High-Z Active Lower Byte Write High-Z Data In Active Upper Byte Write Data In Data In Active Word Write X means don'tcare. (Must be low or high state) Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**) Parameter Supply Voltage Input Voltage Symbol Min Typ Max Unit VCC 1.6 2.0 2.2 V Gnd 0.0 0.0 0.0 V VIH 1.4 - VCC + 0.2 V VIL -0.5* - 0.4 V * VIL min = -1.0V for pulse width less than tRC/2. ** For Industrial Temperature 4 SD116U256/SD116U256L DC Operating Characteristics (Vcc = 1.6 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter Sym Test Conditions -70 -85 -100 -120 Min Max Min Max Min Max Min Max Unit Input Leakage Current IILII Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 A Output Leakage Current IILOI CE = VIH or Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 A Operating Power Supply Current ICC CE = VIL , VIN = VIH or VIL , IOUT = 0 - 3 - 3 - 3 - 3 mA Average Operating Current ICC1 IOUT = 0mA, Min Cycle, 100% Duty - 25 - 20 - 15 - 15 mA ICC2 CE < 0.2V IOUT = 0mA, - 3 - 3 - 3 - 3 mA Cycle Time=1s, Duty=100% Standby Power Supply Current (TTL Level) ISB CE = VIH - 0.3 - 0.3 - 0.3 - 0.3 mA Standby Power Supply Current (CMOS Level) ISB1 CE > Vcc - 0.2V VIN < 0.2V or VIN > Vcc- 0.2V - 15 - 15 - 15 - 15 A - 4 - 4 - 4 - 4 A Output Low Voltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -2 mA 1.4 - 1.4 - 1.4 - 1.4 - V L Capacitance (f = 1MHz, TA = 25oC) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. CL 5 TTL SD116U256/SD116U256L Read Cycle (9) (Vcc = 1.6 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Sym -70 -85 -100 Unit -120 Note Min Max Min Max Min Max Min Max Read Cycle Time tRC 70 - 85 - 100 - 120 - ns Address Access Time tAA - 70 - 85 - 100 - 120 ns Chip Enable Access Time tACE - 70 - 85 - 100 - 120 ns Output Enable Access Time tOE - 40 - 40 - 50 - 50 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tHZ - 30 - 35 - 40 - 45 ns 3,4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns Output Disable to Output in High-Z tOHZ - 25 - 30 - 35 - 35 ns BLE, BHE Enable to Output in Low-Z tBLZ 5 - 5 - 5 - 5 - ns 4,5 BLE, BHE Disable to Output in High-Z tBHZ - 25 - 30 - 35 - 35 ns 3,4,5 BLE, BHE Access Time tBA - 70 - 85 - 100 - 120 ns Write Cycle (11) (Vcc = 1.6 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -70 -85 -100 Unit -120 Min Max Min Max Min Max Min Max Write Cycle Time tWC 70 - 85 - 100 - 120 - ns Chip Enable to Write End tCW 60 - 70 - 80 - 80 - ns Address Setup to Write End tAW 60 - 70 - 80 - 80 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 50 - 60 - 70 - 75 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 30 - 35 - 40 - 45 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWHZ - 30 - 35 - 40 - 45 ns Output Active from Write End tOW 5 - 5 - 5 - 5 - ns BLE, BHE Setup to Write End tBW 60 - 70 - 80 - 80 - ns 6 Note SD116U256/SD116U256L Timing Waveform of Read Cycle 1 (Address Controlled) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle 2 (CE1 Controlled) tRC Address tAA tHZ(3,4,5) tACE CE 1 tLZ(4, t5)BA tBHZ(3,4,5 tBLZ(4,5 )t OE tOHZ ) (UB/LB) OE Data Out High-Z tOH tOLZ Data Valid Timing Waveform of Read Cycle 3 (CE 2 Controlled) tRC Address tAA tHZ(3,4,5) tACE CE 2 tLZ(4, tBHZ(3,4,5 t ) 5) BA (UB/LB) tBLZ(4,5 )t OE tOHZ OE Data Out High-Z tOH tOLZ Data Valid 7 SD116U256/SD116U256L Timing Waveform of Write Cycle 1 (Address Controlled) tWC Address tAW tWR tCW CE (5) (3) tBW UB/LB tAS WE tWP (4) (2) tDW Data In tDH High-Z tOHZ (6) tOW High-Z (8) Data Out Timing Waveform of Write Cycle 2 (CE1 Controlled) tWC Address tAW tWR tCW CE1 (5) (3) tAS tBW (4) UB/LB tWP WE (2) tDW Data In High-Z Data Out High-Z tDH tWHZ (6) tLZ High-Z (8) Timing Waveform of Write Cycle 3 (CE2 Controlled) tWC Address tAW tWR CE2 (5) tCW tAS tBW (3) (4) UB/LB tWP WE (2) tDW Data In High-Z Data Out High-Z tDH tWHZ (6) tLZ High-Z (8) Timing Waveform of Write Cycle 4 (UB/LB Controlled) tWC Address tAW tWR tCW CE tAS tBW (5) (3) (4) UB/LB tWP WE (2) tDW Data In High-Z Data Out High-Z tDH tWHZ (6) tBLZ High-Z (8) 8 SD116U256/SD116U256L Data Retention Characteristics Parameter Symbol Test Condition Min Max Unit 1.0 - V VCC for Data Retention VDR CE1 > VCC - 0.2V or Data Retention Current ICCDR CE2 < + 0.2V - 3 A Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0 - ns Operation Recovery Time(2) tR VIN < 0.2V tRC - ns Data Retention Waveform (TA = 00C to +700C / -400C to +850C) Data Retention Mode VCC Vcc_typ VDR > 1.0V tCDR CE Vcc_typ tR V DR V IH V IH Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is HIGH for read cycle. CE1 and OE are LOW and CE2 is HIGH for read cycle. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. All read cycle timings are referenced from the last valid address to the first transtion address. CE1 or WE must be HIGH or CE2 must be LOW during address transition. All write cycle timings are referenced from the last valid address to the first transition address. 9 SD116U256/SD116U256L Ordering Information Device Type* SD116U256LH-70 SD116U256LH-85 SD116U256LH-100 SD116U256LH-120 Speed 70 ns 85 ns 100 ns 120 ns Package 44-pin TSOP Type 2 SD116U256FG-70 SD116U256FG-85 SD116U256FG-100 SD116U256FG-120 70 ns 85 ns 100 ns 120 ns 48-fpBGA * For Induatrial temperature tested devices, an "I" designator will be added to the end of the device number. Note: Soft Device reserves the right to make changes to its products and to this data sheet at any time, without notice, to improve design or performance. Soft Device makes no representation that circuits shown are free from patent infringments. Circuitry and other examples shown are meant only to indicate the performance and characteristics of our products. Soft Device products are not authorized for use as critical components in life support systems without written permission of the appropriate officer of Soft Device. 10