Memory Array
2048 X 2048
Row Select
I/O Circuit
Pre-Charge Circuit
Column Select
Data
Cont
Data
Cont
Vcc
Vss
A10 A11 A12 A13 A14
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
A16A15 A17
Control Logic
CE
Advance information
SD116U256
SD116U256L
Ultra Low Power
256K x 16 CMOS SRAM
Features
•Low-power consumption
- Active: 25mA ICC at 70ns
- Stand-by: 15 µA (CMOS input/output)
4 µA (CMOS input/output, L version)
•70/85/100/120 ns access time
•Equal access and cycle time
•Single +1.6V to 2.2V Power Supply
•Tri-state output
•Automatic power-down when deselected
•Multiple center power and ground pins for
improved noise immunity
•Individual byte controls for both Read and
Write cycles
•Available in 48-fpBGA/ 44L TSOPII
•CE2 pin available for fpBGA only
Functional Description
The SD116U256 is a Low Power CMOS Static RAM
organized as 262,144 words by 16 bits. Easy memory
expansion is provided by an active LOW (CE1) and (OE)
pin and active HIGH (CE2).
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE1) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW while (CE2) remains HIGH.
Reading from the device is performed by taking Chip
Enable (CE1) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) and (CE2)
are held HIGH.
TSOPII - Pin Description
Rev.8/19/99
20410 TOWN CENTER LANE, STE 270 s CUPERTINO, CA 95014 s TEL (408) 255-1262 s FAX (408) 255-1359
Logic Block Diagram
1
2
3
12
10
11
8
39
13
9
7
6
4
5
26
25
24
2322
21
14
15
16
17
18
19
20
40
41
42
43
44
38
37
36
35
34
33
32
31
30
29
28
27 A9
A8
A7
A6
A5A4
A3
A2
A1
WE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0
CE
Vss
Vcc
A13
A17
A16
A15
A14 A11
A10
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
NC
A12
Vss
Vcc
BHE
BLE
OE
PACKAGE DIMENSION
SD116U256/SD116U256L
2
SIDE VIEW
BOTTOM VIEW
48 Ball - 9x12 fpBGA (Ultra Low Power)
PACKAGE OUTLINE DWG.
SYMBOL UNIT:MM
A
E
E1
e
D1
D
C
A1
G
E
D
C
B
A
123456
aaa
b
SOLDER BALL
A1.05+0.15
A1 0.25+0.05
0.35+.05
0.30(TYP)
12.00+0.10
5.25
9.00+0.10
b
c
D
D1
E
E1
e
aaa
3.75
0.75TYP
0.10F
H
1 2 3 4 5 6
Soft Device, Inc. SD116U256 fpBGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
BLE
I/O9
I/O10
VSS
VCC
I/O15
I/O16
NC
OE
BHE
I/O11
I/O12
I/O13
I/O14
NC
A8
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE1
I/O2
I/O4
I/O5
I/O6
WE
A11
CE2
I/O1
I/O3
VCC
VSS
I/O7
I/O8
NC
Top View
Note: NC means no Ball.
Top View
3
PAD Descriptions
PAD Name Descriptions I/O
CE1, CE2Chip selects I
OE Output enable I
WE Write enable I
BLE Lower Byte selection I
BHE Upper Byte selection I
A0 ~ A17 Address Inputs I
I/O1 ~ I/O16 Data Inputs/Outputs I/O
VCC Power Supply -
VSS Ground -
NC No Connection -
SD116U256/SD116U256L
Absolute Maximum Ratings *
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 +3.3 V
Power Dissipation PT −1.0 W
Storage Temperature (Plastic) Tstg -55 +150 0C
Temperature Under Bias Tbias -40 +85 0C
SD116U256/SD116U256L
Truth Table
Note: X means don’t care. (Must be low or high state)
CE1CE2OE WE BLE BHE I/O1-8 I/O9-16 Power Mode
HX X X X X High-Z High-Z Standby Deselected
XLX X X X High-Z High-Z Standby Deselected
X X X X H H High-Z High-Z Standby Deselected
LH H H LXHigh-Z High-Z Active Output Disabled
LH H H XLHigh-Z High-Z Active Output Disabled
LHLHLHData Out High-Z Active Lower Byte Read
LHLH H LHigh-Z Data Out Active Upper Byte Read
LHLHL L Data Out Data Out Active Word Read
LHXL L HData In High-Z Active Lower Byte Write
LHXLHLHigh-Z Data In Active Upper Byte Write
LHXL L L Data In Data In Active Word Write
4
Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C**)
* VIL min = -1.0V for pulse width less than tRC/2.
** For Industrial Temperature
Parameter Symbol Min Typ Max Unit
VCC 1.6 2.0 2.2 V
Gnd 0.0 0.0 0.0 V
VIH 1.4 -VCC + 0.2 V
VIL -0.5* -0.4 V
Supply Voltage
Input Voltage
SD116U256/SD116U256L
DC Operating Characteristics (Vcc = 1.6 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Input Leakage Current IILII Vcc = Max,
Vin = Gnd to Vcc
-1-1-1-1µA
Output Leakage
Current IILOI CE = VIH or Vcc= Max,
VOUT = Gnd to Vcc -1-1-1-1µA
Operating Power
Supply Current ICC CE = VIL , VIN = VIH or VIL ,
IOUT = 0 -3-3-3-3mA
Average Operating
Current ICC1 IOUT = 0mA,
Min Cycle, 100% Duty -25 -20 -15 -15 mA
ICC2 CE < 0.2V
IOUT = 0mA,
Cycle Time=1µs, Duty=100%
-3-3-3-3mA
Standby Power Supply
Current (TTL Level) ISB CE = VIH -0.3 -0.3 -0.3 -0.3 mA
Standby Power Supply
Current (CMOS
Level)
ISB1 CE > Vcc - 0.2V
VIN < 0.2V or
VIN > Vcc- 0.2V L
-
-
15
4
-
-
15
4
-
-
15
4
-
-
15
4
µA
µA
Output Low Voltage VOL IOL = 2 mA -0.4 -0.4 -0.4 -0.4 V
Output High Voltage VOH IOH = -2 mA 1.4 -1.4 -1.4 -1.4 -V
C
L
TTL
-70 -100 -120
Unit
Parameter Sym Test Conditions
Min Max Min Max Min Max Min Max
-85
5
Capacitance (f = 1MHz, TA = 25oC)
Parameter* Symbol Test Condition Max Unit
Input Capacitance Cin Vin = 0V 7pF
I/O Capacitance CI/O Vin = Vout = 0V 8pF
* This parameter is guaranteed by device characterization and is not production tested.
Parameter Sym Unit Note
Read Cycle Time tRC 70 -85 -100 -120 -ns
Address Access Time tAA -70 -85 -100 -120 ns
Chip Enable Access Time tACE -70 -85 -100 -120 ns
Output Enable Access Time tOE -40 -40 -50 -50 ns
Output Hold from Address Change tOH 10 -10 -10 -10 -ns
Chip Enable to Output in Low-Z tLZ 10 -10 -10 -10 -ns 4,5
Chip Disable to Output in High-Z tHZ -30 -35 -40 -45 ns 3,4,5
Output Enable to Output in Low-Z tOLZ 5-5-5-5-ns
Output Disable to Output in High-Z tOHZ -25 -30 -35 -35 ns
BLE, BHE Enable to Output in Low-Z tBLZ 5-5-5-5-ns 4,5
BLE, BHE Disable to Output in High-Z tBHZ -25 -30 -35 -35 ns 3,4,5
BLE, BHE Access Time tBA -70 -85 -100 -120 ns
Read Cycle (9) (Vcc = 1.6 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Write Cycle (11) (Vcc = 1.6 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter Symbol Unit Note
Write Cycle Time tWC 70 -85 -100 -120 -ns
Chip Enable to Write End tCW 60 -70 -80 -80 -ns
Address Setup to Write End tAW 60 -70 -80 -80 -ns
Address Setup Time tAS 0-0-0-0-ns
Write Pulse Width tWP 50 -60 -70 -75 -ns
Write Recovery Time tWR 0-0-0-0-ns
Data Valid to Write End tDW 30 -35 -40 -45 -ns
Data Hold Time tDH 0-0-0-0-ns
Write Enable to Output in High-Z tWHZ -30 -35 -40 -45 ns
Output Active from Write End tOW 5-5-5-5-ns
BLE, BHE Setup to Write End tBW 60 -70 -80 -80 -ns
Min Max Min Max Min Max Min Max
-70 -85 -100 -120
6
Min Max Min Max Min Max Min Max
-70 -85 -100 -120
SD116U256/SD116U256L
7
Timing Waveform of Read Cycle 2 (CE
1
Controlled)
t
OHZ
t
RC
t
OLZ
t
ACE
t
LZ(4,
5)
CE
1
Address
t
OH
t
AA
t
OE
t
BA
t
BLZ(4,5
)
t
BHZ(3,4,5
)
t
HZ(3,4,5)
(UB/LB)
OE
Data Out Data Valid
High-Z
Timing Waveform of Read Cycle 1
(Address Controlled)
t
RC
t
AA
t
OH
Data Valid
Address
Data Out Previous Data Valid
SD116U256/SD116U256L
Timing Waveform of Read Cycle 3 (CE
2
Controlled)
t
OHZ
t
RC
t
OLZ
t
ACE
t
LZ(4,
5)
CE
2
Address
t
OH
t
AA
t
OE
t
BA
t
BLZ(4,5
)
t
BHZ(3,4,5
)
t
HZ(3,4,5)
(UB/LB)
OE
Data Out Data Valid
High-Z
8
SD116U256/SD116U256L
Timing Waveform of Write Cycle 1
(Address Controlled)
Timing Waveform of Write Cycle 4
(UB/LB Controlled)
Address
High-Z
t
DW
t
DH
t
WP
(2)
t
WC
t
CW
(3)
t
AW
t
WR
(5)
t
AS
(4)
Address
Address
Data In
Data In
Data In
Data Out
Data Out
Data Out
CE
CE1
CE
UB/LB
UB/LB
UB/LB
WE
WE
WE
t
BW
t
LZ
t
BLZ
t
WHZ (6)
High-Z (8)
High-Z
t
WHZ (6)
High-Z (8)High-Z
High-Z
t
DW
t
DH
t
WP
(2)
t
BW
t
AS
(4)
t
WR
(5)
t
CW
(3)
t
AW
t
WC
High-Z
High-Z (8)
t
OW
t
OHZ (6)
t
DW
t
DH
t
WP
(2)
t
BW
t
AS
(4)
t
CW
(3)
t
AW
t
WC
t
WR
(5)
Timing Waveform of Write Cycle 3
(CE2 Controlled)
Address
Data In
Data Out
CE2
UB/LB
WE
t
LZ
t
WHZ (6)
High-Z (8)High-Z
High-Z
t
DW
t
DH
t
WP
(2)
t
BW
t
AS
(4)
t
WR
(5)
t
CW
(3)
t
AW
t
WC
Timing Waveform of Write Cycle 2
(CE1 Controlled)
SD116U256/SD116U256L
Data Retention Characteristics
Parameter Symbol Test Condition Min Max Unit
VCC for Data Retention VDR CE1 > VCC - 0.2V or 1.0 -V
Data Retention Current ICCDR CE2 < + 0.2V
-3µA
Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0- ns
Operation Recovery Time(2) tRVIN < 0.2V tRC - ns
Data Retention Mode
V
DR
>
1.0V
Vcc_typ
V
IH
V
IH
V
DR
V
CC
CE
t
R
t
CDR
Vcc_typ
Data Retention Waveform (TA = 00C to +700C / -400C to +850C)
Notes
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition, Figure A.
4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
9
SD116U256/SD116U256L
Ordering Information
Device Type* Speed Package
SD116U256LH-70 70 ns 44-pin TSOP Type 2
SD116U256LH-85 85 ns
SD116U256LH-100 100 ns
SD116U256LH-120 120 ns
SD116U256FG-70 70 ns 48-fpBGA
SD116U256FG-85 85 ns
SD116U256FG-100 100 ns
SD116U256FG-120 120 ns
Note: Soft Device reserves the right to make changes to its products and to this data sheet at any time, without notice, to improve design or performance.
Soft Device makes no representation that circuits shown are free from patent infringments. Circuitry and other examples shown are meant only to indicate
the performance and characteristics of our products. Soft Device products are not authorized for use as critical components in life support systems without
written permission of the appropriate officer of Soft Device.
10
* For Induatrial temperature tested devices, an
“I”
designator will be added to the end of the device number.