(S) MOTOROLA MC14580B 4x 4MULTIPORT REGISTER The MC14580B is a 4 by 4 multiport register useful in smaii scratch pad memories, arithmetic operations when coupled with an adder, and other data storage applications, It allows independent reading of any two words (or the same word at both outputs) while writing into any one of four words. Address changing and data entry occur on the rising edge of the clock. When the write enable input is low, the contents of any word may be accessed but not altered. No Restrictions on Clock Input Rise or Fall Times 3-State Outputs Single Phase Clocking Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or one Low- power Schottky TTL Load Over the Rated Temperature Range @ Pin Compatible with CD40108 MAXIMUM RATINGS* (voitages Referenced to Vgs) Symbol Parameter Value Unit Vop {DC Supply Voltage ~ ~O.5to + 18.0 v Vin. Vout] (nput or Output Voltage (DC or Transient) -O.5 tO VoD +05 v line four | Input or Output Current (DC or Transient), per Pin 10 mA Pp Power Dissipation. per Packaget 500 mi Tstg | Storage Tenipsratire _ ~* -65 to +150 C Ty" | Lead Temperature (8-Second Soldering) 260 C "Maximum Ratings are those values beyond which damage to the device may occur. tTemperature Derating: Plastic P and D/DW" Packages: ~7.0 mWPC From 65C To 125C Ceramic "L" Packages: 12 mWC From 100C To 125C BLOCK DIAGRAM WO W1 RO, Rig ROgR1g je 2 p's pid yes {19 Clock 16 --- Decoder 3-State A I UT 4 15 H~ 20, - WE & P Ql~ar. | word A 20, st O24 ss Output tol. p} o3,p2 Data / 72] o1 FO 4x4 input Ip2 a Memory aon] 22 Wio3 | _ = a Kj Qigl2? | worge Q2g {2 f Output {1 O38, pi . Yor Vpp = Pin 24 3-State B Vgg = Pin 2 L SUFFIX CERAMIC 2 CASE 623 ~ P SUFFIX PLASTIC CASE 709 DW SUFFIX a SOIC . CASE 751E ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBDW SOIC Ta = -55 to 125C for all packages. PIN ASSIGNMENT 1c ad Vpp [__] 24 2C J a2, Qig f~) 23 3([]3statea Q0g [) 22 4Cloo, 3-Stere 8[] 21 s5Cyat, bof] 20 6 Caz, D1 [} 19 7 Cas, o2 [7] 18 8 C7] write o b3 [717 9 Co write 3 Clock [J 16 10 [J Read 1g WE [J 15 1t ("| Read Og Read 1p ] 14 12 Vss Read 0, [_] 13 6-484MC14580B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vg) a . Vpp 55C 25C 125C . Characteristic Symbol} ydc - Unit Min Max Min Typ # Max Min Max Output Voltage - *0" Level 5.0 _ 0.05 _ 0 0.05 _ 0.05 Vin = Vpp or 0 VOL 10 _ 0.05 - 0 0.05 _ 0.05 | Vde . 15 _ 0.05 _ 0 0.05 _- 0.05 4 Level 5.0 4.95 .| 495 5.0 _ 4.95 _ Vin = 0 or VoD ~ 1 VOH 10 9.95 - 9.95 10 _ 9.95.) Vde 15 14.95 _ 14.95 15 _ 14.95 _ Input Voltage ~ "0" Level (Vo = 450r0.5Vde) ~~ v 5.0 1.5 = 2.25 15 _ 18 | yao (VQ = 9.0 of 1.0 Vde)_ ie io | | 30 450 | 30 | | 30 (Vo = 13.5 or 1.5 Vdc) 15 _ 4.0 - 6.75 4.0 - 4.0 1 Level (VQ = 0.5.0r 4.5 Vdc) VIH 5.0 3.5 - 3.5 2.75 _- 3.5 - | Vie (Vo = 1.0 or 9.0 Vdc) 10 7.0 _ 7.0 5.50 _ 7.0 _ (Vo = 1.5 or 13.5 Vdc) 15. 1 _ 1 8.25 - W - Cutput Drive Current . : (VOR = 2.5 Vde) Source 5.0 ~3.0 _ ~2.4 ~4.2 _ -1.7 _ (VOH = 4.6 Vde) lOH 5.0 | -0,64 _ ~0.51 - 0,88 _ -0.36; | mAde (VoH = 9.5 Vdc) 1} -16) -1.3 | -225 _ -09 | (VoH = 13.5 Vdc) 168 | +42] -3.4 -8.8 _ -24]) (VoL = 0.4 Vde) Sink 5.0 | 064 ; 0.51 0.88 | 036} (VoL = 0.5 Vae) ; ~ lo 10 16) 13 2.25 _ 0.9 | mAdc (VOL = 1.5 Vde} 15 4.2 3.4 8.8 _ 2.4 Input Current lin 15 _ 01 - +0.00001| +0.1 _ 1.0 | pAdc Input Capacitance . Cin -- _ 5.0 75 -| pF (Vin = 9) Quiescent Current lbp 5.0 - 5.0 0.010 5.0 _ 150 | pAdc (Per Package) 10 _ 10 0.020 10 300 15 _ 20 _ 0.030 20 _ 600 Total Supply Current**} | 7 5.0 - fp = (1.18 pAVKHz) f + Ipp pAdc (Dynamic plus Quiescent, 10 Ip = (1.91 wAKHz) f + Ipp Per Package) 15 ly = (2.67 wA/KHZ} f + lop (Cy = 50 pF on all outputs, all buffers switching) Three-State Leakage Current | 1s | | 201 [| |+000001] +01] | +30 | pAde #Data labelled Typ is not to be used for design purposes but is intended as an indication of the 1Cs potential performance. : ~ **The formulas given are for the typical characteristics only at 25C. _ This device contains protection cir- . cuitry to guard against damage due {To calculate total supply current. at loads other than 50 pF: to high static voltages or electric = _ tote _ fields. However, precautions must (CL) = '7(50 pF) + (CL ~ 50) Vik be taken to avoid appiications of any where: IT is.in A (per package), Cy in pF, V = (Vpp Vgs) in volts, voltage higher than maximum rated f in KHz is input frequency, and k = 0.004. oo voltages to this high-impedance cir- cuit. For proper operation, Vip and Vout Should be constrained to the range Vss = (Vin ot Vout) = Vop- Unused inputs must always be tied to an appropriate logic voltage ievel (e.g., either Vgg or Vpp). Unused outputs must be left open. 6-485MC14580B SWITCHING CHARACTERISTICS* (C_=50 pF, Ta = 25C) Characteristic Symbol Yep Min Typ # Max Unit Output Rise and Fall Time TTLH tTHL as tTLH: tTHL= (4.5 ns/pF) C_+25 ns 1 5.0 =~ 100 200 TLH trHL = (0.75 ns/pF) C_ + 12.5 ns (Figures 3 and 8) 10 - 50 100 tTLH> tTHL = (0.55 ns/pF) C_+9.5 ns 15 - 40 80 Propagation Delay Time tPLH tPHL 5.0 _ 850 1300 ns Clock to Output (Figures 3 and 6) 10 - 250 500 15 ~ 170 340 Write Enable Setup Time tsu 5.0 800 400 _ ns {Enabling a Write or Read) (Figure 5) 10 300 150 _ 15 200 100 - Write Enable Removal Time trem 5.0 0 - 100 _ ns {Disabling # Write or Read) (Figure 5) 10 o ~50 _ 15 a ~35 _ Setup Time** tsu . 5.0 50 20 ns Address, Data to Clock (Figure 3) 10 30 0 - 15 25 0 _ Hold Time** th 5.0 480 180 - ns Glock to. Address, Data (Figure 3) 10 195 85 _ 15 150 50 3-State Enable/Disable Delay Time tpHz: (plz 5.0 ~ 130 260 ns tpzH: tpzL 10 _ 60 120 (Figures 4 and 7) 15 - 45 90 Clock Pulse Width ty 5.0 820 410 _ ns (Figure 3) 10 330 165 = 15 220 110 - **When toading repetitive highs, the output may glitch low momentarily after the tising edge of Clock. However, data integrity remains unaffected and data is valid after the Propagation delays listed in the Switching Characteristics Table, . FIGURE 1 ~ OUTPUT DRIVE CURRENT TEST CIRCUIT even Mout O- WE a0, oj wo 1 Q O od wi A ips ORO, a2,po oo Ria Qar-O Sink Currant | Sousce Current . O-| Rdg External Position ot St 2 7 Power osition o oA -O Pulse JL B 90, Supply Vas= Yoo -Voo Generator po = OlgfO Vos* Vout Vour~ Von D1 azpgho O2 DD 2 B32 Q3gfp-oO Vss Og, Z 5 Vss 6-486MC14580B FIGURE 2 POWER DISSIPATION TEST CIRCUIT AND WAVEFORMS (3-State Inputs are High) VoD00o-4 m eoot LI L Output VTS VS OnA.B Pulsa Generator oD RO, Ri A a3 ROg Pulse Rig = a0gh- TT Generator -O IC ai _ 2 pe BfO Le L O1 Q2g io - D2 Cr Pulse a3 L Generator b3 B ~] Mv CL ssh FIGURE 3 ty) anon Clock : : th Address Data 50% \ tPLH: (PHL = Q 50% 90% . 10% TL tTAL FIGURE VoD Vss Vou VoL -- Vpop ~ Yss Yop - Vss FIGURE 4 8-state\"] Vion tttCS~S Yop AorB 50% 50% Ve ~~ Vss tPHZ t 1PZH _ MV, 90% / OH Oa 1% -- = Vo. tpzL | -- tp2t 90% You 28 10% A Vor FIGURE TEST CIRCUIT Test Q Device YJ Under T CL FIGURE 7 TEST CIRCUIT Device Under Test Q 1k Connect to Vcc when testing tpyz and tpz, Il V Vv Connect to GND when testing tpyz and tpzy CL 6-487MC14580B LOGIC DIAGRAM Rig 19 RO, ROg, c Do 3 State c Co 3 State 2 Cc G 3-State O3 a c Oo 3-State Q D2 OQig pO 3 State c a 0g TRUTH TABLE o Clock WE Werte 1] Write O} Read ig] Read O, | Read tp | Read Og | 3 State A}3-State B Oy QnA anB _S_ 0 1 0 1 0 j 1 1 1 1 i J 1 0 1 0 1 0 1 i 1 0 o 0 LT x xX x x x x x 1 1 x No No Change | Change x x x x x x x x Q 0 x z Zz o x x x x x x x 1 1 x No No Change | Change 1 x x x x x x x 1 1 x No No Change | Change J 1 Q oO Qo 1 1 Q 1 1 BD, to | Contents] Contents word 0 | of word tlof word 2 displayed] displayed ae Oo Oo 0 0 1 1 0 1 1 Word 0 | Contents| Contents not [of word Hof word 2 altered | displayedidispiayed Z = High Impedance ~ - - * = Don't care 6-488