ICS601-21
MDS 601-21 H 1Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
LOW PHASE NOISE CLOCK MULTIPLIER
Description
The ICS601-21 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise and low jitter. It is ICS’ lowest
phase noise multiplier. Using ICS’ patented analong
and digital Phase Locked Loop (PLL) techniques, the
chip accepts a 10 - 27 MHz crystal or clock input, and
produces output clocks up to 220 MHz at 3.3 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input
and output skew and jitter are not defined nor
guaranteed.
Features
•Fully integrated PLL, no external loop filter required
•Differential 3.3 V LVPECL outputs
•Uses fundamental 10 - 27 MHz crystal or clock
•Output clocks up to 220 MHz at 3.3 V
•Low phase noise: -122 dBc/Hz at 10 kHz
•Low jitter - 15 ps one sigma typ.
•Powerdown mode lowers power consumption
•Packaged in 16-pin TSSOP
•Advanced, low power, sub-micron CMOS process
•Operating voltage of 3.3 V
•Commercial temperature range available
Block Diagram
CLK
ROM Based
Multipliers
VCO
Divide
X1/ICLK
X2
Crystal or
clock input
Crystal
Oscillator
Reference
Divider
Phase
Comparator
VDD
Charge
Pump
Loop
Filter VCO
S2:0
nCLK
4
GND
LOW PHASE NOISE CLOCK MULTIPLIER
MDS 601-21 H 2Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
Pin Assignment Multiplier Select Table
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
1
2
3
GND
4
VDD
5
6
GND
7
8
CLK
nCLK
S1GND
X2
VDD
S2
VDD
16
X1
VDD
GND
S0
VDD
15
14
13
12
11
10
9
16 Pin (173 mil) TSSOP
S2 S1 S0 Multiplier
000 x1
001 x2
010 x3
011 x4
100 x5
101 x6
110 x8
111 x16
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 X1 XI Crystal or clock input. Connect to a 10-27 MHz fundamental parallel mode
crystal or clock input.
2 - 4 VDD Power Connect to +3.3 V.
5 GND Power Connect to ground.
6 VDD Power Connect to +3.3 V.
7 - 8 GND Power Connect to ground.
9 S2 Input Select pin 2. Internal pull-up resistor.
10 S1 Input Select pin 1. Internal pull-up resistor.
11 S0 Input Select pin 0. Internal pull-up resistor.
12 VDD Power Connect to +3.3 V.
13 nCLK Output Inverted differential clock output.
14 CLK Output Differential clock output.
15 GND Power Connect to ground.
16 X2 XO Crystal connection. Connect to 10-27MHz fundamental parallel mode crystal
or leave unconnected for clock input.
LOW PHASE NOISE CLOCK MULTIPLIER
MDS 601-21 H 3Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
External Components
The ICS601-21 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as
possible. A 50 Ω terminating resistor should be used on each clock output. (See termination diagram on
page 5). The crystal must be connected as close to the chip as possible. The crystal should be
fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal,
capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value of these
capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) =
(CL-5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board
layout, ICS can measure the board capacitance and recommend the exact capacitance value to use.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-21. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature 0 to +70°C
Item Rating
Supply Voltage, VDD 7 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial version 0 to +70 °C
Storage Temperature -65 to +150 °C
Junction Temperature 125 °C
Soldering Temperature 260 °C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature 0 +70 °C
Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.0 3.6 V
Input High Voltage VIH X1/ICLK pin only VDD/2+1 V
Input Low Voltage VIL X1/ICLK pin only VDD/2-1 V
LOW PHASE NOISE CLOCK MULTIPLIER
MDS 601-21 H 4Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
DC Electrical Characteristics (continued)
Note 1: Outputs terminated with 50Ω to VDD-2V
AC Electrical Characteristics
VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C
Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x,
maximum input frequency is 13.75 MHz).
Parameter Symbol Conditions Min. Typ. Max. Units
Input High Voltage VIH Input select pins 2 VDD V
Input Low Voltage VIL Input select pins 0.8 V
Output High Voltage VOH Note 1 VDD-1.4 VDD-1.0 V
Output Low Voltage VOL Note 1 VDD-2.0 VDD-1.7 V
Output Voltage Swing Vswing Peak to Peak 0.6 0.95 V
Operating Supply Current IDD Note 1, 125 MHz 30 45 mA
Input Capacitance CIN Input select pins 5 pF
On Chip Pull-up Resistor RPU Input select pins 510 kΩ
Parameter Symbol Conditions Min. Typ. Max. Units
Crystal Input Frequency Fin Note 2 10 27 MHz
Output Frequency 10 220 MHz
Output Rise Time tOR 20% to 80%, no load 600 900 ps
Output Fall Time tOF 80% to 20%, no load 900 1200 ps
Output Clock Duty Cycle at VDD/2 45 50 55 %
Maximum Absolute Jitter, short
term, 125 MHz
No load ±50 ±75 ps
Maximum Jitter, one sigma,
125 MHz (x5)
No load 12 20 ps
Phase Noise, relative to carrier,
125 MHz (x5)
100 Hz offset -90 -94 dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
1 kHz -116 -120 dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
10 kHz offset -118 -122 dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
100 kHz offset -115 -119 dBc/Hz
LOW PHASE NOISE CLOCK MULTIPLIER
MDS 601-21 H 5Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
Parameter Measurement Information
Period Jitter
VOH
VOL
VREF
HISTOGRAM
Mean Period
(First edge after trigger)
1s contains 68.26% of all measurements
2s contains 95.4% of all measurements
3s contains 99.73% of all measurements
4s contains 99.99366% of all measurements
6s contains (100-1.973x10-7)% of all measurements
Reference Point
Clock
Outputs
80% 80%
20% 20%
tOR tOF
OUTPUT RISE/FALL TIME
VSWING
3.3V Output Load AC Test Circuit
LVPECL
VDD
= 3.3V
GND =0V
SCOPE
50Ω
50Ω
Z = 50Ω
Z = 50ΩQx
nQx
CYCLE-TO-CYCLE JITTER
tjit(cc) = tcycle(n) - tcycle(n+1)
tcycle(n) tcycle(n+1)
nFOUT
FOUT
1000 Cycles
3.3V LVPECL Driver Termination
LVPECL
VDD
= 3.3V
GND =0V
50Ω
50Ω
Z = 50Ω
Z = 50ΩQx
nQx
VDD
-2V = 1.3V
Pulse Width
tPERIOD
OUTPUT DUTY CYCLE AND tPERIOD
tPW
tPERIOD
ODC =
nFOUT
FOUT
LOW PHASE NOISE CLOCK MULTIPLIER
MDS 601-21 H 6Revision 040204
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
ICS601-21
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those
requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
Part / Order Number Marking Shipping
packaging
Package Temperature
ICS601G-21 ICS601G-21 Tubes 16-pin TSSOP 0 to 70° C
ICS601G-21T ICS601G-21 Tape and Reel 16-pin TSSOP 0 to 70° C
INDEX
AREA
1 2
16
D
E1 E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
Millimeters Inches
Symbol Min Max Min Max
A--1.20--0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.19 0.30 0.007 0.012
C 0.09 0.20 0.0035 0.008
D 4.90 5.1 0.193 0.201
E 6.40 BASIC 0.252 BASIC
E1 4.30 4.50 0.169 0.177
e 0.65 Basic 0.0256 Basic
L 0.45 0.75 0.018 0.030
α0°8°0°8°
aaa -- 0.10 -- 0.004
