WEDPS512K32-XBX
May 2011 © 2011 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 7 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
512Kx32 SRAM MULTI-CHIP PACKAGE
FEATURES
Access Times of 12, 15, 17, 20, ns
Packaging
• 16mm x 18mm, 143 PBGA
Organized as 512Kx32, User Confi gurable as 1Mx16 or
2Mx8
Commercial, Industrial and Military Temperature Ranges
TTL Compatible Inputs and Outputs
5V Power Supply
Low Power CMOS
This product is subject to change without notice.
PIN CONFIGURATION FOR WEDPS512K32-XBX
TOP VIEW
123456789101112
A- A2 A1 A0 GND GND VCC VCC A18 A17 A16 GND
BCS#2 A3 A4 D14 D15 NC CS#4 D24 D25 OE# A15 NC
CD9 D8 NC D12 D13 GND VCC D26 D27 WE#4 D31 D30
DD10 D11 GND GND GND GND VCC VCC VCC VCC D28 D29
EWE#2 GND GND GND GND GND VCC VCC VCC VCC VCC NC
FGND GND GND GND GND GND VCC VCC VCC VCC VCC VCC
GVCC VCC VCC VCC VCC VCC GND GND GND GND GND GND
HCS#1 VCC VCC VCC VCC VCC GND GND GND GND GND NC
JD1 D0 VCC VCC VCC VCC GND GND GND GND D23 D22
KD2 D3 NC D7 D5 VCC GND D17 D16 CS#3 D20 D21
LWE#1 A6 A5 D6 D4 NC WE#3 D19 D18 A14 A13 NC
MGND A7 A8 A9 VCC VCC GND GND A10 A11 A12 VCC
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE#1-4 Write Enables
CS#1-4 Chip Selects
OE# Output Enable
VCC Power Supply
GND Ground
NC Not Connected
512K x 8
8
I/O0-7
WE#1 CS#1
512K x 8
8
I/O8-15
WE#2 CS#2
512K x 8
8
I/O16-23
WE#3 CS#3
512K x 8
8
I/O24-31
WE#4 CS#4
A
0-18
OE#
BLOCK DIAGRAM
WEDPS512K32-XBX
May 2011 © 2011 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 7 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
TRUTH TABLE
CS OE WE Mode Data I/O Power
H X X Standby High Z Standby
L L H Read Data Out Active
L H H Out Disable High Z Active
L X L Write Data In Active
BGA THERMAL RESISTANCE
Description Symbol Max Unit Notes
Junction to Ambient (No Airfl ow) Theta JA 16.5 °C/W 1
Junction to Ball Theta JB 11.3 °C/W 1
Junction to Case (Top) Theta JC 9.8 °C/W 1
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
Operating Temperature TA-55 +125 °C
Storage Temperature TSTG -65 +150 °C
Signal Voltage Relative to GND VG-0.5 VCC+0.5 V
Junction Temperature TJ150 °C
Supply Voltage VCC -0.5 7.0 V
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Unit
Supply Voltage VCC 4.5 5.5 V
Input High Voltage VIH 2.2 VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
Operating Temp (Mil) TA-55 +125 °C
CAPACITANCE
(TA = +25°C)
Parameter Symbol Conditions Max Unit
OE# capacitance COE VIN = 0 V, f = 1.0 MHz 30 pF
WE#1-4 capacitance CWE VIN = 0 V, f = 1.0 MHz 10 pF
CS#1-4 capacitance CCS VIN = 0 V, f = 1.0 MHz 10 pF
Data I/O capacitance CI/O VI/O = 0 V, f = 1.0 MHz 10 pF
Address input capacitance CAD VIN = 0 V, f = 1.0 MHz 30 pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Symbol Conditions Min Max Units
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 μA
Output Leakage Current ILO CS# = VIH, OE# = VIH, VOUT = GND to VCC 10 μA
Operating Supply Current x 32 Mode ICC x 32 CS# = VIL, OE# = VIH, f = 5MHz, Vcc = 5.5 660 mA
Standby Current ISB CS# = VIH, OE# = VIH, f = 5MHz, Vcc = 5.5 80 mA
Output Low Voltage VOL IOL = 8mA 0.4 V
Output High Voltage VOH IOH = -4.0mA 2.4 V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
WEDPS512K32-XBX
May 2011 © 2011 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 7 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Symbol -12 -15 -17 -20 Units
Read Cycle Min Max Min Max Min Max Min Max
Read Cycle Time tRC 12 15 17 20 ns
Address Access Time tAA 12 15 17 20 ns
Output Hold from Address Change tOH 0000ns
Chip Select Access Time tACS 12 15 17 20 ns
Output Enable to Output Valid tOE 7 8 9 10 ns
Chip Select to Output in Low Z tCLZ11222ns
Output Enable to Output in Low Z tOLZ10000ns
Chip Disable to Output in High Z tCHZ17 121212ns
Output Disable to Output in High Z tOHZ17 121212ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter Symbol -12 -15 -17 -20 Units
Read Cycle Min Max Min Max Min Max Min Max
Write Cycle Time tWC 12 15 17 20 ns
Chip Select to End of Write tCW 10 13 15 15 ns
Address Valid to End of Write tAW 10 13 15 15 ns
Data Valid to End of Write tDW 8101112ns
Write Pulse Width tWP 10 13 15 15 ns
Address Setup Time tAS 0222ns
Address Hold Time tAH 0000ns
Output Active from End of Write tOW1 2223ns
Write Enable to Output in High Z tWHZ1 78911ns
Data Hold Time tDH 0000
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT AC TEST CONDITIONS
Parameter Typ Unit
Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 .
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Current Source
Current Source
IOL
IOH
Ceff = 50 pf
D.U.T. VZ ≈ 1.5V
(Bipolar Supply)
WEDPS512K32-XBX
May 2011 © 2011 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 7 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
TIMING WAVEFORM – READ CYCLE
A
DDRESS
tRC
CS#
OE#
DATA I/O
tAA
tACS tCHZ
tCLZ
tOE
tOLZ
tOHZ
HIGH IMPEDANCE
DATA VALID
READ CYCLE 2 (WE# = VIH)
A
DDRESS
DATA I/O PREVIOUS DATA VALID DATA VALID
READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH)
tOH
tAA
tRC
WRITE CYCLE – WE# CONTROLLED
A
DDRESS
tWC
tAW
tCW tAH
tAS tWP
tWHZ tDW
tOW
tDH
DATA VALID
CS#
DATA I/O
WE#
WRITE CYCLE 1, WE# CONTROLLED
A
DDRESS
tWC
tAW
tAS tAH
tCW
tWP
tDW tDH
CS#
WE#
DATA I/O DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
WRITE CYCLE – CS# CONTROLLED
WEDPS512K32-XBX
May 2011 © 2011 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 7 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
0.61 (0.024)
NOM
1.27
(0.050)
NOM
A
B
C
D
E
F
G
H
J
K
L
M
13.97 (0.550)
NOM
16.25 (0.640)
MAX
18.25 (0.719)
MAX
13.97 (0.550)
NOM 1.93 (0.076) MAX
1.27 (0.050) NOM
BOTTOM VIEW
12 11 10 9 8 7 6 5 4 3 2 1
PACKAGE 7043 – 143 BALL GRID ARRAY
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
WEDPS512K32-XBX
May 2011 © 2011 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 7 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
MICROSEMI CORPORATION
PLASTIC
SRAM
ORGANIZATION, 512Kx32
User confi gurable as 1Mx16 or 2Mx8
ACCESS TIME (ns)
PACKAGE TYPE:
B = 143 PBGA, 16mm x 18mm, 288mm2
DEVICE GRADE:
M = Military Screened -55°C to +125°C
I = Industrial -40°C to 85°C
C = Commercial 0°C to +70°C
WED P S 512K 32 - XX X X
WEDPS512K32-XBX
May 2011 © 2011 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 7 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Document Title
512K x 32 SRAM Multi-Chip Package
Revision History
Rev # History Release Date Status
Rev 0 Initial Release March 2002 Advanced
Rev 1 1.1 Switch Rows and Columns header position (Pg. 1) March 2002 Advanced
Rev 2 2.1 Switch Rows and Columns header position (Pg. 1) May 2002 Advanced
Rev 3 3.1 Change mechanical outline to more accurate design (Pg. 1, 5) May 2002 Advanced
Rev 4 4.1 Remove references to 25-55ns speed grades (Pg. 1, 2, 3) August 2002 Advanced
Rev 5 Changes (Pg. 1, 2)
5.1 Add Thermal Resistance Table
5.2 Change product status to Final
January 2003 Final
Rev 6 Changes (Pg. 1, 5, 7)
6.1 Change package body height to 1.93mm Max
6.2 Add ball pitch (1.27mm) to package dimension
November 2003 Final
Rev 7 Changes (Pg. 1-7)
7.1 Change document layout from White Electronic Designs to Microsemi
May 2011 Final
