PCF8576CT/1,518 - NXP Semiconductors

1. General description

The PCF8576C is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or

multiplexed LCD containing up to four backplanes and up to 40 segments and can easily

be cascaded for larger LCD applications. The PCF8576C is compatible with most

microcontrollers and communica tes via the two-li ne bidirectio nal I2C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing and by

hardware subaddressing.

For a selection of NXP LCD segment drivers, see Table 24 on page 52.

2. Features and benefits

Single-chip LCD controller and driver

40 segment dr ive s:

Up to twenty 7-segment alphanumeric characters

Up to ten 14-segment alphanumeric characters

Any graphics of up to 160 elements

Versatile blinking modes

No external components required (even in multiple device applications)

Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing

Selectable display bias configuration: static, 1⁄2, or 1⁄3

Internal LCD bias generation with voltage-follower buffers

40 4-bit RAM for display data storage

Auto-incremented display data loading across device subaddress boundaries

Display memory bank switching in static and duplex drive modes

Wide logic LCD supply range:

From 2 V for low-threshold LCDs

Up to 6 V for high-threshold twisted nematic LCDs

Low power consum ption

May be cascaded for large LCD applications (up to 2560 elements possible)

No external components required

Separate or combined LCD and logic supplies

Optimized pinning for plane wiring in both single and multiple PCF8576C applications

Power-saving mode for extremely low power consumption in battery-operated and

telephone applications

PCF8576C

Universal LCD driver for low multiplex rates

Rev. 13 — 16 December 2013 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 20.

Product data sheet Rev. 13 — 16 December 2013 2 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

3. Ordering information

3.1 Ordering options

4. Marking

Ta ble 1. Ordering information

Type number Package

Name Description Version

PCF8576CHL/1 LQFP64 plastic low profile quad flat package;

64 leads; body 10 10 1.4 mm SOT314-2

PCF8576CT/1 VSO56 plastic very small outline package, 56 leads SOT190-1

PCF8576CU/2/F2 bare die bare die; 56 bumps; 3.2  2.92  0.40 m m PCF8576CU /2

PCF8576CU/F1 bare die wire bond die; 56 bonding pads; 3.2  2.92  0.38 mm PCF8576CU

Table 2. Ordering options

Product type number Sales item (12NC) Orderable part

number IC

revision Delivery form

PCF8576CHL/1 935290305118 PCF8576CHL/1,118 1 tape and reel, 13 inch

935290305157 PCF8576CHL/1,157 1 tray pack

PCF8576CT/1 935278818518 PCF8576CT/1,518 1 tape and reel, 13 inch, dry pack

PCF8576CU/2/F2 935261851026 PCF8576CU/2/F2,026 1 chips in tray

PCF8576CU/F1 935208600026 PCF8576CU/F1,026 1 chips in tray

Table 3. Marking codes

Product type number Marking code

PCF8576CHL/1 PCF8576CHL

PCF8576CT/1 PCF8576CT

PCF8576CU/2/F2 PC8576C-2

PCF8576CU/F1 PC8576C-1

Product data sheet Rev. 13 — 16 December 2013 3 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

5. Block diagram

Fig 1. Block diagram of PCF8576C

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Product data sheet Rev. 13 — 16 December 2013 4 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

6. Pinning information

6.1 Pinning

Top view. For mechanical details, see Figure 33.

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Product data sheet Rev. 13 — 16 December 2013 5 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Top view. For mechanical details, see Figure 34.

Fig 3. Pin configura tio n for VS O56 (PCF8 5 76C T/ 1 )

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Product data sheet Rev. 13 — 16 December 2013 6 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Viewed from pin side. For mechanical details, see Figure 36 and Figure 35.

Fig 4. Pin locations of PCF8576CU/F1 and PCF8576CU/2/F2

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Product data sheet Rev. 13 — 16 December 2013 7 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

6.2 Pin description

[1] The substrate (rear side of the die) is connected to VDD and should be electrically isolated.

Table 4. Pin de scription

Input or input/output pins mu st always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol Pin Description

LQFP64

(PCF8576CHL) VSO56

(PCF8576CT) PCF8576CU Type

SDA 10 1 1 input/output I2C-bus serial da ta input and output

SCL 11 2 2 input I2C-bus serial clock input

SYNC 12 3 3 input/output cascade synchronization input and

output

CLK 13 4 4 input/output external clock input/output

VDD 14 5 5[1] supply supply voltage

OSC 15 6 6 input internal oscillator enable input

A0 to A2 16 to 18 7 to 9 7 to 9 input subadd ress inputs

SA0 19 10 10 input I2C-bus address input; bit 0

VSS 20 11 11 supply ground supply voltage

VLCD 21 12 12 supply LCD supply voltage

BP0, BP2,

BP1, BP3 25 to 28 13 to 16 13 to 16 output LCD backplane outputs

S0 to S39 2 to 7, 29 to 32,

34 to 47, 49 to 64 17 to 56 17 to 56 output LCD segment outputs

n.c. 1, 8, 9, 22 to 24,

33, 48 - - - not connected; do not connect and

do not use as fee d through

Product data sheet Rev. 13 — 16 December 2013 8 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7. Functional description

The PCF8576C is a versatile peripheral device designed to interface between any

microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 5). It

can directly drive any static or multiplexed LCD containing up to four backplanes and up to

40 segments.

The possible display configurations of the PCF8576C depend on the number of active

backplane outputs required. A selection of display configurations is shown in Table 5. All

of these configurations can be implemented in the typical system shown in Figure 6.

Fig 5. Example of displays suitable for PCF8576C

Table 5. Selection of po ssi ble display configurations

Number of

Backplanes Icons Digits/Characters Dot matrix/

Elements

7-segment 14-segment

4 160 20 10 160 dots (4  40)

3 120 15 7 120 dots (3  40)

28010580dots (2 40)

1405240dots (140)

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Product data sheet Rev. 13 — 16 December 2013 9 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The host microprocessor or microcontroller maintains the 2-line I2C-bus communication

channel with the PCF8576C.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to VSS. The only other connections required to complete the system are the

power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.

7.1 Power-On-Reset (POR)

At power-on the PCF8576C resets to the following starting conditions:

•All backplane and segment outputs are set to VDD

•The selected drive mode is 1:4 multiplex with 1⁄3 bias

•Blinking is switched off

•Input and output bank selectors are reset

•The I2C-bus interface is initialized

•The data pointer and the subaddress counter are cleared

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

The full-scale LCD voltage (Voper) is obtained from VDD VLCD. The LCD voltage may be

temperature compensated externally through the VLCD supply to pin VLCD.

Fractional LCD biasing voltages are obtained from an internal voltage divider comprising

three series res isto rs connected between VDD and VLCD. The center resistor can be

switched out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex

configuration.

Fig 6. Typical system configuration

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Product data sheet Rev. 13 — 16 December 2013 10 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.3 LCD voltage selector

The LCD voltage selector coord ina te s th e mu ltiplexing of the LCD in accordance with the

selected LCD drive configuration. The operation of the voltage selector is controlled by the

mode-set command from the command decoder. The biasing configurations that apply to

the preferred modes of o per ation , to gether with the biasing cha racteri stics as functions o f

VLCD and the resulting discrimination ratios (D) are given in Table 6.

Discrimination is a term which is defined as the ratio of the on a nd off RMS volt age across

a segment. It can be thought of as a measurement of contrast.

A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD

threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In

the static drive mode, a suitable choice is VLCD >3V

th.

Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and

hence the contrast ratios are smaller.

Bias is calculated by , where the values for a are

a = 1 for 1⁄2 bias

a = 2 for 1⁄3 bias

The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:

(1)

where the values for n are

n = 1 for static drive mode

n = 2 for 1:2 multiplex drive mode

n = 3 for 1:3 multiplex drive mode

n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:

(2)

Discrimination is the ratio of Von(RMS) to Voff(RMS) an d is dete rm in ed from Equation 3:

Table 6. Biasing characteristics

LCD drive

mode Number of: LCD bias

configuration

Backplanes Levels

static 1 2 static 0 1 

1:2 multiplex 2 3 1⁄20.354 0.791 2.236

1:2 multiplex 2 4 1⁄30.333 0.745 2.236

1:3 multiplex 3 4 1⁄30.333 0.638 1.915

1:4 multiplex 4 4 1⁄30.333 0.577 1.732

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VLCD

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VLCD

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Product data sheet Rev. 13 — 16 December 2013 11 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

(3)

Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with

1⁄2bias is and the discrimination for an L CD drive mode of 1:4 multiple x with

1⁄2bias is .

The advanta ge of these LCD drive modes is a reduction of the LCD full scale volta ge VLCD

as follows:

•1:3 multiplex (1⁄2 bias):

•1:4 multiplex (1⁄2 bias):

These compare with when 1⁄3 bias is used.

VLCD is sometimes referred as the LCD operating voltage.

7.3.1 Electro-optical performance

Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The

RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of

the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative

transmission (at Vth(off)) and the other at 90 % re lat ive tran sm iss i on (at Vth(on)), see

Figure 7. For a good contrast performance, the following rules should be followed:

(4)

(5)

Von(RMS) and Voff(RMS) are properties of the display driver and are af fected by the selection

of a (see Equation 1), n (see Equation 3), and the V LCD voltage.

Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module

manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation

voltage Vsat.

It is important to match the module properties to those of the driver in order to achieve

optimum performance.

DVon RMS

Voff RMS

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off RMS

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VLCD 43

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VLCD 3Voff RMS

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Vth off

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Product data sheet Rev. 13 — 16 December 2013 12 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 7. Electro-optical characteristic: relative transmission curve of the liquid

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Product data sheet Rev. 13 — 16 December 2013 13 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 8.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = VLCD.

Vstate2(t) = VSn+1(t)  VBP0(t).

Voff(RMS) = 0 V.

Fig 8. Static drive mode wavefo rms

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Product data sheet Rev. 13 — 16 December 2013 14 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4.2 1:2 Multiplex drive mode

When two backpla ne s ar e pr ov ide d in the LCD , the 1:2 multiple x mo d e ap plie s. The

PCF8576C allows the use of 1⁄2 bias or 1⁄3 bias (see Figure 9 and Figure 10).

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.791VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.354VLCD

Fig 9. W aveforms for the 1:2 multiplex drive mode with 1⁄2 bias

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Product data sheet Rev. 13 — 16 December 2013 15 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Vstate1(t) = VSn(t)  VBP0(t).

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Vstate2(t) = VSn(t)  VBP1(t)

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Fig 10. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias

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Product data sheet Rev. 13 — 16 December 2013 16 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4.3 1:3 Multiplex drive mode

When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as

shown in Figure 11.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.638VLCD.

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Fig 11. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias

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Product data sheet Rev. 13 — 16 December 2013 17 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.4.4 1:4 multiplex drive mode

When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 12.

Vstate1(t) = VSn(t)  VBP0(t).

Von(RMS) = 0.577VLCD.

Vstate2(t) = VSn(t)  VBP1(t).

Voff(RMS) = 0.333VLCD.

Fig 12. Waveforms for the 1:4 multiplex mode with 1⁄3 bias

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Product data sheet Rev. 13 — 16 December 2013 18 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.5 Oscillator

The internal logic a nd the LCD dr ive signals o f the PCF857 6C are timed by the freque ncy

fclk, which equals either the built-in oscillator frequency fosc or the external clock fr equency

fclk(ext).

The clock frequency (fclk) d etermines the LCD frame frequen cy (ffr) and the ma ximum rate

for data recep tion from the I2C-bus. To allow I2C-bus transmissions at their maximum dat a

rate of 100 kHz, fclk should be chosen to be above 125 kHz.

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the

output from pin CLK is the clock signal for any cascaded PCF8576C in the system.

7.5.2 External clock

Connecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the

external clock input.

Remark: A clock signal must always be supplied to the device. Removing the clock,

freezes the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The timing of the PCF8576C seque nces the internal dat a flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. In

cascaded applications, the synchronization signal (SYNC) maintains the correct timing

relationship between the PCF8576Cs in the system. The timing also generates the LCD

frame frequency which is derived as an integer division of the clock frequency (see

Table 7). The fram e frequency is set by the mode-set command (see Table 10) when an

internal clock is used o r by the frequency app lied to the pin CL K when an external cloc k is

used.

[1] The possible values for fclk see Table 17.

[2] For fclk = 200 kHz.

[3] For fclk = 31 kHz.

The ratio between the clock frequency and the LCD frame frequency depen ds on the

power mode in which the device is operating. In the power-saving mode, the reduction

ratio is six times smaller; this allows the clock frequency to be redu ced by a factor of six.

The reduced clock frequency results in a significant reduction in power consumption.

Table 7. LC D frame freq uencies [1]

Power mode Frame freque ncy Nominal frame frequency (Hz)

Normal-pow er mo de 69 [2]

Power-savin g mo de 65 [3]

ffr fclk

2880

-------------

ffr fclk

480

----------

Product data sheet Rev. 13 — 16 December 2013 19 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The lower clock frequency has the disadvantage of increasing the response time when

large amounts of display data are transmitted on the I2C-bus. When a device is unable to

process a display data byte before the next one arrives, it holds the SCL line LOW until

the first display data byte is stored. This slows down the transmission rate of the I2C-bus

but no data loss occurs.

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.8 Shift register

The shift register transfers display information from the display RAM to the display reg ister

while previous data is displayed.

7.9 Segment outputs

The LCD drive section includes 40 segment outputs, S0 to S39, which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data residing in the display register. When less than

40 segment outputs are requir ed, the unused segment outputs should be left open-circuit.

7.10 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

•In 1:4 multiplex drive mode: BP0 to BP3 must be connecte d directly to the LCD.

If less than four backplane outputs are required, the unused outputs can be left as an

open-circuit.

•In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, there fore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

•In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry th e same

signals and can also be paired to increase the drive capabilities.

•In static drive mode: the same signal is carried by all four ba ckplane outpu t s and they

can be connected in parallel for very high drive requirements.

7.11 Display RAM

The display RAM is a static 40  4-bit RAM which stores LCD data.

There is a one-to-one correspondence between

•the bits in the RAM bitmap and the LCD elements

•the RAM columns and the se gm e nt outp u ts

•the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a log ic 0 indic at es th e off-state.

Product data sheet Rev. 13 — 16 December 2013 20 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The display RAM bit map Figure 13 shows the rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the

segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,

second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,

and BP3 respectively.

When display data is transmitted to the PCF8576C, the display bytes received are stored

in the display RAM in accordance with the selected LCD drive mode. The data is stored as

it arrives and does not wait for an acknowledge cycle as wi th the commands. Depending

on the current multiplex drive mode, data is stored singularly, in pairs, triples or

quadruples. To illustrate the filling order, an example of a 7-segment numeric display

showing all drive modes is given in Figure 14; the RAM filling organization depicted

applies equally to other LCD types.

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs; and between the bits in a RAM row and the backplane outputs.

Fig 13. Display RAM bit map

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Product data sheet Rev. 13 — 16 December 2013 21 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

x = data bit unchanged.

Fig 14. Relationsh ip between LCD layout, drive mode, display RAM filling order, and di splay data transmitted over the I2C-bus

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Product data sheet Rev. 13 — 16 December 2013 22 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The following applies to Figure 14:

•In the static drive mode, the eight transmitted data bits are placed in row 0 of eight

successive 4-bit RAM words.

•In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into

row 0 and 1 of fo ur succ es sive 4-bit RAM words.

•In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1, and 2 to

three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is

not recommended to use this bit in a display because of the difficult addressing. This

last bit may, if necessary, be controlled by an additional transfer to this address but

care should be t aken to avoid overwriting adjace nt data because al ways full bytes are

transmitted.

•In the 1:4 multiplex mode, the eight transmitted dat a bits are placed in quadrup les into

row 0, 1, 2, and 3 of two successive 4-bit RAM words.

7.12 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load-data-pointer command (see Table 11). After this, the data byte is

stored starting at the display RAM address indicated by the data pointer (see Figure 14).

Once each byte is stored, the data pointer is automatically incremented based on the

selected LCD configuration.

The contents of the data pointer are incremented as follows:

•In static drive mode by eight.

•In 1:2 multiplex drive mode by four.

•In 1:3 multiplex drive mode by three.

•In 1:4 multiplex drive mode by two.

If an I2C-bus data access terminate s ea rly, the state of the data pointer is unknown .

Consequently, the data pointer must be rewritten prior to further RAM accesses.

7.13 Sub-address counter

The storage of display data is conditioned by the contents of the subaddress counter.

Storage is allowed to take place only when the contents of the subaddress counter match

with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value

is defined by the de vice-select command (see Table 12). If the content s of the subaddress

counter and the hardware subaddress do not match, then data storage is blocked but the

data pointer will be incremented as if data storage had taken place. The subaddress

counter is also incremented when the data pointer overflows.

The storage arrange men ts described lead to extremely ef ficien t data loading in cascaded

applications. When a series of display bytes are sent to the display RAM, automatic

wrap-over to the next PCF8576C occurs when the last RAM address is exceeded.

Subaddressing across device boundaries is successful even if the change to the next

device in the cascade occurs within a transmitted character.

Product data sheet Rev. 13 — 16 December 2013 23 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.14 Bank selector

7.14.1 Output bank selector

The output bank selector (see Table 13), selects one of the four rows per display RAM

address for transfer to the display register. The actual row selected depends on the LCD

drive mode in operation and on the instant in the multiplex sequence.

•In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequen tially

by the contents of row 1, row 2, and then row 3.

•In 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially.

•In 1:2 multiplex mode: rows 0 an d 1 ar e se lect ed .

•In the static mode: row 0 is selected.

The PCF8576C includes a RAM bank switching feature in the static and 1:2 multiplex

drive modes. In the static drive mode, the bank-select command may request the contents

of row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive

mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This

enables preparation of display information in an alternative bank and the ability to switch

to it once it has been assem b led .

7.14.2 Input bank selector

The input bank selector (see Table 13) lo a ds display data into the display RAM ba se d on

the selected LCD drive configuration. Using the bank-select command, display data can

be loaded in row 2 into static drive mode or in rows 2 and 3 into 1:2 multiplex drive mode.

The input bank selector functions independently of the output bank selector.

7.15 Blinking

The display blinking capabilities of the PCF8576C are very versatile. The whole display

can be blinked at frequencies selected by the blink-select command. The blinking

frequencies are integer fractions of the clock frequency; the ratios between the clock and

blinking frequencies depend on the mode in which the device is operating (see Table 8).

An additional feature is for an arbitrary selection of LCD segments to be blinked. This

applies to the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. Usin g the output ban k selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blinking frequency. This mode can also be

specified by the blin k-select command (see Table 14).

Table 8. Blink frequencies

Blinking mode Normal-power mode

ratio Power-saving mode

ratio Blink frequency

off - - blinking off

12 Hz

21 Hz

30.5 Hz

fblink fclk

92160

----------------

fblink fclk

15360

----------------

fblink fclk

184320

--------------------

fblink fclk

30720

----------------

fblink fclk

368640

--------------------

fblink fclk

61440

----------------

Product data sheet Rev. 13 — 16 December 2013 24 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can be blinked by selectively changing the display RAM data at fixed time

intervals.

If the entire display must be blinked at a frequency other than the nominal blink frequency,

this can be done using th e mode-set command to set and reset th e display enable bit E at

the required rate (see Table 10).

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidire ctional, two-line communication between dif ferent ICs or modules.

The two lines are a Serial DAt a line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

7.16.1 Bit transfer

One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain

stable during the HIGH period of the clock pulse. Changes in the data line at this time will

be interpreted as a control signal. Bit transfer is illustrated in Figure 15.

7.16.2 START and STOP conditions

Both data an d clock lines remain HIGH when the bus is not b usy. A HIGH-to-LOW change

of the data line, while the clock is HIGH, is defined as the STAR T condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP

condition (P). The START and STOP conditions are illustrated in Figure 16.

Fig 15. Bit transfer

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Product data sheet Rev. 13 — 16 December 2013 25 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.16.3 System configuration

A device generating a message is a transmitter and a device receiving a message is the

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves. The system configuration is illustrated in

Figure 17.

7.16.4 Acknowledge

The number of data bytes tran sf er re d be tween the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

•A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

•A master receiver must generate an acknowledge after the rece ption of each byte that

has been clocke d ou t of th e sl av e tra n sm i tte r.

•The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

•A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter mus t leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is illustrated in Figure 18.

Fig 17. System configuration

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Product data sheet Rev. 13 — 16 December 2013 26 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.16.5 PCF8576C I2C-bus controller

The PCF8576C acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF8576 C are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, the transferred command data and the hardware subaddress.

In single device application, the hardware subaddress inputs A0, A1, and A2 are normally

tied to VSS which defines the hardware subaddress 0. In multiple device applications

A0, A1, and A 2 ar e tie d to VSS or VDD using a binary coding scheme so that no two

devices with a common I2C-bus slave address have the same hardware subaddress.

In the power-saving mode, it is possible that the PCF85 76C is not able to keep up with the

highest transmission rates when large amounts of display data are transmitted. If this

situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are

completed. This is known as the clock synchronization feature of the I2C-bus and serves

to slow down fast transmitters. Data loss does not occur.

7.16.6 Input filter

To enhance noise immunity in electrically adverse environments, RC low-pass filters are

provided on the SDA and SCL lines.

7.17 I2C-bus protocol

Two I2C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.

The least significant bit of the slave address that a PCF8576C responds to is defin ed by

the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on

the same I2C-bus which allows:

•Up to 16 PCF8576Cs on the same I2C-bus for very large LCD applications.

•The use of two types of LCD multiplexes on the same I2C-bus.

The I2C-bus protocol is shown in Figure 19. The sequence is initiated with a START

condition (S) from the I2C-bus master which is followed by one of the two PCF8576C

slave addresses available. All PCF8576Cs with the co rresponding SA0 level acknowledge

in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore

the whole I2C-bus transfer.

After ackn owledgement, one or more command bytes fo llow which define the statu s of the

addressed PCF8576Cs.

The last command byte is t agged with a cleared most significant bit, the continuation bit C.

The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.

After the last command byte, a series of display data bytes may follow. These display

bytes are stored in the display RAM at the address specified by the data pointer and the

subaddress counter. Both data p ointer and subaddre ss counter are auto matically updated

and the data is directed to the intended PCF8576C device. The acknowledgement after

each byte is made only by the (A0, A1, and A2) addressed PCF8576C. After the last

display byte, the I2C-bus master issues a STOP condition (P).

Product data sheet Rev. 13 — 16 December 2013 27 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.18 Command decoder

The command decoder identifies command bytes that arrive on the I2C-bus. All available

commands carry a continuation bit C in the most significant bit position as shown in

Figure 20. When this bit is set logic 1, it indicates that the next byte of the transfer to arrive

will also represent a command. If this bit is set logic 0, it indicates that the command byte

is the last in the transfer. Further bytes will be regarded as display data.

The five commands available to the PCF8576C are defined in Table 9.

Fig 19. I2C-bus protocol

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(1) C = 0; last command.

(2) C = 1; commands continue.

Fig 20. General format of the comman d byte

Table 9. Definition of PCF8576C commands

Command Operation Code Reference

Bit 7 6 5 4 3 2 1 0

mode-set C 1 0 LP E B M[1:0] Section 7.18.1

load-data-pointer C 0 P[5:0] Section 7.18.2

device-select C1100A[2:0] Section 7.18.3

bank-select C11110I OSection 7.18.4

blink-select C 1 1 1 0 AB BF[1:0] Section 7.18.5

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Product data sheet Rev. 13 — 16 December 2013 28 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.18.1 Mode-set command

[1] The possibility to disable the display allows implementation of blinking under external control.

[2] Bit B is not applicable for the static LCD drive mode.

7.18.2 Load-data-pointer command

7.18.3 Device-select command

Table 10. Mode-set command bit description

Bit Symbol Value Description

7C0, 1see Figure 20

6 to 5 - 10 fixed value

4LP power dissi pation (see Table 7)

0 normal-po wer mode

1 power-savin g mo de

3E display status

0 disabled[1]

1 enabled

2B LCD bias configuration[2]

01⁄3 bias

11⁄2 bias

1 to 0 M[1:0] LCD drive mode selection

01 static; BP0

10 1:2 multiplex; BP0, BP1

11 1:3 multiplex; BP0, BP1, BP2

00 1:4 multiplex; BP0, BP1, BP2, BP3

Table 11. Load-data-pointer command bit des cription

Bit Symbol Value Description

7C0, 1see Figure 20

6 - 0 fixed value

5 to 0 P[5:0] 000000 to

100111 6-bit binary value, 0 to 39; transferred to the data pointer to

define one of forty display RAM addresses

Table 12. Device-select comman d bit description

Bit Symbol Value Description

7C0, 1see Figure 20

6 to 4 - 1100 fixed value

3 to 0 A[2:0] 000 to 111 3-bit binary value, 0 to 7; transferred to the subaddress

counter to define one of eight hardware subaddresses

Product data sheet Rev. 13 — 16 December 2013 29 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

7.18.4 Bank-select command

[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.

7.18.5 Blink-select command

[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

7.19 Display controller

The display controller executes the commands identified by the command decoder. It

contains the status registers of the PCF8576C and coordinates their effects. The

controller is also responsible for loading display data into the display RAM as required by

the filling order.

Table 13. Bank-select command bit description

Bit Symbol Value Description

Static 1:2 multiplex[1]

7 C 0, 1 see Figure 20

6 to 2 - 11110 fixed value

1I input bank selection; storage of arriving display data

0 RAM bit 0 RAM bits 0 an d 1

1 RAM bit 2 RAM bits 2 an d 3

0O output bank sele c tion ; retrieval of LCD display data

0 RAM bit 0 RAM bits 0 an d 1

1 RAM bit 2 RAM bits 2 an d 3

Table 14. Blink-select command bit description

Bit Symbol Value Description

7C0, 1see Figure 20

6 to 3 - 1110 fixed value

2AB blink mode selection

0 normal bli nking[1]

1 alternate RAM bank blinking[2]

1 to 0 BF[1:0] blink frequency selection

00 off

01 1

10 2

11 3

Product data sheet Rev. 13 — 16 December 2013 30 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

8. Internal circuitry

9. Safety notes

Fig 21. Device protection diagram

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CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted

display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.

CAUTION

Semiconductors are light sensitive. Exposure to light sources can cause the IC to

malfunction. The IC must be protected against light. The protection must be applied to all

sides of the IC.

Product data sheet Rev. 13 — 16 December 2013 31 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

10. Limiting values

[1] Values with respect to VDD.

[2] Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114”.

[3] Pass level; Machine Model (MM), according to Ref. 9 “JESD22-A115”.

[4] Pass level; Charged-Device Model (CDM), according to Ref. 10 “JESD22-C101”.

[5] Pass level; latch-up testing according to Ref. 11 “JESD78” at maximum ambient temperature (Tamb(max)).

[6] According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored

at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.

Table 15. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +8.0 V

VLCD LCD supply voltage [1] VDD 8.0 VDD V

VIinput voltage on each of the pins SCL, SDA,

CLK, SYNC, SA0, OSC and

A0 to A2

0.5 +8.0 V

VOoutput voltage on each of the pins

S0 to S39 and BP0 to BP3 [1] 0.5 +8.0 V

IIinput current 20 +20 mA

IOoutput current 25 +25 mA

IDD supply current 50 +50 mA

ISS ground supply current 50 +50 mA

IDD(LCD) LCD supply current 50 +50 mA

Ptot total power dissipation - 400 mW

Pooutput power - 100 mW

VESD electrostatic discharge

voltage HBM [2] -4000 V

CDM [4]

PCF8576CHL

all pins - 500 V

corner pins - 1000 V

PCF8576CT

all pins - 500 V

corner pins - 750 V

Ilu latch-up current [5] - 150 mA

Tstg storage temperature [6] 65 +150 C

Tamb ambient temperature ope rating device 40 +85 C

Product data sheet Rev. 13 — 16 December 2013 32 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

11. Static characteristics

Table 16 . Static characteristics

VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD



2.0 V to VDD



6.0 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 2.0 - 6.0 V

VLCD LCD supply voltage [1] VDD  6.0 - V DD  2.0 V

IDD supply current: fclk = 200 kHz [2] --120A

IDD(lp) low-power mode supply

current VDD = 3.5 V; VLCD =0V; f

clk =35kHz;

A0, A1 and A2 connected to VSS

--60A

Logic

VIL LOW-level input voltage on pins CLK, SYNC, OSC,

A0 to A2 and SA0 VSS -0.3V

DD V

VIH HIGH-level input voltage on pins CLK, SYNC,OSC,

A0 to A2 and SA0 0.7VDD -V

DD V

VOL LOW-level output voltage IOL = 0 mA - - 0. 05 V

VOH HIGH-level output voltage IOH = 0 mA VDD  0.05 - - V

IOL LOW-level output current output sink current;

VOL =1.0V; V

DD =5.0V;

on pins CLK and SYNC

1--mA

ILleakage current VI=V

DD or VSS; on pins

CLK, SCL, SDA, A0 to A2 and SA0 1-+1A

IL(OSC) leakage current on pin OSC VI=V

DD 1-+1A

Ipd pull-down current VI= 1.0 V; VDD =5.0V;

on pins A0 to A2 and OSC 15 50 150 A

RSYNC_N SYNC resistance 20 50 150 k

VPOR power-on reset voltage [3] -1.01.6V

CIinput capacitance [4] --7pF

I2C-bus; pins SDA and SCL

VIL LOW-level input voltage VSS -0.3V

DD V

VIH HIGH-level input voltage 0.7VDD -6.0 V

IOH(CLK) HIGH-level output current on

pin CLK output source current;

VOH =4.0V; V

DD =5.0V 1--mA

IOL(SDA) LOW-level output current on

pin SDA output sink current;

VOL =0.4V; V

DD =5.0V 3--mA

Product data sheet Rev. 13 — 16 December 2013 33 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

[1] VLCD  VDD  3 V for 1⁄3 bias.

[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.

[3] Resets all logic when VDD < VPOR.

[4] Periodically sampled, not 100 % tested.

[5] Outputs measured one at a time.

11.1 Typical supply current characteristics

LCD outputs

VBP voltage on pin BP Cbpl = 35 nF; on pins BP0 to BP3 20 - +20 mV

VSvoltage on pin S Csgm = 5 nF; on pins S0 to S39 20 - +20 mV

RBP resistance on pin BP VLCD =V

DD 5 V; on pins BP0 to BP3 [5] --5k

RSresistance on pin S VLCD =V

DD 5 V; on pins S0 to S39 [5] --7.5k

Table 16 . Static characteristics …continued

VDD = 2.0 V to 6.0 V; VSS = 0 V; VLCD = VDD



2.0 V to VDD



6.0 V; Tamb =





C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VDD = 5 V; VLCD = 0 V; Tamb = 25 CV

DD = 5 V; VLCD = 0 V; Tamb = 25 C

Fig 22. ISS as a function of ffr Fig 23. IDD(LCD) as a function of ffr

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Product data sheet Rev. 13 — 16 December 2013 34 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

11.2 Typical LCD output characteristics

VLCD = 0 V; external clock; Tamb = 25 CV

LCD = 0 V; external clock; Tamb = 25 C

Fig 24. ISS as a function of VDD Fig 25. IDD(LCD) as a function of VDD

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Product data sheet Rev. 13 — 16 December 2013 35 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

12. Dynamic characteristics

[1] fclk < 125 kHz, I2C-bus maximum transmission speed is derated.

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 17. Dy namic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = VDD



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

6.0 V; Tamb =



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C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Timin g characteristics: driver timing waveforms (see Figure 28)

fclk clock frequency normal-power mode;

VDD = 5 V [1] 125 200 315 kHz

power-saving mode;

VDD =3 V 21 31 48 kHz

tclk(H) clock HIGH time 1 - - s

tclk(L) clock LOW time 1 - - s

tPD(SYNC_N) SYNC propagation delay - - 400 ns

tSYNC_NL SYNC LOW time 1 - - s

tPD(drv) driver propagation delay VLCD = 5 V --30s

Timin g characteristics: I2C-bus (see Figure 29)[2]

tBUF bus free time between a STOP and START

condition 4.7 - - s

tHD;STA hold time (repeated) START condition 4.0 - - s

tSU;STA set-up time for a repeate d START condition 4.7 - - s

tLOW LOW period of the SCL clock 4.7 - - s

tHIGH HIGH period of the SCL clock 4.0 - - s

trrise time of both SDA and SCL signals - - 1 s

tffall time of both SDA and SCL signals - - 0.3 s

Cbcapacitive load for each bus line - - 400 pF

tSU;DAT data set-up time 250 - - ns

tHD;DAT data hold time 0 - - ns

tSU;STO set-up time for STOP condition 4.0 - - s

Product data sheet Rev. 13 — 16 December 2013 36 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 28. Driver timing waveforms

Fig 29. I2C-bus timing waveforms

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Product data sheet Rev. 13 — 16 December 2013 37 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

13. Application information

13.1 Cascaded operation

In large display configurations, up to 16 PCF8576Cs can be recognized on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable

I2C-bus slave address (SA0).

Cascaded PCF8576Cs are synchronized. The y can share the backplane signals from one

of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of on ly one device must be through-plated to the

backplane electrodes of the display. The other PCF8576C of the cascade contribute

additional segment output s. The backplanes can either be co nnected together to enhan ce

the drive capability, some can be left open-circuit (as shown in Figure 30) or just some of

one and some of the other device can be taken to facilitate the layout of the display.

Table 18. Addressing cascaded PCF8576C

Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device

100000

0011

0102

0113

1004

1015

1106

1117

210008

0019

01010

01111

10012

10113

11014

11115

Product data sheet Rev. 13 — 16 December 2013 38 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8576Cs. This synch ro niz at i on is guara nt e ed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments; or by the defining a multiplex mode when PCF8576Cs

with differing SA0 levels are cascaded).

SYNC is organized as an input/output pin; the output selection being realized as an

open-drain driver with an internal pull-up resistor . A PCF8576C asserts the SYNC line and

monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is

restored by the first PCF8576C to assert SYNC. The timing relationship between the

backplane wave forms and the SYNC signal for the var ious drive modes o f the PCF857 6C

are shown in Figure 31.

Fig 30. Cascaded PCF8576C configuration

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Product data sheet Rev. 13 — 16 December 2013 39 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Excessive capacitive coupling between SCL or CLK and SYNC causes erroneous synchronization.

If this is a problem, you can increase the capacitance of the SYNC line (e.g. by an external

capacitor between SYNC and VDD.) Degradation of the positive edge of the SYNC pulse can be

countered by an external pull-up resistor.

Fig 31. Synchronization of the cascade for the various PCF8576C dr ive modes

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Product data sheet Rev. 13 — 16 December 2013 40 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 32. Single plane wiri ng of p ac kaged PCF8576CT

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Product data sheet Rev. 13 — 16 December 2013 41 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

14. Package outline

Fig 33. Package outline SOT314-2 (LQFP64) of PCF8576CHL/1

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Product data sheet Rev. 13 — 16 December 2013 42 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Fig 34. Package outline SOT190-1 (VSO56) of PCF8576CT/1

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Product data sheet Rev. 13 — 16 December 2013 43 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

15. Bare die outline

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Product data sheet Rev. 13 — 16 December 2013 44 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

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Product data sheet Rev. 13 — 16 December 2013 45 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Table 19. Pad and bump description for PCF8576CU

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip.

Symbol Pad X (m) Y (m) Description

SDA 1 74 1380 I2C-bus serial data input/output

SCL 2 148 1380 I2C-bus serial clock input

SYNC 3 355 1380 cascade synchronization input/output

CLK 4 534 1380 exte rnal clock input/output

VDD 5 742 1380 supply voltage

OSC 6 913 1380 internal oscillator enable input

A0 7 1087 1380 subaddress input

A1 8 1290 1284 subaddress input

A2 9 1290 1116 subaddress input

SA0 10 1290 945 subaddress input

VSS 11 1290 751 logic ground

VLCD 12 1290 485 LCD supply voltage

BP0 13 1290 125 LCD backplane output

BP2 14 1290 285 LCD backplane output

BP1 15 1290 458 LCD backplane output

BP3 16 1290 618 LCD backplane output

S0 17 1290 791 LCD segment output

S1 18 1290 951 LCD segment output

S2 19 1290 1124 LCD segment output

S3 20 1290 1284 LCD segment output

S4 21 1074 1380 LCD segment output

S5 22 914 1380 LCD segment output

S6 23 741 1380 LCD segment output

S7 24 581 1380 LCD segment output

S8 25 408 1380 LCD segment output

S9 26 248 1380 LCD segment output

S10 27 75 1380 LCD segment output

S11 28 85 1380 LCD segment output

S12 29 258 1380 LCD segment output

S13 30 418 1380 LCD segment output

S14 31 591 1380 LCD segment output

S15 32 751 1380 LCD segment output

S16 33 924 1380 LCD segment output

S17 34 1084 1380 LCD segmen t output

S18 35 1290 1243 LCD segmen t output

S19 36 1290 1083 LCD segmen t output

S20 37 1290 910 LCD segment output

S21 38 1290 750 LCD segment output

S22 39 1290 577 LCD segment output

Product data sheet Rev. 13 — 16 December 2013 46 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

S23 40 1290 417 LCD segment output

S24 41 1290 244 LCD segment output

S25 42 1290 84 LCD segment output

S26 43 1290 89 LCD segment output

S27 44 1290 249 LCD segment output

S28 45 1290 422 LCD segment output

S29 46 1290 582 LCD segment output

S30 47 1290 755 LCD segment output

S31 48 1290 915 LCD segment output

S32 49 1290 1088 LCD segment output

S33 50 1290 1248 LCD segment output

S34 51 1083 1380 LCD segment output

S35 52 923 1380 LCD segment output

S36 53 750 1380 LCD segment output

S37 54 590 1380 LCD segment output

S38 55 417 1380 LCD segment output

S39 56 257 1380 LCD segment output

Table 20. Alignment marks

Symbol X (m) Y (m)

C1 1290 1385

C2 1295 1385

F 1305 1405

Table 19. Pad and bump description for PCF8576CU

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip.

Symbol Pad X (m) Y (m) Description

Product data sheet Rev. 13 — 16 December 2013 47 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent

standards.

17. Packing information

17.1 Tray information

Tray information for the PCF8576CU/F1 and PCF8576CU/2/F2 is shown in Figure 37,

Figure 38 and Table 21.

Fig 37. Tray details

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Product data sheet Rev. 13 — 16 December 2013 48 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Table 21 . Description of tray details

Tray details are shown in Figure 37.

Tray details

Dimensions

ABCDEFGHJ KLMNOUnit

4.4 4.4 3.02 3.3 50.8 45.72 39.6 5.6 5.6 39.6 3.96 2.18 2.49 0.5 mm

Number of pockets

x direction y direction

10 10

Fig 38. Tray alignment

DDD

PDUNLQJFRGH

Product data sheet Rev. 13 — 16 December 2013 49 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 13 — 16 December 2013 50 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

18.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 39) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low en ough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 22 and 23

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 39.

Table 22. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Packag e reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 23. Lead-free pr ocess (from J-STD-020D)

Package thickness (mm) Packag e reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 13 — 16 December 2013 51 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 39. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

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Product data sheet Rev. 13 — 16 December 2013 52 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

19. Appendix

19.1 LCD segment driver selection

Table 24 . Selection of LCD segment drivers

Type name Numbe r of elements at MUX VDD (V) VLCD (V) ffr (Hz) VLCD (V)

charge

pump

VLCD (V)

temperature

compensat.

Tamb (C) Interface Package AEC-

Q100

1:1 1:2 1:3 1:4 1:6 1:8 1:9

PCA8561AHN[5] 18365472---1.8to5.51.8to5.532 to 256

[1] NN 40 to 105 I2CHVQFN32Y

PCA8561BHN[5] 18365472---1.8to5.51.8to5.532 to 256

[1] NN 40 to 105 SPI HVQFN32 Y

PCF8566TS 24487296---2.5to62.5to669 N N 40 to 85 I2C VSO40 N

PCF85162T 32 64 96 128 ---1.8to5.52.5to6.582 N N 40 to 85 I2CTSSOP48N

PCA85162T 326496128---1.8to5.52.5to8110 N N 40 to 95 I2CTSSOP48Y

PCA85262ATT326496128---1.8to5.52.5to8200 N N 40 to 105 I2CTSSOP48Y

PCF8551ATT[5] 3672108144---1.8to5.51.8to5.532 to 128

[1] NN 40 to 85 I2CTSSOP48N

PCF8551BTT[5] 3672108144---1.8to5.51.8to5.532 to 128

[1] NN 40 to 85 SPI TSSOP48 N

PCA8551ATT[5] 3672108144---1.8to5.51.8to5.532 to 256

[1] NN 40 to 105 I2CTSSOP48Y

PCA8551BTT[5] 3672108144---1.8to5.51.8to5.532 to 256

[1] NN 40 to 105 SPI TSSOP48 Y

PCF85176T 40 80 120 160 ---1.8to5.52.5to6.582 N N 40 to 85 I2CTSSOP56N

PCA85176T 4080120160---1.8to5.52.5to8110 N N 40 to 95 I2CTSSOP56Y

PCA85276ATT4080120160---1.8to5.52.5to8200 N N 40 to 105 I2CTSSOP56Y

PCF85176H 40 80 120 160 ---1.8to5.52.5to6.582 N N 40 to 85 I2CTQFP64N

PCA85176H 4080120160---1.8to5.52.5to882 N N 40 to 95 I2CTQFP64Y

PCF8553ATT[5] 4080120160---1.8to5.51.8to5.532 to 128

[1] NN 40 to 85 I2CTSSOP56N

PCF8553BTT[5] 4080120160---1.8to5.51.8to5.532 to 128

[1] NN 40 to 85 SPI TSSOP56 N

PCA8553ATT[5] 4080120160---1.8to5.51.8to5.532 to 256

[1] NN 40 to 105 I2CTSSOP56Y

PCA8553BTT[5] 4080120160---1.8to5.51.8to5.532 to 256

[1] NN 40 to 105 SPI TSSOP56 Y

PCA8546ATT ---176---1.8to5.52.5to960to300

[1] NN 40 to 95 I2CTSSOP56Y

PCA8546BTT ---176---1.8to5.52.5to960to300

[1] NN 40 to 95 SPI TSSOP56 Y

PCA8547AHT[5] 4488-176---1.8to5.52.5to960to300

[1] YY

[3] 40 to 95 I2CTQFP64Y

PCA8547BHT[5] 4488-176---1.8to5.52.5to960to300

[1] YY

[3] 40 to 95 SPI TQFP64 Y

PCF85134HL 60 120 180 240 ---1.8to5.52.5to6.582 N N 40 to 85 I2CLQFP80N

PCA85134H 60120180240---1.8to5.52.5to882 N N 40 to 95 I2CLQFP80Y

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Product data sheet Rev. 13 — 16 December 2013 53 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

[1] Can be selected by command.

[2] Can be selected by pin configuration.

PCA8543AHL 60120-240---2.5to5.52.5to960to300

[1] YY 40 to 105 I2CLQFP80Y

PCF8545ATT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] NN 40 to 85 I2CTSSOP56N

PCF8545BTT - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] NN 40 to 85 SPI TSSOP56 N

PCF8536AT[4] - - - 176 252 320 - 1.8to5.5 2.5to9 60to300

[1] NN 40 to 85 I2CTSSOP56N

PCF8536BT[4] - - - 176 252 320 - 1.8to5.5 2.5to9 60to300

[1] NN 40 to 85 SPI TSSOP56 N

PCA8536AT[4] - - - 176 252 320 - 1.8to5.5 2.5to9 60to300

[1] NN 40 to 95 I2CTSSOP56Y

PCA8536BT[4] - - - 176 252 320 - 1.8to5.5 2.5to9 60to300

[1] NN 40 to 95 SPI TSSOP56 Y

PCF8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY

[3] 40 to 85 I2CTQFP64N

PCF8537BH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY

[3] 40 to 85 SPI TQFP64 N

PCA8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY

[3] 40 to 95 I2CTQFP64Y

PCA8537BH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] YY

[3] 40 to 95 SPI TQFP64 Y

PCA9620H 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300[1] YY

[3] 40 to 105 I2CLQFP80Y

PCA9620U 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300[1] YY

[3] 40 to 105 I2C bare die Y

PCF8552DUG[5] 3672108144---1.8to5.51.8to5.532 to 128

[1] NN 40 to 85 I2C, SPI bare die N

PCA8552DUG[5] 3672108144---1.8to5.51.8to5.532 to 256

[1] NN 40 to 105 I2C, SPI bare die Y

PCF8576DU 4080120160---1.8to5.52.5to6.577 N N 40 to 85 I2C bare die N

PCF8576EUG 4080120160---1.8to5.52.5to6.577 N N 40 to 85 I2C bare die N

PCA8576FUG 4080120160---1.8to5.52.5to8200 N N 40 to 105 I2C bare die Y

PCF85133U 80 160 240 320 ---1.8to5.52.5to6.582, 110

[2] NN 40 to 85 I2C bare die N

PCA85133U 80160240320---1.8to5.52.5to882, 110

[2] NN 40 to 95 I2C bare die Y

PCA85233U 80160240320---1.8to5.52.5to8150, 220[2] NN 40 to 105 I2C bare die Y

PCA8530DUG[5] 102204-408---2.5to5.54to1245to300

[1] YY

[3] 40 to 105 I2C, SPI bare die Y

PCF85132U 160 320 480 640 ---1.8to5.51.8to860to90

[1] NN 40 to 85 I2C bare die N

PCA85132U 160320480640---1.8to5.51.8to860to90

[1] NN 40 to 95 I2C bare die Y

PCA85232U 160320480640---1.8to5.51.8to8117to176

[1] NN 40 to 95 I2C bare die Y

PCF8538UG 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300[1] YY

[3] 40 to 85 I2C, SPI[2] bare die N

PCA8538UG 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300[1] YY

[3] 40 to 105 I2C, SPI[2] bare die Y

Table 24 . Selection of LCD segment drivers …continue d

Type name Numbe r of elements at MUX VDD (V) VLCD (V) ffr (Hz) VLCD (V)

charge

pump

VLCD (V)

temperature

compensat.

Tamb (C) Interface Package AEC-

Q100

1:1 1:2 1:3 1:4 1:6 1:8 1:9

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Product data sheet Rev. 13 — 16 December 2013 54 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

[3] Extra feature: Temperature sensor.

[4] Extra feature: 6 PWM channels.

[5] In development.

Product data sheet Rev. 13 — 16 December 2013 55 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

20. Abbreviations

Table 25. Abbreviations

Acronym Description

CDM Charged-Device Model

DC Direct Current

HBM Huma n Body Model

I2C Inter-Integrated Circuit

IC Integrated Circuit

LCD Liquid Crystal Display

LSB Least Significant Bit

MM Machine Model

MOS Metal-Oxide Semiconductor

MSB Most Significant Bit

MSL Moisture Sensitivity Level

PCB Printed-Circuit Board

POR Power-On Reset

RC Resistance-Capacitance

RAM Random Access Memory

RMS Root Mean Square

SCL Serial CLock lin e

SDA Serial DAta line

SMD Surface-Mount Device

Product data sheet Rev. 13 — 16 December 2013 56 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

21. References

[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD

drivers

[2] AN10365 — Surface mount reflow soldering description

[3] AN10706 — Handling bare die

[4] AN1 1267 — EMC and system level ESD design guidelines for LCD drivers

[5] IEC 60 13 4 — Rating syst ems for electronic tubes and valves and analogous

semiconductor devices

[6] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[7] IPC/JEDEC J-STD-020D — Moisture/R eflow Sensitivity Classific ation for

Nonhermetic Solid State Surface Mount Devices

[8] JESD 22 -A114 — Electrostatic Discharge (ESD) Sensitivity Te sting Human Body

Model (HBM)

[9] JESD 22 -A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[10] JESD22-C101 — Field-Indu ced Charged-Device Mo del Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[11] JESD78 — IC Latch-Up Test

[12] UM10204 — I2C-bus specification and user manual

[13] UM10569 — Store and transport requirements

Product data sheet Rev. 13 — 16 December 2013 57 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

22. Revision history

Table 26. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF8576C v.13 20131216 Product data sheet - PCF8576C v.12

Modifications: •Changed product ordering information

•Enhanced the description of connecting segment and backplane outputs in a cascade

(Section 13)

PCF8576C v.12 20130716 Product data sheet - PCF8576C v.11

PCF8576C v.11 20120330 Product data sheet - PCF8576C v.10

PCF8576C v.10 20100722 Product data sheet - PCF8576C v.9

PCF8576C v.9 20090709 Product data sheet - PCF8576C v.8

PCF8576C v.8 20041122 Product specification - PCF8576C v.7

PCF8576C v.7 20011002 Product specification - PCF8576C v.6

PCF8576C v.6 19980730 Product specification - PCF8576C v.5

PCF8576C v.5 19971114 Product specification - PCF8576C v.4

PCF8576C v.4 19970402 Product specification - PCF8576C v.3

PCF8576C v.3 19970203 Product specification - PCF8576C v.2

PCF8576C v.2 19961209 Product specification - PCF8576C v.1

PCF8576C v.1 19950630 Product specification - -

Product data sheet Rev. 13 — 16 December 2013 58 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

23. Legal information

23.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

23.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond tho se described in the

Product data sheet.

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Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

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contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

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malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe propert y or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applicati ons or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

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NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 13 — 16 December 2013 59 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in au tomotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconductors’

standard warrant y and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English version s.

Bare die — All die are tested on compliance with their related tech nical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

All die sales are conditione d upon and sub ject to the custo mer enter ing into a

written die sale agreement with NXP Semiconductors through its legal

department.

23.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP B.V.

24. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 13 — 16 December 2013 60 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

25. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 5. Selection of possible display configurations. . . .8

Table 6. Biasing characteristics . . . . . . . . . . . . . . . . . . .10

Table 7. LCD frame frequencies [1] . . . . . . . . . . . . . . . .18

Table 8. Blink frequencies . . . . . . . . . . . . . . . . . . . . . . .23

Table 9. Definition of PCF8576C commands . . . . . . . . .27

Table 10. Mode-set command bit description . . . . . . . . .2 8

Table 11. Load-data-pointer command bit description . . .28

Table 12. Device-sele ct command bit description . . . . . .28

Table 13. Bank-se lect comman d bit description . . . . . . .29

Table 14. Bli nk-select command bit description . . . . . . . .29

Table 15. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 16. Static characteristics . . . . . . . . . . . . . . . . . . . .32

Table 17. Dynamic characteristics . . . . . . . . . . . . . . . . . .35

Table 18. Addressing cascaded PCF8576C . . . . . . . . . .3 7

Table 19. Pad and bump description for PCF8576CU . . .45

Table 20. Alignment marks. . . . . . . . . . . . . . . . . . . . . . . .46

Table 21. Description of tray details . . . . . . . . . . . . . . . . .48

Table 22. SnPb eutectic process (from J-STD-020D) . . .50

Table 23. Lead-free proce ss (from J-STD-020D) . . . . . .50

Table 24. Selection of LCD segment drivers . . . . . . . . . .52

Table 25. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 26. Revision history . . . . . . . . . . . . . . . . . . . . . . . .57

Product data sheet Rev. 13 — 16 December 2013 61 of 62

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

26. Figures

Fig 1. Block diagram of PCF8576C . . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for LQFP64 (PCF8576CHL/1) . .4

Fig 3. Pin configuration for VSO56 (PCF8576CT/1) . . . .5

Fig 4. Pin locations of PCF8576CU/F1 and

PCF8576CU/2/F2 . . . . . . . . . . . . . . . . . . . . . . . . .6

Fig 5. Example of displays suitable for PCF8576C . . . . .8

Fig 6. Typical system configuration . . . . . . . . . . . . . . . . .9

Fig 7. Electro-optical characteristic: relative

transmission curve of the liquid . . . . . . . . . . . . . .12

Fig 8. Static drive mode waveforms. . . . . . . . . . . . . . . .13

Fig 9. Waveforms for the 1:2 multi plex drive mode

with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 10. Waveforms for the 1:2 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Fig 11. Waveforms for the 1:3 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 12. Waveforms for the 1:4 multiplex mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 13. Display RAM bit map . . . . . . . . . . . . . . . . . . . . . .20

Fig 14. Relationship between LCD layout, drive mode,

display RAM filling order, and display data

transmitte d ove r th e I 2C-bus . . . . . . . . . . . . . . . .21

Fig 15. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 16. Definition of START and STOP conditions. . . . . .24

Fig 17. System configuration . . . . . . . . . . . . . . . . . . . . . .25

Fig 18. Acknowledgement of the I2C-bus . . . . . . . . . . . .25

Fig 19. I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 20. General format of the command byte . . . . . . . . .2 7

Fig 21. Device protection diag ram. . . . . . . . . . . . . . . . . .30

Fig 22. ISS as a function of ffr . . . . . . . . . . . . . . . . . . . . . .33

Fig 23. IDD(LCD) as a function of ffr . . . . . . . . . . . . . . . . . .33

Fig 24. ISS as a function of VDD . . . . . . . . . . . . . . . . . . . .34

Fig 25. IDD(LCD) as a function of VDD . . . . . . . . . . . . . . . .34

Fig 26. RO(max) as a function of VDD. . . . . . . . . . . . . . . . .34

Fig 27. RO(max) as a function of Tamb . . . . . . . . . . . . . . . .34

Fig 28. Driver timing waveforms . . . . . . . . . . . . . . . . . . .36

Fig 29. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .36

Fig 30. Cascaded PCF8576 C configura tio n . . . . . . . . . .38

Fig 31. Synchronization of the ca scade for the various

PCF8576C drive modes . . . . . . . . . . . . . . . . . . .39

Fig 32. Single plane wiring of packaged PCF8576CT. . .40

Fig 33. Package outline SOT314-2 (LQFP64) of

PCF8576CHL/1 . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 34. Package outline SOT190-1 (VSO56) of

PCF8576CT/1 . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Fig 35. Bare die outline of PCF8576CU/2/F2 . . . . . . . . .4 3

Fig 36. Bare die outline of PCF8576CU/F1. . . . . . . . . . .44

Fig 37. Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 38. Tray alignment. . . . . . . . . . . . . . . . . . . . . . . . . . .48

Fig 39. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

NXP Semiconductors PCF8576C

Universal LCD driver for low multiplex rates

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 16 December 2013

Document identifier: PCF8576C

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

27. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . . 8

7.1 Power-On-Reset (POR) . . . . . . . . . . . . . . . . . . 9

7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 9

7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9

7.3.1 Electro-optical performance . . . . . . . . . . . . . . 11

7.4 LCD drive mode waveforms. . . . . . . . . . . . . . 13

7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 13

7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 14

7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 16

7.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 17

7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.5.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.5.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 18

7.6 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.7 Display register. . . . . . . . . . . . . . . . . . . . . . . . 19

7.8 Shift register . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.9 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 19

7.10 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 19

7.11 Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.12 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.13 Sub-addre ss counter . . . . . . . . . . . . . . . . . . . 22

7.14 Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.14.1 Output bank selector . . . . . . . . . . . . . . . . . . . 23

7.14.2 Input bank selector. . . . . . . . . . . . . . . . . . . . . 23

7.15 Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.16 Characteristics of the I2C-bus. . . . . . . . . . . . . 24

7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.16.2 START and STOP conditions . . . . . . . . . . . . . 24

7.16.3 System configuration . . . . . . . . . . . . . . . . . . . 24

7.16.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.16.5 PCF8576C I2C-bus controller. . . . . . . . . . . . . 26

7.16.6 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.17 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 26

7.18 Command decoder. . . . . . . . . . . . . . . . . . . . . 27

7.18.1 Mode-set command . . . . . . . . . . . . . . . . . . . . 28

7.18.2 Load-data-pointer command. . . . . . . . . . . . . . 28

7.18.3 Device-select command. . . . . . . . . . . . . . . . . 28

7.18.4 Bank-select command . . . . . . . . . . . . . . . . . . 29

7.18.5 Blink-select command . . . . . . . . . . . . . . . . . . 29

7.19 Display controller . . . . . . . . . . . . . . . . . . . . . . 29

8 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 30

9 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31

11 Static characteristics . . . . . . . . . . . . . . . . . . . 32

11.1 Typical supply current characteristics . . . . . . 33

11.2 Typical LCD output characteristics. . . . . . . . . 34

12 Dynamic characteristics. . . . . . . . . . . . . . . . . 35

13 Application information . . . . . . . . . . . . . . . . . 37

13.1 Cascaded operation. . . . . . . . . . . . . . . . . . . . 37

14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 41

15 Bare die outline. . . . . . . . . . . . . . . . . . . . . . . . 43

16 Handling information . . . . . . . . . . . . . . . . . . . 47

17 Packing information . . . . . . . . . . . . . . . . . . . . 47

17.1 Tray information. . . . . . . . . . . . . . . . . . . . . . . 47

18 Soldering of SMD packages. . . . . . . . . . . . . . 49

18.1 Introduction to soldering . . . . . . . . . . . . . . . . . 49

18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 49

18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 49

18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 50

19 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

19.1 LCD segment driver selection . . . . . . . . . . . . 52

20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 55

21 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

22 Revision history . . . . . . . . . . . . . . . . . . . . . . . 57

23 Legal information . . . . . . . . . . . . . . . . . . . . . . 58

23.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 58

23.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

23.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 58

23.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 59

24 Contact information . . . . . . . . . . . . . . . . . . . . 59

25 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

26 Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

27 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

NXP:

PCF8576CT/1,112 PCF8576CT/1,118 PCF8576CTT/1,118 PCF8576CHL/1,157 PCF8576CHL/1,118

PCF8576CT/S480/1,1 PCF8576CU/F1,026 PCF8576CU/2/F2,026 PCF8576CT/1,518