LT4293 LTPoE++/IEEE 802.3bt PD Interface Controller FEATURES DESCRIPTION LTPoE++(R)/IEEE 802.3bt Powered Device (PD) Controller nn Supports Up to 90W PDs nn Distinguishes Between LTPoE++ and IEEE 802.3bt PSEs nn 5-Event Classification Sensing nn Superior Surge Protection (100V Absolute Maximum) nn Wide Junction Temperature Range (-40C to 125C) nn Overtemperature Protection nn Integrated Signature Resistor nn External Hot Swap N-Channel MOSFET for Lowest Power Dissipation and Highest System Efficiency nn Configurable Aux Power Support as Low as 9V nn Pin Compatible with LT4275A/B/C and LT4294 nn Available in 10-Lead MSOP and 3mm x 3mm DFN Packages The LT(R)4293 is an LTPoE++/IEEE 802.3af/at/bt-compliant powered device (PD) interface controller. The T2P output distinguishes between LTPoE++ and IEEE 802.3bt power sourcing equipment (PSE) during mutual identification and negotiation of available power. nn The LT4293 utilizes an external, low RDS(ON), N-channel, hot swap MOSFET and supports the LT4320/LT4321 ideal bridges, to extend the end-to-end power delivery efficiency and eliminate costly heat sinks. The LT4293 also includes a power good output, onboard signature resistor, undervoltage lockout, and thermal protection. Start-up inrush current is adjustable with an external capacitor. Auxiliary power override is supported as low as 9V with the AUX pin. The LT4293 can be configured to support all possible LTPoE++, 802.3bt, 802.3at and 802.3af power levels with external component changes. Pin-for-pin compatibility with the LT4275 and LT4294 family of PD Interface Controllers enables easy migration between LTPoE++ PDs and IEEE 802.3bt-compliant PDs. APPLICATIONS High Power Wireless Data Systems Outdoor Security Camera Equipment nn Commercial and Public Information Displays nn High Temperature Industrial Applications nn nn All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION LTPoE++/IEEE 802.3bt Single-Signature Powered Device Interface VAUX (9V TO 60V) DATA PAIR SPARE PAIR + ~ + ~ - ~ + ~ - CLASS CPORT PSMN040-100MSE VPORT CPD 0.1F 3.3k VIN 47nF VPORT HSGATE RCLASS RCLS++ RUN + VOUT - LT4293 RCLASS++ RCLS HSSRC PWRGD AUX ISOLATED POWER SUPPLY GND T2P OPTO PSE TYPE (TO P) SINGLE-SIGNATURE POWER CLASSIFICATION (AT PD INPUT) LTPoE++ IEEE 802.3bt 0 13W 13W 1 3.84W 3.84W 2 6.49W 6.49W 3 13W 13W 4 25.5W 25.5W 5 38.7W 40W 6 52.7W 51W 7 70W 62W 8 90W 71.3W 4293 TA01a Rev. 0 Document Feedback For more information www.analog.com 1 LT4293 ABSOLUTE MAXIMUM RATINGS (Notes 1, 3) VPORT, HSSRC Voltages.......................... -0.3V to 100V HSGATE Current.................................................. 20mA RCLASS, RCLASS++ Voltages........................... -0.3V to 8V (and VPORT) AUX Current......................................................... 1.4mA T2P, PWRGD Voltage................................ -0.3V to 100V T2P, PWRGD Current................................................5mA Operating Junction Temperature Range (Note 4) LT4293I.................................................-40C to 85C LT4293H............................................. -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec.)...................... 300C (MSOP Only) PIN CONFIGURATION TOP VIEW GND 1 AUX 2 RCLASS 3 RCLASS++ 4 GND 5 TOP VIEW 10 VPORT 11 GND GND AUX RCLASS RCLASS++ GND 9 HSGATE 8 HSSRC 7 PWRGD 6 T2P 1 2 3 4 5 10 9 8 7 6 VPORT HSGATE HSSRC PWRGD T2P MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150C, JC = 45C/W DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 150C, JC = 5C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND ORDER INFORMATION TUBE TAPE AND REEL PACKAGE DESCRIPTION TEMPERATURE RANGE LT4293IDD#PBF LT4293IDD#TRPBF PART MARKING* LHJX 10-Lead (3mm x 3mm) Plastic DFN -40C to 85C LT4293HDD#PBF LT4293HDD#TRPBF LHJX 10-Lead (3mm x 3mm) Plastic DFN -40C to 125C LT4293IMS#PBF LT4293IMS#TRPBF LTHJY 10-Lead Plastic MSOP -40C to 85C LT4293HMS#PBF LT4293HMS#TRPBF LTHJY 10-Lead Plastic MSOP -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPORT Operating Input Voltage At VPORT Pin l 60 V VSIG VPORT Signature Range At VPORT Pin l 1.5 10 V VCLASS VPORT Classification Range At VPORT Pin l 12.5 21 V VMARK VPORT Mark Range At VPORT Pin, Preceded by VCLASS l 5.6 10 V VPORT Aux Mode Range At VPORT Pin, AUX > VAUXT l 8 60 V l 1.0 Signature/Class Hysteresis Window 2 V Rev. 0 For more information www.analog.com LT4293 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) SYMBOL PARAMETER CONDITIONS VRESET Reset Threshold At VPORT Pin, Preceded by VCLASS MIN VHSON Hot Swap Turn-On Voltage l VHSOFF Hot Swap Turn-Off Voltage l 30 Hot Swap On/Off Hysteresis Window l 3 l TYP 2.6 35 MAX UNITS 5.6 V 37 V 31 V V Supply Current Supply Current VVPORT = VHSSRC = 57V Supply Current During Classification VVPORT = 17.5V, RCLASS and RCLASS++ Open l 0.4 Supply Current During Mark Event VVPORT = VMARK After 1st Classification Event l 0.5 Detection Signature Resistance VSIG (Note 2) l 23.7 Resistance During Mark Event RCLASS/RCLASS++ Operating Voltage VMARK (Note 2) l 5.8 -10mA IRCLASS -36mA, VCLASS l 1.32 Classification Signature Stability Time VVPORT Step to 17.5V, 34.8 from RCLASS or RCLASS++ to GND l 2 mA 0.9 mA 2.2 mA 24.4 25.2 k 8.3 11 k 1.40 1.43 l 0.7 Detection and Classification Signature 2 V ms Analog/Digital Interface VAUXT AUX Threshold l 6.1 6.3 IAUXH AUX Pin Hysteresis Current T2P Output Low 6.5 V VAUX = 6.1V l 3.2 5 1mA Load l 7 A 0.8 V PWRGD Output Low 1mA Load l 0.8 V PWRGD Leakage Current VPWRGD = 60V l 5 A T2P Leakage Current T2P = 60V l 5 A -18 A 18 V Hot Swap Control IGPU HSGATE Pull-Up Current VHSGATE - VHSSRC = 5V (Note 6) l -27 VGOC HSGATE Open Circuit Voltage -10A Load, with Respect to HSSRC l 10 HSGATE Pull-Down Current VHSGATE - VHSSRC = 5V l 200 l 690 -22 A Timing VAUX > VAUXT, and RCLASS++ Has Resistor to GND T2P Duty Cycle in PoE Operation (Note 5) After LTPoE++ 3-Event Classification After 4-Event Classification After 5-Event Classification (RCLASS++ Has Resistor to GND) T2P Duty Cycle in Auxiliary VAUX > VAUXT, and RCLASS++ Has Resistor to GND Supply Operation (Note 5) T2P Frequency 1st Classification Event Timing Threshold l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Signature resistance specifications do not include resistance added by the external diode bridge which can add as much as 1.1k to the port resistance. Note 3: All voltages with respect to GND unless otherwise noted. Positive currents are into pins; negative currents are out of pins unless otherwise noted. 31 840 990 Hz 75 50 25 % % % 75 % 87 ms Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: Specified as the percentage of the period which T2P is low impedance with respect to GND. Appears after PWRGD valid. Note 6: IGPU available in PoE powered operation. That is, available after VVPORT > VHSON and VAUX < VAUXT, over the range where VVPORT is between VHSOFF and 60V. Rev. 0 For more information www.analog.com 3 LT4293 TYPICAL PERFORMANCE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Signature Range VPORT VOLTAGE (V) 0.2 35 34 33 32 0.1 2 4 6 VPORT VOLTAGE (V) 30 -50 10 8 -25 0 25 50 75 TEMPERATURE (C) 4293 G01 0 125 35 40 24.75 24.25 1 3 5 7 VPORT VOLTAGE (V) 4.6 4.1 3.6 9 2.6 -50 -25 0 25 50 75 TEMPERATURE (C) T = -40C T = 25C T = 75C T = 125C 940 T2P FREQUENCY (Hz) VOLTAGE (V) VPORT VOLTAGE (V) 1 2 3 CURRENT (mA) 11.5 11.0 4 5 10.0 -50 890 840 790 740 -25 0 25 50 75 TEMPERATURE (C) 100 125 4293 G07 4293 G06 4 T2P Frequency DETECT OR MARK TO CLASS CLASS TO MARK 10.5 0 125 990 12.0 1 100 4293 G05 VPORT Classification Thresholds 12.5 2 0 60 3.1 PWRGD, T2P Output Low Voltage vs Current 3 55 4293 G03 4293 G04 4 45 50 VPORT VOLTAGE (V) 5.1 VPORT VOLTAGE (V) SIGNATURE RESISTANCE (k) 100 Reset Threshold 25.25 23.75 0.5 5.6 T = -40C T = 25C T = 75C T = 125C 25.75 1.0 4293 G02 Detection Signature Resistance vs Input Voltage 26.25 1.5 HOT SWAP OFF 31 0 T = -40C T = 25C T = 75C T = 125C HOT SWAP ON 36 0.3 0 Supply Current During Power-On 2.0 37 T = -40C T = 25C T = 75C T = 125C 0.4 VPORT CURRENT (mA) VPORT Hot Swap Thresholds SUPPLY CURRENT (mA) 0.5 690 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 4293 G08 Rev. 0 For more information www.analog.com LT4293 PIN FUNCTIONS GND (Pins 1, 5, DFN Exposed Pad Pin 11): Device Ground. Exposed pad must be electrically and thermally connected to pin 5 and PCB GND. AUX (Pin 2): Auxiliary Sense. A resistive divider from the auxiliary power input to AUX sets the voltage at which the auxiliary supply takes over. In auxiliary power operation, HSGATE pulls down, the signature resistor disconnects, classification is disabled, the PWRGD pin is high impedance and T2P indicates max available power. The AUX pin sinks IAUXH when below its threshold voltage of VAUXT to provide hysteresis. Connect to GND when not used. RCLASS (Pin 3): Configurable PoE Classification Resistor. See Table 2. RCLASS++ (Pin 4): Configurable PoE Classification Resistor. See Table 2. T2P (Pin 6): PSE Type Indicator, Open-Drain Output. See the T2P Output section in Applications Information for pin behavior. PWRGD (Pin 7): Power Good Indicator, Open-Drain Output. Pulls to GND during VCLASS and inrush. HSSRC (Pin 8): External Hot Swap MOSFET Source. Connect to source of the external MOSFET. HSGATE (Pin 9): External Hot Swap MOSFET Gate Control, Output. Connect to gate of the external MOSFET. VPORT (Pin 10): PD interface upper power rail and external Hot Swap MOSFET drain connection. Rev. 0 For more information www.analog.com 5 LT4293 BLOCK DIAGRAM VPORT VPORT VOLTAGE AND CURRENT REFERENCES PWRGD CONTROL LOGIC HSGATE CHARGE PUMP ON VGOC AUX ~6.5V 6.3V + - OVERTEMP VPORT 1.4V + EN - CLASSIFICATION LOGIC HSSRC T2P VPORT RCLASS EN + - 1.4V RCLASS++ GND 4293 BD 6 Rev. 0 For more information www.analog.com LT4293 APPLICATIONS INFORMATION OVERVIEW POWER ON The LT4293 is an LTPoE++/IEEE 802.3bt-compliant PD interface controller, and allows up to 90W operation while maintaining backwards compatibility with existing PSE systems. The T2P output distinguishes between LTPoE++ and IEEE 802.3bt power sourcing equipment (PSE) during mutual identification and negotiation of available power. The LT4293 controls a low RDS(ON) N-channel MOSFET to maximize efficiency and delivered power. Analog Devices also provides a complete family of PSE, PD and ideal bridge solutions. See Related Parts section at the end of this data sheet. VHSOFF 1ST CLASS VVPORT Power over Ethernet (PoE) continues to gain popularity as products take advantage of DC power and high speed data available from a single RJ45 connector. Powered device (PD) equipment vendors are running into the 25.5W power limit established by the IEEE 802.3at standard. VHSON VCLASSMIN VMARKMAX VRESET DETECT 1ST MARK VSIGMIN 4293 F01 Figure 1. Type 3 or 4 PSE, 1-Event Class Sequence standard references in this data sheet are limited in scope to single-signature PDs. The LT4293 may be deployed in dual-signature PD applications. For more information, contact Analog Devices Applications. MODES OF OPERATION Classification Signature and Mark Detection Signature The classification/mark process varies depending on the PSE type. A PSE, after a successful detection, may apply a classification probe voltage of 14.5V to 20.5V and measure the PD classification signature current. Once the PSE applies a classification probe voltage, the PSE returns the PD voltage to the mark voltage range before applying another classification probe voltage, or powering up the PD. During detection, the PSE looks for a 25k signature resistor which identifies the device as a PD. The PSE will apply two voltages in the range of 2.7V to 10.1V and measure the corresponding currents. Figure 1 shows the detection voltages. The PSE calculates the signature resistance using a V/I measurement technique. The LT4293 presents its precision, temperature-compensated 24.4k resistor between the VPORT and GND pins, allowing the PSE to recognize a PD is present and requesting power to be applied. The LT4293 signature resistor is smaller than 25k to compensate for the additional series resistance introduced by the IEEE required bridge or the LT4321-based ideal bridge. IEEE 802.3bt Single-Signature vs Dual-Signature PDs IEEE 802.3bt defines two PD topologies: single-signature and dual-signature. The LT4293 primarily targets singlesignature PD topologies, eliminating the need for a second PD controller. All PD descriptions and IEEE 802.3 An example of 1-Event classification is shown in Figure 1. In 2-Event classification, a PSE probes for power classification twice as shown in Figure 2. An IEEE 802.3bt PSE may apply as many as 5 events before powering up the PD. IEEE 802.3bt Physical Classification and Demotion IEEE 802.3bt defines physical classification to allow a PD to request a power allocation from the connected PSE and to allow the PSE to inform the PD of the PSE's available power. Demotion is provided if the PD Requested Power level is not available at the PSE. If demoted, the PD must operate in a lower power state. Rev. 0 For more information www.analog.com 7 LT4293 APPLICATIONS INFORMATION POWER ON VHSON VHSOFF VPORT 1ST CLASS 2ND CLASS IEEE 802.3bt provides nine PD classes and four PD types, as shown in Table 2. The LT4293 class is configured by setting the RCLS and RCLS++ resistor values. VCLASSMIN VMARKMAX DETECT VRESET 1ST MARK 2ND MARK VSIGMIN 4293 F02 Figure 2. Type 2 PSE, 2-Event Class Sequence POWER ON IEEE 802.3bt PSEs present a single classification event (see Figure 1) to Class 0 through 3 PDs. A Class 0 through 3 PD presents its class signature to the PSE and is then powered on if sufficient power is available. Power limited IEEE 802.3bt PSEs may issue a single event to Class 4 and higher PDs in order to demote those PDs to Class 3 (13W). Table 1. IEEE 802.3bt PSE Allocated Power VHSON PD REQUESTED CLASS VHSOFF 1ST CLASS 2ND CLASS 3RD CLASS VPORT The number of class/mark events issued by the PSE directly indicates the power allocated to the PD and is summarized in Table 1. VCLASSMIN VMARKMAX DETECT VRESET 1ST MARK 2ND MARK 3RD MARK VSIGMIN 4293 F03 Figure 3. Type 3 or 4 PSE, 3-Event Class Sequence NUMBER OF PSE CLASS/MARK EVENTS 1 2 3 4 0 13W 1 3.84W 2 6.49W 3 13W 4 13W 5 25.5W 5 13W 25.5W 40W 6 13W 25.5W 51W 7 13W 25.5W 51W 62W 8 13W 25.5W 51W 71.3W Note: Bold indicates the PD has been demoted. Table 2. LTPoE++/IEEE802.3bt Single-Signature Classification, Power Levels and Resistor Selection PD REQUESTED CLASS 0 1 2 3 4 LTPoE++ 38.7W or 5 LTPoE++ 52.7W or 6 LTPoE++ 70W or 7 LTPoE++ 90W or 8 8 PD REQUESTED POWER LTPoE++/IEEE802.3bt 13W 3.84W 6.49W 13W 25.5W 38.7W 40W 52.7W 51W 70W 62W 90W 71.3W PD TYPE LTPoE++/IEEE802.3bt Type 1 Type 1 or 3 Type 1 or 3 Type 1 or 3 Type 2 or 3 LTPoE++ or Type 3 LTPoE++ or Type 3 LTPoE++ or Type 4 LTPoE++ or Type 4 NOMINAL CLASS CURRENT 2.5mA 10.5mA 18.5mA 28mA 40mA 40mA/2.5mA 40mA/10.5mA 40mA/18.5mA 40mA/28mA RESISTOR (1%) RCLS RCLS++ 1.00k Open 140 Open 76.8 Open 49.9 Open 34.8 Open 1.00k 37.4 140 46.4 76.8 64.9 49.9 118 Rev. 0 For more information www.analog.com LT4293 APPLICATIONS INFORMATION IEEE 802.3bt PSEs present up to three classification events to Class 4 PDs (see Figure 3). Class 4 PDs present a class signature 4 on all events. The third event differentiates a Class 4 PD from a higher Class PD. Powerlimited IEEE 802.3bt PSEs may issue three events to Class 5 and higher PDs in order to demote those PDs to Class 4 (25.5W). IEEE 802.3bt PSEs present four classification events (see Figure 4) to Class 5 and 6 PDs. Class 5 and 6 PDs present a class signature 4 on the first two events, then present a class signature 0 or 1, respectively, on the remaining events. Power limited IEEE 802.3bt PSEs may issue four events to Class 7 and higher PDs in order to demote those PDs to Class 6 (51W). IEEE 802.3bt PSEs present five classification events (see Figure 5) to Class 7 and 8 PDs. Class 7 and 8 PDs present a class signature 4 on the first two events, then present a class signature 2 or 3, respectively, on the remaining events. POWER ON VHSON VPORT VHSOFF 1ST CLASS 2ND CLASS 3RD CLASS 4TH CLASS VCLASSMIN VMARKMAX 1ST MARK VRESET 2ND MARK 3RD MARK 4TH MARK VSIGMIN Both LTPoE++ and IEEE 802.3 PSEs may demote PDs to a lower power state when the PD Requested Power exceeds the PSE available power. In addition, a powerlimited LTPoE++ PSE may deny power to a PD requesting Class 6 or higher. When 2 or fewer class/mark events are received, PD allocated power is at or below 25.5W and LTPoE++ PSEs are considered equivalent to IEEE 802.3 PSEs, as shown in Table 5. Table 3. LTPoE++ PSE Allocated Power PD REQUESTED CLASS NUMBER OF PSE CLASS/MARK EVENTS 0 13W 1 3.84W 2 6.49W 3 13W 1 2 3 4 13W 5 13W 25.5W 38.7W 6 13W 25.5W 52.7W 7 13W 25.5W 70W 8 13W 25.5W 90W 25.5W Classification Resistors (RCLS and RCLS++) 4293 F04 Figure 4. Type 3 or 4 PSE, 4-Event Class Sequence POWER ON VHSON VPORT LTPoE++ Demotion and Denial Note: Bold indicates the PD has been demoted. DETECT VHSOFF The number of class/mark events is communicated through the LT4293 T2P pin. See T2P Output section for more details. 1ST CLASS 2ND CLASS 3RD CLASS 4TH CLASS The RCLS and RCLS++ resistors set the classification currents corresponding to the PD power classification. Select the value of RCLS and RCLS++ from Table 2 and connect each 1% resistor between the RCLASS, RCLASS++ pins and GND. Detection Signature Corrupt During Mark Event 5TH CLASS During the mark event, the LT4293 presents <11k to the port as required by the LTPoE++/IEEE 802.3 specifications. VCLASSMIN VMARKMAX DETECT VRESET VSIGMIN 1ST MARK 2ND MARK 3RD MARK 4TH MARK 5TH MARK 4293 F05 Figure 5. Type 4 PSE, 5-Event Class Sequence Inrush and Power On Once the PSE detects and classifies the PD, the PSE then powers on the PD. When the port voltage rises above the VHSON threshold, it begins to source IGPU out of the Rev. 0 For more information www.analog.com 9 LT4293 APPLICATIONS INFORMATION HSGATE pin. This current flows into an external capacitor, CGATE in Figure 6, that causes a voltage to ramp up the gate of the external MOSFET. The external MOSFET acts as a source follower and ramps the voltage up on the output bulk capacitor, CPORT, thereby determining the inrush current, IINRUSH. Design IINRUSH to be approximately ~100mA. See equation below: IINRUSH = I GPU * CPORT CGATE IINRUSH VPORT + 3.3k CPORT CGATE HSGATE VPORT Auxiliary Supply Override If the AUX pin is held above VAUXT, the LT4293 enters auxiliary power supply override mode. In this mode the signature resistor disconnects, classification is disabled, HSGATE pulls down, the PWRGD pin is open drain and T2P pin indicates max available power. The AUX pin allows for setting the auxiliary supply turn on and turn off voltage thresholds, VAUXON, and VAUXOFF respectively. The auxiliary supply hysteresis voltage, VAUXHYS, is generated with sinking current, IAUXH, and is active only when the AUX pin voltage is less than VAUXT. Use the following equations to set VAUXON and VAUXOFF via R1 and R2 in Figure 7. Note that an internal 6.5V Zener limits the voltage on the AUX pin. HSSRC R1= LT4293 GND R2 = 4293 F06 Figure 6. Configuring IINRUSH The LT4293 internal charge pump provides an N-channel MOSFET solution, eliminating a larger and more costly P-channel MOSFET. The low RDS(ON) MOSFET also maximizes power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. Power Good R1 VAUXON - VAUXOFF VAUXHYS + = IAUXH IAUXH R1 VAUXOFF - 1 VAUXT VAUX(MAX) - VAUXT 1.4mA LT4293 R1 VAUX AUX R2 GND - 4293 F07 Figure 7. AUX Threshold and Hysteresis Calculation A capacitor up to 1000pF may be placed between the AUX pin and GND to improve noise immunity. VAUXON must be lower than VHSOFF. The PWRGD pin is held low by its open drain output until HSGATE charges up to approximately 7V above HSSRC. The PWRGD pin is used to hold off the downstream circuitry until inrush is complete and the external MOSFET is fully enhanced. The HSGATE pin remains high and the PWRGD pin remains open-drain until the port voltage falls below VHSOFF. T2P Output Delay Start Table 4. T2P Response During Auxiliary Power Operation When the PSE powers up the port, the PD application should not draw more than 350mA for 80ms to comply with the IEEE 802.3 standard. 10 The LT4293 communicates the PSE allocated power to the PD application via the T2P pin. The T2P pin state is determined by the AUX pin, the RCLASS++ pin, and the number of classification events. The LT4293 uses a 5-state encoding for the T2P output. T2P state and the associated PSE allocated power are shown in Table 4 and Table 5. PD REQUESTED CLASS T2P* 0-4 Low-Z 5-8 75% *Specified as the percentage of the period which T2P is low impedance with respect to GND. Rev. 0 For more information www.analog.com LT4293 APPLICATIONS INFORMATION Table 5. T2P Response During PoE Operation POWER SOURCE VCC NUMBER OF CLASS/MARK EVENTS T2P* PSE ALLOCATED POWER 1 Hi-Z Min (PD Requested Power, 13W) 2 Low-Z 25.5W LTPoE++ IEEE 802.3 LT4293 VCC T2P GND 3 75% LTPoE++ PD Requested Power 1 Hi-Z Min (PD Requested Power, 13W) 2 or 3 Low-Z 25.5W 4 50% Min (PD Requested Power, 51W) 5 25% Min (PD Requested Power, 71.3W) *Specified as the percentage of the period which T2P is low impedance with respect to GND. The highest priority input is the AUX pin. AUX is asserted to enter the auxiliary power state and deasserted to enter the PoE state. In the auxiliary power state, the T2P pin indicates the highest available power, based on PD Requested Class. The auxiliary power supply must be sized to provide at least the PD Requested Class Power. Second, PD Requested Class and PD Requested Power are configured using the RCLASS and RCLASS++ pins. 25% Low-Z V(T2P) 75% Hi-Z GND TIME 4293 F08 Figure 8. Response Example for 25% Low-Z, 75% Hi-Z The RCLASS++ pin alone can be used to determine if the PD Class is 0-4, 5-8 or LTPoE++ as shown in Table 2. Last, the PSE type and the number of classification events determine the amount of power allocated by the PSE as described in Table 1 and Table 3. Interoperability Across Various PSEs and Auxiliary Power Source Table 6 summarizes the expected LT4293 T2P response, the PSE allocated power and the number of classification events. The result is a function of PD Requested Class and power source--Auxiliary or PoE. Table 6. LT4293 Interoperability (T2P Response*, Allocated Power, Number of Class/Mark Events) PSE TYPE, CLASS (POWER) IEEE 802.3 TYPE 1 IEEE 802.3 TYPE 2 IEEE 802.3 TYPE 3 IEEE 802.3 TYPE 4 REQUESTED PD CLASS (REQUESTED POWER) CLASS 3 (13W) CLASS 4 (25.5W) CLASS 4 (25.5W) CLASS 5 (40W) CLASS 6 (51W) CLASS 7 (62W) CLASS 8 (71.3W) (38.7W) (52.7W) (70W) (90W) AUXILIARY POWER SOURCE** CLASS 0-3 (Up to 13W) Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Hi-Z Up to 13W 1-Event Low-Z Aux. Power N/A CLASS 4 (25.5W) Hi-Z 13W 1-Event Low-Z 25.5W 2-Event Low-Z 25.5W 3-Event Low-Z 25.5W 3-Event Low-Z 25.5W 3-Event Low-Z 25.5W 3-Event Low-Z 25.5W 3-Event Low-Z 25.5W 2-Event Low-Z 25.5W 2-Event Low-Z 25.5W 2-Event Low-Z 25.5W 2-Event Low-Z Aux. Power N/A CLASS 5 (40W) Hi-Z 13W 1-Event Low-Z 25.5W 2-Event Low-Z 25.5W 3-Event 50% 40W 4-Event 50% 40W 4-Event 50% 40W 4-Event 50% 40W 4-Event 75% 38.7W 3-Event 75% 38.7W 3-Event 75% 38.7W 3-Event 75% 38.7W 3-Event 75% Aux. Power N/A CLASS 6 (51W) Hi-Z 13W 1-Event Low-Z 25.5W 2-Event Low-Z 25.5W 3-Event Low-Z 25.5W 3-Event 50% 51W 4-Event 50% 51W 4-Event 50% 51W 4-Event DENIED 75% 52.7W 3-Event 75% 52.7W 3-Event 75% 52.7W 3-Event 75% Aux. Power N/A CLASS 7 (62W) Hi-Z 13W 1-Event Low-Z 25.5W 2-Event Low-Z 25.5W 3-Event Low-Z 25.5W 3-Event 50% 51W 4-Event 25% 62W 5-Event 25% 62W 5-Event DENIED DENIED 75% 70W 3-Event 75% 70W 3-Event 75% Aux. Power N/A CLASS 8 (71.3W) Hi-Z 13W 1-Event Low-Z 25.5W 2-Event Low-Z 25.5W 3-Event Low-Z 25.5W 3-Event 50% 51W 4-Event 50% 51W 4-Event 25% 71.3W 5-Event DENIED DENIED DENIED 75% 90W 3-Event 75% Aux. Power N/A LTPoE++ T2P Response* PSE Allocated Power Number of Classification Events 75% 90W 3-Event Note 1. Shade of blue indicates the PD has been demoted or denied power. * Specified as the percentage of the period which T2P is low impedance with respect to GND. ** Auxiliary Power Supply must be sized to provide PD Requested Power. Rev. 0 For more information www.analog.com 11 LT4293 APPLICATIONS INFORMATION Overtemperature Protection The IEEE 802.3 specification requires a PD to withstand any applied voltage from 0V to 57V indefinitely. During classification, however, the power dissipation in the LT4293 may be as high as 1.5W. The LT4293 can easily tolerate this power for the maximum IEEE classification timing but overheats if this condition persists abnormally. The LT4293 includes an overtemperature protection feature which is intended to protect the device during momentary overload conditions. If the junction temperature exceeds the overtemperature threshold, the LT4293 pulls down HSGATE pin, and disables classification. EXTERNAL INTERFACE AND COMPONENT SELECTION PoE Input Bridge A PD is required to polarity-correct its input voltage. There are several different options available for bridge rectifiers; silicon diodes, Schottky diodes, and ideal diodes. When silicon or Schottky diode bridges are used, the diode forward voltage drops affect the voltage at the VPORT pin. The LT4293 is designed to tolerate these voltage drops. Note, the voltage parameters shown in the Electrical Characteristics are specified at the LT4293 package pins. For high efficiency applications, the LT4293 supports an LT4321-based PoE ideal diode bridge that reduces the forward voltage drop from 0.7V to 20mV per diode while maintaining IEEE 802.3 compliance. The LT4321 simplifies thermal design, eliminates costly heatsinks, and can operate in space-constrained applications. Auxiliary Input Bridge Some PDs are required to receive AC or DC power from an auxiliary power source. A diode bridge is typically required to handle the voltage rectification and polarity correction. In high efficiency applications, or in low auxiliary input voltage applications, the voltage drop across the rectifier cannot be tolerated. The LT4293 can be configured with an LT4320-based ideal diode bridge to recover the diode voltage drop and ease thermal design. For applications with auxiliary input voltages below 10V, the LT4293 must be configured with an LT4320based ideal diode bridge to recover the voltage drop and guarantee the minimum VPORT voltage is within the VPORT AUX Mode Range as specified in the Electrical Characteristics table. Input Capacitor A silicon diode bridge consumes up to 4% of the available power. In addition, silicon diode bridges exhibit poor pairset-to-pairset unbalance performance. Each branch of a silicon diode bridge shares source/return current, and thermal runaway can cause large, non-compliant current unbalances between pairsets. A 0.1F capacitor is needed from VPORT to GND to meet the input impedance requirement in IEEE 802.3 and to properly bypass the LT4293. When operating with the LT4321, locally bypass each with a 0.047F capacitor, thus keeping the total port capacitance within specification. While using Schottky diodes can help reduce the power loss with a lower forward voltage, the Schottky bridge may not be suitable for high temperature PD applications. Schottky diode bridges exhibit temperature induced leakage currents. The leakage current has a voltage dependency that can invalidate the measured detection signature. In addition, these leakage currents can back-feed through the unpowered branch and the unused bridge, violating IEEE 802.3 specifications. The LT4293 specifies an absolute maximum voltage of 100V and is designed to tolerate brief overvoltage events due to Ethernet cable surges. To protect the LT4293 from an overvoltage event, install a unidirectional transient voltage suppressor (TVS) such as an SMAJ58A between the VPORT and GND pins. For PD applications that require 12 Transient Voltage Suppressor Rev. 0 For more information www.analog.com LT4293 APPLICATIONS INFORMATION an auxiliary power input, install a TVS between VIN and GND. See Layout Considerations for TVS placement. For extremely high cable discharge and surge protection, contact Analog Devices Applications. Exposed Pad The LT4293 DFN package has an exposed pad that is internally connected to GND. The exposed pad may only be connected to GND on the printed circuit board. LAYOUT CONSIDERATIONS Avoid excessive parasitic capacitance on the RCLASS and RCLASS++ pins and place resistors RCLS and RCLS++ close to the LT4293. It is strictly required for maximum protection to place the 0.1F input capacitor, CPD, and transient voltage suppressor as close to the LT4293 as possible. When operating the LT4293 with the LT4321, place a 0.047F capacitor, CPD1, as close as possible to the LT4293 VPORT and GND pins (pin 10 and pin 5, respectively), and a 0.047F capacitor, CPD2, as close as possible to the LT4321 OUTP and OUTN pins. TYPICAL APPLICATIONS LTPoE++/IEEE 802.3bt-Compliant > 99% Efficient 51W Powered Device PSMN075-100MSE x4 PSE TYPE (TO P) OPTO PSMN040-100MSE 1 CPD1 0.047F DATA PAIRS 2 TG12 BG12 BG36 TG36 3 6 IN36 EN LT4321 IN45 + HSGATE HSSRC T2P AUX EN IN12 CPD2 0.047F LT4293 IN78 22F 100k RCLASS++ PWRGD VIN 3.3k 47nF RCLASS GND 4 SPARE PAIRS SMAJ58A OUTP VPORT 4293 TA03 RCLS 140 RCLS++ 46.4 ISOLATED POWER SUPPLY + VOUT - RUN GND OUTN 5 BG78 TG78 7 TG45 BG45 8 WURTH 749022016 PSE TYPE T2P RESPONSE ALLOCATED POWER IEEE 802.3at 25.5W LOW-Z TO GND 25.5W IEEE 802.3bt 51W OR HIGHER POWER 50% LOW-Z 51W LTPoE++ 52.7W OR HIGHER POWER 75% LOW-Z 52.7W PSMN075-100MSE x4 Rev. 0 For more information www.analog.com 13 LT4293 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 0.05 3.55 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (4 SIDES) R = 0.125 TYP 6 0.40 0.10 10 1.65 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 5 0.75 0.05 0.00 - 0.05 1 (DD) DFN REV C 0310 0.25 0.05 0.50 BSC 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 14 Rev. 0 For more information www.analog.com LT4293 PACKAGE DESCRIPTION MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev F) 0.889 0.127 (.035 .005) 5.10 (.201) MIN 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) DETAIL "A" 0.497 0.076 (.0196 .003) REF 0 - 6 TYP GAUGE PLANE 1 2 3 4 5 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 - 0.27 (.007 - .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.1016 0.0508 (.004 .002) MSOP (MS) 0213 REV F Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 15 LT4293 TYPICAL APPLICATION LTPoE++/IEEE 802.3bt > 99% Efficient 71.3W Powered Device PSMN075-100MSE x4 PSE TYPE (TO P) OPTO PSMN040-100MSE 1 CPD1 0.047F DATA PAIRS 2 TG12 BG12 BG36 TG36 3 SMAJ58A OUTP VPORT IN36 EN LT4321 CPD2 0.047F T2P LT4293 PWRGD IN45 IN78 VIN 100k 47nF RCLASS 4293 TA02 22F 3.3k RCLASS++ GND 4 SPARE PAIRS HSSRC AUX EN IN12 6 + HSGATE RCLS 49.9 RCLS++ 118 ISOLATED POWER SUPPLY + VOUT - RUN GND OUTN 5 BG78 TG78 7 TG45 BG45 8 WURTH 749022016 PSMN075-100MSE x4 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT4295 IEEE 802.3bt PD with Forward/Flyback Switching Regulator Controller External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation LT4294 IEEE 802.3bt PD Controller External Switch, IEEE 802.3bt and Aux Support LT4321 PoE Ideal Diode Bridge Controller Controls 8-NMOSFETs for IEEE-Required PD Voltage Rectification without Diode Drops LT4320/LT4320-1 Ideal Diode Bridge Controller 9V to 72V, DC to 600Hz Input. Controls 4-NMOSFETs, Voltage Rectification without Diode Drops LTC4292/LTC4291-1 4-Port IEEE 802.3bt PSE Controller Transformer Isolation, Supports IEEE 802.3bt PDs LTC4279 Single PoE/PoE+/LTPoE++ PSE Controller Supports IEEE 802.3af, IEEE 802.3at, LTPoE++ and Proprietary PDs LT4276A/B/C LTPoE++/PoE+/PoE PD with Forward/ Flyback Switching Regulator Controller External Switch, LTPoE++ Support, User-Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation LT4275A/B/C LTPoE++/PoE+/PoE PD Controller External Switch, LTPoE++ Support LTC4269-1 IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz Forward Switching Regulator to 500kHz, Aux Support LTC4278 IEEE 802.3at PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, 12V Aux Support LTC4267/LTC4267-1/ IEEE 802.3af PD Interface with Integrated Internal 100V, 400mA Switch, Programmable Class, 200kHz/300kHz Constant LTC4267-3 Switching Regulator Frequency PWM LTC4290/LTC4271 16 8-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs Rev. 0 05/19 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2019