LT4293HDD#PBF - ANALOG DEVICES

LT4293

Rev. 0

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TYPICAL APPLICATION

FEATURES DESCRIPTION

LTPoE++/IEEE 802.3bt

PD Interface Controller

The LT

4293 is an LTPoE++/IEEE 802.3af/at/bt-compliant

powered device (PD) interface controller. The T2P output

distinguishes between LTPoE++ and IEEE 802.3bt power

sourcing equipment (PSE) during mutual identification

and negotiation of available power.

The LT4293 utilizes an external, low RDS(ON), N-channel,

hot swap MOSFET and supports the LT4320/LT4321 ideal

bridges, to extend the end-to-end power delivery effi-

ciency and eliminate costly heat sinks. The LT4293 also

includes a power good output, onboard signature resistor,

undervoltage lockout, and thermal protection. Start-up

inrush current is adjustable with an external capacitor.

Auxiliary power override is supported as low as 9V with

the AUX pin.

The LT4293 can be configured to support all possible

LTPoE++, 802.3bt, 802.3at and 802.3af power levels

with external component changes. Pin-for-pin compat-

ibility with the LT4275 and LT4294 family of PD Interface

Controllers enables easy migration between LTPoE++ PDs

and IEEE 802.3bt-compliant PDs.

LTPoE++/IEEE 802.3bt Single-Signature Powered Device Interface

APPLICATIONS

n LTPoE++

/IEEE 802.3bt Powered Device (PD)

Controller

n Supports Up to 90W PDs

n Distinguishes Between LTPoE++ and IEEE 802.3bt PSEs

n 5-Event Classification Sensing

n Superior Surge Protection (100V Absolute Maximum)

n Wide Junction Temperature Range

(–40°Cto125°C)

n Overtemperature Protection

n Integrated Signature Resistor

n External Hot Swap N-Channel MOSFET for Lowest

Power Dissipation and Highest System Efficiency

n Configurable Aux Power Support as Low as 9V

n Pin Compatible with LT4275A/B/C and LT4294

n Available in 10-Lead MSOP and 3mm × 3mm

DFNPackages

n High Power Wireless Data Systems

n Outdoor Security Camera Equipment

n Commercial and Public Information Displays

n High Temperature Industrial Applications

CLASS

SINGLE-SIGNATURE

POWER CLASSIFICATION

(AT PD INPUT)

LTPoE++ IEEE 802.3bt

0 13W 13W

1 3.84W 3.84W

2 6.49W 6.49W

3 13W 13W

4 25.5W 25.5W

5 38.7W 40W

6 52.7W 51W

7 70W 62W

8 90W 71.3W

LT4293

VPORT HSGATE

GND

4293 TA01a

HSSRC

AUX

RCLASS

RCLASS++

RCLS++

PWRGD

T2P

RCLS

CPD

0.1µF

VPORT

DATA

PAIR

SPARE

PAIR

RUN

47nF

3.3k

PSMN040-100MSE

VIN

VOUT

–

ISOLATED

POWER

SUPPLY

OPTO PSE TYPE

(TO µP)

–

CPORT

VAUX (9V TO 60V)

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Rev. 0

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ORDER INFORMATION

ABSOLUTE MAXIMUM RATINGS

VPORT, HSSRC Voltages ......................... –0.3V to 100V

HSGATE Current.................................................. ±20mA

RCLASS, RCLASS++

Voltages .......................... –0.3V to 8V (and ≤ VPORT)

AUX Current ........................................................ ±1.4mA

T2P, PWRGD Voltage ............................... –0.3V to 100V

T2P, PWRGD Current ...............................................5mA

(Notes 1, 3)

TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT4293IDD#PBF LT4293IDD#TRPBF LHJX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LT4293HDD#PBF LT4293HDD#TRPBF LHJX 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT4293IMS#PBF LT4293IMS#TRPBF LTHJY 10-Lead Plastic MSOP –40°C to 85°C

LT4293HMS#PBF LT4293HMS#TRPBF LTHJY 10-Lead Plastic MSOP –40°C to 125°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

TOP VIEW

GND

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

TJMAX = 150°C, θJC = 5°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND

1VPORT

HSGATE

HSSRC

PWRGD

T2P

GND

AUX

RCLASS

RCLASS++

GND

AUX

RCLASS

RCLASS++

GND

VPORT

HSGATE

HSSRC

PWRGD

T2P

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 150°C, θJC = 45°C/W

PIN CONFIGURATION

Operating Junction Temperature Range (Note 4)

LT4293I ................................................–40°C to 85°C

LT4293H ............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature

(Soldering, 10 sec.) ..................... 300°C (MSOP Only)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VPORT Operating Input Voltage At VPORT Pin l60 V

VSIG VPORT Signature Range At VPORT Pin l1.5 10 V

VCLASS VPORT Classification Range At VPORT Pin l12.5 21 V

VMARK VPORT Mark Range At VPORT Pin, Preceded by VCLASS l5.6 10 V

VPORT Aux Mode Range At VPORT Pin, AUX > VAUXT l8 60 V

Signature/Class Hysteresis Window l1.0 V

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

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ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VRESET Reset Threshold At VPORT Pin, Preceded by VCLASS l2.6 5.6 V

VHSON Hot Swap Turn-On Voltage l35 37 V

VHSOFF Hot Swap Turn-Off Voltage l30 31 V

Hot Swap On/Off Hysteresis Window l3 V

Supply Current

Supply Current VVPORT = VHSSRC = 57V l2 mA

Supply Current During Classification VVPORT = 17.5V, RCLASS and RCLASS++ Open l0.4 0.7 0.9 mA

Supply Current During Mark Event VVPORT = VMARK After 1st Classification Event l0.5 2.2 mA

Detection and Classification Signature

Detection Signature Resistance VSIG (Note 2) l23.7 24.4 25.2 kΩ

Resistance During Mark Event VMARK (Note 2) l5.8 8.3 11 kΩ

RCLASS/RCLASS++ Operating Voltage –10mA ≥ IRCLASS ≥ –36mA, VCLASS l1.32 1.40 1.43 V

Classification Signature Stability Time VVPORT Step to 17.5V,

34.8Ω from RCLASS or RCLASS++ to GND

l2 ms

Analog/Digital Interface

VAUXT AUX Threshold l6.1 6.3 6.5 V

IAUXH AUX Pin Hysteresis Current VAUX = 6.1V l3.2 5 7 µA

T2P Output Low 1mA Load l0.8 V

PWRGD Output Low 1mA Load l0.8 V

PWRGD Leakage Current VPWRGD = 60V l5 µA

T2P Leakage Current T2P = 60V l5 µA

Hot Swap Control

IGPU HSGATE Pull-Up Current VHSGATE – VHSSRC = 5V (Note 6) l–27 –22 –18 µA

VGOC HSGATE Open Circuit Voltage –10µA Load, with Respect to HSSRC l10 18 V

HSGATE Pull-Down Current VHSGATE – VHSSRC = 5V l200 µA

Timing

T2P Frequency VAUX > VAUXT, and RCLASS++ Has Resistor to GND l690 840 990 Hz

T2P Duty Cycle in PoE Operation (Note 5) After LTPoE++ 3-Event Classification

After 4-Event Classification

After 5-Event Classification

(RCLASS++ Has Resistor to GND)

T2P Duty Cycle in Auxiliary

Supply Operation (Note 5)

VAUX > VAUXT, and RCLASS++ Has Resistor to GND 75 %

1st Classification Event Timing

Threshold

l31 87 ms

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Signature resistance specifications do not include resistance

added by the external diode bridge which can add as much as 1.1k to the

port resistance.

Note 3: All voltages with respect to GND unless otherwise noted.

Positive currents are into pins; negative currents are out of pins unless

otherwisenoted.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: Specified as the percentage of the period which T2P is low

impedance with respect to GND. Appears after PWRGD valid.

Note 6: IGPU available in PoE powered operation. That is, available after

VVPORT > VHSON and VAUX < VAUXT, over the range where VVPORT is

between VHSOFF and 60V.

LT4293

Rev. 0

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TYPICAL PERFORMANCE CHARACTERISTICS

Detection Signature Resistance

vs Input Voltage Reset Threshold

PWRGD, T2P Output Low

Voltage vs Current VPORT Classification Thresholds T2P Frequency

Input Current vs Input Voltage 25k

Detection Signature Range

VPORT Hot Swap Thresholds Supply Current During Power-On

VPORT VOLTAGE (V)

VPORT CURRENT (mA)

0.2

0.3

0.4

0.5

0.1

4293 G01

1062 4

T = –40°C

T = 25°C

T = 75°C

T = 125°C

TEMPERATURE (°C)

–50

VPORT VOLTAGE (V)

30 100

4293 G02

12575–25 50250

HOT SWAP OFF

HOT SWAP ON

VPORT VOLTAGE (V)

SUPPLY CURRENT (mA)

1.0

1.5

2.0

0.5

055

4293 G03

605040 45

T = –40°C

T = 25°C

T = 75°C

T = 125°C

VPORT VOLTAGE (V)

SIGNATURE RESISTANCE (kΩ)

25.25

25.75

26.25

24.75

24.25

23.75

4293 G04

973 5

T = –40°C

T = 25°C

T = 75°C

T = 125°C

TEMPERATURE (°C)

–50

VPORT VOLTAGE (V)

3.6

4.1

5.1

4.6

5.6

3.1

2.6 100

4293 G05

12575–25 50250

CURRENT (mA)

VOLTAGE (V)

4293 G06

531 2

T = –40°C

T = 25°C

T = 75°C

T = 125°C

TEMPERATURE (°C)

–50

VPORT VOLTAGE (V)

11.0

11.5

12.0

12.5

10.5

10.0 100

4293 G07

12575–25 50250

DETECT OR MARK TO CLASS

CLASS TO MARK

TEMPERATURE (°C)

–50

T2P FREQUENCY (Hz)

840

740

890

940

990

790

690 100

4293 G08

12575–25 50250

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PIN FUNCTIONS

GND (Pins 1, 5, DFN Exposed Pad Pin 11): Device

Ground. Exposed pad must be electrically and thermally

connected to pin 5 and PCB GND.

AUX (Pin 2): Auxiliary Sense. A resistive divider from the

auxiliary power input to AUX sets the voltage at which the

auxiliary supply takes over. In auxiliary power operation,

HSGATE pulls down, the signature resistor disconnects,

classification is disabled, the PWRGD pin is high imped-

ance and T2P indicates max available power. The AUX pin

sinks IAUXH when below its threshold voltage of VAUXT to

provide hysteresis. Connect to GND when not used.

RCLASS (Pin 3): Configurable PoE Classification Resistor.

See Table2.

RCLASS++ (Pin 4): Configurable PoE Classification

Resistor. See Table2.

T2P (Pin 6): PSE Type Indicator, Open-Drain Output. See

the T2P Output section in Applications Information for

pin behavior.

PWRGD (Pin 7): Power Good Indicator, Open-Drain

Output. Pulls to GND during VCLASS and inrush.

HSSRC (Pin 8): External Hot Swap MOSFET Source.

Connect to source of the external MOSFET.

HSGATE (Pin 9): External Hot Swap MOSFET Gate Control,

Output. Connect to gate of the external MOSFET.

VPORT (Pin 10): PD interface upper power rail and exter-

nal Hot Swap MOSFET drain connection.

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BLOCK DIAGRAM

4293 BD

CONTROL

LOGIC

CLASSIFICATION

LOGIC

VOLTAGE AND

CURRENT REFERENCES

CHARGE

PUMP

OVERTEMP

GND

VPORT VPORT

VGOC

6.3V

~6.5V

1.4V 1.4V

–

–EN

–

VPORT

AUX

RCLASS RCLASS++

T2P

HSSRC

HSGATE

PWRGD

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APPLICATIONS INFORMATION

OVERVIEW

Power over Ethernet (PoE) continues to gain popularity

as products take advantage of DC power and high speed

data available from a single RJ45 connector. Powered

device(PD) equipment vendors are running into the 25.5W

power limit established by the IEEE 802.3at standard.

The LT4293 is an LTPoE++/IEEE 802.3bt-compliant PD

interface controller, and allows up to 90W operation while

maintaining backwards compatibility with existing PSE

systems. The T2P output distinguishes between LTPoE++

and IEEE 802.3bt power sourcing equipment (PSE) during

mutual identification and negotiation of available power.

The LT4293 controls a low RDS(ON) N-channel MOSFET

to maximize efficiency and deliveredpower.

Analog Devices also provides a complete family of PSE,

PD and ideal bridge solutions. See Related Parts section

at the end of this data sheet.

MODES OF OPERATION

Detection Signature

During detection, the PSE looks for a 25k signature resis-

tor which identifies the device as a PD. The PSE will apply

two voltages in the range of 2.7V to 10.1V and measure

the corresponding currents. Figure1 shows the detec-

tion voltages. The PSE calculates the signature resistance

using a ∆V/∆I measurement technique.

The LT4293 presents its precision, temperature-compen-

sated 24.4k resistor between the VPORT and GND pins,

allowing the PSE to recognize a PD is present and request-

ing power to be applied. The LT4293 signature resistor is

smaller than 25k to compensate for the additional series

resistance introduced by the IEEE required bridge or the

LT4321-based ideal bridge.

IEEE 802.3bt Single-Signature vs Dual-Signature PDs

IEEE 802.3bt defines two PD topologies: single-signature

and dual-signature. The LT4293 primarily targets single-

signature PD topologies, eliminating the need for a sec-

ond PD controller. All PD descriptions and IEEE 802.3

Figure1. Type 3 or 4 PSE, 1-Event Class Sequence

standard references in this data sheet are limited in scope

to single-signature PDs.

The LT4293 may be deployed in dual-signature PD appli-

cations. For more information, contact Analog Devices

Applications.

Classification Signature and Mark

The classification/mark process varies depending on the

PSE type. A PSE, after a successful detection, may apply

a classification probe voltage of 14.5V to 20.5V and mea-

sure the PD classification signature current. Once the PSE

applies a classification probe voltage, the PSE returns

the PD voltage to the mark voltage range before apply-

ing another classification probe voltage, or powering up

thePD.

An example of 1-Event classification is shown in Figure1.

In 2-Event classification, a PSE probes for power clas-

sification twice as shown in Figure2. An IEEE 802.3bt

PSE may apply as many as 5 events before powering up

the PD.

IEEE 802.3bt Physical Classification and Demotion

IEEE 802.3bt defines physical classification to allow a PD

to request a power allocation from the connected PSE and

to allow the PSE to inform the PD of the PSE’s available

power. Demotion is provided if the PD Requested Power

level is not available at the PSE. If demoted, the PD must

operate in a lower power state.

4293 F01

VPORT

VHSON

VHSOFF

VCLASSMIN

VMARKMAX

VSIGMIN

VRESET

DETECT

1ST MARK

1ST CLASS

POWER ON

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Figure2. Type 2 PSE, 2-Event Class Sequence

APPLICATIONS INFORMATION

Table2. LTPoE++/IEEE802.3bt Single-Signature Classification, Power Levels and Resistor Selection

PD REQUESTED CLASS

PD REQUESTED POWER

LTPoE++/IEEE802.3bt

PD TYPE

LTPoE++/IEEE802.3bt NOMINAL CLASS CURRENT

RESISTOR (1%)

RCLS RCLS++

0 13W Type 1 2.5mA 1.00kΩ Open

1 3.84W Type 1 or 3 10.5mA 140Ω Open

2 6.49W Type 1 or 3 18.5mA 76.8Ω Open

3 13W Type 1 or 3 28mA 49.9Ω Open

4 25.5W Type 2 or 3 40mA 34.8Ω Open

LTPoE++ 38.7W or 5 38.7W 40W LTPoE++ or Type 3 40mA/2.5mA 1.00kΩ 37.4Ω

LTPoE++ 52.7W or 6 52.7W 51W LTPoE++ or Type 3 40mA/10.5mA 140Ω 46.4Ω

LTPoE++ 70W or 7 70W 62W LTPoE++ or Type 4 40mA/18.5mA 76.8Ω 64.9Ω

LTPoE++ 90W or 8 90W 71.3W LTPoE++ or Type 4 40mA/28mA 49.9Ω 118Ω

Figure3. Type 3 or 4 PSE, 3-Event Class Sequence

The number of class/mark events issued by the PSE

directly indicates the power allocated to the PD and is

summarized in Table1.

IEEE 802.3bt provides nine PD classes and four PD types,

as shown in Table2. The LT4293 class is configured by

setting the RCLS and RCLS++ resistor values.

IEEE 802.3bt PSEs present a single classification event

(see Figure 1) to Class 0 through 3 PDs. A Class 0

through 3 PD presents its class signature to the PSE and

is then powered on if sufficient power is available. Power

limited IEEE 802.3bt PSEs may issue a single event to

Class 4 and higher PDs in order to demote those PDs to

Class3(13W).

Table1. IEEE 802.3bt PSE Allocated Power

PD REQUESTED

CLASS

NUMBER OF PSE CLASS/MARK EVENTS

12345

0 13W

1 3.84W

2 6.49W

3 13W

413W 25.5W

513W 25.5W 40W

613W 25.5W 51W

713W 25.5W 51W 62W

813W 25.5W 51W 71.3W

Note: Bold indicates the PD has been demoted.

4293 F02

PORT

VHSON

VHSOFF

VCLASSMIN

VMARKMAX

VSIGMIN

VRESET

DETECT

1ST CLASS

1ST MARK 2ND MARK

2ND CLASS

POWER ON

4293 F03

PORT

VHSON

VHSOFF

VCLASSMIN

VMARKMAX

VSIGMIN

VRESET

DETECT

1ST CLASS

1ST MARK 2ND MARK 3RD MARK

2ND CLASS 3RD CLASS

POWER ON

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IEEE 802.3bt PSEs present up to three classification

events to Class 4 PDs (see Figure3). Class 4 PDs pres-

ent a class signature 4 on all events. The third event dif-

ferentiates a Class 4 PD from a higher Class PD. Power-

limited IEEE 802.3bt PSEs may issue three events to

Class 5 and higher PDs in order to demote those PDs to

Class4(25.5W).

IEEE 802.3bt PSEs present four classification events (see

Figure4) to Class 5 and 6 PDs. Class 5 and 6 PDs present

a class signature 4 on the first two events, then present

a class signature 0 or 1, respectively, on the remaining

events. Power limited IEEE 802.3bt PSEs may issue four

events to Class 7 and higher PDs in order to demote those

PDs to Class 6 (51W).

IEEE 802.3bt PSEs present five classification events

(seeFigure5) to Class 7 and 8 PDs. Class 7 and 8 PDs

present a class signature 4 on the first two events, then

present a class signature 2 or 3, respectively, on the

remaining events.

The number of class/mark events is communicated

through the LT4293 T2Ppin. See T2P Output section for

more details.

LTPoE++ Demotion and Denial

Both LTPoE++ and IEEE 802.3 PSEs may demote PDs

to a lower power state when the PD Requested Power

exceeds the PSE available power. In addition, a power-

limited LTPoE++ PSE may deny power to a PD requesting

Class 6 or higher. When 2 or fewer class/mark events are

received, PD allocated power is at or below 25.5W and

LTPoE++ PSEs are considered equivalent to IEEE 802.3

PSEs, as shown in Table5.

Table3. LTPoE++ PSE Allocated Power

PD REQUESTED

CLASS

NUMBER OF PSE CLASS/MARK EVENTS

123

0 13W

1 3.84W

2 6.49W

3 13W

413W 25.5W

513W 25.5W 38.7W

613W 25.5W 52.7W

713W 25.5W 70W

813W 25.5W 90W

Note: Bold indicates the PD has been demoted.

Classification Resistors (RCLS and RCLS++)

The RCLS and RCLS++ resistors set the classification cur-

rents corresponding to the PD power classification. Select

the value of RCLS and RCLS++ from Table2 and connect

each 1% resistor between the RCLASS, RCLASS++ pins

and GND.

Detection Signature Corrupt During Mark Event

During the mark event, the LT4293 presents <11kΩ to the

port as required by the LTPoE++/IEEE 802.3 specifications.

Inrush and Power On

Once the PSE detects and classifies the PD, the PSE then

powers on the PD. When the port voltage rises above

the VHSON threshold, it begins to source IGPU out of the

Figure5. Type 4 PSE, 5-Event Class Sequence

APPLICATIONS INFORMATION

Figure4. Type 3 or 4 PSE, 4-Event Class Sequence

4293 F04

VPORT

VHSON

VHSOFF

VCLASSMIN

VMARKMAX

VSIGMIN

VRESET

DETECT

1ST

CLASS

2ND

CLASS

3RD

CLASS

4TH

CLASS

POWER ON

1ST

MARK

2ND

MARK

3RD

MARK

4TH

MARK

4293 F05

VPORT

VHSON

VHSOFF

VCLASSMIN

VMARKMAX

VSIGMIN

VRESET

DETECT

1ST

CLASS

2ND

CLASS

3RD

CLASS

4TH

CLASS

5TH

CLASS

POWER ON

1ST

MARK

2ND

MARK

3RD

MARK

4TH

MARK

5TH

MARK

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Figure6. Configuring IINRUSH

LT4293

HSGATE

GND

4293 F06

VPORT HSSRC

CGATE

3.3k

PORT

VPORT

INRUSH

HSGATE pin. This current flows into an external capaci-

tor, CGATE in Figure6, that causes a voltage to ramp up

the gate of the external MOSFET. The external MOSFET

acts as a source follower and ramps the voltage up on

the output bulk capacitor, CPORT, thereby determining the

inrush current, IINRUSH. Design IINRUSH to be approxi-

mately ~100mA. See equation below:

IINRUSH =IGPU •

PORT

GATE

APPLICATIONS INFORMATION

Auxiliary Supply Override

If the AUX pin is held above V

AUXT

, the LT4293 enters

auxiliary power supply override mode. In this mode the

signature resistor disconnects, classification is disabled,

HSGATE pulls down, the PWRGD pin is open drain and

T2P pin indicates max available power.

The AUX pin allows for setting the auxiliary supply turn

on and turn off voltage thresholds, VAUXON, and VAUXOFF

respectively. The auxiliary supply hysteresis voltage,

VAUXHYS, is generated with sinking current, IAUXH, and is

active only when the AUX pin voltage is less than VAUXT.

Use the following equations to set VAUXON and VAUXOFF

via R1 and R2 in Figure7. Note that an internal 6.5V Zener

limits the voltage on the AUX pin.

Figure7. AUX Threshold and Hysteresis Calculation

LT4293

GND

4293 F07

AUX

VAUX

–

R1=

AUXON −

AUXOFF

IAUXH

AUXHYS

IAUXH

R2 =R1

VAUXOFF

VAUXT

−1

⎛

⎝

⎜⎞

⎠

⎟

R1≥VAUX(MAX) −VAUXT

1.4mA

The LT4293 internal charge pump provides an N-channel

MOSFET solution, eliminating a larger and more costly

P-channel MOSFET. The low RDS(ON) MOSFET also maxi-

mizes power delivery and efficiency, reduces power and

heat dissipation, and eases thermal design.

Power Good

The PWRGD pin is held low by its open drain output until

HSGATE charges up to approximately 7V above HSSRC.

The PWRGD pin is used to hold off the downstream cir-

cuitry until inrush is complete and the external MOSFET

is fully enhanced. The HSGATE pin remains high and the

PWRGD pin remains open-drain until the port voltage falls

below VHSOFF.

Delay Start

When the PSE powers up the port, the PD application

should not draw more than 350mA for 80ms to comply

with the IEEE 802.3 standard.

A capacitor up to 1000pF may be placed between the AUX

pin and GND to improve noise immunity. VAUXON must be

lower than VHSOFF.

T2P Output

The LT4293 communicates the PSE allocated power to the

PD application via the T2P pin. The T2P pin state is deter-

mined by the AUX pin, the RCLASS++ pin, and the number

of classification events. The LT4293 uses a 5-state encod-

ing for the T2P output. T2P state and the associated PSE

allocated power are shown in Table4 and Table5.

Table4. T2P Response During Auxiliary Power Operation

PD REQUESTED CLASS T2P*

0 − 4 Low-Z

5 − 8 75%

*Specified as the percentage of the period which T2P is low impedance

with respect to GND.

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The highest priority input is the AUX pin. AUX is asserted

to enter the auxiliary power state and deasserted to

enter the PoE state. In the auxiliary power state, the T2P

pin indicates the highest available power, based on PD

Requested Class. The auxiliary power supply must be

sized to provide at least the PD Requested Class Power.

Second, PD Requested Class and PD Requested Power

are configured using the RCLASS and RCLASS++ pins.

The RCLASS++ pin alone can be used to determine if the

PD Class is 0−4, 5−8 or LTPoE++ as shown in Table2.

Last, the PSE type and the number of classification events

determine the amount of power allocated by the PSE as

described in Table1 and Table3.

Interoperability Across Various PSEs and Auxiliary

Power Source

Table6 summarizes the expected LT4293 T2P response,

the PSE allocated power and the number of classification

events. The result is a function of PD Requested Class

and power source—Auxiliary or PoE.

APPLICATIONS INFORMATION

Table5. T2P Response During PoE Operation

POWER

SOURCE

NUMBER OF

CLASS/MARK

EVENTS T2P* PSE ALLOCATED POWER

LTPoE++

1 Hi-Z Min (PD Requested Power, 13W)

2 Low-Z 25.5W

3 75% LTPoE++ PD Requested Power

IEEE

802.3

1 Hi-Z Min (PD Requested Power, 13W)

2 or 3 Low-Z 25.5W

4 50% Min (PD Requested Power, 51W)

5 25% Min (PD Requested Power, 71.3W)

*Specified as the percentage of the period which T2P is low impedance

with respect to GND.

Figure8. Response Example for 25% Low-Z, 75% Hi-Z

LT4293

4293 F08

VCC

GND

T2P

V(T2P)

GND

VCC

25%

Low-Z

75%

Hi-Z

TIME

Table6. LT4293 Interoperability (T2P Response*, Allocated Power, Number of Class/Mark Events)

REQUESTED PD CLASS

(REQUESTED POWER)

PSE TYPE, CLASS (POWER)

AUXILIARY

POWER

SOURCE**

IEEE 802.3

TYPE 1

IEEE 802.3

TYPE 2

IEEE 802.3

TYPE 3

IEEE 802.3

TYPE 4 LTPoE++

CLASS 3

(13W)

CLASS 4

(25.5W)

CLASS 4

(25.5W)

CLASS 5

(40W)

CLASS 6

(51W)

CLASS 7

(62W)

CLASS 8

(71.3W) (38.7W) (52.7W) (70W) (90W)

CLASS 0−3

(Up to 13W)

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Hi-Z

Up to 13W

1-Event

Low-Z

Aux. Power

N/A

CLASS 4

(25.5W)

Hi-Z

13W

1-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

2-Event

Low-Z

Aux. Power

N/A

CLASS 5

(40W)

Hi-Z

13W

1-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

3-Event

50%

40W

4-Event

50%

40W

4-Event

50%

40W

4-Event

50%

40W

4-Event

75%

38.7W

3-Event

75%

38.7W

3-Event

75%

38.7W

3-Event

75%

38.7W

3-Event

75%

Aux. Power

N/A

CLASS 6

(51W)

Hi-Z

13W

1-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

3-Event

50%

51W

4-Event

50%

51W

4-Event

50%

51W

4-Event

DENIED

75%

52.7W

3-Event

75%

52.7W

3-Event

75%

52.7W

3-Event

75%

Aux. Power

N/A

CLASS 7

(62W)

Hi-Z

13W

1-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

3-Event

50%

51W

4-Event

25%

62W

5-Event

25%

62W

5-Event

DENIED DENIED

75%

70W

3-Event

75%

70W

3-Event

75%

Aux. Power

N/A

CLASS 8

(71.3W)

Hi-Z

13W

1-Event

Low-Z

25.5W

2-Event

Low-Z

25.5W

3-Event

Low-Z

25.5W

3-Event

50%

51W

4-Event

50%

51W

4-Event

25%

71.3W

5-Event

DENIED DENIED DENIED

75%

90W

3-Event

75%

Aux. Power

N/A

↓

T2P Response* →

PSE Allocated Power →

Number of Classification Events →

75%

90W

3-Event

Note 1. Shade of blue indicates the PD has been demoted or denied power.

* Specified as the percentage of the period which T2P is low impedance with respect to GND.

** Auxiliary Power Supply must be sized to provide PD Requested Power.

LT4293

Rev. 0

For more information www.analog.com

Overtemperature Protection

The IEEE 802.3 specification requires a PD to withstand

any applied voltage from 0V to 57V indefinitely. During

classification, however, the power dissipation in the

LT4293 may be as high as 1.5W. The LT4293 can easily

tolerate this power for the maximum IEEE classification

timing but overheats if this condition persists abnormally.

The LT4293 includes an overtemperature protection

feature which is intended to protect the device during

momentary overload conditions. If the junction tempera-

ture exceeds the overtemperature threshold, the LT4293

pulls down HSGATE pin, and disables classification.

EXTERNAL INTERFACE AND COMPONENT SELECTION

PoE Input Bridge

A PD is required to polarity-correct its input voltage. There

are several different options available for bridge rectifiers;

silicon diodes, Schottky diodes, and ideal diodes. When

silicon or Schottky diode bridges are used, the diode for-

ward voltage drops affect the voltage at the VPORT pin.

The LT4293 is designed to tolerate these voltage drops.

Note, the voltage parameters shown in the Electrical

Characteristics are specified at the LT4293 package pins.

A silicon diode bridge consumes up to 4% of the avail-

able power. In addition, silicon diode bridges exhibit poor

pairset-to-pairset unbalance performance. Each branch of

a silicon diode bridge shares source/return current, and

thermal runaway can cause large, non-compliant current

unbalances between pairsets.

While using Schottky diodes can help reduce the power

loss with a lower forward voltage, the Schottky bridge

may not be suitable for high temperature PD applications.

Schottky diode bridges exhibit temperature induced leak-

age currents. The leakage current has a voltage depen-

dency that can invalidate the measured detection signa-

ture. In addition, these leakage currents can back-feed

through the unpowered branch and the unused bridge,

violating IEEE 802.3 specifications.

For high efficiency applications, the LT4293 supports an

LT4321-based PoE ideal diode bridge that reduces the

forward voltage drop from 0.7V to 20mV per diode while

maintaining IEEE 802.3 compliance. The LT4321 simpli-

fies thermal design, eliminates costly heatsinks, and can

operate in space-constrained applications.

Auxiliary Input Bridge

Some PDs are required to receive AC or DC power from an

auxiliary power source. A diode bridge is typically required

to handle the voltage rectification and polaritycorrection.

In high efficiency applications, or in low auxiliary input

voltage applications, the voltage drop across the rectifier

cannot be tolerated. The LT4293 can be configured with

an LT4320-based ideal diode bridge to recover the diode

voltage drop and ease thermal design.

For applications with auxiliary input voltages below

10V, the LT4293 must be configured with an LT4320-

based ideal diode bridge to recover the voltage drop and

guarantee the minimum VPORT voltage is within the

VPORT AUX Mode Range as specified in the Electrical

Characteristicstable.

Input Capacitor

A 0.1μF capacitor is needed from VPORT to GND to meet

the input impedance requirement in IEEE 802.3 and to

properly bypass the LT4293. When operating with the

LT4321, locally bypass each with a 0.047μF capacitor, thus

keeping the total port capacitance within specification.

Transient Voltage Suppressor

The LT4293 specifies an absolute maximum voltage of

100V and is designed to tolerate brief overvoltage events

due to Ethernet cable surges. To protect the LT4293 from

an overvoltage event, install a unidirectional transient

voltage suppressor (TVS) such as an SMAJ58A between

the VPORT and GND pins. For PD applications that require

APPLICATIONS INFORMATION

LT4293

Rev. 0

For more information www.analog.com

an auxiliary power input, install a TVS between VIN and

GND. See Layout Considerations for TVS placement.

For extremely high cable discharge and surge protection,

contact Analog Devices Applications.

Exposed Pad

The LT4293 DFN package has an exposed pad that is

internally connected to GND. The exposed pad may only

be connected to GND on the printed circuitboard.

TYPICAL APPLICATIONS

4293 TA03

LT4321

TG36BG12

PSMN075-100MSE ×4

WURTH 749022016

BG36

IN36

IN45

IN78

IN12

DATA

PAIRS

SPARE

PAIRS

OUTN

OUTP SMAJ58A

VPORT

PWRGD

AUX

RCLASS

T2P

RCLASS++

HSGATE

PSMN040-100MSE

LT4293

GND

TG12

BG45TG78 TG45BG78

HSSRC

ISOLATED

POWER

SUPPLY

GND

RUN

VOUT

VIN

22µF

–

RCLS

140Ω

RCLS++

46.4Ω

47nF

3.3k

100k

CPD2

0.047µF

CPD1

0.047µF

OPTO PSE TYPE

(TO µP)

PSE TYPE T2P RESPONSE ALLOCATED POWER

IEEE 802.3at 25.5W LOW-Z TO GND 25.5W

IEEE 802.3bt 51W 50% LOW-Z 51W

OR HIGHER POWER

LTPoE++ 52.7W 75% LOW-Z 52.7W

OR HIGHER POWER

LTPoE++/IEEE 802.3bt-Compliant > 99% Efficient 51W Powered Device

LAYOUT CONSIDERATIONS

Avoid excessive parasitic capacitance on the RCLASS

and RCLASS++ pins and place resistors RCLS and RCLS++

close to the LT4293.

It is strictly required for maximum protection to place the

0.1μF input capacitor, CPD, and transient voltage suppres-

sor as close to the LT4293 as possible. When operating

the LT4293 with the LT4321, place a 0.047μF capacitor,

CPD1, as close as possible to the LT4293 VPORT and

GND pins (pin 10 and pin 5, respectively), and a 0.047μF

capacitor, CPD2, as close as possible to the LT4321 OUTP

and OUTN pins.

APPLICATIONS INFORMATION

LT4293

Rev. 0

For more information www.analog.com

PACKAGE DESCRIPTION

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.125

TYP

2.38 ±0.10

(2 SIDES)

106

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV C 0310

0.25 ±0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.15 ±0.05

0.50

BSC

0.70 ±0.05

3.55 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

LT4293

Rev. 0

For more information www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

PACKAGE DESCRIPTION

MSOP (MS) 0213 REV F

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ±0.152

(.193 ±.006)

0.497 ±0.076

(.0196 ±.003)

REF

8910 76

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ±0.038

(.0120 ±.0015)

TYP

0.50

(.0197)

BSC

0.1016 ±0.0508

(.004 ±.002)

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661 Rev F)

LT4293

Rev. 0

For more information www.analog.com

 ANALOG DEVICES, INC. 2019

05/19

www.analog.com

TYPICAL APPLICATION

RELATED PARTS

LTPoE++/IEEE 802.3bt > 99% Efficient 71.3W Powered Device

PART NUMBER DESCRIPTION COMMENTS

LT4295 IEEE 802.3bt PD with Forward/Flyback

Switching Regulator Controller

External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback

Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V,

Including Housekeeping Buck, Slope Compensation

LT4294 IEEE 802.3bt PD Controller External Switch, IEEE 802.3bt and Aux Support

LT4321 PoE Ideal Diode Bridge Controller Controls 8-NMOSFETs for IEEE-Required PD Voltage Rectification without DiodeDrops

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Diode Drops

LTC4292/LTC4291-1 4-Port IEEE 802.3bt PSE Controller Transformer Isolation, Supports IEEE 802.3bt PDs

LTC4279 Single PoE/PoE+/LTPoE++ PSE Controller Supports IEEE 802.3af, IEEE 802.3at, LTPoE++ and Proprietary PDs

LT4276A/B/C LTPoE++/PoE+/PoE PD with Forward/

Flyback Switching Regulator Controller

External Switch, LTPoE++ Support, User-Configurable Class, Forward or No-Opto

Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V,

Including Housekeeping Buck, Slope Compensation

LT4275A/B/C LTPoE++/PoE+/PoE PD Controller External Switch, LTPoE++ Support

LTC4269-1 IEEE 802.3at PD Interface with Integrated

Flyback Switching Regulator

2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

50kHz to 250kHz, Aux Support

LTC4269-2 IEEE 802.3at PD Interface with Integrated

Forward Switching Regulator

2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz

to 500kHz, Aux Support

LTC4278 IEEE 802.3at PD Interface with Integrated

Flyback Switching Regulator

2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

50kHz to 250kHz, 12V Aux Support

LTC4267/LTC4267-1/

LTC4267-3

IEEE 802.3af PD Interface with Integrated

Switching Regulator

Internal 100V, 400mA Switch, Programmable Class, 200kHz/300kHz Constant

FrequencyPWM

LTC4290/LTC4271 8-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs

4293 TA02

LT4321

TG36BG12

PSMN075-100MSE ×4

WURTH 749022016

BG36

IN36

IN45

IN78

IN12

DATA

PAIRS

SPARE

PAIRS

OUTN

OUTP SMAJ58A

VPORT

PWRGD

AUX

RCLASS

T2P

RCLASS++

HSGATE

PSMN040-100MSE

LT4293

GND

TG12

BG45TG78 TG45BG78

HSSRC

ISOLATED

POWER

SUPPLY

GND

RUN

OUT

VIN

22µF

–

RCLS

49.9Ω

RCLS++

118Ω

47nF

3.3k

100k

CPD2

0.047µF

CPD1

0.047µF

OPTO PSE TYPE

(TO µP)