January 2002 Advance information AS6VB51216 2.7V to 3.3V 512K X 16 IntelliwattTM Super Low-Power CMOS SRAM Features * * * * * * * AS6VB51216 IntelliwattTM active power circuitry Industrial and commercial temperature ranges available Organization: 524,288 words x 16 bits 2.7V to 3.3V power supply range Fast access time of 55 ns Low power consumption: ACTIVE - 132 mW max at 3.3V and 55 ns * 1.5V data retention * Equal access and cycle times * Easy memory expansion with CS1, CS2, OE inputs * Smallest footprint packages - 48-ball FBGA; 7.0 x 9.0 mm * ESD protection 2000 volts * Latch-up current 200 mA * Low power consumption: STANDBY - 66 W max at 3.3V Pin arrangement (top view) Logic block diagram I/O0-I/O7 I/O8-I/O15 Row Decoder A0~A8 48-CSP Ball-Grid-Array Package VDD 512K x 16 Array (8,388,608) I/O buffer Control circuit A B C D E F G H VSS Column decoder WE 1 LB I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 3 OE A0 UB A3 I/O10 A5 I/O11 A17 I/O12 VSS I/O13 A14 NC A12 A8 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CS I/O1 I/O3 I/O4 I/O5 WE A11 6 CS2 I/O0 I/O2 VCC VSS I/O6 I/O7 DNU1 '18 'R1RW8VH A9~A18 UB OE LB CS1 CS2 6HOHFWLRQJXLGH VCC Range Power Dissipation Typ2 (V) Max (V) Speed (ns) Operating (ICC1) Standby (ISB2) Product Min (V) Max (mA) Max (A) AS6VB51216-55 2.7 3.0 3.3 55 4 25 AS6VB51216-70 2.7 3.0 3.3 70 4 25 AS6VB51216-85 2.7 3.0 3.3 85 4 25 1/21/02; V.0.9.6 Alliance Semiconductor P. 1 of 10 Copyright (c) Alliance Semiconductor. All rights reserved. AS6VB51216 Functional description The AS6VB51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words x 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55/70/85 ns are ideal for low-power applications. Active high and low chip enables (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems. When CS1 is high or CS2 is low, or UB and LB are high, the device enters standby mode: the AS6VB51216 is guaranteed not to exceed 66 W power consumption at 3.3V. The device also retains data when VCC is reduced to 1.5V for even lower power consumption. The device can also be put into standby mode when deselected (CS1 is high or CS2 is low, or UB and LB are high). The input/ output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CS1 is high or CS2 is low, or UB and LB are high), outputs are disabled (OE High), UB and LB are disabled (UB, LB High), or during a write operation ( CS1 is low or CS2 is high and WE Low). Writing to the device is accomplished by taking Chip Enables CS1 Low, CS2 High and Write Enable (WE) input Low. If Byte Low Enable (LB) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). Reading from the device is accomplished by taking Chip Enable CS1 Low, CS2 High and Output Enable (OE) Low while forcing the Write Enable (WE) High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (UB) is Low, then data from memory will appear on I/O8 to I/O15. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0-I/O7, and UB controls the higher bits, I/O8-I/O15. All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the JEDEC 48-ball FBGA package. $EVROXWHPD[LPXPUDWLQJV Parameter Symbol Min Max Unit Voltage on VCC relative to VSS VtIN -0.5 VCC + 0.5 V Voltage on any I/O pin relative to GND VtI/O -0.5 VCC + 0.5 V Power dissipation PD - 1.0 W Storage temperature (plastic) Tstg -65 +150 C Temperature with VCC applied Tbias -55 +125 C DC output current (low) IOUT - 20 mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1/21/02; V.0.9.6 Alliance Semiconductor P. 2 of 10 AS6VB51216 7UXWKWDEOH CS1 CS2 WE OE LB UB H X X X X X X X X X H H X L X X X X L X H H X X L H H L L L H L H H L L X Supply Current I/O0-I/O7 I/O8-I/O15 Mode ISB High Z High Z Standby ICC High Z High Z Output disable DOUT High Z High Z DOUT L DOUT DOUT L H DIN High Z H L High Z DIN L L DIN DIN ICC ICC Read Write Key: X = Don't care, L = Low, H = High. '&5HFRPPHQGHGRSHUDWLQJFRQGLWLRQ RYHUWKHRSHUDWLQJUDQJH Parameter Description Test Conditions Min Max Unit Vcc Supply voltage - 2.7 3.3 V VOH Output HIGH Voltage IOH = -1.0mA 2.4 VOL Output LOW Voltage IOL = 2.1mA VIH Input HIGH Voltage - VIL Input LOW Voltage IIX V 0.4 V 2.2 VCC + 0.2 V - -0.2 0.6 V Input Load Current GND < VIN < VCC -1 +1 A IOZ Output Load Current GND < VO < VCC; Outputs High Z -1 +1 A ICC VCC Operating Supply Current IOUT = 0mA, f=0 3 mA ICC1 @ 1 MHz Average VCC Operating Supply Current at 1 MHz IOUT = 0mA, f =1MHz 4 mA ICC2 Average VCC Operating Supply Current 40 mA at 55ns IOUT = 0mA, f = fMax 30 mA at 70ns mA 25 mA at 85ns ISB CS Power Down Current; TTL Inputs CS1 > VCC - 0.2V or CS2< 0.2V or UB = LB. > Vcc -0.2V. [Other inputs = VIL or VIH, f = 0] 300 A ISB1 CS Power Down Current; CMOS Inputs CS1 > VCC - 0.2V or CS2< 0.2V or UB = LB > VCC - 0.2V. [Other inputs = 0V - VCC, f = fMax] 20 A 1/21/02; V.0.9.6 Alliance Semiconductor P. 3 of 10 AS6VB51216 Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL) Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CS, CS2, WE, OE, LB, UB VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF Read cycle (over the operating range) -55 Parameter -70 -85 Symbol Min Max Min Max Min Max Unit Notes Read cycle time tRC 55 - 70 - 85 - ns Address access time tAA - 55 - 70 - 85 ns 3 Chip enable (CS) access time tACS - 55 - 70 - 85 ns 3 Output enable (OE) access time tOE - 25 - 35 - 35 ns Output hold from address change tOH 10 - 10 - 10 - ns 5 CSORZWo output in low Z tCLZ 10 - 10 - 10 - ns 4, 5 CS high to output in high Z tCHZ 0 20 0 25 0 25 ns 4, 5 OE low to output in low Z tOLZ 5 - 5 - 5 - ns 4, 5 UB/LB access time tBA - 55 - 70 - 85 ns UB/LB low to low Z tBLZ 10 - 10 - 10 - ns 4, 5 UB/LB high to high Z tBHZ 0 20 0 25 0 25 ns 4, 5 OE high to output in high Z tOHZ 0 20 0 25 0 25 ns 4, 5 Power up time tPU 0 - 0 - 0 - ns 4, 5 Power down time tPD - 55 - 70 - 85 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined/don't care Read waveform 1 (address controlled) (CS1=OE=LB=UB=Low, CS2=High) tRC Address tOH DOUT 1/21/02; V.0.9.6 tAA Previous data valid tOH Data valid Alliance Semiconductor P. 4 of 10 AS6VB51216 Read waveform 2 (CS1, CS2, OE, UB, LB controlled) [WE=High] tRC Address tAA OE tOE tOLZ tOH CS1 tOHZ tACS CS2 tLZ tHZ LB, UB tBLZ tBA tBHZ DOUT Data valid Write cycle (over the operating range) -55 Parameter -70 -85 Symbol Min Max Min Max Min Max Unit Write cycle time tWC 55 - 70 - 85 - ns Chip enable to write end tCW 45 - 60 - 60 - ns Address setup to write end tAW 45 - 60 - 60 - ns Address setup time tAS 0 - 0 - 0 - ns Write pulse width tWP 40 - 50 - 50 - ns Address hold from end of write tAH 0 - 0 - 0 - ns Data valid to write end tDW 25 - 30 - 30 - ns Data hold time tDH 0 - 0 - 0 - ns 4, 5 Write enable to output in high Z tWZ 0 20 0 20 0 20 ns 4, 5 Output active from write end tOW 5 - 5 - 5 - ns 4, 5 UB/LB low to end of write tBW 45 - 60 - 60 - ns 1/21/02; V.0.9.6 Alliance Semiconductor Notes 12 12 P. 5 of 10 AS6VB51216 Write waveform 1 (WE controlled) tWC Address tAH tCW CS1 tBW CS2 LB, UB tAW tAS tWP WE tDW DIN Data valid tWZ DOUT tDH tOW Data undefined High Z Write waveform 2 (CS controlled) tWC Address tAS CS1 tAH tCW CS2 tAW tBW LB, UB tWP WE tDW DIN DOUT 1/21/02; V.0.9.6 tCLZ High Z tWZ Data undefined Alliance Semiconductor tDH Data valid tOW High Z P. 6 of 10 AS6VB51216 Data retention characteristics (over the operating range) Parameter Symbol Test conditions Min Max Unit VCC for data retention VDR 1.5 3.3 V Data retention current ICCDR - 10 A Chip deselect to data retention time tCDR VCC = 1.5V CS VCC - 0.1V or UB = LB = > VCC - 0.1V VIN VCC - 0.1V or VIN 0.1V 0 - ns tRC - ns Data retention mode tR Operation recovery time tR Data retention waveform controlled CS1 tCDR VCC 1.65V 1.4V VDR CS1, LB/UB GND CS2 CS1VCC -0.2, LB=UB VCC -0.2V controlled Data retention mode VCC 1.65V CS2 tCDR tR VDR 0.4V CS20.2V GND 1/21/02; V.0.9.6 Alliance Semiconductor P. 7 of 10 AS6VB51216 AC test loads and waveforms Thevenin equivalent: R1 VCC OUTPUT R1 VCC OUTPUT 30 pF 5 pF (a) R2 INCLUDING JIG AND SCOPE V ALL INPUT PULSES R2 INCLUDING JIG AND SCOPE RTH OUTPUT VCC Typ GND 90% 10% (b) 90% < 5 ns 10% (c) Parameters VCC = 2.7V Unit R1 992 Ohms R2 1842 Ohms RTH 645 Ohms VTH 1.755V Volts Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS and OE are LOW for read cycle. Address valid prior to or coincident with CS transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. 1.5V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at high Z and low Z parameters, where C = 5pF. 1/21/02; V.0.9.6 Alliance Semiconductor P. 8 of 10 AS6VB51216 Package diagrams and dimensions 48-ball FBGA Top View Bottom View 6 5 4 3 2 1 Ball #A1 Index Ball #A1 A B SRAM Die C D C1 C E F A G H Elastomer A B B1 Detail View Side View A 2 D E2 Y E Die Die 1 0.3/Typ Minimum Typical Maximum A - 0.75 - B 6.90 7.00 7.10 B1 - 3.75 - C 8.4 9.0 8.6 C1 - 5.25 - D 0.30 0.35 0.40 E - - 1.20 E1 - 0.68 - E2 0.22 0.25 0.27 Y - - 0.08 1/21/02; V.0.9.6 Notes 1. Bump counts: 48 (8 row x 6 column). 2. Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are 0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max). Alliance Semiconductor P. 9 of 10 AS6VB51216 Ordering codes Speed (ns) Ordering Code Package Type 55 AS6VB51216-55BI 48-ball fine pitch BGA 70 AS6VB51216-70BI 48-ball fine pitch BGA 85 AS6VB51216-85BI 48-ball fine pitch BGA 55 AS6VB51216-55BC 48-ball fine pitch BGA 70 AS6VB51216-70BC 48-ball fine pitch BGA 85 AS6VB51216-85BC 48-ball fine pitch BGA Operating Range Industrial Commercial Part numbering system AS6UA 51216 -55/70/85 B C or I SRAM IntelliwattTM prefix Device number Nano-seconds Package: B: CSP BGA Temperature range: C: Commercial: 0 C to 70 C I: Industrial: -40 C to 85 C 1/21/02; V.0.9.6 Alliance Semiconductor P. 10 of 10 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. 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