1 of 16GS2974A HD-LINX™ III Adaptive Cable Equalizer www.gennum.com
Data Sheet
42216 - 3 January 2009
GS2974A HD-LINX™ III Adaptive Cable Equalizer
Features
• SMPTE 424M, SMPTE 292M and SMPTE 259M
compliant
•Automatic cable equalization
• 0.3UI Maximum Output Jitter at 2.97Gb/s
• Multi-standard operation from 143Mb/s to 2.97Gb/s
• Supports DVB-ASI at 270Mb/s
• Small footprint (4mm x 4mm)
• Pb-free and RoHS compliant
• Manual bypass (useful for low data rates with slow
rise/fall times)
• Performance optimized for 1.485Gb/s and 2.97Gb/s
• Typical equalized length of Belden 1694A cable: 120m
at 2.97Gb/s, 200m at 1.485Gb/s, and 350m at 270Mb/s
•50Ω differential output (internal 50Ω pull-ups)
• Programmable mute based on max cable length adjust
• Single 3.3V power supply operation
• Operating temperature range: 0°C to +70°C
Applications
• SMPTE 424M, SMPTE 292M and SMPTE 259M Coaxial
Cable Serial Digital Interfaces.
Description
The GS2974A is a high-speed BiCMOS integrated circuit
designed to equalize and restore signals
received over 75
Ω
co-axial cable
.
The GS2974A is designed to support SMPTE 424M, SMPTE
292M and SMPTE 259M, and is optimized for performance
at 1.485Gb/s and 2.97Gb/s.
The GS2974A features DC restoration to compensate for
the DC content of SMPTE pathological test patterns.
A voltage programmable mute threshold (MCLADJ),
applicable for SD mode (refer to Section 4.3), is included to
allow muting of the GS2974A output when an approximate
selected cable length is reached for SMPTE 259M signals.
This feature allows the GS2974A to distinguish between
low amplitude SD-SDI signals and noise at the input of the
device. The serial digital outputs of the GS2974A may be
forced to a mute state by applying a voltage to the MUTE
pin.
Power consumption is typically 215mW using a 3.3V
power supply. The GS2974A is lead-free, and the
encapsulation compound does not contain halogenated
flame retardant.
This component and all homogeneous subcomponents are
RoHS compliant.
GS2974A Functional Block Diagram
CABLE LENGTH ADJUSTOR
CARRIER
DETECT MUTE
EQUALIZER DC RESTORE OUTPUT
AGC
CD
MUTE
SDO
BYPASS
SDOSDI
SDI
MCLADJ
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Data Sheet
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Revision History
Version ECR PCN Date Changes and/or Modifications
3 151331 – January 2009 Added 2500pc reel size to 6.6 Ordering
Information. Changed the Output Voltage
Swing from 550mVp-p to 600mVp-p in
Table 2-2: AC Electrical Characteristics.
2 149719 – April 2008 Added “0.3UI Maximum Output Jitter at
2.97Gb/s” to Features Section and Table
2-2: AC Electrical Characteristics. Changed
cables lengths from 100 to 120 and 400 to
350 in Section 4. Detailed Description.
Re-wrote Section 4.3 Programmable
Maximum Cable Length Adjust (MCLADJ).
Added Tape & Reel to 6.6 Ordering
Information.
1 145131 – May 2007 Converted to Data Sheet.
0 144247 – February 2007 Converted to Preliminary Data Sheet.
Removed ‘Proprietary and Confidential’
footer. Modified DC Electrical
Characteristics and AC Electrical
Characteristics table. Added section 6.4
Marking Diagram.
A 143102 – December 2006 New Document.
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Data Sheet
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Contents
Features.................................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Revision History .................................................................................................................................................2
1. Pin Out...............................................................................................................................................................4
1.1 GS2974A Pin Assignment .............................................................................................................. 4
1.2 GS2974A Pin Descriptions .............................................................................................................4
2. Electrical Characteristics ............................................................................................................................6
2.1 Absolute Maximum Ratings ..........................................................................................................6
2.2 DC Electrical Characteristics ........................................................................................................6
2.3 AC Electrical Characteristics ........................................................................................................7
Test Circuit ...........................................................................................................................................................8
3. Input/Output Circuits ..................................................................................................................................8
4. Detailed Description.....................................................................................................................................9
4.1 Serial Digital Inputs .........................................................................................................................9
4.2 Cable Equalization ........................................................................................................................ 10
4.3 Programmable Maximum Cable Length Adjust (MCLADJ) ............................................. 10
4.4 Mute and Carrier Detect .............................................................................................................. 11
5. Application Information .......................................................................................................................... 12
5.1 PCB Layout ....................................................................................................................................... 12
5.2 Typical Application Circuit ........................................................................................................ 12
6. Package & Ordering Information .......................................................................................................... 13
6.1 Package Dimensions ..................................................................................................................... 13
6.2 Packaging Data ............................................................................................................................... 13
6.3 Recommended PCB Footprint ................................................................................................... 14
6.4 Marking Diagram ........................................................................................................................... 14
6.5 Solder Reflow Profiles .................................................................................................................. 15
6.6 Ordering Information ................................................................................................................... 15
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Data Sheet
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1. Pin Out
1.1 GS2974A Pin Assignment
Figure 1-1: 16-Pin QFN
1.2 GS2974A Pin Descriptions
GS2974A
(top view)
1
V
EE
_A
V
EE
_A
SDI
SDI 2
3
4
SDO
SDO
V
EE
_D
V
EE
_D
12
11
10
9
AGC
AGC
BYPASS
MCLADJ
57
68
VCC_A
MUTE
CD
VCC_D
13
14
15
16
Center Pad
(bottom of package, internally
bonded to VEE_A)
Table 1-1: GS2974A Pin Descriptions
Pin Number Name Timing Type Description
1, 4 VEE_A Analog Power Most negative power supply for analog circuitry.
Connect to GND.
2, 3 SDI, SDI Analog Input Serial digital differential input.
5, 6 AGC, AGC Analog – External AGC capacitor.
Connect pin 5 and pin 6 together as shown in the Typical
Application Circuit on page 12.
7BYPASS Not
Synchronous
Input Forces the Equalizing and DC RESTORE stages into bypass mode
when HIGH. No equalization occurs in this mode.
8MCLADJAnalog Input Maximum cable length adjust.
Adjusts the approximate maximum amount of cable to be
equalized. See Section 4.3. and Section 4.4
9 VEE_D Analog Power Most negative power supply for the digital circuitry and output
buffer.
Connect to GND.
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Data Sheet
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10, 11 SDO, SDO Analog Output Equalized serial digital differential output.
12 VEE_D Analog Power Most negative power supply for the digital circuitry and output
buffer.
Connect to GND.
13 VCC_D Analog Power Most positive power supply for the digital I/O pins of the device.
Connect to +3.3V DC.
14 MUTE Not
Synchronous
Input CONTROL SIGNAL INPUT
levels are LVCMOS/LVTTL compatible. (3.3V Tolerant)
Controls output behaviour on SDO and SDO
See Section 4.4.
15 CDNot
Synchronous
Output STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Indicates the presence of a good input signal.
See Section 4.4.
16 VCC_A Analog Power Most positive power supply for the analog circuitry of the device.
Connect to +3.3V DC.
–Center Pad – Power Internally bonded to VEE_A.
Table 1-1: GS2974A Pin Descriptions (Continued)
Pin Number Name Timing Type Description
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Data Sheet
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 DC Electrical Characteristics
Parameter Value
Supply Voltage -0.3V to +3.6 VDC
Input ESD Voltage 2kV
Storage Temperature Range -50°C < Ts < 125°C
Input Voltage Range (any input) -0.3 to (VCC +0.3)V
Operating Temperature Range 0°C to 70°C
Solder Reflow Temperature 260°C
Table 2-1: DC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
Supply Voltage VCC – 3.135 3.3 3.465 V ±5%
Power Consumption PDTA = 25°C– 215 343 mW –
Supply Current IsTA = 25°C–6598mA–
Output Common Mode
Voltage
VCMOUT TA = 25°C–V
CC - ΔVSDO/2 – V –
Input Common Mode Voltage VCMIN TA = 25°C–1.75–V–
MCLADJ DC Voltage (to mute
signal)
–0m, T
A = 25°C–3.2–V–
MCLADJ Range – TA = 25°C–0.5–V–
CD Output Voltage VCD(OH) Carrier not
present
2.4 – – V –
VCD(OL) Carrier present – – 0.4 V –
Mute Input Voltage Required
to Force Outputs to Mute
VMute Min to Mute 2.0 – – V –
Mute Input Voltage Required
to Force Outputs Active
VMute Max to
Activate
––0.8V–
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2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
Serial input data rate DRSDO – 143 – 2970 Mb/s –
Input Voltage Swing ΔVSDI TA =25°C, differential,
270Mb/s and 1.485Gb/s
720 800 950 mVp-p 1
TA =25°C, differential,
2.97Gb/s
720 800 880 mVp-p 1
Output Voltage Swing ΔVSDO 100Ω load, TA =25°C,
differential
600 750 1050 mVp-p –
Output Jitter of Various
Cable Lengths and Data
Rates
– 270Mb/s
Belden 1694A: 0-300m
––0.2UI2,5
– 270Mb/s
Belden 1694A: 300-350m
– 0.2 – UI 4,5
– 1.485Gb/s
Belden 1694A: 0-140m
– 0.25 UI 2,5
– 1.485Gb/s
Belden 1694A: 140-200m
– 0.3 – UI 4,5
– 2.97Gb/s
Belden 1694A: 0-70m
––0.3UI2,5
– 2.97Gb/s
Belden 1694A: 70-120m
– 0.3 – UI 4,5
Output Rise/Fall time – 20% - 80% 40 80 220 ps –
Mismatch in rise/fall time – – – – 30 ps –
Duty cycle distortion – – – – 30 ps –
Overshoot – – – – 10 % –
Input Return Loss – – 15 21 – dB 3
Input Resistance – single ended – 1.52 – kΩ–
Input Capacitance – single ended – 1 – pF –
Output Resistance – single ended – 50 – Ω–
NOTES:
1. 0m cable length.
2. All parts were production tested. In order to guarantee jitter over the full range of specification (VCC = 3.3V ±5%, TA = 0°C to 70°C, and
720-880mV launch swing from the SDI cable driver) the recommended applications circuit must be used.
3. Tested on CB2974A board from 5MHz to 3GHz.
4. Based on characterization data using the recommended applications circuit, at VCC = 3.3V, TA = 25°C and 800mV launch swing from the SDI
cable driver
5. Equalizer Pathological test signal was used.
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Data Sheet
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Test Circuit
Figure 2-1: Test Circuit
3. Input/Output Circuits
BERT Pattern
Generator
EXT.
CLOCK
CLOCK
OUT
DATA
OUT
EXT.
CLOCK
2.97GHz/1.485GHz/
270MHz
GS2974A
TEST BOARD TDS 820
CH. 1
CH. 2
OUTIN
OUT
EXT. TRIGGER
50/75
1694A CABLE
Figure 3-1: Input Equivalent Circuit
Figure 3-2: MCLADJ Equivalent Circuit
3k
3.6k
3k
3.6k
RC
SDI SDI
V
CC
MCLADJ
12.2k
150µ
+
-
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Data Sheet
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4. Detailed Description
The GS2974A is a high speed BiCMOS IC designed to equalize serial digital signals.
The GS2974A can equalize both HD and SD serial digital signals, and will typically
equalize 120m of Belden 1694A cable at 2.97Gb/s, 200m at 1.
485Gb/
s and 350m at
270Mb/s.The GS2974A is powered from a single +3.3V power supply and consumes
approximately 215mW of power.
4.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a
differential or single-ended configuration. AC-coupling of the inputs is recommended,
as the SDI and SDI inputs are internally biased at approximately 1.8V.
Figure 3-3: Output Circuit
Figure 3-4: MUTE and BYPASS Circuits Figure 3-5: CD Circuit
50
50
SDOSDO
MUTE,
BYPASS
CD
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4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency
response closely matches the inverse of the cable loss characteristic. In addition, the
variation of the frequency response with control voltage imitates the variation of the
inverse cable loss characteristic with cable length.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an internal and
an external AGC filter capacitor providing a steady control voltage for the gain stage. As
the frequency response of the gain stage is automatically varied by the application of
negative feedback, the edge energy of the equalized signal is kept at a constant level
which is representative of the original edge energy at the transmitter. The equalized
signal is also DC restored, effectively restoring the logic threshold of the equalized signal
to its correct level independent of shifts due to AC coupling. The digital output signals
have a nominal voltage of 750mVpp differential, or 375mVpp single ended when
terminated with 50Ω as shown in Figure 4-1.
Figure 4-1: Typical Output Voltage Levels
4.3 Programmable Maximum Cable Length Adjust (MCLADJ)
For SMPTE 259M inputs, the GS2974A incorporates a programmable Maximum Cable
Length Adjust (MCLADJ) threshold.
This feature can be useful in applications where there are multiple input channels using
the GS2974A and the maximum gain can be limited to avoid crosstalk.
The MCLADJ pin acts to change the threshold of the Carrier Detect (CD) pin. When the
input signal drops below a certain threshold, the CD pin will be driven high, indicating
that there is not a valid input signal. In order to enable automatic muting of the output
of the GS2974A, the CD pin should be connected directly to the MUTE pin. In
applications where programmable maximum cable length adjust is not required, the
MCLADJ pin may be left unconnected.
This feature has been designed for use in applications such as routers, where signal
crosstalk and circuit noise cause the Equalizer to output erroneous data when no input
signal is present. The use of a Carrier Detect function with a fixed internal reference
50 50
SDO
SDO
+187.5mV
-187.5mV
VCM = 2.925V
typical
+187.5mV
-187.5mV
VCM = 2.925V
typical
GS2974A HD-LINX™ III Adaptive Cable Equalizer
Data Sheet
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does not solve this problem, since the signal to noise ratio on the circuit board could be
significantly less than the default signal detection level set by the on chip reference.
NOTE: MCLADJ is only recommended for data rates up to 360Mb/s. For data rates above
this, MCLADJ should be left floating.
4.4 Mute and Carrier Detect
The GS2974A includes a MUTE input pin that allows the application interface to mute the
serial digital output at any time. Set the MUTE pin HIGH to mute SDO and SDO. In this
case, the outputs will mute regardless of the setting of the BYPASS pin.
A Carrier Detect output pin (CD) indicates the presence of a valid signal at the input of
the GS2974A. When CD is LOW, the device has detected a valid input on SDI and SDI.
When CD is HIGH, the device has not detected a valid input.
NOTE: This pin may be connected directly to the CD pin to allow mute on loss of carrier.
NOTE: CD will only detect loss of carrier for data rates greater than 19Mb/s. The CD
output pin may be connected directly to the MUTE input pin to enable automatic muting
of the GS2974A when no valid input signal has been detected.
NOTE: If the maximum cable length is exceeded and the device is not in bypass mode
the GS2974A will not assert the CD pin even if a carrier is present.
Table 4-1: Mute Input Table
Mute Function
0SDO and SDO operate normally
1SDO and SDO are forced to a steady
state
Table 4-2: CD Output Table
CD Input Status
0 Valid Input on SDI, SDI pins
1 Input is not valid
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5. Application Information
5.1 PCB Layout
Special attention must be paid to component layout when designing serial digital
interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance
transmission lines are required for PCB traces longer than approximately 1cm. Note the
following PCB artwork features used to optimize performance:
• PCB trace width for HD rate signals is closely matched to SMT component width to
minimize reflections due to change in trace impedance.
• The PCB ground plane is removed under the GS2974A input components to
minimize parasitic capacitance.
• The PCB ground plane is removed under the GS2974A output components to
minimize parasitic capacitance.
• High speed traces are curved to minimize impedance changes.
5.2 Typical Application Circuit
Figure 5-1: GS2974A Typical Application Circuit
GS2974A
SDI
CD
SDI
VEE_D
MUTE
VCC_D
AGC
BYPASS
MCLADJ
VEE_A
NOTE: All resistors in Ohms, capacitors in Farads,
and inductors in Henrys, unless otherwise noted.
* Value dependent on layout
VEE_A
AGC
VCC_A
SDO
SDO
VEE_D
10n
1
10n
SDO
4u7
4u7
+
+
SDO
CD
MUTE
VCC
BYPASS
MCLADJ
470n
6.2n*
75
SDI
1u
75
1u
37R4
VCC
4
56
2
3
8
7
16
12
13
11
14
15
9
10
470n
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Data Sheet
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6. Package & Ordering Information
6.1 Package Dimensions
6.2 Packaging Data
4.00+/-0.05
B
4.00+/-0.05
2X
2X
0.15
0.15
C
C
0.10 C
16X
0.08 C
SEATING PLANE
0.85+/-0.05
0.00-0.05
0.65/2
0.65
DETAIL B
SCALE:NTS
DATUM A OR B
TERMINAL TIP
0.20 REF
DATUM B
0.65
16X
0.35+/-0.05
0.10
0.05 C
AB
C
DATUM A
2.76+/-0.10
0.40+/-0.05
2.76+/-0.10
DETAIL B
CENTER TAB
PIN 1 AREA
A
C
Parameter Value
Package Type 4mm x 4mm 16-pin QFN
Package Drawing Reference JEDEC M0220
Moisture Sensitivity Level 3
Junction to Case Thermal Resistance, θj-c 31.0°C/W
Junction to Air Thermal Resistance, θj-a (at zero airflow) 43.8°C/W
Psi, ψ11.0°C/W
Pb-free and RoHS compliant Yes
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6.3 Recommended PCB Footprint
The Center Pad should be connected to the most negative power supply plane for analog
circuitry in the device (VEE_A) by a minimum of five vias.
NOTE: Suggested dimensions only. Final dimensions should conform to customer
design rules and process optimizations.
6.4 Marking Diagram
Pin 1 ID
G
S
29
7
4
A
XXXXE
3
Y
Y
WW
YYWW - Date Code
YY - 2-digit year
WW - 2-digit week number
XXXX - Lot/Work Order ID
GS2974A HD-LINX™ III Adaptive Cable Equalizer
Data Sheet
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6.5 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed
using the maximum Pb-free reflow profile shown in Figure 6-1. The recommended
standard Pb reflow profile is shown in Figure 6-2.
Figure 6-1: Maximum Pb-free Solder Reflow Profile (Preferred)
Figure 6-2: Standard Pb Solder Reflow Profile
6.6 Ordering Information
25°C
150°C
200°C
217°C
260°C
250°C
Time
Temperature
8 min. max
60-180 sec. max
60-150 sec.
20-40 sec.
3°C/sec max
6°C/sec max
25°C
100°C
150°C
183°C
230°C
220°C
Time
Temperature
6 min. max
120 sec. max
60-150 sec.
10-20 sec.
3°C/sec max
6°C/sec max
Part Number Package Temperature Range
GS2974A GS2974ACNE3 16-pin QFN 0°C to 70°C
GS2974A GS2974ACTE3 16-pin QFN Tape &
Reel (250pcs)
0°C to 70°C
GS2974A GS2974ACNTE3Z 16-pin QFN Tape &
Reel (2,500pcs)
0°C to 70°C
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
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DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make changes to
the product at any time without notice to improve reliability, function or
design, in order to provide the best product possible.
GS2974A HD-LINX™ III Adaptive Cable Equalizer
Data Sheet
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Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of
the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent
infringement.
All other trademarks mentioned are the properties of their respective owners.
GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.
© Copyright 2006 Gennum Corporation. All rights reserved. Printed in Canada.
www.gennum.com
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