1
Features
•Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
•8K Bytes Internal SRAM
•Fully-programmable External Bus Interface (EBI)
– 128 M Bytes of Maximum External Address Space
– 8 Chip Selects
– Software Programmable 8-/16-bit External Databus
•8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 8 External Interrupts, Including a High-priority, Low-latency Interrupt Request
•58 Programmable I/O Lines
•6-channel 16-bit Timer/Counter
– Six External Clock Inputs
– Two Multi-purpose I/O Pins per Channel
•Three USARTs
•Master/Slave SPI Interface
– 8-bit to 16-bit Programmable Data Length
– Four External Slave Chip Selects
•Programmable Watchdog Timer
•8-channel 10-bit ADC
•2-channel 10-bit DAC
•Clock Generator with On-chip Main Oscillator and PLL for Multiplication
– 3 MHz to 20 MHz Frequency Range Main Oscillator
•Real-time Clock with On-chip 32 kHz Oscillator
– Battery Backup Operation and External Alarm
•8-channel Peripheral Data Controller for USARTs and SPIs
•Advanced Power Management Controller (APMC)
– Normal, Wait, Slow, Standby and Power-down Modes
•IEEE 1149.1 JTAG Boundary-scan on All Digital Pins
•
Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at V
DDCORE
= 3.0 V, 85°C
•2.7V to 3.6V Core Operating Range
•2.7V to 5.5V I/O Operating Range
•2.7V to 3.6V Analog Operating Range
•1.8V to 3.6V Backup Battery Operating Range
•2.7V to 3.6V Oscillator and PLL Operating Range
•-40°C to +85°C Temperature Range
•Available in a 176-lead TQFP or 176-ball BGA Package
Description
The AT91M55800A is a member of the Atmel AT91 16-/32-bit microcontroller family,
which is based on the ARM7TDMI processor core. This processor has a high perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption. In addition, a large number of internally banked registers result in
very fast exception handling, making the device ideal for real-time control applications.
The fully-programmable External Bus Interface provides a direct connection to off-chip
memory in as fast as one clock cycle for a read or write operation. An eight-level prior-
ity vectored interrupt controller in conjunction with the Peripheral Data Controller
significantly improve the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combin-
ing the ARM7TDMI processor core with an on-chip SRAM and a wide range of
peripheral functions, analog interfaces and low-power oscillators on a monolithic chip,
the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible
and cost-effective solution to many ultra low-power applications.
AT91
ARM® Thumb®
Microcontroller
s
AT91M55800A
Electrical
Characteristics
Rev. 1727B–01/02
2AT91M55800A
1727B–01/02
Absolute Maximum Ratings*
Operating Temperature (Industrial).......-40°C to +85°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device at these or other con-
ditions beyond those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect device reliability.
Storage Temperature............................-60°C to + 150°C
Voltage on VDDBU Powered Input Pins
with Respect to Ground: ...........................-0.3V to +3.9V
Voltage on Any Other Input Pin
with Respect to Ground......................... ...-0.3V to +5.5V
Maximum Operating Voltage
(VDDCORE, VDDA, VDDPLL and VDDBU) ......................... 3.6V
Maximum Operating Voltage (VDDIO) ....................... 5.5V
DC Output Current (VDDIO)...................................... 4 mA
DC Output Current (VDDBU)..................................... 6 mA
3
AT91M55800A
1727B–01/02
DC Characteristics
The following characteristics are applicable to the Operating Temperature range: TA = -40°C to 85°C, unless otherwise
specified and are certified for a Junction Temperature up to TJ = 100°C.
Notes: 1. VDD is applicable to VDDIO, VDDA and VDDPLL.
2. IO = Output Current.
Table 1. DC Characteristics
Symbol Parameter Conditions Min Typ Max Units
VDDBU DC Supply Backup
Battery 1.8 3.6 V
VDDCORE DC Supply Core 2.7 3.6 V
VDDPLL DC Supply Oscillator and
PLL VDDCORE 3.6 V
VDDA DC Supply Analog I/Os VDDCORE 3.6 V
VDDIO DC Supply Digital I/Os VDDCORE
VDDCORE + 2.0
or 5.5 V
VIL Input Low-level Voltage NRSTBU and WAKEUP pins -0.3 0.3 x VDDBU V
Other pins -0.3 0.8
VIH Input High-level Voltage NRSTBU and WAKEUP pins 0.7 x VDDBU VDDBU + 0.3 V
Other pins 2 VDD + 0.3(1)
VOL Output Low-level Voltage
SHDN pin:
VDDBU = 3.0V
IOL = 0.3 mA(2)
GNDBU + 0.1
V
Other pins:
IOL = 4 mA(2)
IOL = 0 mA(2)
0.4
0.2
VOH Output High-level Voltage
SHDN pin:
VDDBU = 3.0V
IOH = 0.3 mA(2)
VDDBU - 0.1
V
Other pins:
IOH = 4 mA(2)
IOH = 0 mA(2
VDD - 0.4(1)
VDD - 0.2(1)
ILEAK Input Leakage Current 392 nA
IPULL Input Pull-up Current
Blocks powered by VDDBU,
VDDBU = 3.6V, VIN = 0 352
µA
Blocks powered by VDDIO,
VDDA and VDDPLL,
VDD = 3.6V(1), VIN = 0
280
CIN Input Capacitance 176-TQFP Package 6 pF
ISC Static Current
VDD(1) = VDDCORE = 3.6V,
MCK = 0 Hz TA = 25°C 25
µA
All inputs driven TMS,
TDI, TCK, NRST = 1 TA = 85°C 500
4AT91M55800A
1727B–01/02
Power
Consumption
The values in the following tables are measured values in the operating conditions indicated
(i.e., VDDIO = 3.3V, VDDCORE = 3.3V, TA = 25°C) on the AT91EB55 Evaluation Board. They rep-
resent the power consumption on the VDDCORE power supply unless otherwise specified.
Notes: 1. Power consumption on the VDDPLL power supply.
2. With a reference frequency equal to 16 MHz, output frequency of 32 MHz and R = 287Ω,=C1
= 680 pF, C2 = 68 pF as loop filter.
Table 2. Power Consumption
Mode Conditions Consumption Unit
Normal
Fetch in ARM mode out of internal SRAM
All peripheral clocks activated
6.55
mW/MHz
Fetch in ARM mode out of internal SRAM
All peripheral clocks deactivated
4.59
Idle All peripheral clocks activated 3.85
All peripheral clocks deactivated 1.78
Table 3. Power Consumption per Peripheral
Peripheral Consumption Unit
PIO Controller 0.22
mW/MHz
Timer/Counter Channel 0.15
Timer/Counter Block (3 Channels) 0.42
USART 0.40
SPI 0.40
ADC 0.23
DAC 0.29
PLL (1) (2) 2.6 mW
Table 4. Battery Supply Voltage Consumption
Condition Consumption Unit
VDDBU = 3.0 V Power consumption on the VDDBU Power Supply.
Without any capacitor connected to the RTC oscillator pins (XIN32,
XOUT32)
0.9 µA
5
AT91M55800A
1727B–01/02
Thermal and
Reliability
Considerations
Thermal Data In Table 5, the device lifetime is estimated with the MIL-217 standard in the “moderately con-
trolled” environmental model (this model is described as corresponding to an installation in a
permanent rack with adequate cooling air), depending on the device Junction Temperature.
(For details see the section “Junction Temperature” on page 6.)
Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217
model is pessimistic with respect to observed values due to the way the data/models are
obtained (test under severe conditions). The life test results that have been measured are
always better than the predicted ones.
Table 6 summarizes the thermal resistance data related to the package of interest.
Reliability Data The number of gates and the device die size are provided for the user to calculate reliability
data with another standard and/or in another environmental model.
Table 5. MTBF Versus Junction Temperature
Junction Temperature (TJ) (°C) Estimated Lifetime (MTBF) (Year)
100 25
125 14
150 8
175 5
Table 6. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
θJA=Junction-to-ambient thermal resistance Still Air TQFP176 21
°C/W
PBGA176 66
θJC Junction-to-case thermal resistance TQFP176 9.2
PBGA176 20.1
Table 7. Reliability Data
Parameter Data Unit
Number of Logic Gates 524 K gates
Number of Memory Gates 400 K gates
Device Die Size 29.0 mm2
6AT91M55800A
1727B–01/02
Junction
Temperature
The average chip-junction temperature TJ in °C can be obtained from the following:
1.
2.
Where:
•θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 6 on
page 5.
•θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in
Table 6 on page 5.
•θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
•P
D = device power consumption (W) estimated from data provided in the section “Power
Consumption” on page 4.
•T
A = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and thereby
decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the
second equation should be used to compute the resulting average chip-junction temperature
TJ in °C.
TJTAPDθJA
×()+=
TJTAP(Dθ( HEATSINK
×θ
JC ))++=
7
AT91M55800A
1727B–01/02
Conditions
Timing Results The delays are given as typical values in the following conditions:
•VDDIO = 5V
•VDDCORE = 3.3V
• Ambient Temperature = 25°C
• Load Capacitance is 0 pF.
• The output level change detection is (0.5 x VDDIO).
• The input level is (0.3 x VDDIO) for a low-level detection and is (0.7 x VDDIO) for a high level
detection.
• The Master Clock (MCK) source is a crystal oscillator connected to the XIN input.
The minimum and maximum values given in the AC characteristics tables of this datasheet
take into account the process variation and the design. In order to obtain the timing for other
conditions, the following equation should be used.
where:
•δT° is the derating factor in temperature given in Figure 1.
•δVDDCORE is the derating factor for the Core Power Supply given in Figure 2 on page 8.
•tDATASHEET is the minimum or maximum timing value given in this datasheet for a load
capacitance of 0 pF.
•δVDDIO is the derating factor for the IO Power Supply given in Figure 3 on page 9.
•CSIGNAL is the capacitance load on the considered output pin. (1)
•δCSIGNAL is the load derating factor depending on the capacitance load on the related
output pins given in Min and Max in this datasheet.
The input delays are given as typical values.
Note: 1. The user must take into account the package capacitance load contribution (CIN) described
in Table 1 on page 3.
tδT°δVDDCORE tDATASHEET
×()δ
VDDIO CSIGNAL δCSIGNAL
×()×()+()×=
8AT91M55800A
1727B–01/02
Temperature
Derating Factor
Figure 1. Derating Curve for Different Operating Temperatures
Core Voltage
Derating Factor
Figure 2. Derating Curve for Different Core Supply Voltages
0.8
0.9
1
1.1
1.2
1.3
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Operating Temperature (°C)
Derating
Factor
Typ Case Derating Factor is 1
0.5
1
1.5
2
2.5
3
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8
Core Supply Voltage (V)
Derating Factor
Typ Case Derating
Factor is 1
9
AT91M55800A
1727B–01/02
IO Voltage
Derating Factor
Figure 3. Derating Curve for Different IO Supply Voltages
Note: This derating factor in this example is applicable only to timings related to output pins.
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
IO Supply Voltage (V)
Derating Factor
Ty p Cas e
Derating
Factor is 1
10 AT91M55800A
1727B–01/02
Crystal Oscillator Characteristics
Table 8. RTC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
1/(tCPRTC) Crystal Oscillator Frequency 32.768 KHz
CL1, CL2 Internal Load Capacitance
(CL1 = CL2)12 pF
CLEquivalent Load Capacitance CL1 = CL2 = 12 pF 6 pF
Duty Cycle Measured at the MCKO output pin 45 50 55 %
tST Startup Time VDDBU = 1.8V
Without any capacitor connected to
the RTC oscillator pins (XIN32 and
XOUT32)
240 ms
Table 9. Main Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
1/(tCPMAIN) Crystal Oscillator Frequency 3 16 20 MHz
CL1, CL2 Internal Load Capacitance
(CL1 = CL2) 25 pF
CLEquivalent Load Capacitance CL1 = CL2 = 25 pF 12.5 pF
Duty Cycle 45 50 55 %
tST Startup Time VDDPLL = 2.7V
1/(tCPMAIN) = 3 MHz
Without any capacitor connected to the
main oscillator pins (XIN and XOUT)
1.8 ms
11
AT91M55800A
1727B–01/02
Clock Waveforms
Note: 1. Applicable only when MCKO outputs Master Clock.
Figure 4. Clock Waveform
Table 10. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Units
1/(tCPMCK) Master Clock Frequency 41.8 MHz
tCPMCK Master Clock Period 23.9 ns
tCHMCK Master Clock High Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns
tCLMCK Master Clock Low Half-period 0.45 x tCPMCK 0.55 x tCPMCK ns
Table 11. Clock Propagation Times
Symbol Parameter Conditions Min Max Units
tCDLH (1) MCK Rising to MCKO Rising Edge CMCKO = 0 pF 7.5 11.7 ns
CMCKO derating 0.053 0.083 ns/pF
tCDHL (1) MCK Falling to MCKO Falling Edge CMCKO = 0 pF 7.7 12.1 ns
CMCKO derating 0.059 0.092 ns/pF
tCHMCK tCPMCK
MCK
MCKO
tCDLH tCDHL
tCLMCK
0.5 VDDIO
0.5 VDDIO
12 AT91M55800A
1727B–01/02
APMC Characteristics
Backup Battery Reset Signal
Internally to the device, the NRSTBU signal is maintained low for RSTBU1 time after the rising edge of the external signal.
Therefore, the NRSTBU signal needs to be asserted only during the VDDBU power ramp up by the user. This feature covers
the requirement of an NRSTBU signal assertion of 10(tCPRTC) at a minimum at VDDBU power up.
Figure 5. NRSTBU Assertion Sequence
Note: 1. The MCKO Signal is certified to be valid at the NRSTBU Internal Signal rising edge.
Table 12. Master Clock Source Switch Times
MCK Source Switch Time
From To Min Typ Max
RTC Oscillator Output PLL Output 4 x tCPRTC + 3 x tCPPLL
PLL Output RTC Oscillator Output 5 x tCPRTC
Main Oscillator Output PLL Output 5 x tCPRTC + 3 x tCPPLL
PLL Output Main Oscillator Output 4 x tCPRTC + 3 x tCPMAIN
RTC Oscillator Output Main Oscillator Output 3 x tCPRTC + 3 x tCPMAIN
Main Oscillator Output RTC Oscillator Output 5 x tCPRTC
PLL Output Freq. 1 PLL Output Freq. 2 7 x tCPRTC + 3 x tCPPLL2
Table 13. Backup Battery Reset Signal Internal Assertion Delay
Symbol Parameter Typical Internal Delay Units
RSTBU1NRSTBU Internal Assertion Delay 1 s
0V
V
DDBU
RTC Oscillator Output
External Signal
Internal Signal
NRSTBU
V
DDBU
RSTBU
1
MCKO
(1)
13
AT91M55800A
1727B–01/02
Wake Up Signal
Figure 6. Wake Up Signal
Table 14. Wake Up Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
WK1Wake Up Minimum Pulse Width 46 µs
WK
1
Wake Up
14 AT91M55800A
1727B–01/02
Analog
Characteristics
ADC
Table 15. Channel Conversion Time Relative to ADC Clock
Symbol Parameter Typ Units
tCChannel Conversion Time 11 (tCPADC)µs
Table 16. External Voltage Reference Input
Symbol Parameter Min Max Units
VREF
ADVREF Input Voltage Range 2.4 VDDA V
ADVREF Input Resistance 12 24 kΩ
Table 17. Analog Inputs
Parameter Min Typ Max Units
Input Voltage Range 0 VREF V
Input Leakage Current -0.1 0.1 µA
Input Capacitance 30 pF
Table 18. Dynamic Performance
Parameter Conditions Min Max Units
Signal-to-noise Ratio TBD dB
Total Harmonic Distortion TBD dB
Inter-modulation Distortion TBD dB
Channel-to-Channel Isolation TBD dB
Table 19. Transfer Characteristics
Parameter Conditions Min Max Units
Resolution 10 Bit
Integral Non-linearity VDDA = 3.3V ±10%,
ADVREF = VDDA
4LSB
Differential Non-linearity VDDA = 3.3V ±10%,
ADVREF = VDDA
4LSB
Offset Error ±2 LSB
Gain Error ±4 LSB
15
AT91M55800A
1727B–01/02
DAC
Table 20. DAC Timing Characteristics
Parameter Conditions Min Max Units
Channel Setting Time
0.85V to 1.85V
or
1.85V to 0.85V
6µs
Table 21. External Voltage Reference Input
Symbol Parameter Min Max Units
VREF DAVREF Input Voltage Range 2.4 VDDA V
DAVREF Input Resistance 12 24 kΩ
Table 22. Output Op Amp Characteristics
Parameter Conditions Min Max Units
Output Voltage Range 0 VREF V
Input Offset Voltage 10 mV
Output Source Current 5 mA
Output Sink Current 5 mA
Slew Rate Rise or Fall 0.2 V/µs
Startup Time Load = 50 pF=/10 kΩ (in
parallel) 100 µs
Overshoot 100 mV@ vcm 20 %
Table 23. Dynamic Performance
Parameter Conditions Min Max Units
Total Harmonic Distortion TBD dB
Table 24. Transfer Characteristics
Parameter Conditions Min Max Units
Resolution 10 Bit
Integral Non-linearity VDDA = 3.3V ±10%, DAVREF >
2.4V 4LSB
Differential Non-linearity VDDA = 3.3V ±10%, DAVREF >
2.4V 4LSB
Offset Error 2 LSB
Gain Error 4 LSB
16 AT91M55800A
1727B–01/02
AC Characteristics
EBI Signals Relative to MCK
The following tables show timings relative to operating condition limits defined in the section “Timing Results” on page 7
Table 25. General-purpose EBI Signals
Symbol Parameter Conditions Min Max Units
EBI1MCK Falling to NUB Valid CNUB = 0 pF 8.9 17 ns
CNUB derating 0.053 0.092 ns/pF
EBI2MCK Falling to NLB/A0 Valid CNLB = 0 pF 8.3 14.8 ns
CNLB derating 0.053 0.092 ns/pF
EBI3MCK Falling to A1 - A23 Valid CADD = 0 pF 8 15.2 ns
CADD derating 0.053 0.092 ns/pF
EBI4MCK Falling to Chip Select Change CNCS = 0 pF 8.2 15.6 ns
CNCS derating 0.053 0.092 ns/pF
EBI5NWAIT Setup before MCK Rising -0.4 ns
EBI6NWAIT Hold after MCK Rising 5.9 ns
17
AT91M55800A
1727B–01/02
.
Notes: 1. The derating factor is not to be applied to tCHMCK or tCPMCK.
2. n = number of standard wait states inserted.
Table 26. EBI Write Signals
Symbol Parameter Conditions Min Max Units
EBI7
MCK Rising to NWR Active
(No Wait States)
CNWR = 0 pF 8.2 13 ns
CNWR derating 0.059 0.092 ns/pF
EBI8
MCK Rising to NWR Active
(Wait States)
CNWR = 0 pF 9 14.1 ns
CNWR derating 0.059 0.092 ns/pF
EBI9
MCK Falling to NWR Inactive
(No Wait States)
CNWR = 0 pF 8.6 13.5 ns
CNWR derating 0.053 0.083 ns/pF
EBI10
MCK Rising to NWR Inactive
(Wait States)
CNWR = 0 pF 8.9 13.9 ns
CNWR derating 0.053 0.083 ns/pF
EBI11 MCK Rising to D0 - D15 Out Valid CDATA = 0 pF 8.3 15.4 ns
CDATA derating 0 0.086 ns/pF
EBI12 NWR High to NUB Change CNUB = 0 pF 4.8 9.6 ns
CNUB derating 0.053 0.092 ns/pF
EBI13 NWR High to NLB/A0 Change CNLB = 0 pF 4.6 7.4 ns
CNLB derating 0.059 0.092 ns/pF
EBI14 NWR High to A1 - A23 Change CADD = 0 pF 4.4 8.1 ns
CADD = derating 0.059 0.092 ns/pF
EBI15 NWR High to Chip Select Inactive CNCS = 0 pF 4.4 8.6 ns
CNCS derating 0.053 0.083 ns/pF
EBI16
Data Out Valid before NWR High
(No Wait States) (1)
C = 0 pF tCHMCK - 1.9 ns
CDATA derating - 0.086 ns/pF
CNWR derating 0.083 ns/pF
EBI17
Data Out Valid before NWR High
(Wait States) (1)
C = 0 pF n x tCPMCK - 1.5 (2) ns
CDATA derating -0.086 ns/pF
CNWR derating 0.083 ns/pF
EBI18 Data Out Valid after NWR High 4.4 ns
EBI19
NWR Minimum Pulse Width
(No Wait States) (1)
CNWR = 0 pF tCHMCK + 0.3 ns
CNWR derating -0.009 ns/pF
EBI20 NWR Minimum Pulse Width
(Wait States) (1)
CNWR = 0 pF n x tCPMCK - 0.2(2) ns
CNWR derating -0.009 ns/pF
18 AT91M55800A
1727B–01/02
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
3. The derating factor is not to be applied to tCHMCK or tCPMCK.
4. n =number of standard Wait States inserted.
5. Only one of these two timings needs to be met.
Table 27. EBI Read Signals
Symbol Parameter Conditions Min Max Units
EBI21 MCK Falling to NRD Active (1) CNRD = 0 pF 8.5 14.5 ns
CNRD derating 0.059 0.092 ns/pF
EBI22 MCK Rising to NRD Active (2) CNRD = 0 pF 7.7 14.2 ns
CNRD derating 0.059 0.092 ns/pF
EBI23 MCK Falling to NRD Inactive (1) CNRD = 0 pF 8.3 14.5 ns
CNRD derating 0.053 0.083 ns/pF
EBI24 MCK Falling to NRD Inactive (2) CNRD = 0 pF 7.9 12.4 ns
CNRD derating 0.053 0.083 ns/pF
EBI25 D0-D15 in Setup before MCK Falling (5) -2.2 ns
EBI26 D0-D15 in Hold after MCK Falling (5) 6.8 ns
EBI27 NRD High to NUB Change CNUB = 0 pF 5 9.6 ns
CNUB derating 0.053 0.092 ns/pF
EBI28 NRD High to NLB/A0 Change CNLB = 0 pF 4.7 7.4 ns
CNLB derating 0.059 0.092 ns/pF
EBI29 NRD High to A1-A23 Change CADD = 0 pF 4.5 8 ns
CADD derating 0.059 0.092 ns/pF
EBI30 NRD High to Chip Select Inactive CNCS = 0 pF 4.4 8.5 ns
CNCS derating 0.053 0.083 ns/pF
EBI31 Data Setup before NRD High (5) CNRD = 0 pF 11 ns
CNRD derating 0.083 ns/pF
EBI32 Data Hold after NRD High (5) CNRD = 0 pF -3.6 ns
CNRD derating -0.053 ns/pF
EBI33 NRD Minimum Pulse Width (1) (3) CNRD = 0 pF (n +1) x tCPMCK - 1.5 (4) ns
CNRD derating -0.009 ns/pF
EBI34 NRD Minimum Pulse Width (2) (3)
CNRD = 0 pF n x tCPMCK
+ (tCHMCK - 1.7)(4)
ns
CNRD derating -0.009 ns/pF
19
AT91M55800A
1727B–01/02
Notes: 1. If this condition is not met, the action depends on the read protocol intended for use.
• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.
• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.
2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be
programmed.
Table 28. EBI Read and Write Control Signals. Capacitance Limitation
Symbol Parameter Conditions Min Max Units
TCPLNRD(1) Master Clock Low Due to NRD Capacitance CNRD = 0 pF 11.2 ns
CNRD derating 0.083 ns/pF
TCPLNWR(2) Master CLock Low Due to NWR Capacitance CNWR = 0 pF 10.3 ns
CNWR derating 0.083 ns/pF
20 AT91M55800A
1727B–01/02
Figure 7. EBI Signals Relative to MCK
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
NCS
A1 - A23
NRD(1)
D0 - D15 Read
MCK
NUB/NLB/A0
NRD(2)
NWAIT
NWR (No Wait States)
D0 - D15 to Write
NWR (Wait States)
No Wait Wait
EBI1/EBI2
EBI3
EBI4
EBI5EBI6
EBI7EBI9
EBI8EBI10
EBI11
EBI21
EBI22
EBI25 EBI26
EBI23
EBI4
EBI27-30
EBI32
EBI12-15
EBI16 EBI18 EBI18
EBI33
EBI24
EBI34
EBI31
EBI19
EBI20
EBI17
21
AT91M55800A
1727B–01/02
Peripheral Signals
USART Signals The inputs must meet the minimum pulse width and period constraints shown in Table 29 and
Table 30, and represented in Figure 8.
Figure 8. USART Signals
Table 29. USART Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
US1SCK/RXD Minimum Pulse Width 5(tCPMCK/2) ns
Table 30. USART Minimum Input Period
Symbol Parameter Min Input Period Units
US2SCK Minimum Input Period 9(tCPMCK/2) ns
SCK
RXD
US1
US1
US2
22 AT91M55800A
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SPI Signals The inputs must meet the minimum pulse width and period constraints shown in Figure 31 and
Figure 32, and represented in Figure 9.
Figure 9. SPI Signals
Table 31. SPI Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
SPI1SPK/MISO/MOSI/NSS Minimum Pulse Width 3(tCPMCK/2) ns
Table 32. SPI Minimum Input Period
Symbol Parameter Min Input Period Units
SPI2 SPCK Minimum Input Period 5(tCPMCK/2) ns
SPCK
SPCK/MISO/MOSI/NSS
SPI1
SPI1
SPI2
23
AT91M55800A
1727B–01/02
Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a
corresponding output event. This delay is 3(tCPMCK) in Waveform Event Detection mode and
4(tCPMCK) in Waveform Total-count Detection mode. The inputs must meet the minimum pulse
width and minimum input period shown in Table 33 and Table 34, and as represented in Fig-
ure 10.
Figure 10. Timer Input
Reset Signals A minimum pulse width is necessary, as shown in Table 35 and as represented in Figure 11.
Figure 11. Reset Signal
Only the NRST rising edge is synchronized with MCK. The falling edge is asynchronous.
Table 33. Timer Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
TC1TCLK/TIOA/TIOB Minimum Pulse Width 3(tCPMCK/2) ns
Table 34. Timer Input Minimum Period
Symbol Parameter Min Input Period Units
TC2TCLK/TIOA/TIOB Minimum Input Period 5(tCPMCK/2) ns
MCK
TIOA/
TIOB/
TCLK
TC2
TC1
3(tCPMCK/2) 3(tCPMCK/2)
Table 35. Reset Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
RST1NRST Minimum Pulse Width 310 µs
NRST
RST1
24 AT91M55800A
1727B–01/02
Advanced Interrupt
Controller Signals
Inputs must meet the minimum pulse width and minimum input period shown in Table 36 and
Table 37, and represented in Figure 12.
Figure 12. AIC Signals
Parallel I/O Signals The inputs must meet the minimum pulse width shown in Table 38 and represented in Figure
13.
Figure 13. PIO Signal
Table 36. AIC Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
AIC1FIQ/IRQ[6:0] Minimum Pulse Width 3(tCPMCK/2) ns
Table 37. AIC Input Minimum Period
Symbol Parameter Min Input Period Units
AIC2AIC Minimum Input Period 5(tCPMCK/2) ns
MCK
FIQ/IRQ
[6:0]Input
AIC1
AIC2
Table 38. PIO Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
PIO1PIO Input Minimum Pulse Width 3(tCPMCK/2) ns
PIO
Inputs
PIO1
25
AT91M55800A
1727B–01/02
ICE Interface Signals
Figure 14. ICE Interface Signal
Table 39. ICE Interface Timing Specifications
Symbol Parameter Conditions Min Max Units
ICE0NTRST Minimum Pulse Width 19.3 ns
ICE1NTRST High Recovery to TCK
High
0.4 ns
ICE2NTRST High Removal from TCK
High
0.5 ns
ICE3TCK Low Half-period 42.3 ns
ICE4TCK High Half-period 40.3 ns
ICE5TCK Period 82.5 ns
ICE6TDI, TMS, Setup before TCK
High
0.9 ns
ICE7TDI, TMS, Hold after TCK High 0.7 ns
ICE8TDO Hold Time CTDO = 0 pF 6.4 ns
CTDO derating 0 ns/pF
ICE9TCK Low to TDO Valid CTDO = 0 pF 14 ns
CTDO derating 0.092 ns/pF
TCK
ICE3ICE4
ICE7
ICE6
ICE9
ICE8
T
MS/TDI
TDO
ICE0
ICE5
NTRST
ICE1ICE2
26 AT91M55800A
1727B–01/02
JTAG Interface Signals
Table 40. JTAG Interface Timing Specifications
Symbol Parameter Conditions Min Max Units
JTAG0NTRST Minimum Pulse Width 19.3 ns
JTAG1NTRST High Recovery to TCK Toggle -0.1 ns
JTAG2NTRST High Removal from TCK Toggle 2.7 ns
JTAG3TCK Low Half-period 10.9 ns
JTAG4TCK High Half-period 3 ns
JTAG5TCK Period 13.8 ns
JTAG6TDI, TMS Setup before TCK High 1.5 ns
JTAG7TDI, TMS Hold after TCK High 1.9 ns
JTAG8TDO Hold Time CTDO = 0 pF 3.8 ns
CTDO derating 0 ns/pF
JTAG9TCK Low to TDO Valid CTDO = 0 pF 8.5 ns
CTDO derating 0.086 ns/pF
JTAG10 Device Inputs Setup Time -0.4 ns
JTAG11 Device Inputs Hold Time 3.4 ns
JTAG12 Device Outputs Hold Time COUT = 0 pF 5.3 ns
COUT derating 0 ns/pF
JTAG13 TCK to Device Outputs Valid COUT = 0 pF 12.6 ns
COUT derating 0.086 ns/pF
27
AT91M55800A
1727B–01/02
Figure 15. JTAG Interface Signal
TCK
JTAG7
JTAG6
JTAG9
JTAG8
TMS/TDI
TDO
NTRST
JTAG12
JTAG13
Device
Outputs
JTAG5
JTAG4
JTAG3
JTAG0
JTAG1JTAG2
JTAG11
JTAG10
Device
Inputs
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1727B–01/02/0M
