CH7317B Chrontel CH7317B SDVO / RGB DAC Features * * * * * * * * General Description Supporting analog RGB outputs for a display monitor Supporting maximum pixel rate of 165MP/s or graphics resolutions up to 1920x1200* High-speed SDVO (1G~2Gbps) AC-coupled serial differential RGB inputs Supporting monitor connection detection Programmable power management Fully programmable through serial port Configuration through Intel(R) SDVO Opcode Offered in 64-pin LQFP package and 64-pin QFN package * Reduced Blanking Intel(R) Proprietary. The CH7317B is a Display Controller device interfaces seamlessly to HDTV or PC monitors that is equipped with a VGA RGB interface display connector. Its input port, complied with Intel SDVO Specification 1.2, can accept a digital graphics, high-speed, AC-coupled, serialdifferential RGB input signal, and convert it to analog RGB signal for driving the display. The CH7317B supports maximum pixel rate of 165MP/s and is capable of displaying up to 1920x1200 resolution with reduced blanking. The built-in serial port controller will allow the graphics chipset to obtain the monitor's EDID information or communicate with CH7317B internal registers through SDVO Opcodes. In addition, the transmitter is designed with a monitor connection detection algorithm that allows the graphics chipset to read back the connection status through CH7317B internal registers. The CH7317B provides the Boundary-scan test to help system developers to check the interconnection between chip I/O and the printed circuit board for faults. When the device is powered down by the graphics chipset, its current consumption is less than 100uA. The CH7317B is available in 64-pin LQFP and 64-pin QFN packages. AS SPC SPD Serial Port Control RESET* SC _D DC SD _D DC SC _PRO M SD _PRO M SD VO_ Clk(+,-) SDVO_R(+,-) SDVO_G(+,-) SDVO_B(+,-) 2 6 C lock D river 2 Data Latch, Serial to Parallel 10 bit-8 bit decoder VSYN C, HSYN C D AC 2 DAC2 D AC 1 DAC1 D AC 0 DAC0 10 bit DAC ISET Figure 1: Functional Block Diagram 201-0000-097 Rev. 1.7, 11/26/2012 1 CH7317B CHRONTEL Table of Contents 1.0 1.1 1.2 2.0 2.1 2.2 2.3 Package Diagram ___________________________________________________________________4 Pin Description _____________________________________________________________________6 Functional Description________________________________________________________ 8 Input Interface______________________________________________________________________8 VGA Output Operation_______________________________________________________________8 Command Interface _________________________________________________________________9 3.0 Register Control ____________________________________________________________ 12 4.0 Electrical Specifications ______________________________________________________ 13 4.1 4.2 4.3 4.4 4.5 2 Pin-Out ____________________________________________________________________ 4 Absolute Maximum Ratings __________________________________________________________13 Recommended Operating Conditions ___________________________________________________13 Electrical Characteristics ____________________________________________________________14 DC Specifications __________________________________________________________________14 AC Specifications __________________________________________________________________16 5.0 Package Dimensions _________________________________________________________ 18 6.0 Revision History ____________________________________________________________ 20 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL Figures and Tables List of Figures Figure 1: Functional Block Diagram ....................................................................................................................................1 Figure 2: 64-Pin LQFP Package ...........................................................................................................................................4 Figure 3: 64-Pin QFN Package.............................................................................................................................................5 Figure 4: Control Bus Switch .............................................................................................................................................10 Figure 5: NAND Tree Connection .....................................................................................................................................10 Figure 6: 64 Pin LQFP Package .........................................................................................................................................18 Figure 7: 64 Pin QFN Package (8 X 8 mm)........................................................................................................................19 List of Tables Table 1: Pin Description .......................................................................................................................................................6 Table 2: CH7317B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns ..........................................8 Table 3: Various VGA resolutions. ......................................................................................................................................9 Table 4: Video DAC Configurations for CH7317B .............................................................................................................9 Table 5: Signal Order in the NAND Tree Testing ..............................................................................................................11 Table 6: Signals not Tested in NAND Test besides power pins .........................................................................................11 Table 7: Revisions ..............................................................................................................................................................20 201-0000-097 Rev. 1.7, 11/26/2012 3 CH7317B CHRONTEL 1.0 Pin-Out AVDD SDVO_GSDVO_G+ AGND SDVO_RSDVO_R+ AVDD T2 RPLL AGND 58 57 55 54 52 51 50 49 53 SDVO_B+ 59 56 SDVO_CLK+ AGND SDVO_B62 60 SDVO_CLK63 61 AVDD 64 Package Diagram T1 1 48 Reserved SD_DDC 2 47 Reserved SC_DDC 3 46 SD_PROM 4 45 Reserved NC SC_PROM 5 44 NC 6 RESET* 7 AS 8 NC 9 40 DGND 10 39 NC NC NC NC SPD 11 38 NC SPC 12 37 DGND DVDD 13 36 VSYNC BSCAN 14 35 DVDD Reserved 15 34 HSYNC VDAC2 16 33 NC 43 42 22 23 24 25 26 27 28 29 30 31 32 NC DACA[1] NC NC VDAC0 DACA[0] NC NC GDAC0 ISET 41 GDAC1 21 NC 19 VDAC1 20 18 NC DACA[2] 17 Chrontel CH7317B GDAC2 1.1 NC NC Figure 2: 64-Pin LQFP Package 4 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B AVDD SDVO_G- SDVO_G+ AGND SDVO_R- SDVO_R+ AVDD T2 RPLL AGND 58 56 55 53 52 51 50 49 54 SDVO_B+ 59 57 AGND SDVO_B61 60 SDVO_CLKSDVO_CLK+ 63 62 AVDD 1 16 32 VDAC2 ISET 15 31 Reserved GDAC0 14 30 BSCAN 45 NC 44 NC 43 NC 42 NC NC 36 NC 13 29 DVDD 28 12 Reserved 37 DACA[0] NC SPC 46 38 27 11 VDAC0 SPD Reserved 39 26 10 NC DGND Reserved 47 40 25 9 NC NC 24 8 48 41 DACA[1] AS Chrontel CH7317 CH7317B 7317B 23 7 GDAC1 RESET* 22 6 NC NC 21 5 NC SC_PROM 20 4 19 SD_PROM VDAC1 DACA[2] 3 18 SC_DDC 17 2 NC SD_DDC GDAC2 T1 64 CHRONTEL NC NC NC DGND 35 VSYNC DVDD 34 HSYNC 33 NC Figure 3: 64-Pin QFN Package 201-0000-097 Rev. 1.7, 11/26/2012 5 CH7317B CHRONTEL 1.2 Pin Description Table 1: Pin Description Pin # 1,51 Type Out Symbol T1, T2 Description Test These pins are reserved for factory test and default to high impedance. 2 In/Out SD_DDC 3 In/Out SC_DDC 4 In/Out SD_PROM 5 In/Out SC_PROM Routed Serial Port Data Output to DDC This pin functions as the bi-directional data pin of the serial port to DDC receiver. This pin will require a 10K pull-up resistor to the desired high state voltage. Leave open if unused. Routed Serial Port Clock Output to DDC This pin functions as the clock bus of the serial port to DDC receiver. This pin will require a 10K pull-up resistor to the desired high state voltage. Leave open if unused. Routed Data Output to PROM This pin functions as the bi-directional data pin of the serial port for PROM on ADD2 card. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused. Routed Clock Output to PROM This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pin will require a pull-up resistor to the desired high state voltage. Leave open if unused. 7 In RESET* Reset* Input (Internal pull-up) When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port register. This pin is 3.3V compliant. 8 In AS Address Select (Internal pull-up) This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS is low the address is 72h, when high the address is 70h. 11 In/Out SPD Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port and operates with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external 4K - 9K pull-up resistor to 2.5V. 12 In/Out SPC Serial Port Clock Input This pin functions as the clock input of the serial port and operates with inputs from 0 to 2.5V. This pin requires an external 4K - 9K pull-up resistor to 2.5V. 14 In BSCAN BSCAN (Internal pull-down) This pin should be pulled low with a 10K ohm resistor. This pin enables the boundary scan for in-circuit testing. Voltage level is 0 to DVDD. 15 In Reserved Reserved (Internal pull-down) 20,24,28 Out DACA[2:0] This pin should be pulled low with a 10K ohm resistor. DAC Output A Video Digital-to-Analog outputs. RGB Bypass outputs. Each output is capable of driving a 75-ohm doubly terminated load. 6 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL Table 1: Pin Description (contd.) Pin # 32 Type In Symbol ISET Description Current Set Resistor Input This pin sets the DAC current. A 1.2Kohm resistor should be connected between this pin and DAC ground (pin 31) using short and wide traces. 34 Out HSYNC Horizontal Sync Output 36 Out VSYNC VSYNC 46 47 48 50 Out Out Out In Reserved Reserved Reserved RPLL This pin should be left open. This pin should be left open. This pin should be left open. PLL Resistor Input External resistor 10Kohm should be connected between this pin and pin 49. SDVO Data Channel Inputs A buffered version of VGA horizontal sync can be acquired from this pin. A buffered version of VGA vertical sync can be acquired from this pin. 53,54,56,57 In 59,60 62,63 SDVO_R+/-, These pins accept 3 AC-coupled differential pair of inputs from a digital video port SDVO_G+/-, of a graphics controller. These 3 pair of inputs can be R, G, B or Y, Cr, Cb. SDVO_B+/SDVO_CLK+/- Differential Clock Input associated with SDVOB Data channel (SDVOB_R+/-, In SDVOB_G+/-, SDVOB_B+/-) The range of this clock pair is 100~200MHz. For specified pixel rates in specified modes this clock pair will run at an integer multiple of the pixel rate. Refer to to section 2.1.3 for details. 13,35 10,37 16 17 19 23 27 31 52,58,64 49,55,61 Power Power Power Power Power Power Power Power Power Power 201-0000-097 DVDD DGND VDAC2 GDAC2 VDAC1 GDAC1 VDAC0 GDAC0 AVDD AGND Rev. 1.7, Digital Supply Voltage (2.5V) Digital Ground DAC Supply Voltage (3.3V) DAC Ground DAC Supply Voltage (3.3V) DAC Ground DAC Supply Voltage (3.3V) DAC Ground Analog Supply Voltage (2.5V) Analog Ground 11/26/2012 7 CH7317B CHRONTEL 2.0 Functional Description 2.1 2.1.1 Input Interface Overview One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate (SDVOB_CLK+/-). The CH7317B de-serializes the input into 10-bit parallel data with synchronization and alignment. Then the 10-bit characters are mapped into 8-bit color data or control data (HSYNC, VSYNC, DE). 2.1.2 Interface Voltage Levels All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The differential p-p output voltage has a min of 0.8V, with a max of 1.2V. 2.1.3 Input Clock and Data Timing A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of the SDVOB_CLK+ edge. The skew among input lanes is required to be no larger than 2ns. The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x, 4x depending on the pixel rate) so that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a multiple of the pixel rate, there isn't enough pixel data to fill the data channels. Dummy fill characters (`0001111010') are used to stuff the data stream. The CH7317B supports the following clock rate multipliers and fill patterns shown in Table 2. Table 2: CH7317B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns Pixel Rate Clock Rate - Multiplier Stuffing Format Data Transfer Rate - Multiplier 25~50 MP/s 100~200 MHz - 4xPixel Rate Data, Fill, Fill, Fill 1.00~2.00Gbits/s - 10xClock Rate 50~100 MP/s 100~200 MHz - 2xPixel Rate Data, Fill 1.00~2.00Gbits/s - 10xClock Rate 100~200 MP/s 100~200 MHz - 1xPixel Rate Data 1.00~2.00Gbits/s - 10xClock Rate 2.1.4 Synchronization Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during the blank period. The CH7317B synchronizes during the initialization period and subsequently uses the blank periods to resynch to the data stream. 2.2 VGA Output Operation The CH7317B can operate in VGA RGB Bypass mode. In VGA RGB Bypass mode, data from the graphics device, after proper decoding, are bypassed directly to the video DACs to implement a second RGB DAC function. Sync signals, after proper decoding, are buffered internally, and can be output to drive the VGA Monitor. The CH7317B can support a pixel rate of 200MHz. This operating mode uses 8-bits of three of the DAC's 10-bit range, and provides a nominal signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75 doubly terminated load. No scaling, scan conversion or flicker filtering is applied in VGA RGB Bypass modes. Table 3 lists some of the VGA resolutions. 8 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL Table 3: Various VGA resolutions. Name Resolution 320x200 QVGA 320x240 400x300 640x350, 640x400 VGA 640x480 512x384 704x480, 704x576 720x350, 720x400, 720x480, 720x540, 720x576 768x480, 768x576 SVGA/WSVGA 800x600 832x624 848x480 920x766 960x600 1024x600 XGA/WXGA 1024x768 1124x768 1152x720 1280x768, 1280x720, 1280x800, 1280x960 SXGA/WSXGA 1280x1024 1360x768, 1360x1024, 1366x768, 1466x768 SXGA+/WSXGA+ 1400x1050 1400x1200 1536x960 1680x1050 UXGA/WUXGA 1600x1200 1704x960 1920x1080 1920x1200 1 Note: 1. With reduced blanking. Table 4 below lists the DAC output configurations of the CH7317B. Table 4: Video DAC Configurations for CH7317B Output Type DACA[0] DACA[1] VGA RGB B G 2.3 DACA[2] R Command Interface Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7317B accepts incoming control clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card PROM, DDC, or CH7317B internal registers. The control bus is able to run up to 1MHz when communicating with internal registers, up to 400kHz for the PROM and up to 100kHz for the DDC. 201-0000-097 Rev. 1.7, 11/26/2012 9 CH7317B CHRONTEL Internal Device Registers observer control the switch on/off SPC, SPD DDC default position PROM Figure 4: Control Bus Switch Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this stage, the CH7317B observes the control bus traffic. If the observing logic sees a control bus transaction destined for the internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal registers. In the condition that traffic is to the internal registers, an Opcode command is used to set the redirection circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at the stage of traffic to DDC occurs on observing a STOP after a START on the control bus. 2.3.1 Boundary scan Test CH7317B provides a called "NAND TREE Testing" to verify IO cell function at the PC board level. This test will check the interconnection between chip I/O and the printed circuit board for faults (soldering, bend leads, open printed circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input mode, connects all inputs with NAND gates as shown in the figure below and switches each signal to high or low according to the sequence in Table 11. The test results then pass out at pin 51 (T2). Figure 5: NAND Tree Connection Set BSCAN =1; (internal weak pull-low) Set all signals listed in to 1. Set all signals listed in to 0, toggle one by one with certain time period, suggested 100 ns. Pin 51 (T2) will change its value each time an input value changed. 10 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL Table 5: Signal Order in the NAND Tree Testing Order 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Name SD_DDC SC_DDC SD_PROM SC_ PROM RESETB AS SPD SPC DACA[2] DACA[1] DACA[0] ISET HSYNC VSYNC Reserved Reserved Reserved T2 LQFP Pin 2 3 4 5 7 8 11 12 20 24 28 32 34 36 46 47 48 51 Table 6: Signals not Tested in NAND Test besides power pins Pin Name SDVO_R+ SDVO_RSDVO_G+ SDVO_GSDVO_B+ SDVO_BSDVO_CLK+ SDVO_CLKRESET* BSCAN Reserved T1 201-0000-097 Rev. 1.7, LQFP Pin 53 54 56 57 59 60 62 63 7 14 15 1 11/26/2012 11 CH7317B CHRONTEL 3.0 Register Control The CH7317B is controlled via a serial control port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device will retain all register values during power down modes. Registers 00h to 11h are reserved for Opcode use. All registers except bytes 00h to 11h are reserved for internal factory use. For details regarding Intel(R) SDVO Opcodes, please contact Intel(R). 12 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL 4.0 Electrical Specifications 4.1 Absolute Maximum Ratings Symbol Description Min All 2.5V power supplies relative to GND All 3.3V power supplies relative to GND -0.5 -0.5 TSC Analog output short circuit duration TAMB Ambient operating temperature (Commercial / Automotive Grade 4) Ambient operating temperature (Industrial / Automotive Grade 3) TAMB Typ Max Units 3.5 5.0 V Indefinite Sec 0 70 C -40 85 C -65 150 C TSTOR Storage temperature TJ Junction temperature 150 C TVPS Vapor phase soldering (5 second) Vapor phase soldering (11 second) Vapor phase soldering (1 minute) 260 245 225 C Note: 1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated under the normal operating condition of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor phase soldering apply to all standard and lead free parts. 2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can induce destructive latch-up. 4.2 Recommended Operating Conditions Symbol Description Min Typ Max Units AVDD Analog Power Supply Voltage 2.375 2.5 2.625 V DVDD Digital Power Supply Voltage 2.375 2.5 2.625 V VDAC DAC Power Supply 3.100 3.3 3.500 V VDD33 Generic for all 3.3V supplies 3.100 3.3 3.500 V VDD25 Generic for all 2.5V supplies 2.375 2.5 2.625 V Rset Resistor on ISET pin (32) 1188 1200 1212 RRPLL Resistor on RPLL pin (50) 9900 10000 10100 201-0000-097 Rev. 1.7, 11/26/2012 13 CH7317B CHRONTEL 4.3 Electrical Characteristics (Operating Conditions: TA = 0C to 70C for parts qualified as Commercial / Automotive Grade 4, TA = -40C to 85C for parts qualified as Industrial / Automotive Grade 3, VDD25 =2.5V 5%, VDD33 = 3. 3V 5%,) Symbol Description Min Typ Max Units 10 10 10 bits Video D/A Resolution Full scale output current 17.63 Video level error 10 % 100 110 mA Total VDD33 supply current (3.3V supplies) with VGA ByPass output and 1024x768@60Hz input 75 80 mA Total Power Down Current 0.1 IVDD25,VGA Total VDD25 supply current (2.5V supplies) with VGA ByPass output and 1024x768@60Hz input IVDD33,VGA IPD 4.4 mA mA DC Specifications Symbol Description Test Condition Typ Max Units 1.200 V VRX-DIFFp-p SDVO Receiver Differential Input Peak to Peak Voltage ZRX-DIFF-DC SDVO Receiver DC Differential Input Impedance 80 100 120 ZRX-COM-DC SDVO Receiver DC Common Mode Input Impedance 40 50 60 Impedance allowed when receiver terminations are first turned on 5 50 60 Impedance allowed when receiver terminations are not powered 20k 200k 0.8 1.2 V 0.4 V ZRX-COM-INITIAL- SDVO Receiver Initial DC Common Mode Input Impedance DC ZRX-COM-HighIMP-DC TVCLK Differential Pk - Pk Output Voltage VPP_TVCLK 0.175 VSDOL 1 SPD (serial port data) Output Low Voltage VSPIH 2 Serial Port (SPC, SPD) Input High Voltage 1.0 VDD33 + 0.5 V VSPIL 2 Serial Port (SPC, SPD) Input Low Voltage GND-0.5 0.4 V VHYS VDDCIH VDDCIL VPROMIH 14 SDVO Receiver Powered Down DC Common Mode Input Impedance VRX-DIFFp-p = 2 * VRX-D+ - VRX-D- Min IOL = 2.0 mA Hysteresis of Serial Port Inputs 0.25 V DDC Serial Port Input High Voltage 4.0 +5V +0.5 DDC Serial Port Input Low Voltage GND-0.5 0.4 PROM Serial Port Input High Voltage 4.0 +5V +0.5 V V 201-0000-097 Rev. 1.7, V 11/26/2012 CH7317B CHRONTEL Symbol Description VPROMIL PROM Serial Port Input Low Voltage VSD_DDCOL 3 Test Condition SPD (serial port data) Output Low Voltage from SD_DDC (or SD_EPROM) Min Typ Max Units V GND-0.5 Input is VINL at SD_DDC or SD_EPROM. 0.4 0.9*VINL + 0.25 V 0.933*VINL + 0.35 V 0.933*VINL + 0.35 V 2.7 VDD33 + 0.5 V GND-0.5 0.5 V 2.0 VDD25 + 0.5 V GND-0.5 0.5 V 4.0k pull-up to 2.5V. VDDCOL SC_DDC and SD_DDC Output Input is VINL at SPC and SPD. Low Voltage 5.6k pull-up to 5.0V. 4 VEPROMOL 5 SC_EPROM and SD_EPROM Output Low Voltage Input is VINL at SPC and SPD. 5.6k pull-up to 5.0V. VMISC1IH 6 RESET* Input High Voltage VMISC1IL 6 RESET* Input Low Voltage 7 AS, BSCAN Input High Voltage 7 AS, BSCAN Input Low Voltage DVDD=2.5V IPU AS, RESET* Pull-Up Current VIN = 0V 10 30 uA IPD BSCAN VIN = 2.5V 10 30 uA HSYNC, VSYNC Output High Voltage IOH = -0.4mA 2.0 HSYNC, VSYNC Output Low Voltage IOL = 3.2mA VMISC2IH VMISC2IL Pull-Down Current VSYNCOH VSYNCOL 8 8 V 0.4 V Notes: 1. VSDOL is the SPD output low voltage when transmitting from internal registers, not from DDC or EEPROM. 2. VSPIH and VSPIL are the serial port (SPC and SPD) input low voltage when transmitting to internal registers. Separate requirements may exist for transmission to the DDC and EEPROM. 3. VSD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_EPROM is VINL. Maximum output voltage has been calculated with the worst case of pull-up of 4.0k to 2.5V on SPD. 4. VDDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is VINL. Maximum output voltage has been calculated with 5.6k pull-up to 5V on SC_DDC and SD_DDC. 5. VEPROMOL is the output low voltage at the SC_EPROM and SD_EPROM pins when the voltage at SPC and SPD is VINL. Maximum output voltage has been calculated with 5.6k pull-up to 5V on SC_EPROM and SD_EPROM. 6. VMISC1 - refers to RESET* input which is 3.3V compliant. 7. VMISC2 - refers to AS, BSCAN, which are 2.5V compliant 8. VSYNC - refers to HSYNC and VSYNC outputs. 201-0000-097 Rev. 1.7, 11/26/2012 15 CH7317B CHRONTEL 4.5 AC Specifications Symbol Description UIDATA fSDVOB_CLK Min Typ Max Units SDVO Receiver Unit Interval for Data Channels Typ. - 300ppm 1/[Data Transfer Rate] Typ. + 300ppm ps SDVO CLK Input Frequency 100 200 MHz SDVO Receiver Pixel frequency 25 165 MHz fSYMBOL SDVO Receiver Symbol frequency 1 2 GHz tRX-EYE SDVO Receiver Minimum Eye Width fPIXEL tRX-EYE-JITTER Test Condition 0.4 UI SDVO Receiver Max. time between jitter median and max. deviation from median 0.3 UI VRX-CM-ACp SDVO Receiver AC Peak Common Mode Input Voltage 150 mV RLRX-DIFF Differential Return Loss 50MHz - 1.25GHz 15 dB RLRX-CM Common Mode Return Loss 50MHz - 1.25GHz 6 dB SPC, SPD Rise Time Standard mode 100k 1000 ns (20% - 80%) Fast mode 400k 300 ns 1M running speed 150 ns TSPR TSPF SPC, SPD Fall Time Standard mode 100k 300 ns (20% - 80%) Fast mode 400k 300 ns 1M running speed 150 ns TPROMR SC_PROM, SD_PROM Rise Time (20% - 80%) Fast mode 400K 300 ns TPROMF SC_PROM, SD_PROM Rise Time (20% - 80%) Fast mode 400K 300 ns TDDCR SC_DDC, SD_DDC Rise Time (20% - 80%) Standard mode 100k 1000 ns TDDCF SC_DDC, SD_DDC Fall Standard mode 100k 300 ns Time (20% - 80%) 1 TDDCR-DELAY 1 TDDCF-DELAY SC_DDC, SD_DDC Rise Time Delay (50%) Standard mode 100k 0 ns SC_DDC, SD_DDC Fall Standard mode 100k 3 ns Time Delay (50%) tSKEW tR SDVO Receiver Total Lane to Lane Skew of Inputs Across all lanes HSYNC and VSYNC (when configured as outputs) 15pF load 2 ns 1.50 ns DVDD = 2.5V Output Rise Time (20% - 80%) 16 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL tF H and V (when configured as outputs) 15pF load 1.50 ns DVDD = 2.5V Output Fall Time (20% - 80%) Notes: 1. Refers to the figure below, the delay refers to the time pass through the internal switches. 3.3V typ. 2.5V typ. R=5K To SPC/SPD pin To DDC pin 201-0000-097 Rev. 1.7, 11/26/2012 17 CH7317B CHRONTEL 5.0 Package Dimensions A B 1X 4 I 1 A B H 5 3X C D J LEAD CO-PLANARITY E .004 " F G Figure 6: 64 Pin LQFP Package Table of Dimensions No. of Leads 64 (10 X 10 mm) MilliMIN meters MAX Notes: 1. 2. 3. 4. 5. 18 A 11.80 12.20 B 10.00 C 0.50 D 0.17 0.27 SYMBOL E F 1.35 0.05 1.45 0.15 G 1.00 H 0.45 0.75 I 0.09 0.20 J 0 7 Conforms to JEDEC standard JESD-30 MS-026D. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. (1X) Corner in quadrant with Pin1 identifier (dot) is always chamfered. Exact shape of chamfer is optional. (3X) Corners in quadrants without Pin1 identifier (dot) may be square or chamfered. Exact shape of corner or chamfer is optional. 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL TOP VIEW BOTTOM VIEW A B 64 49 48 1 Pin 1 3 C A 33 16 17 F 32 4 E D (4x) 2 I G H Figure 7: 64 Pin QFN Package (8 X 8 mm) Table of Dimensions No. of Leads 64 (8 X 8 mm) MilliMIN meters MAX A 7.9 8.1 B 4.85 6.3 C 4.85 6.3 D 0.4 SYMBOL E 0.15 0.25 F 0.30 0.50 G 0.7 1 H 0 0.05 I 0.2 Notes: 1. Conforms to JEDEC standard JESD-30 MO-220. 2 Side of body may be square or curved. 3 Exposed pad may have chamfer in area of Pin 1. 4 Pins may protrude from edge of body by 0.05 mm. 201-0000-097 Rev. 1.7, 11/26/2012 19 CH7317B CHRONTEL 6.0 Revision History Table 7: Revisions Rev. # Date 1.0 04/06/09 1.1 05/06/09 1.2 1.3 05/14/09 06/12/09 1.4 04/04/10 1.5 1.6 01/14/11 05/08/12 Section All 2.2, 2.3 4.2 4.4, 4.5 1.0 1.2 5.0 Figure 1, Table 1 Table 3 4.1, 4.2 1.2, 4.1, 4.2, 4.3, 5.0 1.7 11/26/12 1.2 20 Description Official release. Update Table 3, Table 4 and Figure 4. Update Ambient operating temperature. Add some parameters and notes. Update Figure 2 and Figure 3, Pin definition of Pin34. Update Table 1, Pin definition of Pin34. Update Figure 7, QFN package drawing. Make some pin type clear. Make some description more clear. Update ambient operating temperature. Update ambient operating temperature into Commercial / Automotive Grade 4 and Industrial / Automotive Grade 3. Unify the description of pin 14 and pin 15. Modify some "Absolute Maximum Ratings". Add some notes for "Package Dimensions". Pin 14 and pin 15 should be connected to ground through a 10K resistor. 201-0000-097 Rev. 1.7, 11/26/2012 CH7317B CHRONTEL Disclaimer This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death. ORDERING INFORMATION Part Number Package Type Number of Pins Voltage Supply Temperature Grade CH7317B-TF Lead Free LQFP 64 2.5V & 3.3V Commercial / Automotive Grade 4 CH7317B-TF-I Lead Free LQFP 64 2.5V & 3.3V Industrial / Automotive Grade 3 64 2.5V & 3.3V Commercial / Automotive Grade 4 64 2.5V & 3.3V Industrial / Automotive Grade 3 CH7317B-TF-TR CH7317B-TF-I-TR Lead Free LQFP in Tape & Reel Lead Free LQFP in Tape & Reel CH7317B-BF Lead Free QFN 64 2.5V & 3.3V Commercial / Automotive Grade 4 CH7317B-BF-I Lead Free QFN 64 2.5V & 3.3V Industrial / Automotive Grade 3 64 2.5V & 3.3V Commercial / Automotive Grade 4 64 2.5V & 3.3V Industrial / Automotive Grade 3 CH7317B-BF-TR CH7317B-BF-I-TR 201-0000-097 Rev. 1.7, Lead Free QFN in Tape & Reel Lead Free QFN in Tape & Reel 11/26/2012 21 CH7317B CHRONTEL Chrontel 2210 O'Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com 2012 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 22 201-0000-097 Rev. 1.7, 11/26/2012