1/42April 2011
M29W160ET
M29W160EB
16 Mbit (2Mb x8 or 1Mb x16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
SUPPLY VOLTAGE
–V
CC = 2.7V to 3.6V for Program, Erase
and Read
ACCESS TIMES: 70, 90ns
PROGRAMMING TIME
– 10µs per Byte/Word typical
35 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 3 Parameter and 31 Main Blocks
PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program
algorithms
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
TEMPORARY BLOCK UNPROTECTION
MODE
COMMON FLASH INTERFACE
– 64 bit Security Code
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W160ET: 22C4h
– Bottom Device Code M29W160EB: 2249h
Automotive Grade Parts Available
Figure 1. Packages
BGA
TSOP48 (N)
12 x 20mm
TFBGA48 (ZA)
6 x 8mm
FBGA
FBGA64 (ZS)
11 x 13 mm
M29W160ET, M29W160EB
2/42
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. FBGA 64-ball Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/Block Temporary Unprotect ( RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3/42
M29W160ET, M29W160EB
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Program/Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 13.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline, top view . 27
Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 27
Figure 17.TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Outline, bottom view. . . . . 28
Table 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Mechanical Data. . . . . . . . 28
Figure 18.FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package outline, bottom view29
Table 18. FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package mechanical data. . 29
M29W160ET, M29W160EB
4/42
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 20. Top Boot Block Addresses, M29W160ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 21. Bottom Boot Block Addresses, M29W160EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 23. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 24. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 26. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 28. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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M29W160ET, M29W160EB
SUMMARY DESCRIPTION
The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Figures 6 and 7, Block Addresses.
The first or last 64 KBytes have been divided into
four additional blocks. The 16 KByte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 KByte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered TSOP48 (12 x 20mm) and
TFBGA48 (0.8mm pitch) packages. The memory
is supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram Table 1. Signal Names
AI06849B
20
A0-A19
W
DQ0-DQ14
VCC
M29W160ET
M29W160EB
E
VSS
15
G
RP
DQ15A–1
RB
BYTE
A0-A19 Address Inpu ts
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
M29W160ET, M29W160EB
6/42
Figure 3. TSOP Connections
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
A7
DQ7
NC
NC
AI06850
M29W160ET
M29W160EB
12
1
13
24 25
36
37
48
DQ8
NC
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14 VSS
E
A0
RP
VSS
7/42
M29W160ET, M29W160EB
Figure 4. TFBGA Connections (Top view through package)
AI02985B
654321
VSS
DQ15
A–1
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
NC
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 NC
A16
BYTE
G
F
E
B
A
D
C
H
M29W160ET, M29W160EB
8/42
Figure 5. FBGA 64-ball Connections (Top view through package)
654321
VSS
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
VPP
/
WP
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 NC
A16
BYTE
C
B
A
E
D
F
G
H
DQ15
A–1
AI12719_16-Mbit_bis
87
NC
VCC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
9/42
M29W160ET, M29W160EB
Figure 6. Block Addresses (x8)
Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.
AI06851
16 KByte
1FFFFFh
1FC000h
64 KByte
01FFFFh
010000h
64 KByte
00FFFFh
000000h
M29W160ET
Top Boot Block Addresses (x8)
32 KByte
1F7FFFh
1F0000h
64 KByte
1E0000h
1EFFFFh
Total of 31
64 KByte Blocks
16 KByte
1FFFFFh
1F0000h 64 KByte
64 KByte
003FFFh
000000h
M29W160EB
Bottom Boot Block Addresses (x8)
32 KByte
1EFFFFh
01FFFFh 64 KByte
1E0000h
010000h
Total of 31
64 KByte Blocks
00FFFFh
008000h
8 KByte
8 KByte
1FBFFFh
1FA000h
1F9FFFh
1F8000h
8 KByte
8 KByte
007FFFh
006000h
005FFFh
004000h
M29W160ET, M29W160EB
10/42
Figure 7. Block Addresses (x16)
Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.
AI06852
8 KWord
FFFFFh
FE000h
32 KWord
0FFFFh
08000h
32 KWord
07FFFh
00000h
M29W160ET
Top Boot Block Addresses (x16)
16 KWord
FBFFFh
F8000h
32 KWord
F0000h
F7FFFh
Total of 31
32 KWord Blocks
8 KWord
FFFFFh
F8000h 32 KWord
32 KWord
01FFFh
00000h
M29W160EB
Bottom Boot Block Addresses (x16)
16 KWord
F7FFFh
0FFFFh 32 KWord
F0000h
08000h
Total of 31
32 KWord Blocks
07FFFh
04000h
4 KWord
4 KWord
FDFFFh
FD000h
FCFFFh
FC000h
4 KWord
4 KWord
03FFFh
03000h
02FFFh
02000h
11/42
M29W160ET, M29W160EB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Sign al
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the Program/
Erase Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading t he Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 15 and Figure 15, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, VOL. Ready/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 15 and Figure
15, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organizat ion Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16- bit Bu s modes of
the memory. When Byte/Word Organization Se-
lect is Low, VIL, the memory is in 8-bit mode, when
it is High, VIH, the memory is in 16-bit mode.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC3.
VSS Ground. The VSS Ground is the reference for
all voltage measurements. The two VSS pins of the
device must be connected to the system ground.
M29W160ET, M29W160EB
12/42
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs, applying a Low signa l, VIL, to Chip Enab le
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 12, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enab le
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 13 and 14, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations un-
til the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus opera-
tions can be performed to read the Electronic Sig-
nature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usu-
ally used in applications. They require VID to be
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow d a ta to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Blocks Unprotect opera-
tions are described in Appendix C.
Table 2. Bus Operations, BYTE = VIL
Note: X = VIL or VIH.
Operation E G W Address Inputs
DQ15A–1, A0-A19 Data Input s/Outputs
DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Writ e VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z 20h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z C4h (M29W160ET)
49h (M29W160EB)
13/42
M29W160ET, M29W160EB
Table 3. Bus Operations, BYTE = VIH
Note: X = VIL or VIH.
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 4, or 5, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH. The Manufacturer
Code for Numonyx is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH. The
Device Code for the M29W160ET is 22C4h and
for the M29W160EB is 2249h.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, and A12-A19 specifying th e address of
the block. The other address bits may be set to ei-
ther VIL or VIH. If the addressed b lock is protected
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data, and starts
the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory returns to the Read mode, unless an error
Operation E G W Address Inputs
A0-A19 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Writ e VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH X Hi-Z
Standby VIH X X X Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH 0020h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH 22C4h (M29W160ET)
2249h (M29W160EB)
M29W160ET, M29W160EB
14/42
has occurred. When an error occurs the memory
continues to output the Status Register. A Read/
Reset command must be issued to reset the error
condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass co mmand.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data,
and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block ca nnot be programmed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 6. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
15/42
M29W160ET, M29W160EB
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend with in
the Erase Suspend Latency Time (refer to Table 6
for value) of the Erase Suspend Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Sele ct, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device is in the Read
Array mode, or when the device is in Auto Select
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operation s read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Auto Select mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Auto Select
mode.
See Appendix B, Tables 22, 23, 24, 25, 26 and 27
for details on the information contained in the
Common Flash Interface (CFI) memory area.
M29W160ET, M29W160EB
16/42
Table 4. Commands, 16-bit mode, BYTE = VIH
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the c ommands; A11-A 19, DQ8-DQ14 and DQ15 are Don ’t
Care. DQ15A–1 is A–1 wh en BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode. Add add itional Blocks during Block Erase Command with additional
Bus Write Operations until Timeout Bit is set.
Unlock By pass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock By pass Res e t . After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After th e Erase Suspend command read non -erasing memory blocks as normal, issue Aut o Select and Program com-
mands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-
gram/Erase Cont roller completes and the memory returns to Read Mode.
CFI Query. Command is valid when device is ready to read array data or when device is in Auto Select mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3555 AA2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 A A 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 55 98
17/42
M29W160ET, M29W160EB
Table 5. Commands, 8-bit mode, BYTE = VIL
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the c ommands; A11-A 19, DQ8-DQ14 and DQ15 are Don ’t
Care. DQ15A–1 is A–1 wh en BYTE is VIL or DQ15 when BYTE is VIH.
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode. Add add itional Blocks during Block Erase Command with additional
Bus Write Operations until Timeout Bit is set.
Unlock By pass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock By pass Res e t . After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After th e Erase Suspend command read non -erasing memory blocks as normal, issue Aut o Select and Program com-
mands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-
gram/Erase Cont roller completes and the memory returns to Read Mode.
CFI Query. Command is valid when device is ready to read array data or when device is in Auto Select mode.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Unlock Byp ass 3 AAA AA 555 55 AAA 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 AA 98
M29W160ET, M29W160EB
18/42
Table 6. Program/Erase Times and Program/Erase Endurance Cycles
Note: 1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles .
4. Maximum value measured at worst case conditions for both temperature and VCC.
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Regist er a re summar ized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 8, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a pro tecte d block,
the operation is aborted, no err or is signalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
ror is signalled and DQ6 toggles for approximately
1µs.
Figure 9, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset comma nd must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Parameter Min Typ (1,2) Max(2) Unit
Chip Erase 29 60 (3) s
Block Erase (64 KBytes ) 0.8 1.6 (4) s
Erase Suspend Latency Time 20 25 (4) µs
Program (Byte or Word) 13 200 (3) µs
Chip Program (Byte by Byte) 26 120 (3) s
Chip Program (Word by Word) 13 60 (3) s
Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years
19/42
M29W160ET, M29W160EB
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operatio ns from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Err or Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Table 7. Status Register Bits
Note: Unspecified data bits should be ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle 0 – – 0
Program During Erase
Suspend Any Address DQ7 Toggle 0 – – 0
Program Error Any Address DQ7 Toggle 1 – – 0
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend Erasing Block 1 No Toggle 0 – Tog gle 1
Non-Erasing Block Data read as normal 1
Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0
Faulty Block Address 0 Togg le 1 1 Toggle 0
M29W160ET, M29W160EB
20/42
Figure 8. Data Polling Flowchart Figure 9. Data Toggle Flowchart
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the Numonyx SURE Pro-
gram and other relevant quality documents.
Table 8. Absolute Maximum Ratings
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum volt age may overshoot to VCC +2V during transi tion and fo r less than 20 ns during transitio ns.
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI03598
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V
VCC Supply Volt age –0.6 4 V
VID Identification Voltage –0.6 13.5 V
21/42
M29W160ET, M29W160EB
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
Figure 10. AC Measurement I/O Waveform Figure 11. AC Measurement Load Circuit
Parameter
M29W160E
Unit70 7A 80 1
1.This option is allowed on ly with –40 °C to 125 °C devices.
90
Min Max Min Max Min Max Min Max
VCC Supply Voltage 2.7 3.6 2.7 3.6 2.5 3.6 2.7 3.6 V
Ambient Operating
Temperature –40 85 / 125 2
2.85 °C is for industrial part code, while 125 °C is for the autograde part.
–40 85 –40 125 –40 85 °C
Load Capacit ance
(CL)30 30 30 30 pF
Input Rise and Fall
Times 10 10 10 10 ns
Input Pulse
Voltages 0 to VCC 0 to VCC 0 to VCC 0 to VCC V
Input and Output
Timing Ref.
Voltages VCC/2 VCC/2 VCC/2 VCC/2 V
AI04498
VCC
0V
VCC/2
AI04499
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25kΩ
VCC
25kΩ
VCC
0.1µF
M29W160ET, M29W160EB
22/42
Table 10. Device Capacitance
Note: Sampled only, not 100% tested.
Table 11. DC Characteristics
Note: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6pF
COUT Output Capacitance VOUT = 0V 12 pF
Symbol Parameter Test Condition Min Typ Max Unit
ILI Input Leaka ge Current 0V VIN VCC ±1 µA
ILO Output Leakage Current 0V VOUT VCC ±1 µA
ICC1 Supply Current (Read) E = VIL, G = VIH,
f = 6MHz 4.5 10 mA
ICC2 Supply Current (Standby) E = VCC ±0.2V,
RP = VCC ±0.2V 35 100 µA
ICC3 (1) Supply Current
(Program/Erase) Program/Erase
Controller active 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC +0.3 V
VOL Output Low Voltage IOL = 1.8mA 0.45 V
VOH Output High Voltage IOH = –100µAVCC –0.4 V
VID Identification Voltage 11.5 12.5 V
IID Identification Curr ent A9 = VID 100 µA
VLKO Program/Erase Lockout
Supply Voltage 1.8 2.3 V
23/42
M29W160ET, M29W160EB
Figure 12. Read Mode AC Waveforms
Table 12. Read AC Characteristics
Note: 1. Sampled only, not 100% tested.
2. 70 ns becomes 80 ns if the 80 ns device code is used.
Symbol Alt Parameter Test Condition M29W160E Unit
70/7A/80 (2) 90
tAVAV tRC Address Valid to Next Address Valid E = VIL,
G = VIL Min7090ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G = VIL Max 70 90 ns
tELQX (1) tLZ Chip Enable Low to Outp ut Transition G = VIL Min 0 0 ns
tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 90 ns
tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns
tGLQV tOE Output Enable Low to Outpu t Valid E = VIL Max 25 35 ns
tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 30 ns
tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 30 ns
tEHQX
tGHQX
tAXQX tOH Chip Enable, Output Enable or Address
T ransition to Output Transition Min 0 0 ns
tELBL
tELBH tELFL
tELFH Chip Enable to BYTE Low or High Max 5 5 ns
tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns
tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns
AI02922
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A19/
A–1
G
DQ0-DQ7/
DQ8-DQ15
E
tELQV tEHQX
tGHQZ
VALID
tBHQV
tELBL/tELBH tBLQZ
BYTE
M29W160ET, M29W160EB
24/42
Figure 13. Write AC Waveforms, Write Enable Controlled
Table 13. Write AC Characteristics, Write Enable Controlled
Note: 1. Sampled only, not 100% tested.
2. 70 ns becomes 80 ns if the 80 ns device code is used.
Symbol Alt Parameter M29W160E Unit
70/7A/80 (2) 90
tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 45 50 ns
tDVWH tDS Input Valid to Write Enable High Min 45 50 ns
tWHDX tDH Write Enable High to Input Transition Min 0 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns
tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns
tWLAX tAH Write En able Low to Address T r ansition Min 45 50 ns
tGHWL Output Enable High to Write Enable Low Min 0 0 ns
tWHGL tOEH Wri te Enable High to Output Enable Low Min 0 0 ns
tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns
tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs
AI02923
E
G
W
A0-A19/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
25/42
M29W160ET, M29W160EB
Figure 14. Write AC Waveforms, Chip Enable Controlled
Table 14. Write AC Characteristics, Chip Enable Controlled
Note: 1. Sampled only, not 100% tested.
2. 70 ns becomes 80 ns if the 80 ns device code is used.
Symbol Alt Parameter M29W160E Unit
70/7A/80 (2) 90
tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 45 50 ns
tDVEH tDS Input Valid to Chip Enable High Min 45 50 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 ns
tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns
tELAX tAH Chip Enable Low to Address Transition Min 45 50 ns
tGHEL Output Enable High Chip Enable Low Min 0 0 ns
tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns
tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns
tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs
AI02924
E
G
W
A0-A19/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
M29W160ET, M29W160EB
26/42
Figure 15. Reset/Block Temporary Unprotect AC Waveforms
Table 15. Reset/Block Temporary Unprotect AC Characteristics
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29W160E Unit
70/7A/80 90
tPHWL (1)
tPHEL
tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 50 50 ns
tRHWL (1)
tRHEL (1)
tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 0 0 ns
tPLPX tRP RP Pulse Width Min 500 500 ns
tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs
tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns
AI02931B
RB
W,
RP tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
tRHWL, tRHEL, tRHGL
27/42
M29W160ET, M29W160EB
PACKAGE MECHANICAL
Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline, top view
Note: Drawing is not to scale.
Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.080 0.0031
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
L1 0.800 0.0315
305305
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
M29W160ET, M29W160EB
28/42
Figure 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Outline, bottom view
Table 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 4.000 – – 0.1575 – –
ddd 0.100 0.0039
E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.600 – – 0.2205 – –
e 0.800 – – 0.0315 – –
FD 1.000 – – 0.0394 – –
FE 1.200 – – 0.0472 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
E1E
D1
D
eb
A2
A1
A
BGA-Z32
ddd
FD
FE SD
SE
e
BALL "A1"
29/42
M29W160ET, M29W160EB
Figure 18. FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package outline, bottom view
E1E
D1
D
eb
SD
SE
A2
A1
A
BGA-Z23
ddd
FD
FE
BALL "A1"
Table 18. FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A — — 1.40 — — 0.055
A1 0.48 0.43 0.53 0.018 0.016
A2 0.80 — — 0.031 — —
b — 0.55 0.65 — 0.021 0.025
D 11.00 10.90 11.10 0.433 0.429 0.437
D1 7.00 — — 0.275 — —
ddd — — 0.15 — — 0.0059
e 1.00 — — 0.039 — —
E 13.0 12.90 13.10 0.511 0.507 0.515
E1 7.00 — — 0.275 — —
FD 2.00 — — 0.078 — —
FE 3.00 — — 0.118 — —
SD 0.50 — — 0.0196 — —
SE 0.50 — — 0.0196 — —
M29W160ET, M29W160EB
30/42
PART NUMBERING
Table 19. Ordering Information Scheme
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the Numonyx Sales Office nearest to you.
Example: M29W160EB 7A N 3 S E
Device Type
M29 = Parallel Flash Memory
Device Function
W = 2.7 V to 3.6 V main family
Array Size
160E = 16 Mbit Memory Array
Configuration
T = Top Boot
B = Bottom Boot
Speed Class
7A = 70 ns device speed in conjunction with temperature
range = 6 to denote Auto Grade (–40 to 85 °C) parts
70 = 70 ns device speed in conjunction with temperature
range = 6 to denote Industrial Grade (–40 to 85 °C) parts;
or in conjunction with temperature range = 3 to denote
Auto Grade (–40 to 125 °C ) parts
80 = 80 ns access time Auto Device in conjunction with
temperature range = 3 and voltage extension = S
90 = 90 ns device speed in conjunction with temperature
range = 6 to denote Industrial Grade (–40 to 85 °C) parts
Package Option
N = TSOP48: 12 x 20 mm
ZA = TFBGA48: 6x8 mm, 0.80mm pitch
ZS = FBGA64: 11 x 13 mm, 1 mm pitch
Temperature Range
6 = Temperature range (–40 to 85 °C)
3 = Automotive temperature range (–40 to 125 °C)
Voltage Extension
Blank = Standard option
S = VCCmin extension to 2.5V of VCC and available only
with 80 ns Speed Class Option
Packing Option
Blank = Standard Packing
T = Tape and Reel Packing
E = RoHS, Standard Packing
F = RoHS, Tape & Reel Packing
31/42
M29W160ET, M29W160EB
APPENDIX A. BLOCK ADDRESS TABLE
Table 20. Top Boot Block Addresses,
M29W160ET Table 21. Bottom Boot Block Addresses,
M29W160EB
#Size
(KBytes) Address Range
(x8) Address Range
(x16)
34 16 1FC000h-1FFFFFh FE000h-FFFFFh
33 8 1FA000h-1FBFFFh FD000h-FDFFFh
32 8 1F8000h-1F9FFFh FC000h-FCFFFh
31 32 1F0000h-1F7FFFh F8000h-FBFFFh
30 64 1E0000h-1EFFFFh F0000h-F7FFFh
29 64 1D0000h-1DFFFFh E8000h-EFFFFh
28 64 1C0000h-1CFFFFh E0000h-E7FFFh
27 64 1B0000h-1BFFFFh D8000h-DFFFFh
26 64 1A0000h-1AFFFFh D0000h-D7FFFh
25 64 190000h-19FFFFh C8000h-CFFFFh
24 64 180000h-18FFFFh C0000h-C7FFFh
23 64 170000h-17FFFFh B8000h-BFFFFh
22 64 160000h-16FFFFh B0000h-B7FFFh
21 64 150000h-15FFFFh A8000h-AFFFFh
20 64 140000h-14FFFFh A0000h-A7FFFh
19 64 130000h-13FFFFh 98000h-9FFFFh
18 64 120000h-12FFFFh 90000h-97FFFh
17 64 110000h-11FFFFh 88000h-8FFFFh
16 64 100000h-10FFFFh 80000h-87FFFh
15 64 0F0000h-0FFFFFh 78000h-7FFFFh
14 64 0E0000h-0EFFFFh 70000h-77FFFh
13 64 0D0000h-0DFFFFh 68000h-6FFFFh
12 64 0C0000h-0CFFFFh 60000h-67FFFh
11 64 0B0000h-0BFFFFh 58000h-5FFFFh
10 64 0A0000h-0AFFFFh 50000h-57FFFh
9 64 090000h-09FFFFh 48000h-4FFFFh
8 64 080000h-08FFFFh 40000h-47FFFh
7 64 070000h-07FFFFh 38000h-3FFFFh
6 64 060000h-06FFFFh 30000h-37FFFh
5 64 050000h-05FFFFh 28000h-2FFFFh
4 64 040000h-04FFFFh 20000h-27FFFh
3 64 030000h-03FFFFh 18000h-1FFFFh
2 64 020000h-02FFFFh 10000h-17FFFh
1 64 010000h-01FFFFh 08000h-0FFFFh
0 64 000000h-00FFFFh 00000h-07FFFh
#Size
(KBytes) Address Range
(x8) Address Range
(x16)
34 64 1F0000h-1FFFFFh F8000h-FFFFFh
33 64 1E0000h-1EFFFFh F0000h-F7FFFh
32 64 1D0000h-1DFFFFh E8000h-EFFFFh
31 64 1C0000h-1CFFFFh E0000h-E7FFFh
30 64 1B0000h-1BFFFFh D8000h-DFFFFh
29 64 1A0000h-1AFFFFh D0000h-D7FFFh
28 64 190000h-19FFFFh C8000h-CFFFFh
27 64 180000h-18FFFFh C0000h-C7FFFh
26 64 170000h-17FFFFh B8000h-BFFFFh
25 64 160000h-16FFFFh B0000h-B7FFFh
24 64 150000h-15FFFFh A8000h-AFFFFh
23 64 140000h-14FFFFh A0000h-A7FFFh
22 64 130000h-13FFFFh 98000h-9FFFFh
21 64 120000h-12FFFFh 90000h-97FFFh
20 64 110000h-11FFFFh 88000h-8FFFFh
19 64 100000h-10FFFFh 80000h-87FFFh
18 64 0F0000h-0FFFFFh 78000h-7FFFFh
17 64 0E0000h-0EFFFFh 70000h-77FFFh
16 64 0D0000h-0DFFFFh 68000h-6FFFFh
15 64 0C0000h-0CFFFFh 60000h-67FFFh
14 64 0B0000h-0BFFFFh 58000h-5FFFFh
13 64 0A0000h-0AFFFFh 50000h-57FFFh
12 64 090000h-09FFFFh 48000h-4FFFFh
11 64 080000h-08FFFFh 40000h-47FFFh
10 64 070000h-07FFFFh 38000h-3FFFFh
9 64 060000h-06FFFFh 30000h-37FFFh
8 64 050000h-05FFFFh 28000h-2FFFFh
7 64 040000h-04FFFFh 20000h-27FFFh
6 64 030000h-03FFFFh 18000h-1FFFFh
5 64 020000h-02FFFFh 10000h-17FFFh
4 64 010000h-01FFFFh 08000h-0FFFFh
3 32 008000h-00FFFFh 04000h-07FFFh
2 8 006000h-007FFFh 03000h-03FFFh
1 8 004000h-005FFFh 02000h-02FFFh
0 16 000000h-003FFFh 00000h-01FFFh
M29W160ET, M29W160EB
32/42
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
is read from the memory. Tables 22, 23, 24, 25, 26
and 27 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 27, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by Numonyx. Issue a
Read command to return to Read mode.
Note: The Common Flash Interface is only avail-
able for Temperature range 6 (–40 to 85°C).
Table 22. Query Structure Overview
Note: Query data are always presented on the lowest order data outputs.
Table 23. CFI Query Identification String
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
Address Sub-section Name Description
x16 x8
10h 20h CFI Query Identificati on String Command set ID and algorithm data offset
1Bh 36h System Interface Information Device timing & voltage information
27h 4Eh Device Geometry Definition Flash device layout
40h 80h Primary Algorithm-specific Extended
Query table Additional information specific t o the Primary
Algorithm (optional)
61h C2h Security Code Area 64 bit unique device number
Address Data Description Value
x16 x8
10h 20h 0051h "Q"
11h 22h 0052h Query Unique ASCII St ring "QRY" "R"
12h 24h 0059h "Y"
13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm AMD
Compatible
14h 28h 0000h
15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 25) P = 40h
16h 2Ch 0000h
17h 2Eh 0000h Alternate Vendor Command Set and Control Interf ace ID Code second
vendor - specified algorithm supported NA
18h 30h 0000h
19h 32h 0000h Address for Alternate Algorithm extended Query table NA
1Ah 34h 0000h
33/42
M29W160ET, M29W160EB
Table 24. CFI Query System Interface Inf ormation
Address Data Description Value
x16 x8
1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 2.7V
1Ch 38h 0036h VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 3.6V
1Dh 3Ah 0000h VPP [Programming] Supply Minimum Program/Erase voltage NA
1Eh 3Ch 0000h VPP [Programming] Supply Maximum Program/Erase voltage NA
1Fh 3Eh 0004h Typical timeout per single Byte/Word program = 2n µs 16µs
20h 40h 0000h Typical timeout for minimum size write buff er program = 2n µs NA
21h 42h 000Ah Typical timeout per individual block erase = 2n ms 1s
22h 44h 0000h Typical timeout for full chip erase = 2n ms NA
23h 46h 0004h Maximum timeout for Byte/Word program = 2n times typical 256µs
24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA
25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 8s
26h 4Ch 0000h Maximum timeout for chip erase = 2n times typical NA
M29W160ET, M29W160EB
34/42
Table 25. Device Geometry Definition
Address Data Description Value
x16 x8
27h 4Eh 0015h Device Size = 2n in number of Bytes 2 MByte
28h
29h 50h
52h 0002h
0000h Flash Device Interface Code descr i ption x8, x16
Async.
2Ah
2Bh 54h
56h 0000h
0000h Maximum number of Bytes in multi-Byte progr am or page = 2n NA
2Ch 58h 0004h Number of Erase Block Regions within the device.
It specifies the number of regions within the device cont aining
contiguous Erase Blocks of the same size. 4
2Dh
2Eh 5Ah
5Ch 0000h
0000h Region 1 Information
Number of identical size erase bl ock = 0000h+1 1
2Fh
30h 5Eh
60h 0040h
0000h Region 1 Information
Block size in Region 1 = 0040h * 256 Byte 16 KByte
31h
32h 62h
64h 0001h
0000h Region 2 Information
Number of identical size erase bl ock = 0001h+1 2
33h
34h 66h
68h 0020h
0000h Region 2 Information
Block size in Region 2 = 0020h * 256 Byte 8 KByte
35h
36h 6Ah
6Ch 0000h
0000h Region 3 Information
Number of identical size erase bl ock = 0000h+1 1
37h
38h 6Eh
70h 0080h
0000h Region 3 Information
Block size in Region 3 = 0080h * 256 Byte 32 KByte
39h
3Ah 72h
74h 001Eh
0000h Region 4 Information
Number of identical-size erase block = 001Eh+1 31
3Bh
3Ch 76h
78h 0000h
0001h Region 4 Information
Block size in Region 4 = 0100h * 256 Byte 64 KByte
35/42
M29W160ET, M29W160EB
Table 26. Primary Algorithm-Specific Extended Query Table
Table 27. Security Code Area
Address Data Description Value
x16 x8
40h 80h 0050h
Primary Algorithm extended Query table unique ASCII string “PRI”
"P"
41h 82h 0052h "R"
42h 84h 0049h "I"
43h 86h 0031h Major version number, ASCII "1"
44h 88h 0030h Minor version number, ASCII "0"
45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h 8Ch 0002h Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write 2
47h 8Eh 0001h Block Protection
00 = not supported, x = number of blocks in per group 1
48h 90h 0001h Temporary Block Unprotect
00 = not supported , 01 = supported Yes
49h 92h 0004h Block Protect /Unprotect
04 = M29W400B 4
4Ah 94h 0000h Simultaneous Operations, 00 = not supported No
4Bh 96h 0000h Burst Mod e, 00 = not supported, 01 = supported No
4Ch 98h 0000h Page Mode, 00 = not support ed, 01 = 4 page Word, 02 = 8 p age Word No
Address Data Description
x16 x8
61h C3h, C2h XXXX
64 bit: unique device number
62h C5h, C4h XXXX
63h C7h, C6h XXXX
64h C9h, C8h XXXX
M29W160ET, M29W160EB
36/42
APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the Flash
memory. Each Block can be protected individually.
Once protected, Program and Erase operations
on the block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Sign al De-
scriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks could change between differ-
ent Flash memory suppliers.
Programmer Technique
The Programmer technique uses high (VID) volt-
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure 19,
Programmer Equipment Block Protect Flowchart.
During the Block Protect algorithm, the A19-A12
Address Inputs indicate the address of the block to
be protected. The block will be correctly protected
only if A19-A12 remain valid and stable, and if
Chip Enable is kept Low, VIL, all along the Protect
and Verify phases.
The Chip Unprotect algorithm is used to unprotect
all the memory blocks at the same time. This algo-
rithm can only be used if all of the blocks are pr o-
tected first. To unprotect the chip follow Figure 20,
Programmer Equipment Chip Unprotect Flow-
chart. Table 28, Programmer Technique Bus Op -
erations, gives a summary of each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the Flash memory has been fitte d to
the system.
To protect a block follow the flowchart in Figure 21,
In-System Block Protect Flowchart. To unprotect
the whole chip it is necessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Fig-
ure 22, In-System Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Table 28. Programmer Technique B us Operations, BYTE = VIH or VIL
Operation E G W Address Inputs
A0-A19 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block Protect VIL VID VIL Pulse A9 = VID, A12-A19 Block Address
Others = X X
Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH
Others = X X
Block Protection
Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
A12-A19 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block Unprotection
Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,
A12-A19 Block Address
Others = X
Retry = XX01h
Pass = XX00h
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M29W160ET, M29W160EB
Figure 19. Programmer Equipment Block Protect Flowchart
Note: 1. Addre ss Inputs A19-A 12 give the addre ss of the block t hat is to be prot ected. It is impe rative that the y remain stable during the
operation.
2. During the Protect and Verify phases of the algorithm, Chip Enable E must be kept Low, VIL.
ADDRESS = BLOCK ADDRESS
AI03469b
G, A9 = VID,
E = VIL
n = 0
Wait 4µs
Wait 100µs
W = VIL
(1)
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
A9 = VIH
E, G = VIH
++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
W = VIH
E = VIL
(1)
Wait 4µs
G = VIL
Wait 60ns
Read DATA
Verify Protect Set-upEnd
A9 = VIH
E, G = VIH
M29W160ET, M29W160EB
38/42
Figure 20. Programmer Equipment Chip Unprotect Flowchart
PROTECT ALL BLOCKS
AI03470
A6, A12, A15 = VIH(1)
E, G, A9 = VID
DATA
W = VIH
E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1, A6 = VIH
Wait 10ms
=
00h
INCREMENT
CURRENT BLOCK
n = 0
CURRENT BLOCK = 0
Wait 4µs
W = VIL
++n
= 1000
START
YES
YESNO
NO LAST
BLOCK
YES
NO
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
FAIL PASS
Verify Unprotect Set-upEnd
A9 = VIH
E, G = VIH A9 = VIH
E, G = VIH
39/42
M29W160ET, M29W160EB
Figure 21. In-System Equipment Block Protect Flowchart
AI03471
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
n = 0
Wait 100µs
WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VIH ++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
RP = VIH
Wait 4µs
Verify Protect Set-upEnd
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
M29W160ET, M29W160EB
40/42
Figure 22. In-System Equipment Chip Unprotect Flowchart
AI03472
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
n = 0
CURRENT BLOCK = 0
Wait 10ms
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VIH
++n
= 1000
START
FAIL PASS
YES
NO
DATA
=
00h
YESNO
RP = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PROTECT ALL BLOCKS
INCREMENT
CURRENT BLOCK
LAST
BLOCK
YES
NO
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Verify Unprotect Set-upEnd
41/42
M29W160ET, M29W160EB
REVISION HISTORY
Table 29. Document Revis ion History
Date Version Revision Details
06-Aug-2002 -01 First Issue: originates from M29W160D dat asheet dated 24-Jun-2002
27-Nov-2002 1.1
9x8mm FBGA48 package replaced by 6x8mm. VDD(min) reduced for -70ns
speed class.
Erase Suspend Latency Time (typical and maximum) added to Program, Erase
T i mes and Program, Erase Endurance Cycles table. Logic Diagram corrected.
03-Dec-2002 1.2 Package information corrected in ordering info rmation table.
21-Mar-2003 2.0 Document promoted to full Datasheet status. Block Protect and Chip Unprotect
algorithms specified in Appendix C, BLOCK PROTECTION.
27-Jun-2003 2.1 TSOP48 package information updated (see Figure 16 and Table 16).
26-Jan-2004 3.0 Block Erase Command clarified.
27-Mar-2008 4.0 Applied Numonyx branding.
12-March-2009 5.0 Added FBGA (ZS) package and ballout information.
7-April-2009 6.0
Revised Chip Erase signal value (maximum) in Table 6., Program/Erase Times
and Program/Erase Endu rance Cycles from 120 to 60 seconds
Revised Block Erase (64-Kbytes) signal value (maximum) in Table 6., Program/
Erase Times and Program/Erase Endurance Cycles from 6 to 1.6 seconds.
Revised tGLQV (70 ns speed) value in Table 12., Read AC Characteristics from
30 to 25 ns.
7-May-2009 7.0
Added 7A and 80 ns columns to Table 9., Operating and AC Measurement
Conditions;
Added note 2 to tables: 12, 13, and 14.
Updated the order information table as follows:
Added 7A, 70, 80, and 90 ns speed class options
Added temperature range = 3 Automotive
Added Voltage extension option S.
18-June-2009 8.0 Corrected VCC supply volt age typograp hical errors in Tabl e 9., Operat ing and AC
Measurement Conditions
11-April-2011 9.0 Change to parameter blocks/main blocks in Features Summary
Changed voltage extension to 2.5V of VCC in Table 19, Ordering Information
Scheme
M29W160ET, M29W160EB
42/42
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