0.01 GHz to 10 GHz,
GaAs, pHEMT, MMIC,
Low Noise Amplifier
Data Sheet
HMC8410
Rev. D Document Feedback
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FEATURES
Low noise figure: 1.1 dB typical
High gain: 19.5 dB typical
High output third-order intercept (IP3): 33 dBm typical
6-lead, 2 mm × 2 mm LFCSP package
APPLICATIONS
Software defined radios
Electronic warfare
Radar applications
FUNCTIONAL BLOCK DIAGRAM
RFIN/VGG1RFOUT/VDD
HMC8410
14657-001
Figure 1.
GENERAL DESCRIPTION
The HMC8410 is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic high
electron mobility transistor (pHEMT), low noise wideband
amplifier that operates from 0.01 GHz to 10 GHz. The HMC8410
provides a typical gain of 19.5 dB, a 1.1 dB typical noise figure,
and a typical output IP3 of 33 dBm, requiring only 65 mA from
a 5 V supply voltage. The saturated output power (PSAT) of up to
22.5 dBm enables the low noise amplifier (LNA) to function as a
local oscillator (LO) driver for many of Analog Devices, Inc.,
balanced, I/Q or image rejection mixers.
The HMC8410 also features inputs/outputs (I/Os) that are
internally matched to 50 Ω, making it ideal for surface-mounted
technology (SMT)-based, high capacity microwave radio
applications.
The HMC8410 is housed in a RoHS-compliant, 2 mm × 2 mm,
LFCSP package.
Multifunction pin names can be referenced by their relevant
function only.
HMC8410 Data Sheet
Rev. D | Page 2 of 17
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications ................................................................... 3
0.01 GHz to 3 GHz Frequency Range ........................................ 3
3 GHz to 8 GHz Frequency Range ............................................. 3
8 GHz to 10 GHz Frequency Range ........................................... 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ..............................6
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 13
Applications Information .............................................................. 14
Recommended Bias Sequencing .............................................. 14
Typical Application Circuit ....................................................... 14
Evaluation Board ............................................................................ 15
Evaluation Board Schematic ..................................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
6/2019—Rev. C to Rev. D
Changes to Table 4 ............................................................................ 5
Changes to Figure 11 ........................................................................ 7
Changes to Figure 25 ...................................................................... 10
1/2019—Rev. B to Rev. C
Changes to Figure 11 ........................................................................ 7
Added Figure 16, Renumbered Sequentially ................................ 8
Updated Outline Dimensions ....................................................... 17
9/2018—Rev. A to Rev. B
Changes to Return Loss Parameter, Table 2 .................................. 3
Changes to Return Loss Parameter, Table 3 .................................. 4
Changes to Figure 38 ...................................................................... 14
11/2017—Rev. 0 to Rev. A
Change to Noise Figure Parameter, Table 1 ................................... 3
Change to Continuous Power Dissipation (PDISS) Parameter,
Table 4 ................................................................................................. 5
Changes to Figure 11 ......................................................................... 7
Changes to Figure 17 ......................................................................... 8
Changes to Figure 18 and Figure 20 Caption ................................ 9
Changes to Figure 33 and Figure 34 Caption ............................. 11
Added Figure 36; Renumbered Sequentially .............................. 12
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
7/2016—Revision 0: Initial Version
Data Sheet HMC8410
Rev. D | Page 3 of 17
ELECTRICAL SPECIFICATIONS
0.01 GHz TO 3 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 0.01 3 GHz
GAIN 17.5 19.5 dB
Gain Variation Over Temperature 0.01 dB/°C
NOISE FIGURE 1.1 1.6 dB 0.3 GHz to 3 GHz
RETURN LOSS
Input 15 dB
Output 24 dB
OUTPUT
Output Power for 1 dB Compression P1dB 19.0 21.0 dBm
Saturated Output Power PSAT 22.5 dBm
Output Third-Order Intercept IP3 33 dBm
SUPPLY CURRENT IDQ 65 80 mA Adjust VGG1 to achieve IDQ = 65 mA typical
SUPPLY VOLTAGE VDD 2 5 6 V
3 GHz TO 8 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, a n d I DQ = 65 mA, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 3 8 GHz
GAIN 15.5 18 dB
Gain Variation Over Temperature 0.01 dB/°C
NOISE FIGURE 1.4 1.9 dB
RETURN LOSS
Input 10 dB
Output 16 dB
OUTPUT
Output Power for 1 dB Compression P1dB 18.0 21.0 dBm
Saturated Output Power PSAT 22.5 dBm
Output Third-Order Intercept IP3 31.5 dBm
SUPPLY CURRENT IDQ 65 80 mA Adjust VGG1 to achieve IDQ = 65 mA typical
SUPPLY VOLTAGE VDD 2 5 6 V
HMC8410 Data Sheet
Rev. D | Page 4 of 17
8 GHz TO 10 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, a n d I DQ = 65 mA, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE 8 10 GHz
GAIN 13 16 dB
Gain Variation Over Temperature 0.01 dB/°C
NOISE FIGURE 1.7 2.2 dB
RETURN LOSS
Input 8 dB
Output 7 dB
OUTPUT
Output Power for 1 dB Compression P1dB 17.5 19.5 dBm
Saturated Output Power PSAT 21.5 dBm
Output Third-Order Intercept IP3 33 dBm
SUPPLY CURRENT IDQ 65 80 mA Adjust VGG1 to achieve IDQ = 65 mA typical
SUPPLY VOLTAGE VDD 2 5 6 V
Data Sheet HMC8410
Rev. D | Page 5 of 17
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter1 Rating
Drain Bias Voltage (VDD) 7 V dc
Radio Frequency (RF) Input Power (RFIN) 20 dBm
Continuous Power Dissipation (PDISS), T = 85°C
(Derate 7.8 mW/°C above 85°C)
0.7 W
Channel Temperature 175°C
Storage Temperature Range
−65°C to +150°C
Operating Temperature Range
−40°C to +85°C
Thermal Resistance (Channel to Ground
Paddle)
128.92°C/W
Maximum Peak Reflow Temperature (MSL3)2 260°C
ESD Sensitivity
Human Body Model (HBM) Class1B Passed
500 V
1 When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the specification is listed.
For the full pin names of multifunction pins, refer to the Pin Configuration
and Function Descriptions section.
2 See the Ordering Guide section for more information.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
HMC8410 Data Sheet
Rev. D | Page 6 of 17
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
6
5
1
2
3 4
GND
RFIN/V
GG
1
NIC
NIC
RFOUT/V
DD
NIC
HMC8410
TOP VIEW
(No t t o Scal e)
14657-002
NOTES
1. NI C = NOT INT E RNALL Y CONNECTED. T HIS P IN
MUST BE CO NNE CTED TO THE RF/ DC GRO UND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF/ DC GRO UND.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Ground. This pin must be connected to the RF/dc ground. See Figure 3 for the interface schematic.
2 RFIN/VGG1 RF Input (RFIN). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic.
Gate Bias of the Amplifier (VGG1). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface
schematic.
3, 4, 6 NIC Not Internally Connected. This pin must be connected to the RF/dc ground.
5 RFOUT/VDD RF Output (RFOUT). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic.
Drain Bias for Amplifier (VDD). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
GND
14657-003
Figure 3. GND Interface Schematic
RFIN/VGG1
14657-004
Figure 4. RFIN/VGG1 Interface Schematic
RFOUT/VDD
14657-005
Figure 5. RFOUT/VDD Interface Schematic
Data Sheet HMC8410
Rev. D | Page 7 of 17
TYPICAL PERFORMANCE CHARACTERISTICS
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
012345678910
GAI N (dB) AND RETURN L OSS ( dB)
FREQUENCY (GHz)
S21
S11
S22
14657-006
Figure 6. Gain and Return Loss vs. Frequency
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
0 1 2 3 4 5 6 7 8 9 10
INPUT RETURN L OSS ( dB)
FREQUENCY (G Hz)
–40°C
+25°C
+85°C
14657-007
Figure 7. Input Return Loss vs. Frequency for Various Temperatures
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0246810
NOISE FIGURE (dB)
FREQUENCY (GHz)
–40°C
+25°C
+85°C
14657-008
Figure 8. Noise Figure vs. Frequency for Various Temperatures
8
10
12
14
16
18
20
22
0246810
GAI N (dB)
FREQUENCY(GHz)
–40°C
+25°C
+85°C
14657-009
Figure 9. Gain vs. Frequency for Various Temperatures
–25
–20
–15
–10
–5
0
012345678910
OUTPUT RE TURN L OSS ( dB)
FREQUENCY (GHz)
–40°C
+25°C
+85°C
14657-010
Figure 10. Output Return Loss vs. Frequency for Various Temperatures
0
4
8
2
6
11
1
5
9
10
3
7
NOISE FIGURE (dB)
FREQUENCY (MHz)
14657-011
–40°C
+25°C
+85°C
10 25 70 85 130 145 19040 55 100 115 160 175 205
Figure 11. Noise Figure vs. Frequency for Various Temperatures,
10 MHz to 200 MHz
HMC8410 Data Sheet
Rev. D | Page 8 of 17
15
16
17
18
19
20
21
22
23
24
25
0246810
P1d B ( dBm)
FREQUENCY (G Hz)
–40°C
+25°C
+85°C
14657-012
Figure 12. P1dB vs. Frequency for Various Temperatures
15
16
17
18
19
20
21
22
23
24
25
0246810
P
SAT
(d Bm)
FREQUENCY (G Hz)
–40°C
+25°C
+85°C
14657-013
Figure 13. PSAT vs. Frequency for Various Temperatures
18
20
22
24
26
28
30
32
34
36
0246810
OUTPUT IP3 ( dBm)
FREQUENCY GHz)
–40°C
+25°C
+85°C
14657-014
Figure 14. Output IP3 vs. Frequency for Various Temperatures,
Output Power (POUT)/Tone = 5 dBm
20
25
30
35
40
45
50
0 2 4 6 8 10
OUTPUT IP2 ( dBm)
FREQUENCY (G Hz)
14657-015
Figure 15. Output IP2 vs. Frequency at POUT/Tone = 5 dBm
20
25
30
35
40
45
50
55
0 2 4 6 8 10
OUTPUT IP2 (dB)
FRE Q UE NCY ( GHz)
65mA
85mA
105mA
125mA
140mA
14657-116
Figure 16. Output IP2 vs. Frequency for Various Supply Currents (IDQ),
POUT/Tone=5 dBm, VDD = 5 V
–35
–30
–25
–20
–15
–10
–5
0
012345678910
REVERSE ISOLATION (dB)
FRE Q UE NCY ( GHz)
–40°C
+25°C
+85°C
14657-016
Figure 17. Reverse Isolation vs. Frequency for Various Temperatures
Data Sheet HMC8410
Rev. D | Page 9 of 17
18
20
22
24
26
28
30
32
34
36
0246810
OUTPUT IP3 ( dBm)
FREQUENCY (G Hz)
0dBm
5dBm
14657-017
Figure 18. Output IP3 vs. Frequency for Various POUT/Tone
10
15
20
25
30
35
40
0.1 0.2 0.4 0.6 0.8 1.00.3 0.5 0.7 0.9
GAI N (dB) , P1dB (dBm), P
SAT
(d Bm) ,
AND OUTPUT IP3 ( dBm)
FREQUENCY (G Hz)
GAIN
P1dB
P
SAT
OUTPUT IP3
14657-018
Figure 19. Gain, P1dB, PSAT, and Output IP3 vs. Frequency
0
5
10
15
20
25
30
35
40
0246810
P1d B ( dBm) AND PAE ( %)
FREQUENCY (GHz)
P1dB
PAE
14657-019
Figure 20. P1dB and Power Added Efficiency (PAE) vs. Frequency
55
60
65
70
75
80
85
90
95
100
0
5
10
15
20
25
30
35
40
45
–10 –5
I
DD
(mA)
0510
P
OUT
(d Bm) , GAIN (dB), AND PAE ( %)
INPUT POW E R ( dBm)
P
OUT
GAIN
PAE
I
DD
14657-020
Figure 21. POUT, Gain, PAE, and Supply Current with RF Applied (IDD) vs.
Input Power at 5 GHz
0
5
10
15
20
25
30
35
40
45
50
55
0246810
P
SAT
(d Bm) AND PAE ( %)
FREQUENCY (G Hz)
P
SAT
PAE
14657-021
Figure 22. PSAT and PAE vs. Frequency
0
0.1
0.2
0.3
0.4
0.5
0.6
–10 –8 –6 –4 –2 0246810 12 14
POWER DISSIPATION (W)
INPUT POW E R ( dBm)
1GHz
3GHz
5GHz
7GHz
9GHz
14657-022
Figure 23. Power Dissipation at 85°C vs. Input Power at Various Frequencies
HMC8410 Data Sheet
Rev. D | Page 10 of 17
8
10
12
14
16
18
20
22
0246810
GAI N (dB)
FREQUENCY (G Hz)
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
14657-023
Figure 24. Gain vs. Frequency for Various Supply Currents, VDD = 5 V
0
1
2
3
4
5
6
8
7
024681357910
NOISE FIGURE (dB)
FREQUENCY ( GHz)
5mA
25mA
45mA
70mA
15mA
35mA
65mA
75mA
14657-024
Figure 25. Noise Figure vs. Frequency for Various Supply Currents (IDQ),
VDD = 5 V
14657-025
0
5
10
15
20
25
0246810
P1d B ( dBm)
FREQUENCY (G Hz)
5mA
25mA
45mA
70mA
15mA
35mA
65mA
75mA
Figure 26. P1dB vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
18
19
20
21
22
23
24
25
0 2 4 6 8 10
P
SAT
(d Bm)
FREQUENCY (G Hz)
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
14657-026
Figure 27. PSAT vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
5mA
15mA
25mA
35m
45mA
65mA
70mA
75mA
15
20
25
30
35
40
45
0246810
OUTPUT IP3 ( dBm)
FREQUENCY (G Hz)
14657-027
Figure 28. Output IP3 vs. Frequency for Various Supply Currents (IDQ),
POUT/Tone = 5 dBm, VDD = 5 V
8
10
12
14
16
18
20
22
0 2 46810
GAI N (dB)
FREQUENCY (GHz)
2V
3V
4V
5V
6V
7V
14657-028
Figure 29. Gain vs. Frequency for Various Supply Voltages, IDQ = 65 mA
Data Sheet HMC8410
Rev. D | Page 11 of 17
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0246810
NOISE FIGURE (dB)
FREQUENCY (GHz)
2V
3V
4V
5V
6V
7V
14657-129
Figure 30. Noise Figure vs. Frequency for Various Supply Voltages, IDQ = 65 mA
10
12
14
16
18
20
22
24
0246810
P1d B ( dBm)
FREQUENCY (GHz)
2V
3V
4V
5V
6V
7V
14657-130
Figure 31. P1dB vs. Frequency for Various Supply Voltages, IDQ = 65 mA
13
15
17
19
21
23
25
27
0246810
P
SAT
(d Bm)
FREQUENCY (G Hz)
2V
3V
4V
5V
6V
7V
14657-131
Figure 32. PSAT vs. Frequency for Various Supply Voltages, IDQ = 65 mA
15
20
25
30
35
40
45
0246810
OUTPUT IP3 ( dBm)
FREQUENCY (G Hz)
2V
3V
4V
5V
6V
7V
14657-132
Figure 33. Output IP3 vs. Frequency for Various Supply Voltages,
POUT/Tone = 5 dBm
0
10
20
30
40
50
60
70
80
90
–0.90 –0.85 –0.80 –0.75 –0.70 –0.65 –0.60
VGG1 (V)
–0.55 –0.50 –0.45
IDQ ( mA)
14657-133
Figure 34. Supply Current (IDQ) vs. VGG1, VDD = 5 V,
Representative of a Typical Device
0
20
40
60
80
100
120
–10 –5 0 5 10 15
I
DD
(mA)
INPUT POW E R ( dBm)
5mA
25mA
45mA
70mA
80mA
15mA
35mA
65mA
75mA
14657-134
Figure 35. Supply Current with RF Applied (IDD) vs. Input Power for
Various Supply Currents (IDQ) at 5 GHz, VDD = 5 V
HMC8410 Data Sheet
Rev. D | Page 12 of 17
6
8
10
12
14
16
18
20
–10 –5 0 5 10 15
GAIN (dB)
INPUT POWER (dBm)
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
80mA
14657-135
Figure 36. Gain vs. Input Power for Various Supply Currents (IDQ) at 5 GHz,
VDD = 5 V
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
–
70
10 100 1k 10k
OFFSET FREQUENCY (Hz)
PHASE NOISE (dB/Hz)
100k 1M
14657-136
Figure 37. Additive Phase Noise vs. Offset Frequency, RF Frequency = 5 GHz,
RF Input Power = 3 dBm (P1dB)
Data Sheet HMC8410
Rev. D | Page 13 of 17
THEORY OF OPERATION
The HMC8410 is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic (pHEMT),
low noise wideband amplifier.
The cascode amplifier uses a fundamental cell of two field effect
transistors (FETs) in series, source to drain. The basic schematic for
the cascode cell is shown in Figure 38, which forms a low noise
amplifier operating from 0.01 GHz to 10 GHz with excellent
noise figure performance.
VDD
RFOUT
RFIN
VGG1
14657-029
Figure 38. Basic Schematic for the Cascode Cell
The HMC8410 has single-ended input and output ports whose
impedances are nominally equal to 50 Ω over the 0.01 GHz to
10 GHz frequency range. Consequently, it can directly insert
into a 50 Ω system with no required impedance matching
circuitry, which also means that multiple HMC8410 amplifiers
can be cascaded back to back without the need for external
matching circuitry.
The input and output impedances are sufficiently stable vs.
variations in temperature and supply voltage that no impedance
matching compensation is required.
Note that it is critical to supply very low inductance ground
connections to the ground pins as well as to the backside
exposed paddle to ensure stable operation.
To achieve optimal performance from the HMC8410 and prevent
damage to the device, do not exceed the absolute maximum
ratings.
HMC8410 Data Sheet
Rev. D | Page 14 of 17
APPLICATIONS INFORMATION
Figure 39 shows the basic connections for operating the
HMC8410. AC couple the input and output of the HMC8410
with appropriately sized capacitors. DC block capacitors and RF
choke inductors are supplied on the RFIN and RFOUT pins of
the HMC8410 evaluation board. See Table 6 for additional
information. These dc block capacitors and RF choke inductors
form wideband bias tees on the input and output ports to provide
both ac coupling and the necessary supply voltages to the RFIN
and RFOUT pins. A 5 V dc bias is supplied to the amplifier
through the choke inductor connected to the RFOUT pin, and
the negative VGG1 voltage is supplied to the RFIN pin through
the choke inductor.
RECOMMENDED BIAS SEQUENCING
To not damage the amplifier, follow the recommended bias
sequencing.
During Power-Up
The recommended bias sequence during power-up for the
HMC8410 follows:
1. Connect to GND.
2. Set VGG1 to −2 V.
3. Set VDD to 5 V.
4. Increase VGG1 to achieve a typical supply current (IDQ) =
65 mA.
5. Apply the RF signal.
During Power-Down
The recommended bias sequence during power-down for the
HMC8410 follows:
1. Turn off the RF signal.
2. Decrease VGG1 to −2 V to achieve a typical IDQ = 0 mA.
3. Decrease VDD to 0 V.
4. Increase VGG1 to 0 V.
The bias conditions previously listed (VDD = 5 V and IDQ =
65 mA) are the recommended operating points to achieve
optimum performance. The data used in this data sheet was
taken with the recommended bias conditions. When using the
HMC8410 with different bias conditions, different performance
than what is shown in the Typical Performance Characteristics
section can result.
Figure 19, Figure 31, and Figure 32 show that increasing the
voltage from 2 V to 7 V typically increases P1dB and PSAT at the
expense of power consumption with minor degradation on
noise figure (NF).
TYPICAL APPLICATION CIRCUIT
14657-030
PACKAGE
BASE
GND
V
DD
RFOUT
J2
RFIN/V
GG
1
J1
L2
590nH
C16
20pF
C5
2.2µF
C4
100nF
C3
DNI
+
6
5
1
2
3 4
HMC8410
V
GG
1
L1
590nH
C15
20pF
C14
4.7µF
C13
100nF
+
R2
15Ω
R1
0Ω
C1
10nF
C2
10nF
C12
DNI
Figure 39. Typical Application Circuit
Data Sheet HMC8410
Rev. D | Page 15 of 17
EVALUATION BOARD
The HMC8410 evaluation board is a 4-layer board fabricated
using a Rogers 4350 and the best practices for high frequency
RF design. The RF input and RF output traces have a 50 Ω
characteristic impedance.
The HMC8410 evaluation board and populated components
operate over the −40°C to +85°C ambient temperature range.
For proper bias sequence, see the Applications Information
section.
The HMC8410 evaluation board schematic is shown in Figure 41.
A fully populated and tested evaluation printed circuit board
(PCB) is available from Analog Devices, Inc., upon request
(see Figure 40).
14657-031
Figure 40. HMC8410 Evaluation PCB
HMC8410 Data Sheet
Rev. D | Page 16 of 17
EVALUATION BOARD SCHEMATIC
J1
C15
20pF
C2
10nF
C14
4.7µF
VGG1
C13
100nF
VDD
C5
2.2µF
C4
100nF
VGG2
C8
DNI
C7
DNI
J2
RFOUT
L2
590nH
J8 J3
J4
GND
THRU CAL
C9
DNI DNI
DNI
DNI
C10
J6 J7
R1
0Ω
R2
15Ω
C16
20pF
C3
DNI
C12
DNI
6
5
1
2
3 4
GND
RFIN/VGG1
NIC
NIC
RFOUT/VDD
NIC
HMC8410
EPAD
J5
DNI
RFIN
L1
590nH
C1
10nF
C6
DNI
14657-032
+
Figure 41. HMC8410 Evaluation Board Schematic
Table 6. Bill of Materials for Evaluation PCB EV1HMC8410LP2F
Item Description
J1, J2 PCB mount SMA RF connectors, SRI 21-146-1000-01
J3, J4, J8 DC bias test points
C1, C2 Capacitors, broadband, 10 nF and 82 pF, 0502, 160 kHz and 40 GHz; Presidio Components MBB0502X103MLP5N8L
C3, C6 to C10, C12, J5 to J7 Do not install (DNI)
C4, C13 Capacitors, ceramic, 100 nF, 0402 package
C5 Capacitor, tantalum, 2.2 μF, Size A
C14 Capacitor, tantalum, 4.7 μF, 3216 package
C15, C16 Capacitors, ceramic, 20 pF, 0402 package
L1, L2
Inductors, 590 nH, 0402, 5%, ferrite DF, Coilcraft 0402DF-591XJRU
R1 0 Ω resistor
R2 15 Ω resistor, 0402 package
U1 Amplifier, HMC8410
Heat sink Heat sink
PCB
600-01660-00 evaluation PCB; circuit board material: Rogers 4350
Data Sheet HMC8410
Rev. D | Page 17 of 17
OUTLINE DIMENSIONS
1.65
1.60
1.55
0.30
0.25
0.20
TOP VIEW
SIDE VIEW
0.35
0.30
0.25
BOTTOM VIEW
PIN 1 INDEX
AREA
0.90
0.85
0.80
1.05
1.00
0.95
0.203 REF
0.05 M AX
0.02 NO M
0.65 BSC
0.20
MIN
EXPOSED
PAD
08-17-2018-B
PKG-005040
2.05
2.00 SQ
1.95
46
1
3
COPLANARITY
0.08
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
PIN 1
INDIC ATORAR EAOP TIONS
(SEEDETAIL A)
DETAIL A
(JEDEC 95)
Figure 42. 6-Lead Lead Frame Chip Scale Package [LFCSP]
2 mm × 2 mm Body and 0.85 mm Package Height
(CP-6-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Lead Finish Package Description Package Option
HMC8410LP2FE −40°C to +85°C MSL3 100% Matte Sn 6-Lead LFCSP CP-6-9
HMC8410LP2FETR −40°C to +85°C MSL3 100% Matte Sn 6-Lead LFCSP CP-6-9
EV1HMC8410LP2F Evaluation PCB
1 The HMC8410LP2FE and HMC8410LP2FETR are RoHS Compliant Parts.
2 See the Absolute Maximum Ratings section for additional information.
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D14657-0-6/19(D)
