TL082
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier
Literature Number: SNOSBW5B
TL082
Wide Bandwidth Dual JFET Input Operational Amplifier
General Description
These devices are low cost, high speed, dual JFET input
operational amplifiers with an internally trimmed input offset
voltage (BI-FET II™technology). They require low supply
current yet maintain a large gain bandwidth product and fast
slew rate. In addition, well matched high voltage JFET input
devices provide very low input bias and offset currents. The
TL082 is pin compatible with the standard LM1558 allowing
designers to immediately upgrade the overall performance of
existing LM1558 and most LM358 designs.
These amplifiers may be used in applications such as high
speed integrators, fast D/A converters, sample and hold
circuits and many other circuits requiring low input offset
voltage, low input bias current, high input impedance, high
slew rate and wide bandwidth. The devices also exhibit low
noise and offset voltage drift.
Features
nInternally trimmed offset voltage: 15 mV
nLow input bias current: 50 pA
nLow input noise voltage: 16nV/√Hz
nLow input noise current: 0.01 pA/√Hz
nWide gain bandwidth: 4 MHz
nHigh slew rate: 13 V/µs
nLow supply current: 3.6 mA
nHigh input impedance: 10
12
Ω
nLow total harmonic distortion: ≤0.02%
nLow 1/f noise corner: 50 Hz
nFast settling time to 0.01%: 2 µs
Typical Connection
00835701
Connection Diagram
DIP/SO Package (Top View)
00835703
Order Number TL082CM or TL082CP
See NS Package Number M08A or N08E
Simplified Schematic
00835702
BI-FET II™is a trademark of National Semiconductor Corp.
August 2000
TL082 Wide Bandwidth Dual JFET Input Operational Amplifier
© 2004 National Semiconductor Corporation DS008357 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage ±18V
Power Dissipation (Note 2)
Operating Temperature Range 0˚C to +70˚C
T
j(MAX)
150˚C
Differential Input Voltage ±30V
Input Voltage Range (Note 3) ±15V
Output Short Circuit Duration Continuous
Storage Temperature Range −65˚C to +150˚C
Lead Temp. (Soldering, 10 seconds) 260˚C
ESD rating to be determined.
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which the
device is functional, but do not guarantee specific performance limits.
DC Electrical Characteristics (Note 5)
Symbol Parameter Conditions TL082C Units
Min Typ Max
V
OS
Input Offset Voltage R
S
=10kΩ,T
A
= 25˚C 5 15 mV
Over Temperature 20 mV
∆V
OS
/∆T Average TC of Input Offset R
S
=10kΩ10 µV/˚C
Voltage
I
OS
Input Offset Current T
j
= 25˚C, (Notes 5, 6) 25 200 pA
T
j
≤70˚C 4 nA
I
B
Input Bias Current T
j
= 25˚C, (Notes 5, 6) 50 400 pA
T
j
≤70˚C 8 nA
R
IN
Input Resistance T
j
= 25˚C 10
12
Ω
A
VOL
Large Signal Voltage Gain V
S
=±15V, T
A
= 25˚C 25 100 V/mV
V
O
=±10V, R
L
=2kΩ
Over Temperature 15 V/mV
V
O
Output Voltage Swing V
S
=±15V, R
L
=10kΩ±12 ±13.5 V
V
CM
Input Common-Mode Voltage V
S
=±15V ±11 +15 V
Range −12 V
CMRR Common-Mode Rejection Ratio R
S
≤10 kΩ70 100 dB
PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB
I
S
Supply Current 3.6 5.6 mA
TL082
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AC Electrical Characteristics (Note 5)
Symbol Parameter Conditions TL082C Units
Min Typ Max
Amplifier to Amplifier Coupling T
A
= 25˚C, f = 1Hz- −120 dB
20 kHz (Input Referred)
SR Slew Rate V
S
=±15V, T
A
= 25˚C 8 13 V/µs
GBW Gain Bandwidth Product V
S
=±15V, T
A
= 25˚C 4 MHz
e
n
Equivalent Input Noise Voltage T
A
= 25˚C, R
S
= 100Ω, 25 nV/√Hz
f = 1000 Hz
i
n
Equivalent Input Noise Current T
j
= 25˚C, f = 1000 Hz 0.01 pA/√Hz
THD Total Harmonic Distortion A
V
= +10, R
L
= 10k,
V
O
=20Vp−p,
BW = 20 Hz−20 kHz
<0.02 %
Note 2: For operating at elevated temperature, the device must be derated based on a thermal resistance of 115˚C/W junction to ambient for the N package.
Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 4: The power dissipation limit, however, cannot be exceeded.
Note 5: These specifications apply for VS=±15V and 0˚C ≤TA≤+70˚C. VOS,I
Band IOS are measured at VCM =0.
Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj. Due to the limited
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, PD.T
j=T
A+θjA PDwhere θjA is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS
=±6V to ±15V.
Typical Performance Characteristics
Input Bias Current Input Bias Current
00835718 00835719
TL082
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Typical Performance Characteristics (Continued)
Supply Current
Positive Common-Mode Input
Voltage Limit
00835720 00835721
Negative Common-Mode Input
Voltage Limit Positive Current Limit
00835722 00835723
Negative Current Limit Voltage Swing
00835724 00835725
TL082
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Typical Performance Characteristics (Continued)
Output Voltage Swing Gain Bandwidth
00835726
00835727
Bode Plot Slew Rate
00835728 00835729
Distortion vs Frequency
Undistorted Output
Voltage Swing
00835730 00835731
TL082
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Typical Performance Characteristics (Continued)
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
00835732 00835733
Power Supply Rejection
Ratio
Equivalent Input Noise
Voltage
00835734
00835735
Open Loop Voltage
Gain (V/V) Output Impedance
00835736 00835737
TL082
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Typical Performance Characteristics (Continued)
Inverter Setting Time
00835738
Pulse Response
Small Signal Inverting
00835706
Small Signal Non-Inverting
00835707
Large Signal Inverting
00835708
Large Signal Non-Inverting
00835709
TL082
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Pulse Response (Continued)
Current Limit (R
L
= 100Ω)
00835710
Application Hints
These devices are op amps with an internally trimmed input
offset voltage and JFET input devices (BI-FET II). These
JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the
inputs. Therefore, large differential input voltages can easily
be accommodated without a large increase in input current.
The maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will cause a reversal of the phase to the output and force the
amplifier output to the corresponding high or low state. Ex-
ceeding the negative common-mode limit on both inputs will
force the amplifier output to a high state. In neither case
does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus
the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
The amplifiers will operate with a common-mode input volt-
age equal to the positive supply; however, the gain band-
width and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on ±6V power sup-
plies. Supply voltages less than these may result in lower
gain bandwidth and slew rate.
The amplifiers will drivea2kΩload resistance to ±10V over
the full temperature range of 0˚C to +70˚C. If the amplifier is
forced to drive heavier load currents, however, an increase
in input offset voltage may occur on the negative voltage
swing and finally reach an active current limit on both posi-
tive and negative swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
Because these amplifiers are JFET rather than MOSFET
input op amps they do not require special handling.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3
dB frequency of the closed loop gain and consequently there
is negligible effect on stability margin. However, if the feed-
back pole is less than approximately 6 times the expected 3
dB frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the added
capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
TL082
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Detailed Schematic
00835711
Typical Applications
Three-Band Active Tone Control
00835712
TL082
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Typical Applications (Continued)
00835713
•All potentiometers are linear taper
•Use the LF347 Quad for stereo applications
Note 8: All controls flat.
Note 9: Bass and treble boost, mid flat.
Note 10: Bass and treble cut, mid flat.
Note 11: Mid boost, bass and treble flat.
Note 12: Mid cut, bass and treble flat.
Improved CMRR Instrumentation Amplifier
00835714
Cand are separate isolated grounds
Matching of R2’s, R4’s and R5’s control CMRR
With AVT = 1400, resistor matching = 0.01%: CMRR = 136 dB
•Very high input impedance
•Super high CMRR
TL082
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Typical Applications (Continued)
Fourth Order Low Pass Butterworth Filter
00835715
Fourth Order High Pass Butterworth Filter
00835716
TL082
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Typical Applications (Continued)
Ohms to Volts Converter
00835717
TL082
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Physical Dimensions inches (millimeters)
unless otherwise noted
Order Number TL082CM
NS Package M08A
Order Number TL082CP
NS Package N08E
TL082
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Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
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TL082 Wide Bandwidth Dual JFET Input Operational Amplifier
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