Dual 12-/14-/16-Bit 800 MSPS DAC
with Low Power 32-Bit Complex NCO
AD9785/AD9787/AD9788
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Low power, fine complex NCO allows carrier placement
anywhere in DAC bandwidth while adding <300 mW power
Auxiliary DACs allow I and Q gain matching and offset control
Includes programmable I and Q phase compensation
Internal digital upconversion capability
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP package
APPLICATIONS
Wireless infrastructure
WCDMA, CDMA2000, TD-SCDMA, WiMAX, GSM
Digital high or low IF synthesis
Transmit diversity
Wideband communications
LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit,
high dynamic range TxDAC® devices, respectively, that provide
a sample rate of 800 MSPS, permitting multicarrier generation
up to the Nyquist frequency. Features are included for optimizing
direct conversion transmit applications, including complex
digital modulation, as well as gain, phase, and offset compens-
ation. The DAC outputs are optimized to interface seamlessly
with analog quadrature modulators, such as the ADL537x
family from Analog Devices, Inc. A serial peripheral interface
(SPI) provides for programming and readback of many internal
parameters. Full-scale output current can be programmed over
a range of 10 mA to 30 mA. The AD978x family is manufactured
on a 0.18 m CMOS process and operates from 1.8 V and 3.3 V
supplies. It is enclosed in a 100-lead TQFP package.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
2. Proprietary DAC output switching technique enhances
dynamic performance.
3. CMOS data input interface with adjustable setup and hold.
4. Low power complex 32-bit numerically controlled
oscillators (NCOs).
TYPICAL SIGNAL CHAIN
FPGA/ASIC/DSP
DC
COMPLEX I AND Q
DC LO
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
I DAC
Q DAC
DIGITAL INTERPOLATION FILTERS
POST DAC
ANALOG FILTER
A
07098-001
Figure 1.
AD9785/AD9787/AD9788
Rev. A | Page 2 of 64
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications .......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Serial Port Interface .................................................................... 21
SPI Register Map ............................................................................. 24
SPI Register Descriptions .......................................................... 25
Input Data Ports .............................................................................. 33
Single-Port Mode ........................................................................ 33
Dual-Port Mode .......................................................................... 33
Input Data Referenced to DATACLK ...................................... 33
Input Data Referenced to REFCLK .......................................... 35
Optimizing the Data Input Timing .......................................... 36
Input Data RAM ......................................................................... 37
Digital Datapath ............................................................................. 38
Interpolation Filters ................................................................... 38
Quadrature Modulator .............................................................. 40
Numerically Controlled Oscillator .......................................... 40
Inverse Sinc Filter ....................................................................... 40
Digital Amplitude and Offset Control .................................... 41
Digital Phase Correction ........................................................... 41
Device Synchronization ................................................................. 42
Synchronization Logic Overview ............................................. 42
Synchronizing Devices to a System Clock .............................. 44
Synchronizing Multiple Devices to Each Other ..................... 45
Interrupt Request Operation .................................................... 46
Driving the REFCLK Input ........................................................... 47
DAC REFCLK Configuration ................................................... 47
Analog Outputs............................................................................... 50
Digital Amplitude Scaling ......................................................... 50
Power Dissipation ........................................................................... 52
AD9785/AD9787/AD9788 Evaluation Boards........................... 54
Output Configuration ................................................................ 54
Digital Picture of Evaluation Board ......................................... 54
Evaluation Board Software ........................................................ 55
Evaluation Board Schematics ................................................... 56
Outline Dimensions ....................................................................... 62
Ordering Guide .......................................................................... 62
REVISION HISTORY
2/09—Rev. 0 to Rev. A
Added Settling Time, to Within ±0.5 LSBs Parameter, Table 1 .. 3
Added REFCLK Frequency Range, PLL Enabled Parameter,
Table 2 ................................................................................................ 4
Changes to SPI_SDIO—Serial Data I/O Section ....................... 23
Changes to Table 9 .......................................................................... 24
Changes to Table 11 ........................................................................ 26
Changes to Table 12 ........................................................................ 27
Changes to Table 13 ....................................................................... 28
Changes to Table 22 ....................................................................... 32
Changes to Dual-Port Mode Section ........................................... 33
Changes to Input Data RAM Section .......................................... 37
Changes to Digital Amplitude and Offset Control Section ...... 41
Changes to Direct Clocking Section ............................................ 47
1/08—Revision 0: Initial Version
AD9785/AD9787/AD9788
Rev. A | Page 3 of 64
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE 1596 reduced range link, unless otherwise noted.
Table 1.
AD9785 AD9787 AD9788
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION 12 14 16 Bits
ACCURACY
Differential Nonlinearity (DNL) ±0.2 ±0.5 ±2.1 LSB
Integral Nonlinearity (INL) ±0.3 ±1.0 ±3.7 LSB
MAIN DAC OUTPUTS
Offset Error –0.001 0 +0.001 −0.001 0 +0.001 −0.001 0 +0.001 % FSR
Gain Error (with Internal Reference) ±2 ±2 ±2 % FSR
Full-Scale Output Current 8.66 20.2 31.66 8.66 20.2 31.66 8.66 20.2 31.66 mA
Output Compliance Range –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 V
Output Resistance 10 10 10 MΩ
Gain DAC Monotonicity
Guaranteed
10 10 10 Bits
Settling Time, to Within ±0.5 LSBs 20 20 20 ns
MAIN DAC TEMPERATURE DRIFT
Offset 0.04 0.04 0.04 ppm/°C
Gain 100 100 100 ppm/°C
Reference Voltage 30 30 30 ppm/°C
AUX DAC OUTPUTS
Resolution 10 10 10 Bits
Full-Scale Output Current1 –1.998 +1.998 –1.998 +1.998 –1.998 +1.998 mA
Output Compliance Range (Source) 0 1.6 0 1.6 0 1.6 V
Output Compliance Range (Sink) 0.8 1.6 0.8 1.6 0.8 1.6 V
Output Resistance 1 1 1 MΩ
Aux DAC Monotonicity Guaranteed 10 10 10 Bits
REFERENCE
Internal Reference Voltage 1.2 1.2 1.2 V
Output Resistance 5 5 5 kΩ
ANALOG SUPPLY VOLTAGES
AVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
CVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
DIGITAL SUPPLY VOLTAGES
DVDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V
DVDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V
POWER CONSUMPTION
1× Mode, fDATA = 100 MSPS,
PLL Off, IF = 2 MHz
375 450 375 450 375 450 mW
2× Mode, fDATA = 100 MSPS,
Inverse Sinc Off, PLL Off
533 533 533 mW
4× Mode, fDATA = 100 MSPS,
Inverse Sinc Off, PLL Off
754 754 754 mW
8× Mode, fDATA = 100 MSPS,
Inverse Sinc Off, PLL Off
1054 1054 1054 mW
Power-Down Mode 2.5 9.0 2.5 9.0 2.5 9.0 mW
OPERATING RANGE –40 +25 +85 –40 +25 +85 –40 +25 +85 °C
1 Based on a 10 Ω external resistor.
AD9785/AD9787/AD9788
Rev. A | Page 4 of 64
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
CMOS INPUT LOGIC LEVEL
Input VIN Logic High 2.0 V
Input VIN Logic Low
0.8 V
LVDS INPUT (SYNC_I+, SYNC_I−) SYNC_I+ = V1A, SYNC_I− = V1B
Input Voltage Range, VIA or VIB 825 1575 mV
Input Differential Threshold, VIDTH –100 +100 mV
Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV
Receiver Differential Input Impedance, RIN 80 120
LVDS Input Rate (fSYNC_I = fDATA) 30 MHz
Setup Time, SYNC_I to DAC Clock 0.45 ns
Hold Time, SYNC _I to DAC Clock 0.25 ns
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination
Output Voltage High, VOA or VOB 825 1575 mV
Output Voltage Low, VOA or VOB 1025 mV
Output Differential Voltage, |VOD| 150 200 250 mV
Output Offset Voltage, VOS 1150 1250 mV
Output Impedance, Single-Ended, RO 80 100 120
DAC CLOCK INPUT (REFCLK+, REFCLK–)
Differential Peak-to-Peak Voltage 400 800 1600 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate
DVDD18 = 1.8 V ± 5% 800 MHz
DVDD18 = 1.9 V ± 5% 900 MHz
REFCLK Frequency Range, PLL Enabled 30 250 MHz
MAXIMUM INPUT DATA RATE
1× Interpolation 250 MSPS
2× Interpolation 250 MSPS
4× Interpolation
DVDD18 = 1.8 V ± 5% 200 MSPS
DVDD18 = 1.9 V ± 5% 225 MSPS
8× Interpolation
DVDD18 = 1.8 V ±5% 100 MSPS
DVDD18 = 1.9 V ± 5% 112.5 MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK) 40 MHz
Minimum Pulse Width High 12.5 ns
Minimum Pulse Width Low 12.5 ns
Setup Time, SPI_SDIO to SCLK 2.8 ns
Hold Time, SPI_SDIO to SCLK 0.0 ns
Setup Time, SPI_CSB to SCLK 3.0 ns
Data Valid, SPI_SDO to SCLK 10.0 ns
INPUT DATA All modes, −40°C to +85°C1
Setup Time, Input Data to DATACLK 460 ns
Hold Time, Input Data to DATACLK −1.5 ns
Setup Time, Input Data to REFCLK −0.25 ns
Hold Time, Input Data to REFCLK 2.4 ns
AD9785/AD9787/AD9788
Rev. A | Page 5 of 64
Parameter Test Conditions/Comments Min Typ Max Unit
LATENCY (DACCLK CYCLES)
1× Interpolation With or without modulation 40 Cycles
2× Interpolation With or without modulation 83 Cycles
4× Interpolation With or without modulation 155 Cycles
8× Interpolation With or without modulation 294 Cycles
Inverse Sinc 18 Cycles
POWER-UP TIME2 260 ms
DAC Wake-Up Time3 I
OUT current settling to 1% 22 ms
DAC Sleep Time4 I
OUT current to less than 1% of full scale 22 ms
1 Timing vs. temperature and data valid windows are delineated in Table 25.
2 Measured from SPI_CSB rising edge on Register 0x00; toggle Bit 4 from 0 to 1. VREF decoupling capacitor = 0.1 µF.
3 Measured from SPI_CSB rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 0 to 1.
4 Measured from SPI_CSB rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 1 to 0.
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
AD9785 AD9787 AD9788
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
SPURIOUS-FREE DYNAMIC RANGE (IN-BAND SFDR)
fDACCLK = 200 MSPS, fOUT = 70 MHz 1× Interpolation 80 82 83 dBc
fDACCLK = 200 MSPS, fOUT = 70 MHz 2× Interpolation 80 82 83 dBc
fDACCLK = 200 MSPS, fOUT = 70 MHz 4× Interpolation 78 80 81 dBc
fDACCLK = 800 MSPS, fOUT = 40 MHz 8× Interpolation 85 87 90 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDATA = 200 MSPS, fOUT = 50 MHz 1× Interpolation 80 82 83 dBc
fDATA = 200 MSPS, fOUT = 50 MHz 2× Interpolation 78 79 80 dBc
fDATA = 200 MSPS, fOUT = 100 MHz 4× Interpolation 78 79 80 dBc
fDATA = 100 MSPS, fOUT = 100 MHz 8× Interpolation 70 70 70 dBc
NOISE SPECTRAL DENSITY (NSD), EIGHT TONE, 500 kHz TONE
SPACING
fDACCLK = 200 MSPS, fOUT = 80 MHz −154 −157 −158 dBm/Hz
fDACCLK = 400 MSPS, fOUT = 80 MHz −154 −158 −161 dBm/Hz
fDACCLK = 800 MSPS, fOUT = 80 MHz −154 −159 −162 dBm/Hz
WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDACCLK = 491.52 MSPS, fOUT = 100 MHz 4× Interpolation 78 80 82 dBc
fDACCLK = 491.52 MSPS, fOUT = 200 MHz 4× Interpolation 72 74 76 dBc
WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO
(ACLR), SINGLE CARRIER
fDACCLK = 491.52 MSPS, fOUT = 100 MHz 4× Interpolation 80 82 88 dBc
fDACCLK = 491.52 MSPS, fOUT = 200 MHz 4× Interpolation 78 80 82 dBc
AD9785/AD9787/AD9788
Rev. A | Page 6 of 64
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
AVDD33 to AGND, DGND, CGND −0.3 V to +3.6 V
DVDD33, DVDD18, CVDD18
to AGND, DGND, CGND
−0.3 V to +2.1 V
AGND to DGND, CGND −0.3 V to +0.3 V
DGND to AGND, CGND −0.3 V to +0.3 V
CGND to AGND, DGND −0.3 V to +0.3 V
I120, VREF, IPTAT to AGND −0.3 V to AVDD33 + 0.3 V
OUT1_P, OUT1_N, OUT2_P, OUT2_N,
AUX1_P, AUX1_N, AUX2_P,
AUX2_N to AGND
−1.0 V to AVDD33 + 0.3 V
P1D[15] to P1D[0], P2D[15] to P2D[0]
to DGND
−0.3 V to DVDD33 + 0.3 V
DATACLK, TXENABLE to DGND −0.3 V to DVDD33 + 0.3 V
REFCLK+, REFCLK−, RESET, IRQ,
PLL_LOCK, SYNC_O+, SYNC_O−,
SYNC_I+, SYNC_I− to CGND
−0.3 V to CVDD18 + 0.3 V
RESET, IRQ, PLL_LOCK, SYNC_O+,
SYNC_O−, SYNC_I+, SYNC_I−,
SPI_CSB, SCLK, SPI_SDIO, SPI_SDO
to DGND
−0.3 V to DVDD33 + 0.3 V
Junction Temperature 125°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
For this 100-lead, thermally enhanced TQFP, the exposed paddle
(EPAD) must be soldered to the ground plane. Note that these
specifications are valid with no airflow movement.
Table 5. Thermal Resistance
Resistance Unit Conditions
θJA 19.1°C/W EPAD soldered. No airflow.
θJB 12.4°C/W EPAD soldered. No airflow.
θJC 7.1°C/W EPAD soldered. No airflow.
ESD CAUTION
AD9785/AD9787/AD9788
Rev. A | Page 7 of 64
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
74 VREF
73 IPTAT
72 AGND
69 SPI_CSB
70 RESET
71 IRQ
75 I120
68 SCLK
67 SPI_SDIO
66 SPI_SDO
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 NC
58 NC
57 NC
56 NC
55 P2D[0]
54 DGND
53 DVDD18
52 P2D[1]
51 P2D[2]
65 PLL_LOCK
PIN 1 INDICATOR
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D[4]
27
P1D[3]
28
P1D[2]
29
P1D[1]
30
P1D[0]
31
NC
32
DGND
33
DVDD18
34
NC
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D[11]
41
P2D[10]
42
P2D[9]
43
DVDD18
44
DGND
45
P2D[8]
46
P2D[7]
47
P2D[6]
48
P2D[5]
49
P2D[4]
50
P2D[3]
2
CVDD18
3
CGND
4
CGND
7
CGND
6
REFCLK–
5
REFCLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I
15
DGND
16
DVDD18
17
P1D[11]
18
P1D[10]
19
P1D[9]
20
P1D[8]
21
P1D[7]
22
DGND
23
DVDD18
24
P1D[6]
25
P1D[5]
11
CGND
AD9785
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
07098-005
Figure 2. AD9785 Pin Configuration
Table 6. AD9785 Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 9, 10 CVDD18 1.8 V Clock Supply.
3, 4, 7, 8, 11 CGND Clock Common.
5 REFCLK+ Differential Clock Input, Positive.
6 REFCLK− Differential Clock Input, Negative.
12, 72, 77, 79, 81, 82, 85,
88, 91, 94, 95, 97, 99
AGND Analog Common.
13 SYNC_I+ Differential Synchronization Input, Positive.
14 SYNC_I− Differential Synchronization Input, Negative.
15, 22, 32, 44, 54, 64 DGND Digital Common.
16, 23, 33, 43, 53, 60 DVDD18 1.8 V Digital Supply.
17 P1D[11] Port 1, Data Input D11 (MSB).
18 P1D[10] Port 1, Data Input D10.
19 P1D[9] Port 1, Data Input D9.
20 P1D[8] Port 1, Data Input D8.
21 P1D[7] Port 1, Data Input D7.
24 P1D[6] Port 1, Data Input D6.
25 P1D[5] Port 1, Data Input D5.
26 P1D[4] Port 1, Data Input D4.
27 P1D[3] Port 1, Data Input D3.
28 P1D[2] Port 1, Data Input D2.
AD9785/AD9787/AD9788
Rev. A | Page 8 of 64
Pin No. Mnemonic Description
29 P1D[1] Port 1, Data Input D1.
30 P1D[0] Port 1, Data Input D0 (LSB).
31, 34 to 36, 56 to 59 NC No Connection Necessary.
37 DATACLK Data Clock Output.
38, 61 DVDD33 3.3 V Digital Supply.
39 TXENABLE Transmit Enable.
40 P2D[11] Port 2, Data Input D11 (MSB).
41 P2D[10] Port 2, Data Input D10.
42 P2D[9] Port 2, Data Input D9.
45 P2D[8] Port 2, Data Input D8.
46 P2D[7] Port 2, Data Input D7.
47 P2D[6] Port 2, Data Input D6.
48 P2D[5] Port 2, Data Input D5.
49 P2D[4] Port 2, Data Input D4.
50 P2D[3] Port 2, Data Input D3.
51 P2D[2] Port 2, Data Input D2.
52 P2D[1] Port 2, Data Input D1.
55 P2D[0] Port 2, Data Input D0 (LSB).
62 SYNC_O− Differential Synchronization Output, Negative.
63 SYNC_O+ Differential Synchronization Output, Positive.
65 PLL_LOCK PLL Lock Indicator.
66 SPI_SDO SPI Port Data Output.
67 SPI_SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 SPI_CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
73 IPTAT
Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 A at
25°C with approximately 20 nA/°C slope. This pin should remain floating.
74 VREF Voltage Reference Output.
75 I120 120 A Reference Current.
76, 78, 80, 96, 98, 100 AVDD33 3.3 V Analog Supply.
83 OUT2_P Differential DAC Current Output, Positive, Channel 2.
84 OUT2_N Differential DAC Current Output, Negative, Channel 2.
86 AUX2_P Auxiliary DAC Current Output, Positive, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Negative, Channel 2.
89 AUX1_N Auxiliary DAC Current Output, Negative, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Positive, Channel 1.
92 OUT1_N Differential DAC Current Output, Negative, Channel 1.
93 OUT1_P Differential DAC Current Output, Positive, Channel 1.
Exposed Paddle EPAD Conductive Heat Sink. Connect to analog common (AGND).
AD9785/AD9787/AD9788
Rev. A | Page 9 of 64
74 VREF
73 IPTAT
72 AGND
69 SPI_CSB
70 RESET
71 IRQ
75 I120
68 SCLK
67 SPI_SDIO
66 SPI_SDO
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 NC
58 NC
57 P2D[0]
56 P2D[1]
55 P2D[2]
54 DGND
53 DVDD18
52 P2D[3]
51 P2D[4]
65 PLL_LOCK
PIN 1 INDICATOR
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D[6]
27
P1D[5]
28
P1D[4]
29
P1D[3]
30
P1D[2]
31
P1D[1]
32
DGND
33
DVDD18
34
P1D[0]
35
NC
36
NC
37
DATACLK
38
DVDD33
39
TXENABLE
40
P2D[13]
41
P2D[12]
42
P2D[11]
43
DVDD18
44
DGND
45
P2D[10]
46
P2D[9]
47
P2D[8]
48
P2D[7]
49
P2D[6]
50
P2D[5]
2
CVDD18
3
CGND
4
CGND
7
CGND
6
REFCLK–
5
REFCLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I
15
DGND
16
DVDD18
17
P1D[13]
18
P1D[12]
19
P1D[11]
20
P1D[10]
21
P1D[9]
22
DGND
23
DVDD18
24
P1D[8]
25
P1D[7]
11
CGND
AD9787
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
NC = NO CONNECT
07098-004
Figure 3. AD9787 Pin Configuration
Table 7. AD9787 Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 9, 10 CVDD18 1.8 V Clock Supply.
3, 4, 7, 8, 11 CGND Clock Common.
5 REFCLK+ Differential Clock Input, Positive.
6 REFCLK− Differential Clock Input, Negative.
12, 72, 77, 79, 81, 82, 85,
88, 91, 94, 95, 97, 99
AGND Analog Common.
13 SYNC_I+ Differential Synchronization Input, Positive.
14 SYNC_I− Differential Synchronization Input, Negative.
15, 22, 32, 44, 54, 64 DGND Digital Common.
16, 23, 33, 43, 53, 60 DVDD18 1.8 V Digital Supply.
17 P1D[13] Port 1, Data Input D13 (MSB).
18 P1D[12] Port 1, Data Input D12.
19 P1D[11] Port 1, Data Input D11.
20 P1D[10] Port 1, Data Input D10.
21 P1D[9] Port 1, Data Input D9.
24 P1D[8] Port 1, Data Input D8.
25 P1D[7] Port 1, Data Input D7.
26 P1D[6] Port 1, Data Input D6.
27 P1D[5] Port 1, Data Input D5.
28 P1D[4] Port 1, Data Input D4.
29 P1D[3] Port 1, Data Input D3.
30 P1D[2] Port 1, Data Input D2.
AD9785/AD9787/AD9788
Rev. A | Page 10 of 64
Pin No. Mnemonic Description
31 P1D[1] Port 1, Data Input D1.
34 P1D[0] Port 1, Data Input D0 (LSB).
35, 36, 58, 59 NC No Connection Necessary.
37 DATACLK Data Clock Output.
38, 61 DVDD33 3.3 V Digital Supply.
39 TXENABLE Transmit Enable.
40 P2D[13] Port 2, Data Input D13 (MSB).
41 P2D[12] Port 2, Data Input D12.
42 P2D[11] Port 2, Data Input D11.
45 P2D[10] Port 2, Data Input D10.
46 P2D[9] Port 2, Data Input D9.
47 P2D[8] Port 2, Data Input D8.
48 P2D[7] Port 2, Data Input D7.
49 P2D[6] Port 2, Data Input D6.
50 P2D[5] Port 2, Data Input D5.
51 P2D[4] Port 2, Data Input D4.
52 P2D[3] Port 2, Data Input D3.
55 P2D[2] Port 2, Data Input D2.
56 P2D[1] Port 2, Data Input D1.
57 P2D[0] Port 2, Data Input D0 (LSB).
62 SYNC_O− Differential Synchronization Output, Negative.
63 SYNC_O+ Differential Synchronization Output, Positive.
65 PLL_LOCK PLL Lock Indicator.
66 SPI_SDO SPI Port Data Output.
67 SPI_SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 SPI_CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
73 IPTAT
Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 A
at 25°C with approximately 20 nA/°C slope. This pin should remain floating.
74 VREF Voltage Reference Output.
75 I120 120 A Reference Current.
76, 78, 80, 96, 98, 100 AVDD33 3.3 V Analog Supply.
83 OUT2_P Differential DAC Current Output, Positive, Channel 2.
84 OUT2_N Differential DAC Current Output, Negative, Channel 2.
86 AUX2_P Auxiliary DAC Current Output, Positive, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Negative, Channel 2.
89 AUX1_N Auxiliary DAC Current Output, Negative, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Positive, Channel 1.
92 OUT1_N Differential DAC Current Output, Negative, Channel 1.
93 OUT1_P Differential DAC Current Output, Positive, Channel 1.
Exposed Paddle EPAD Conductive Heat Sink. Connect to analog common (AGND).
AD9785/AD9787/AD9788
Rev. A | Page 11 of 64
74 VREF
73 IPTAT
72 AGND
69 SPI_CSB
70 RESET
71 IRQ
75 I120
68 SCLK
67 SPI_SDIO
66 SPI_SDO
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 P2D[0]
58 P2D[1]
57 P2D[2]
56 P2D[3]
55 P2D[4]
54 DGND
53 DVDD18
52 P2D[5]
51 P2D[6]
65 PLL_LOCK
PIN 1 INDICATOR
100
AVDD33
99
AGND
98
AVDD33
97
AGND
96
AVDD33
95
AGND
94
AGND
93
OUT1_P
92
OUT1_N
91
AGND
90
AUX1_P
89
AUX1_N
88
AGND
87
AUX2_N
86
AUX2_P
85
AGND
84
OUT2_N
83
OUT2_P
82
AGND
81
AGND
80
AVDD33
79
AGND
78
AVDD33
77
AGND
76
AVDD33
26
P1D[8]
27
P1D[7]
28
P1D[6]
29
P1D[5]
30
P1D[4]
31
P1D[3]
32
DGND
33
DVDD18
34
P1D[2]
35
P1D[1]
36
P1D[0]
37
DATACLK
38
DVDD33
39
T
XENABLE
40
P2D[15]
41
P2D[14]
42
P2D[13]
43
DVDD18
44
DGND
45
P2D[12]
46
P2D[11]
47
P2D[10]
48
P2D[9]
49
P2D[8]
50
P2D[7]
2
CVDD18
3
CGND
4
CGND
7
CGND
6
REFCLK–
5
REFCLK+
1
CVDD18
8
CGND
9
CVDD18
10
CVDD18
12
AGND
13
SYNC_I+
14
SYNC_I
15
DGND
16
DVDD18
17
P1D[15]
18
P1D[14]
19
P1D[13]
20
P1D[12]
21
P1D[11]
22
DGND
23
DVDD18
24
P1D[10]
25
P1D[9]
11
CGND
AD9788
TOP VIEW
(Not to Scale)
ANALOG DOMAIN
DIGITAL DOMAIN
0
7098-003
Figure 4. AD9788 Pin Configuration
Table 8. AD9788 Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 9, 10 CVDD18 1.8 V Clock Supply.
3, 4, 7, 8, 11 CGND Clock Common.
5 REFCLK+ Differential Clock Input, Positive.
6 REFCLK− Differential Clock Input, Negative.
12, 72, 77, 79, 81, 82, 85,
88, 91, 94, 95, 97, 99
AGND Analog Common.
13 SYNC_I+ Differential Synchronization Input, Positive.
14 SYNC_I− Differential Synchronization Input, Negative.
15, 22, 32, 44, 54, 64 DGND Digital Common.
16, 23, 33, 43, 53, 60 DVDD18 1.8 V Digital Supply.
17 P1D[15] Port 1, Data Input D15 (MSB).
18 P1D[14] Port 1, Data Input D14.
19 P1D[13] Port 1, Data Input D13.
20 P1D[12] Port 1, Data Input D12.
21 P1D[11] Port 1, Data Input D11.
24 P1D[10] Port 1, Data Input D10.
25 P1D[9] Port 1, Data Input D9.
26 P1D[8] Port 1, Data Input D8.
27 P1D[7] Port 1, Data Input D7.
28 P1D[6] Port 1, Data Input D6.
29 P1D[5] Port 1, Data Input D5.
30 P1D[4] Port 1, Data Input D4.
AD9785/AD9787/AD9788
Rev. A | Page 12 of 64
Pin No. Mnemonic Description
31 P1D[3] Port 1, Data Input D3.
34 P1D[2] Port 1, Data Input D2.
35 P1D[1] Port 1, Data Input D1.
36 P1D[0] Port 1, Data Input D0 (LSB).
37 DATACLK Data Clock Output.
38, 61 DVDD33 3.3 V Digital Supply.
39 TXENABLE Transmit Enable.
40 P2D[15] Port 2, Data Input D15 (MSB).
41 P2D[14] Port 2, Data Input D14.
42 P2D[13] Port 2, Data Input D13.
45 P2D[12] Port 2, Data Input D12.
46 P2D[11] Port 2, Data Input D11.
47 P2D[10] Port 2, Data Input D10.
48 P2D[9] Port 2, Data Input D9.
49 P2D[8] Port 2, Data Input D8.
50 P2D[7] Port 2, Data Input D7.
51 P2D[6] Port 2, Data Input D6.
52 P2D[5] Port 2, Data Input D5.
55 P2D[4] Port 2, Data Input D4.
56 P2D[3] Port 2, Data Input D3.
57 P2D[2] Port 2, Data Input D2.
58 P2D[1] Port 2, Data Input D1.
59 P2D[0] Port 2, Data Input D0 (LSB).
62 SYNC_O− Differential Synchronization Output, Negative.
63 SYNC_O+ Differential Synchronization Output, Positive.
65 PLL_LOCK PLL Lock Indicator.
66 SPI_SDO SPI Port Data Output.
67 SPI_SDIO SPI Port Data Input/Output.
68 SCLK SPI Port Clock.
69 SPI_CSB SPI Port Chip Select Bar.
70 RESET Reset, Active High.
71 IRQ Interrupt Request.
73 IPTAT
Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 A
at 25°C with approximately 20 nA/°C slope. This pin should remain floating.
74 VREF Voltage Reference Output.
75 I120 120 A Reference Current.
76, 78, 80, 96, 98, 100 AVDD33 3.3 V Analog Supply.
83 OUT2_P Differential DAC Current Output, Positive, Channel 2.
84 OUT2_N Differential DAC Current Output, Negative, Channel 2.
86 AUX2_P Auxiliary DAC Current Output, Positive, Channel 2.
87 AUX2_N Auxiliary DAC Current Output, Negative, Channel 2.
89 AUX1_N Auxiliary DAC Current Output, Negative, Channel 1.
90 AUX1_P Auxiliary DAC Current Output, Positive, Channel 1.
92 OUT1_N Differential DAC Current Output, Negative, Channel 1.
93 OUT1_P Differential DAC Current Output, Positive, Channel 1.
Exposed Paddle EPAD Conductive Heat Sink. Connect to analog common (AGND).
AD9785/AD9787/AD9788
Rev. A | Page 13 of 64
TYPICAL PERFORMANCE CHARACTERISTICS
170
0 100
f
OUT
(MHz)
NSD (dBm/Hz)
142
20 40 60 80
166
162
158
154
146
07098-064
150
Figure 5. AD9785 Noise Spectral Density vs. fOUT, Multitone Input,
fDATA = 200 MSPS
170
0 100
f
OUT
(MHz)
NSD (dBm/Hz)
142
20 40 60 80
166
162
158
154
150
146
07098-065
Figure 6. AD9785 Noise Spectral Density vs. fOUT, Single-Tone Input,
fDATA = 200 MSPS
90
0 260
f
OUT
(MHz)
ACLR (dBc)
55
20 40 60 80 100 120 140 160 180 200 220 240
85
80
75
70
65
60
07098-066
FIRST ADJ CHAN
THIRD ADJ CHAN
SECOND ADJ CHAN
Figure 7. AD9785 ACLR, 4× Interpolation, fDATA = 122.88 MSPS
50
0 100
f
OUT
(MHz)
SFDR (dB)
100
20 40 60 80
55
60
65
70
75
80
85
90
95
07098-067
250 MSPS
160 MSPS
200 MSPS
Figure 8. AD9785 In-Band SFDR vs. fOUT, 2× Interpolation
50
0 400
f
OUT
(MHz)
IMD (dBc)
100
40 80 120 160 200 240 280 320 360
60
70
80
90
07098-068
100 MSPS
200 MSPS
150 MSPS
Figure 9. AD9785 IMD vs. fOUT, 4× Interpolation
07098-069
f
OUT
(MHz)
ACLR (dBc)
–90
–85
–80
–75
–70
–65
–60
–55
0 20 40 60 80 100 120 140 160 180 200 220 240 260
THIRD ADJ CHAN
FIRST ADJ CHAN
SECOND ADJ CHAN
Figure 10. AD9787 ACLR, 4× Interpolation, fDATA = 122.88 MSPS
AD9785/AD9787/AD9788
Rev. A | Page 14 of 64
07098-070
f
OUT
(MHz)
ACLR (dBc)
–90
–85
–80
–75
–70
–65
–60
55
0 20 40 60 80 100 120 140 160 180 200 220 240 260
THIRD ADJ CHAN
FIRST ADJ CHAN
SECOND ADJ CHAN
Figure 11. AD9787 ACLR, 4× Interpolation, fDATA = 122.88 MSPS,
Amplitude = −3 dB
50
60
70
80
90
100
0 40 80 120 160 200 240 280 320 360 400
07098-071
f
OUT
(MHz)
IMD (dBc)
100MSPS
150MSPS
200MSPS
Figure 12. AD9787 IMD vs. fOUT, 4× Interpolation
55
60
65
70
75
80
85
90
95
20 40 60 80 100
50
100
0
07098-072
f
OUT
(MHz)
SFDR (dB)
160MSPS
250MSPS
200MSPS
Figure 13. AD9787 In-Band SFDR vs. fOUT, 2× Interpolation
–170
–166
–162
–158
–154
–150
–146
–142
20 40 60 80 100
0
07098-073
f
OUT
(MHz)
NSD (dBm/Hz)
Figure 14. AD9787 Noise Spectral Density vs. fOUT over Output Frequency of
Multitone Input, fDATA = 200 MSPS
–170
–166
–162
–158
–154
–150
–146
142
20 40 60 80 100
0
07098-074
f
OUT
(MHz)
NSD (dBm/Hz)
Figure 15. AD9787 Noise Spectral Density vs. fOUT, Single-Tone Input,
fDATA = 200 MSPS
–90
0 260
f
OUT
(MHz)
ACLR (dBc)
55
4020 60 80 100 120 140 160 180 200 220 240
85
80
75
70
65
60
07098-076
0 dBFS PLL ON
0 dBFS PLL OFF
3 dBFS PLL OFF
6 dBFS PLL OFF
Figure 16. AD9788 ACLR for First Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, NCO Translates Baseband Signal to IF
AD9785/AD9787/AD9788
Rev. A | Page 15 of 64
–90
0 260
f
OUT
(MHz)
ACLR (dBc)
55
4020 60 80 100 120 140 160 180 200 220 240
85
80
75
70
65
60
07098-077
0 dBFS PLL ON
0 dBFS PLL OFF
3 dBFS PLL OFF
6 dBFS PLL OFF
Figure 17. AD9788 ACLR for Second Adjacent Band WCDMA,
4× Interpolation, fDATA = 122.88 MSPS, NCO Translates Baseband Signal to IF
–90
0 260
f
OUT
(MHz)
ACLR (dBc)
70
4020 60 80 100 120 140 160 180 200 220 240
85
80
75
07098-078
0 dBFS PLL ON
0 dBFS PLL OFF
6 dBFS PLL OFF
3 dBFS PLL OFF
Figure 18. AD9788 ACLR for Third Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, NCO Translates Baseband Signal to IF
50
60
70
80
90
100
0 20 40 60 80 100 120
07098-079
f
OUT
(MHz)
IMD (dBc)
200MSPS
160MSPS
250MSPS
Figure 19. AD9788 IMD vs. fOUT, 1× Interpolation
50
60
70
80
90
100
0 50 100 150 200
07098-080
f
OUT
(MHz)
IMD (dBc)
200MSPS
160MSPS
250MSPS
Figure 20. AD9788 IMD vs. fOUT, 2× Interpolation
50
60
70
80
90
100
0 40 80 120 160 200 240 280 320 360 400
07098-081
f
OUT
(MHz)
IMD (dBc)
200MSPS
150MSPS
100MSPS
Figure 21. AD9788 IMD vs. fOUT, 4× Interpolation
50
60
70
80
90
100
0 20 40 60 80 100 120 140 160 180 200
07098-082
f
OUT
(MHz)
IMD (dBc)
PLL ON
PLL OFF
Figure 22. AD9788 IMD vs. fOUT, 8× Interpolation, fDATA = 100 MSPS,
PLL On/PLL Off
AD9785/AD9787/AD9788
Rev. A | Page 16 of 64
50
60
70
80
90
100
07098-083
f
OUT
(MHz)
IMD (dBc)
0 50 100 150 200 250 300 350 400 450
100MSPS
75MSPS
50MSPS
Figure 23. AD9788 IMD vs. fOUT, 8× Interpolation
50
60
70
80
90
100
0 40 80 120 160 200 240 280 320 360 400
07098-084
f
OUT
(MHz)
IMD (dBc)
–6dBFS
0dBFS
–3dBFS
Figure 24. AD9788 IMD Performance vs. Digital Full-Scale Input,
4× Interpolation, fDATA = 200 MSPS
50
60
70
80
90
100
0 40 80 120 160 200 240 280 320 360 400
07098-085
fOUT
(MHz)
IMD (dBc)
20mA
10mA
30mA
Figure 25. AD9788 IMD Performance vs. Full-Scale Output Current,
4× Interpolation, fDATA = 200 MSPS
50
60
70
80
90
100
0 40 80 120 160 200 240 280 320 360 400
07098-086
fOUT
(MHz)
IMD (dBc)
55
65
75
85
95
Figure 26. AD9788 IMD vs. fOUT, over 50 Parts, 4× Interpolation,
fDATA = 200 MSPS
07098-087
f
OUT
(MHz)
NSD (dBm/Hz)
–170
–166
–162
–158
–154
–150
–146
142
0 20 40 60 80 100
0dBFS
–3dBFS
–6dBFS
Figure 27. AD9788 Noise Spectral Density vs. Digital Full-Scale Single-Tone
Input, fDATA = 200 MSPS, 2× Interpolation
07098-088
fOUT
(MHz)
NSD (dBm/Hz)
–170
–166
–162
–158
–154
–150
–146
142
01020304050
Figure 28. AD9788 Noise Spectral Density vs. fOUT, Multitone Input,
fDATA = 100 MSPS
AD9785/AD9787/AD9788
Rev. A | Page 17 of 64
07098-089
fOUT
(MHz)
NSD (dBm/Hz)
–170
–166
–162
–158
–154
–150
–146
142
01020304050
Figure 29. AD9788 Noise Spectral Density vs. fOUT, Single-Tone Input,
fDATA = 100 MSPS
07098-090
f
OUT
(MHz)
NSD (dBm/Hz)
–170
–166
–162
–158
–154
–150
–146
142
020406080100
Figure 30. AD9788 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
07098-091
f
OUT
(MHz)
NSD (dBm/Hz)
–170
–166
–162
–158
–154
–150
–146
142
020406080100
Figure 31. AD9788 Noise Spectral Density vs. fDAC, Full-Scale Single-Tone
Input at −6 dB, fDATA = 200 MSPS
55
60
65
70
75
80
85
250MSPS
07098-092
f
OUT
(MHz)
SFDR (dB)
50
90
020406080100
160MSPS
200MSPS
Figure 32. AD9788 In-Band SFDR vs. fOUT, 1× Interpolation
50
55
60
65
70
75
80
0102030405060708090100
07098-093
f
OUT
(MHz)
SFDR (dB)
250MSPS
200MSPS
160MSPS
Figure 33. AD9788 Out-of-Band SFDR vs. fOUT, 2× Interpolation
20mA
50
55
60
65
70
75
80
85
90
95
30mA
0 1020304050607080
07098-094
f
OUT
(MHz)
SFDR (dB)
10mA
Figure 34. AD9788 In-Band SFDR vs. Full-Scale Output Current,
2× Interpolation, fDATA = 200 MSPS
AD9785/AD9787/AD9788
Rev. A | Page 18 of 64
50
60
70
80
90
100
110
0102030405060708090
07098-095
fOUT (MHz)
SFDR (dB)
100MSPS
150MSPS
200MSPS
Figure 35. AD9788 In-Band SFDR vs. fOUT, 4× Interpolation
50
55
60
65
70
75
80
0102030405060708090
07098-096
f
OUT
(MHz)
SFDR (dB)
150MSPS
200MSPS
100MSPS
Figure 36. AD9788 Out-of-Band SFDR vs. fOUT, 4× Interpolation
55
60
65
70
75
80
85
90
01020304050607080
50
07098-097
fOUT (MHz)
SFDR (dB)
–6dBFS
0dBFS –3dBFS
Figure 37. AD9788 In-Band SFDR vs. Digital Full-Scale Input,
2× Interpolation, fDATA = 200 MSPS
50
55
60
65
70
75
80
85
90
95
100
0 20406080100
250MSPS
07098-098
f
OUT
(MHz)
SFDR (dB)
200MSPS
160MSPS
Figure 38. AD9788 In-Band SFDR vs. fOUT, 2× Interpolation
50
60
70
80
90
100
110
0 1020304050
50MSPS
100MSPS
07098-099
f
OUT
(MHz)
SFDR (dB)
Figure 39. AD9788 In-Band SFDR vs. fOUT, 8× Interpolation
50
55
60
65
70
75
80
85
90
0 5 10 15 20 25 30 35 40 45
07098-100
f
OUT
(MHz)
SFDR (dB)
50MSPS
100MSPS
Figure 40. AD9788 Out-of-Band SFDR vs. fOUT, 8× Interpolation