~ ANALOG DEVICES AN-381 APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 e 617/329-4700 Obtaining the Best Performance from the AD7893, 12-Bit Serial A/D Converter by Albert OGrady and Mike Byrne INTRODUCTION This application note discusses a proper printed circuit layout and contains application hints on how to obtain the best performance from the AD7893. Topics for dis- cussion include the design and layout of a printed cir- cuit board and the advantages and disadvantages of different timing and control sequences. The AD7893 is a fast 12-bit successive approximation A/D which oper- ates from a single +5 V supply and incorporates an on- chip track-and-hold amplifier, on-chip clock and a high speed serial interface. All of these functions are housed in a small 8-pin mini-DIP or 8-pin SOIC. The serial inter- face allows the AD7893 to connect directly to digital signal processors (ADSP-2101, TMS320C25, etc.) and microcontrollers (8XC51, 68HC11,etc.). The perfor- mance of the AD7893, like that of any high resolution ADC, is influenced by surrounding circuitry, board lay- out and microprocessor interfacing. The AD7893 uses a successive approximation technique in providing the analog-to-digital function. The conver- sion time for the A/D is 6 us, requiring the internal volt- age comparator to make a bit decision every 500 ns. In order to achieve 12-bit performance these decisions must be accurate to 1/2 LSB. This amounts to 305 pV for the 0 V to 2.5 V input range and 2.44 mV in the +10 V analog input range part. To achieve this performance, the circuit designer must be conscious of noise both in the ADC itself and in the preceding analog circuitry. Other major causes for concern are ground loops and digital feedthrough from the interface bus. These are factors that influence any ADC design, and a proper printed circuit board layout that minimizes these effects is essential to achieve 12-bit performance. PRINTED CIRCUIT BOARD LAYOUT HINTS The board should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally found to be the best for ground planes as this gives the best shielding. Digital and analog grounds planes should be joined only in one place. If the AD7893 is the only device that requires AGND and DGND connection, then the ground planes should be connected at the AGND and DGND pins of the ADC. If the AD7893 is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point, a star ground point which should be established as close as possible to the AD7893. Data and address buses on the board should be buffered or latched to isolate the high frequency bus of the pro- cessor from the bus of the high resolution converter. These act as a Faraday shield and will increase the signal-to-noise performance of the converters by reduc- ing the amount of high frequency digital coupling. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7893 to avoid noise coupling. The power supply lines to the AD7893 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near analog inputs of devices. Avoid crossovers of digital and analog signals. Traces for analog inputs should be kept as wide and as short as possible and should be shielded with analog ground where possible. When buffering analog inputs, the buffer should be kept as close to the analog input of the ADC as possible. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Good decoupling is vitally important when using high resolution ADCs. All analog supplies should be decoupled with 10 pF tantalum in parallel with 0.1 uF ceramic capaci- tors to analog ground. To achieve the best from the decoupling components, these must be placed as close to the device as possibleideally right up against the IC socket. The main aim of a bypassing element is to maxi- mize the charge stored in the bypass loop while simulta- neously minimizing the inductance of this loop. Inductance in the loop acts as an impedance to high fre- quency transients and results in power supply spiking. By keeping the decoupling as close to the device as possible, the loop area is kept as small as possible, thus reducing the possibility of power supply spikes. Vop and Vss Sup- plies of amplifiers should be decoupled again with 10 uF and 0.1 pF to AGND. All logic chips should be decoupled with 0.1 uF disc ceramic capacitors to digital ground. EVALUATING AD7893 PERFORMANCE Figure 1 shows the application circuit schematic for the AD7893 circuit board. The design and tayout of this board uses the recommendations discussed in Printed Circuit Board Layout Hints on the previous page. The circuit schematic shown in Figure 1 differs from that used in the evaluation board (MC/BV-AD7893-EB) available from Ana- log Devices. The MC/BV-AD7893-EB layout contains some extra circuitry used to evaluate the AD7890, another 12- bit ADC in the AD789X series of ADCs. The same layout and grounding techniques are used on both circuit boards. The board designed from Figure 1 is used specifically for evaluating the AD7893, and the redundant circuitry re- quired for the AD7890 has been omitted. Onboard compo- nents include an AD780, a pin programmable +2.5 V or 3 V ultrahigh precision bandgap reference, bus buffers for the serial data lines and an input buffer amplifier to buffer the analog input. Interfacing to this board is through a 9- way D-type connector. External sockets are provided for the conversion start input, analog input and an external reference input option. Figures 13, 14 and 15 at the back of this application note show the silkscreen, component and solder side artworks for the schematic shown in Figure 1. Refer to the section titled Operating the AD7893 Circuit Board for more information on setting up and operating this board. TIMING AND CONTROL FOR OPTIMUM PERFORMANCE OF THE AD7893 Figure 2 shows the control sequence required to obtain optimum performance from the AD7893. Inthe sequence shown, conversion is initiated on the rising edge of CONVST and new data from this conversion is available in the output register of the AD7893 6 us later. Once the read operation has taken place, a further 600 ns should be al- lowed before the next rising edge of CONVST to optimize 5vO Vin O.1pF AD780 + 6) Vout 10uF ; DVop Ct 10nF Ic 3 C2 v GND C10 == 0.1pF 1 (4) re) 3 10 19 EXT REF DATAOUT (7) : (5) SDATA BSW KI SKT4 tfe 2 9 | REFIN (1) DGND | bo @ soux our ov = \ TOHF O.AuF | AD7893 c7 ce 14 | 14s + SKT2 scik (1) 3 I (7) CONVST 6 + pS 0) V7! Vin (2) 1c 2 2 ANALOG Ica INPUT DVop (8) 1/3 74HC4050 G) (3) AB Ov, O-O PY TORE O1uF OO C5 Ota O v- = ict 7 + CONVST LK3 SKI1 SKT3 Figure 1. Evaluation Board Circuit Diagram50ns MIN r< 7 CONVST | LJ I " T j | tconvert CONVERSION IS CONVERSION INITIATED AND ENDS 6ys TRACK/HOLD GOES LATER INTO HOLD SERIAL READ OPERATION READ OPERATION OUTPUT SERIAL SHOULDEND SHIFT REGISTER 600ns PRIOR TO IS RESET NEXT RISING EDGE OF CONVST Figure 2. Optimum Control Sequence for the AD7893 the settling of the track/hold amplifier before the next conversion is initiated. Using the maximum serial clock frequency with this sequence gives a maximum throughput rate of 117 kHz. The serial interface to the AD7893 consists of just two wires, a serial clock input (SCLK) and the serial data output (SDATA). Due to the small pin count, there is no status signal provided to in- dicate end of conversion. Applications that want to achieve optimum performance from the AD7893 will have to ensure that the data read does not occur during conversion or 600ns prior to the rising edge of CONVST. One way to achieve this is to ensure in soft- ware that the read operation is not initiated unti! 6 us after the rising edge of CONVST. This will only be pos- sible if the software knows when the CONVST command is issued. 94 Fsampte = 102. 91 TIMING SETUP AS IN FIGURE 2 88 85 82 dB 79 76 73 70 67 64 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 FREQUENCY - Hz Figure 3. THD & SNR vs. Frequency @ 100 kHz Sampling Figures 3, 4, 5 and 6 show the performance of the AD7893 when used in the AD7893 circuit board. The tim- ing setup for the experiments is as in Figure 2. The sam- pling frequency used is 100 kHz and the seria! clock frequency used is 8 MHz. Figure 3 shows a plot for THD and SNR versus frequency. These results show that for an input frequency of 10 kHz the SNR is typically 71.5 dB and the THD is -82.5 dB. Figure 4 shows a noise histo- gram for the same setup as above. The analog input was centered on code 2047 and 8000 conversions were taken from the AD7893. The results show that the code distri- bution is three counts. The rms noise calculated from this distribution is 0.198 LSBs. Figure 5 shows a typical FFT plot for an input frequency of 10 kHz while Figure 6 shows an FFT for a 50 kHz input. The plots show that the second and third harmonics have increased in ampli- tude when going from a 10 kHz input to a 50 kHz input. This contributes to the reduction in SNR and THD shown in Figure 3. 8000 7000 Fsampce = 102.4kHz Fsci x = 8MHz, Ay CENTERED 6000 ON CODE 2047, 7 ul RMS NOISE = 0.198 LSBs oO Q 5000 Ww Fa = 4000 OQ Oo 3000 2000 1000 0 _ nn 2046 2047 2048 CODE Figure 4. Noise Histogram @ 100 kHz SamplingFoampte = 102.4kHz -20 Fin = 10kHz S SNR = 71,54dB THD = ~82.43dB 40 -60 30720 i 20480 FREQUENCY - Hz 40960 Figure 5. Typical FFT Plot for a 10 kHz Input READING DURING CONVERSION The throughput rate of the AD7893 can be increased by reading data during conversion. The track and hold re- turns to the track mode at the end of conversion and re- quires 1.5 ys to acquire an input signal to an accuracy level of 12 bits. The conversion time for the ADC is inter- nally timed using a laser-trimmed clock oscillator and requires 6 us to convert the signal. The minimum through- put time is 7.5 us (6us+1.5s) resulting ina maximum throughput rate of 133 kHz. Figure 7 shows the timing setup when operating the AD7893 in this arrangement. The output register of the AD7893 is normally updated at the end of conversion. However, if a serial read is in progress at this time, the update is deferred until this read 5Ons MIN 6 Ww a. sou ! UL ) tconverr = SHS CONVERSION IS SERIAL READ INITIATED AND OPERATION TRACK/HOLD GOES INTO HOLD Fgampie = 102.4kH2 ~20 Fiy = 5OkHz SNR = 69.890B THD = -75.62dB 40 m 60 -8o ++ 100 -120 T 1 o! to2zad =. 20480!': 0720 40g6d 51200 FREQUENCY - Hz Figure 6. Typical FFT Plot for a 50 kHz Input is completed. If the read has not been completed before the next falling CONVST edge, the output register will be updated on this edge and the output shift register count reset. To ensure that the track and hold correctly acquires the input signal in applications where a serial read takes place during the conversion time of the ADC, a time of 1.5 ps should be allowed between the last serial clock fall- ing edge and the rising edge of the CONVST. When run- ning the AD7893 at its maximum throughput rate, the signal-to-noise ratio will degrade and the code flicker from the part will also increase. WHEN READING DURING CONVERSION, THE READ OPERATION SHOULD END 1.5p:s PRIOR TO NEXT RISING EDGE OF CONVST OUTPUT SERIAL SHIFT REGISTER IS RESET Figure 7. Timing Setup for 133 kHz ThroughputFigures 8, 9, 10 and 11 show the performance of the AD7893 using the circuit as in Figure 1 and using a sam- pling rate of 133 kHz. The layout used is shown in Fig- ures 14 and 15. The timing setup for the experiments is as in Figure 7. Figure 8 shows a plot for THD and SNR versus frequency. These results show that for an input frequency of 10 kHz the SNR is typically 68.7 dB and the THD is -82.5 dB. The SNR is 3dB worse in this case where the read occurs during conversion than in the previous case where the read did not occur during con- version. The THD numbers are similar to the optimum timing case (Figure 2), so the decrease in SNR is due to the increase in the noise floor caused by noise being coupled from the serial clock during conversion. Fig- ure 9 shows a noise histogram for the same setup as above. The analog input was centered on code 2047 and 90 Fsampte = 1 87 TIMING SETUP AS IN FIGURE 7 a4 81 78 dB 75 72 69 66 63 60 0 6650 13300 19950 26600 33250 39900 46550 53200 59850 66500 FREQUENCY - Hz Figure 8. THD & SNR vs. Frequency @ 133 kHz Sampling 0 Fgampie = 133kHz 20 Fin = 10kHz SNR = 68.7dB THD = -82.85dB 40 a 60 80 -100 120 53248 13312 26624 39936 FREQUENCY - Hz 66560 Figure 9. Typical FFT Plot for a 10 kHz Input 8000 conversions were taken from the AD7893. The results show that the code distribution is three counts. This is similar to that achieved in the previous case (Fig- ure 4}, but a larger number of conversions fall into the outer bins. This causes rms noise to increase; the value calculated from this distribution is 0.229 LSBs. This ties in with the results from the SNR versus frequency ex- periment. Figure 9 shows a typical FFT plot for an input frequency of 10 kHz while Figure 11 shows an FFT for a 65 kHz input. The plots show that the second and third harmonics have increased in amplitude when going from a 10 kHz input to a 65 kHz input. There is also some leakage into the bins around the fundamental fre- quency. These contribute to the reduction in SNR and THD shown in Figure 8. 8000 7000 Foampce = 133kHz 4 Fc = 8MHz RMS NOISE = 0.229 LSBS 6000 & 5000 = Ww f 4000 9 Ve 3000 2000 1000 o a 7 2046 2047 2048 CODE Figure 10. Noise Histogram @ 133 kHz Sampling 0 FsampLe = 133kHz -20 }F yy = 65kHz SNR = 62.74dB THD = -71.2dB 40 @ -60 -80 | 1 -100 -120 T t 0 13312 26624 39936 53248 66560 FREQUENCY - Hz Figure 11. Typical FFT Plot for a 65 kHz InputOPERATING THE AD7893 CIRCUIT BOARD. POWER SUPPLIES: This circuit board has four analog power supply inputs: +5 V, V+, AGND and V-. The +5 V input is used to drive the AD7893 Vpp and also supplies the input to the AD780 volt- age reference. The V+ and V- are used to power the on- board buffer amplifier. This amplifier may be a single supply amplifier operated from +5 V and GND if the 0 V to 2.5 V version of the AD7893 is being used. An appropriate amplifier for this would be the AD820. When using a single supply amplifier, LK3 should be placed in position A, thus connecting the Vss to AGND, and the V+ should be con- nected to the +5 V input. When using the +10 V input range part, an AD711 or AD845 would be an appropriate buffer amplifier. In this case a +15 V supply should be connected to V+ and a-15 V supply connected to the V- input and LK3 placed in position B. There are two digital power supply inputs, DVpp and DGND, which are used to power the digi- tal logic on the board. These supplies can be provided through the D-type connector or through the connection pins labelled on the board. All supplies are decoupled to ground with 10 uF tantalum and 0.1 .F ceramic disc capacitors. Analog supplies are decoupled to AGND while the digital supplies are decoupled to the DGND plane. The circuit board uses extensive ground planing to mini- mize any high frequency noise interference from the on- board clocks or any other sources. Once again, the ground planing for the analog section is kept separate from that for the digital section, and they are joined only at the AD7893 AGND and DGND pins. SHORTING PLUG OPTIONS There are three shorting plug options that must be set be- fore using the circuit board. These are outlined below: LK1 This option is used to select the reference source for the AD7893 REFIN pin. With this link in position A an external reference ap- plied to SKT4 is routed to the AD7893 REFIN pin. In position B the AD780 2.5 V reference is selected as the reference for the AD7893. LK2 This link option is in series with the analoginput from the external socket SKT2. With this link in position the analog input signal applied to SKT2 is routed to the buffer amplifier IC2. if additional signal conditioning is required before the buffer, this link can be removed and the input signal tapped off to the additional cir- cuitry which can be built on the grid area provided. LK3 This option is used to select the Vss supply for the buffer amplifier used on the evaluation board. When using a single supply amplifier, this link should be in position A; in this position the Vgg pin of the amplifier is connected to AGND. If a dual supply amplifier is used, this link should be in position B whereby the Ves of the amplifier is routed from the V pin. EVALUATION BOARD INTERFACING Interfacing to the evaluation board is via a 9-way D-Type connector, SKT1. The pinout for this connector is shown in Figure 12, and its pin designations are given in Table l. SKT1 PIN DESCRIPTION SCLK Serial Clock Input. An external serial clock is applied through this input to obtain serial data from the part. This serial clock is buf- fered using a 74HC4050 buffer on the evalua- tion board. DGND Digital Ground. This line is connected to the digital ground plane on the evaluation board. It allows the user to provide the digital supply via the connector along with the other digital signals. DATAOUT Serial Data Output. Serial data from the part is obtained at this output. This data is buff- ered by 74HC4050 hex buffer before arriving at the DATAOUT pin of the connector. The se- rial data is clocked out by the rising edge of SCLK and is valid on the falling edge of SCLK. DVpp Digital +5 V Supply. This line is connected to the DVpp supply line on the evaluation board. It allows the user to provide the digital supply via the connector along with the other digital signals. Figure 12. Pin Configuration for SKT1, D-Type ConnectorSOCKETS Table |. SKT1 Pin Functions a = Pa Mnemonic SCLK N/C N/C N/C NIC DGND DATAQUT DVop N/C OOnN A TA PwWKH = There are four sockets relevant to the operation of the AD7893 on this circuit board. The function of these sockets is outlined in Table II. Table ll. Socket Functions Socket | Function SKT1 9-Way D-Type Connector SKT2 Subminiature BNC Sockets for Analog Input SKT3 Subminiature BNC Socket for CONVST Input SKT4 Subminiature BNC Socket for External Reference SETUP CONDITIONS Care should be taken before applying power and signals to the evaluation board to ensure that all link positions Figure 13 shows the silkscreen layout of the board in order to ease setup. When using the AD7893-2 (0 V2.5 V input range) with a single supply buffer amplifier, the links should be set up as follows: LK 1 should be in position B, LK 2 should be in place and LK 3 should be in position A. With the AD7893-10 (+10 V i/p range) using a buffer amplifier, the following are the recommended link positions: LK1 should be in position B, LK2 should be put in place and are as per the required operating mode. LK3 should be in position B. COMPONENT LIST Integrated Circuits Ic1 AD7893 IC2 Buffer Amplifier IC3 AD780 Voltage Reference Ic4 74HC4050 Hex Buffer Capacitors C2, C4, C6, C8, C10 C1, C3, C5, C7, C9 10 uF Tantalum Capacitors Links LK1, LK2, LK3 Shorting Plugs Sockets SKT1 9-Way D Type Connector SKT2 to SKT4 Subminiature BNC Sockets s egenrer el fl By iB] - 000000000000000 SKT 4 2900000080000000 fo] panpb 0000000000050000 00600000060000000 cs 0000000000000000 [2] pvpp eooo00es0ne000000 c9 eo0e00000050 00000 o000000000000000 LK1 eI 00000609050000000 p 0900000090000005000 [o-@] C10 oo000000000000000 ocoo0000000000000 a, | Skt ooo00000000000000 o oovoeg0g000000000 0? o ooc000000 0000000 0? o o eoo00000000005000 ooogd0000000000000 Ici CDODDGOCHOOHHOHODGOD00000000000000 DAODGHOCOHOHDOOOGOHOHDO0000000000000 9 0000000000000000000000000000000 Ic4 CAKOHGOOCHOODGOHOGOD5F0000000000000 C0KOGCTDGHO0000000050000 CA2KHKHCOOCOHDOOO00RDD DANO DNGNGO00N 0000000000000000000000 ODDDHAHOHOHOODDO0000000000GC000000 P90K9GCOOCHOD000000050000 CoOKoKDCCOOCOOODOONDD0DN0DNDOADOGOOD 9009000000000000000000006 O000K0GOOGOKO05000000000000000090 DOO0SCCOODODNDD0OG000000 CAOSTKDDCODLOODDODOG0D0DNNOOOOC000 22000000000000005600005 POBKDGHOOGODOD005G0000000C0000000 DooeoOORODODNDDADAOCOOS eoocoDDOOOODDO GC ODDO OOAOOODCONDD 000000000090000000000006 POK0OKCOOHODODOOODO000000OND0DND ecvn0cccod oD ac eee ceo oo0 SKT3 poososooe Doo oD DO OGoOOOOCOOD DO OOOO 0COKKTODOO0O00000000006 T COOOCKOOGDFO9CD000D000CFOCOC 0000 090600000560000000000606 COOCHOKDOHDFOD0O0OHDGHOOOO0000000000 o0ocoeO000g0202000000000 pl CODODODDOODOO00DDOD000000000000 COKODODDGOOD0OD00DGFOODCOOONNND 4D7893 EVALUATION BOARD CONVET FDOCOHOD000000ORCDADODOOTOODND Figure 13. Silkscreen Layout for Circuit Board 0.1 uF Disc Ceramic Capacitors96/6-6-976L3 WS'A NI GALNIdd @) 9990909000000000000090000000000000 @ 9O9OH0OG90O00000000000000000000000 999O0O0O00H0O090H00990900000000000 9000090OH0000090O09909000900090000000 foROLoLoLoLoLoLoxoLolopoLosoLoxoL Olof osoLoLoLevOLOLS) QOOO0ONGO9N90009990000000 SOLO ToL oLoLoROLoloLoLoLOLO LOLOL OLOLOLOLCLOLOLO) ORSTOLORGLOLOROLOLOLOLOLCLOLOLCLOLOLOL OL} QOQ0O090900900900000000 to) lOZOTO} OOO ISTOTO) LoLOTO) fOLOTO} lofOTO] lOLOTO} lofoTo) lofOTG} lOfOTO} lOLOTO} fOTOTO} ooo 200 OOO loTOTG} 10] 10] 10) 10) Q 10] OOOOOO000 OOOOOODO QOOOOOOO 10} [o) 10) 10] 10) Q 9 (o) [9] (0) [0] lO} 10] lO} io} iC} Qo iC] 9 iC] lofoZoLoforoxoxoxo) fo) 10) 10] 10] 9 10) 10] Q lo} 10] 10] 9 10) [0} 10] 10] DOOOQOCOODOOOOOO9D DODOVDDOOOOOOS O Figure 14. Component Side Layout for the AD7893 Board [OlOLOTOIORMOIo) OOOOO000- 0000 fa OROZO) OODDOOOGDODODOOOCOO0000 DOOOVODOOOD ODO OOOOOG000 DOOODOOOGODODOOGODOO000 QDODOODOOOGOD ODDO OCOOO000 DOOVDODOODAGOOOGODOOOOO lofololofoforloroloyorlolojlosolorlororororojoro) lofololororolofoxololorojolorlorojolololololomm 3 Figure 15. Solder Side Layout for the AD7893 Board