LMC6772AIMMX/NOPB - NATIONAL SEMICONDUCTOR

LMC6772

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SNOS749F –SEPTEMBER 1995–REVISED MARCH 2013

Dual Micropower Rail-To-Rail Input CMOS Comparator with Open Drain Output

Check for Samples: LMC6772

1FEATURES DESCRIPTION

The LMC6772 is an ultra low power dual comparator

2(Typical Unless Otherwise Noted) with a maximum 10 μA/comparator power supply

• Low Power Consumption (Max): IS= 10 current. It is designed to operate over a wide range of

μA/comp supply voltages, with a minimum supply voltage of

• Wide Range of Supply Voltages: 2.7V to 15V 2.7V.

• Rail-to-Rail Input Common Mode Voltage The common mode voltage range of the LMC6772

Range exceeds both the positive and negative supply rails, a

significant advantage in single supply applications.

• Open Drain Output The open drain output of the LMC6772 allows for

• Short Circuit Protection: 40 mA wired-OR configurations. The open drain output also

• Propagation Delay (@VS= 5V, 100 mV offers the advantage of allowing the output to be

Overdrive): 5 μspulled to any voltage rail up to 15V, regardless of the

supply voltage of the LMC6772.

• LMC6772Q is AEC-Q Qualified

• LMC6772Q has −40°C to 125°C Temperature The LMC6772 is targeted for systems where low

Range power consumption is the critical parameter. Ensured

operation at supply voltages of 2.7V and rail-to-rail

performance makes this comparator ideal for battery-

APPLICATIONS powered applications.

• Laptop Computers Refer to the LMC6762 datasheet for a push-pull

• Mobile Phones output stage version of this device.

• Metering Systems

• Hand-Held Electronics

• RC Timers

• Alarm and Monitoring Circuits

• Window Comparators, Multivibrators

Connection Diagram

8-Pin PDIP/SOIC/VSSOP - Top View

See Package Number P0008E/D0008A/DGK0008A

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMC6772

SNOS749F –SEPTEMBER 1995–REVISED MARCH 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)

Value Unit

ESD Tolerance(2) 1.5 kV

Differential Input Voltage (V+)+0.3V to (V−)−0.3 V

Voltage at Input/Output Pin (V+)+0.3V to (V−)−0.3 V

Supply Voltage (V+–V−) 16 V

Current at Input Pin(3) ±5 mA

Current at Output Pin(4) (5) ±30 mA

Current at Power Supply Pin, LMC6772 40 mA

Lead Temperature (Soldering, 10 seconds) 260 °C

Storage Temperature Range −65°C to 150 °C

Junction Temperature(6) 150 °C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test

conditions, see the electrical characteristics.

(2) Human body model, 1.5 kΩin series with 100 pF. The output pins of the two comparators (pin 1 and pin 7) have an ESD tolerance of

1.5 kV. All other pins have an ESD tolerance of 2 kV.

(3) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.

(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in

exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely

affect reliability.

(5) Do not short circuit output to V+, when V+ is > 12V or reliability will be adversely affected.

(6) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) – TA)/θJA. All numbers apply for packages soldered directly into a PC board.

Operating Ratings(1)

Value Unit

Supply Voltage 2.7 ≤VS≤15 V

Junction Temperature Range

LMC6772AI, LMC6772BI −40°C ≤TJ≤85 °C

LMC6772Q −40°C ≤TJ≤125 °C

Thermal Resistance (θJA)

8-Pin PDIP 100 °C/W

8-Pin SOIC 172 °C/W

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test

conditions, see the electrical characteristics.

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SNOS749F –SEPTEMBER 1995–REVISED MARCH 2013

2.7V Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = V+/2. Boldface limits apply at the

temperature extremes.

Symbol Parameter Conditions Typ(1) LMC6772AI LMC6772BI LMC6772Q Units

Limit(2) Limit(2) Limit(2)

VOS Input Offset Voltage 3 5 15 10 mV

8 18 13 max

TCVOS Input Offset Voltage Temperature 2.0 μV/°C

Drift

Input Offset Voltage Average See(3) 3.3 μV/Mont

Drift h

IBInput Current 0.02 pA

IOS Input Offset Current 0.01 pA

CMRR Common Mode Rejection Ratio 75 dB

PSRR Power Supply Rejection Ratio ±1.35V < VS< ±7.5V 80 dB

AVVoltage Gain (By Design) 100 dB

VCM Input Common-Mode Voltage CMRR > 55 dB 3.0 2.9 2.9 2.9 V

Range 2.7 2.7 2.7 min

−0.3 −0.2 −0.2 −0.2 V

0.0 0.0 0.2 max

VOL Output Voltage Low ILOAD = 2.5 mA 0.2 0.3 0.3 0.3 V

0.4 0.4 0.45 max

ISSupply Current For Both Comparators 12 20 20 20 μA

(Output Low) 25 25 25 max

ILeakage Output Leakage Current VIN(+) = 0.5V, 0.1 500 500 500 nA

VIN(−) = 0V, VO= 15V 1000

(1) Typical Values represent the most likely parametric norm.

(2) All limits are specified by testing or statistical analysis.

(3) Input offset voltage Average Drift is calculated by dividing the accelerated operating life drift average by the equivalent operational time.

The input offset voltage average drift represents the input offset voltage change at worst-case input conditions.

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5.0V and 15.0V Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5.0V and 15.0V, V−= 0V, VCM = V+/2. Boldface limits apply

at the temperature extremes.

Symbol Parameter Conditions Typ(1) LMC6772AI LMC6772BI LMC6772Q Units

Limit(2) Limit(2) Limit(2)

VOS Input Offset Voltage 3 5 15 10 mV

8 18 13 max

TCVOS Input Offset Voltage Temperature V+= 5V 2.0 μV/°C

Drift V+= 15V 4.0

Input Offset Voltage Average V+= 5V(3) 3.3 μV/Mont

Drift h

V+= 15V(3) 4.0

IBInput Current V = 5V 0.04 pA

IOS Input Offset Current V+= 5V 0.02 pA

CMRR Common Mode Rejection Ratio V+= 5V 75 dB

V+= 15V 82

PSRR Power Supply Rejection Ratio ±2.5V < VS< ±5V 80 dB

AVVoltage Gain (By Design) 100 dB

VCM Input Common-Mode Voltage V+= 5.0V 5.3 5.2 5.2 5.2 V

Range CMRR > 55 dB 5.0 5.0 5.0 min

−0.3 −0.2 −0.2 −0.2 Vmax

0.0 0.0 0.0

V+= 15.0V 15.3 15.2 15.2 15.2 V

CMRR > 55 dB 15.0 15.0 15.0 min

−0.3 −0.2 −0.2 −0.2 V

0.0 0.0 0.0 max

VOL Output Voltage Low V+= 5V 0.2 0.4 0.4 0.4 V

ILOAD = 5 mA 0.55 0.55 0.55 max

V+= 15V 0.2 0.4 0.4 0.4 V

ILOAD = 5 mA 0.55 0.55 0.55 max

ISSupply Current For Both Comparators 12 20 20 20 μA

(Output Low) 25 25 25 max

ISC Short Circuit Current V+= 15V, Sinking, VO= 45 mA

12V(4)

(1) Typical Values represent the most likely parametric norm.

(2) All limits are specified by testing or statistical analysis.

(3) Input offset voltage Average Drift is calculated by dividing the accelerated operating life drift average by the equivalent operational time.

The input offset voltage average drift represents the input offset voltage change at worst-case input conditions.

(4) Do not short circuit output to V+, when V+ is > 12V or reliability will be adversely affected.

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SNOS749F –SEPTEMBER 1995–REVISED MARCH 2013

AC Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2. Boldface limits apply at the

temperature extreme.

Symbol Parameter Conditions Typ(1) LMC6772AI LMC6772BI Units

Limit(2) Limit(2)

tRISE Rise Time f = 10 kHz, CL= 50 pF, 0.3 μs

Overdrive = 10 mV(3)

tFALL Fall Time f = 10 kHz, CL= 50 pF, 0.3 μs

Overdrive = 10 mV(3)

tPHL Propagation Delay f = 10 kHz, 10 mV 10 μs

(High to Low) CL= 50 pF(3) 100 mV 4 μs

V+= 2.7V, 10 μs

10 mV

f = 10 kHz,

CL= 50 pF(3) 100 mV 4 μs

tPLH Propagation Delay f = 10 kHz, 10 mV 10 μs

(Low to High) CL= 50 pF(3) 100 mV 4 μs

V+= 2.7V, 8 μs

10 mV

f = 10 kHz,

CL= 50 pF(3) 100 mV 4 μs

(1) Typical Values represent the most likely parametric norm.

(2) All limits are specified by testing or statistical analysis.

(3) CLinlcudes the probe and jig capacitance. The rise time, fall time and propagation delays are measured with a 2V input step.

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Typical Performance Characteristics

V+= 5V, Single Supply, TA= 25°C unless otherwise specified

Supply Current Supply Current

vs. vs.

Supply Voltage (Output High) Supply Voltage (Output Low)

Figure 1. Figure 2.

Input Current Input Current

vs. vs.

Common-Mode Voltage Common-Mode Voltage

Figure 3. Figure 4.

Input Current Input Current

vs. vs.

Common-Mode Voltage Temperature

Figure 5. Figure 6.

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Typical Performance Characteristics (continued)

V+= 5V, Single Supply, TA= 25°C unless otherwise specified

ΔVOS ΔVOS

vs vs

ΔVCM, VS= 2.7V ΔVCM, VS= 5V

Figure 7. Figure 8.

ΔVOS Output Voltage

vs vs.

ΔVCM, VS= 15V Output Current (Sinking)

Figure 9. Figure 10.

Output Voltage Output Voltage

vs. vs.

Output Current (Sinking) Output Current (Sinking)

Figure 11. Figure 12.

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Typical Performance Characteristics (continued)

V+= 5V, Single Supply, TA= 25°C unless otherwise specified

Output Short Circuit Current (Sinking) Leakage Current

vs. vs.

Supply Voltage Output Voltage

Figure 13. Figure 14.

Response Time for Overdrive (tPLH) Response Time for Overdrive (tPHL)

Figure 15. Figure 16.

Response Time for Overdrive (tPLH) Response Time for Overdrive (tPHL)

Figure 17. Figure 18.

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Typical Performance Characteristics (continued)

V+= 5V, Single Supply, TA= 25°C unless otherwise specified

Response Time for Overdrive (tPLH) Response Time for Overdrive (tPHL)

Figure 19. Figure 20.

Response Time

vs.

Capacitive Load

Figure 21.

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0 1 2 3 4 5 6 7 8 9 10

100

200

300

400

500

600

700

OUTPUT VOLTAGE (mV)

OUTPUT CURRENT (mA)

VS = 15V

125°C

85°C

25°C

-40°C

2 3 4 5 6 7 8 9 10 11 12

100

120

140

OUTPUT SHORT CIRCUIT CURRENT (mA)

SUPPLY VOLTAGE (V)

-40°C

25°C

85°C

125°C

0 1 2 3 4 5 6 7 8 9 10

100

200

300

400

500

600

700

OUTPUT VOLTAGE (mV)

OUTPUT CURRENT (mA)

VS = 5V

125°C

85°C

25°C

-40°C

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

100

200

400

500

600

OUTPUT VOLTAGE (mV)

OUTPUT CURRENT (mA)

300

125°C

85°C

25°C

-40°C

VS = 2.7V

2 4 6 7 910 12 13 15

SUPPLY CURRENT (PA)

(Both Comparators)

SUPPLY VOLTAGE (V)

5811 14

125°C 85°C

25°C -40°C

Pos Input = 0.1V

Neg Input = 0.0V

2 4 6 7 910 12 13 15

SUPPLY CURRENT (PA)

(Both Comparators)

SUPPLY VOLTAGE (V)

5811 14

125°C 85°C

25°C -40°C

Pos Input = 0.0V

Neg Input = 0.1V

LMC6772

SNOS749F –SEPTEMBER 1995–REVISED MARCH 2013

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LMC6772Q

Supply Current Supply Current

vs. vs.

Supply Voltage (Output High) Supply Voltage (Output Low)

Figure 22. Figure 23.

Output Voltage Output Voltage

vs. vs.

Output Current (Sinking) Output Current (Sinking)

Figure 24. Figure 25.

Output Voltage Output Short Circuit Current

vs. vs.

Output Current (Sinking) Supply

Figure 26. Figure 27.

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OUTPUT LEAKAGE (nA)

24 6 8 10 11 13 15

OUTPUT VOLTAGE (V)

0.0001

0.001

0.01

0.1

100

12 149

125°C

85°C

25°C

-40°C (estimated)

VS = 2.7V

LMC6772

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SNOS749F –SEPTEMBER 1995–REVISED MARCH 2013

LMC6772Q (continued)

Output Leakage

vs.

Output Voltage

Figure 28.

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APPLICATION INFORMATION

INPUT COMMON-MODE VOLTAGE RANGE

At supply voltages of 2.7V, 5V and 15V, the LMC6772 has an input common-mode voltage range which exceeds

both supplies. As in the case of operational amplifiers, CMVR is defined by the VOS shift of the comparator over

the common-mode range of the device. A CMRR (ΔVOS/ΔVCM) of 75 dB (typical) implies a shift of < 1 mV over

the entire common-mode range of the device. The absolute maximum input voltage at V+= 5V is 200 mV beyond

either supply rail at room temperature.

Figure 29. An Input Signal Exceeds the LMC6772 Power Supply Voltages with No Output Phase

Inversion

A wide input voltage range means that the comparator can be used to sense signals close to ground and also to

the power supplies. This is an extremely useful feature in power supply monitoring circuits.

An input common-mode voltage range that exceeds the supplies, 20 fA input currents (typical), and a high input

impedance makes the LMC6772 ideal for sensor applications. The LMC6772 can directly interface to sensors

without the use of amplifiers or bias circuits. In circuits with sensors which produce outputs in the tens to

hundreds of millivolts, the LMC6772 can compare the sensor signal with an appropriately small reference

voltage. This reference voltage can be close to ground or the positive supply rail.

LOW VOLTAGE OPERATION

Comparators are the common devices by which analog signals interface with digital circuits. The LMC6772 has

been designed to operate at supply voltages of 2.7V, without sacrificing performance, to meet the demands of 3V

digital systems.

At supply voltages of 2.7V, the common-mode voltage range extends 200 mV (ensured) below the negative

supply. This feature, in addition to the comparator being able to sense signals near the positive rail, is extremely

useful in low voltage applications.

Figure 30. Even at Low-Supply Voltage of 2.7V, an Input Signal which Exceeds the Supply Voltages

Produces No Phase Inversion at the Output

At V+= 2.7V, propagation delays are tPLH =4μs and tPHL =4μs with overdrives of 100 mV. Please refer to the

performance curves for more extensive characterization.

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OUTPUT SHORT CIRCUIT CURRENT

The LMC6772 has short circuit protection of 40 mA. However, it is not designed to withstand continuous short

circuits, transient voltage or current spikes, or shorts to any voltage beyond the supplies. A resistor is series with

the output should reduce the effect of shorts. For outputs which send signals off PC boards additional protection

devices, such as diodes to the supply rails, and varistors may be used.

HYSTERESIS

If the input signal is very noisy, the comparator output might trip several times as the input signal repeatedly

passes through the threshold. This problem can be addressed by making use of hysteresis as shown below.

Figure 31. Canceling the Effect of Input Capacitance

The capacitor added across the feedback resistor increases the switching speed and provides more short term

hysteresis. This can result in greater noise immunity for the circuit.

SPICE MACROMODEL

A Spice Macromodel is available for the LMC6772. The model includes a simulation of:

• Input common-mode voltage range

• Quiescent and dynamic supply current

• Input overdrive characteristics

and many more characteristics as listed on the macromodel disk.

A SPICE macromodel of this and many other op amps is available at no charge from the WEBENCH Design

Center Team at www.ti.com

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TYPICAL APPLICATIONS

UNIVERSAL LOGIC LEVEL SHIFTER

The output of the LMC6772 is the uncommitted drain of the output NMOS transistor. Many drains can be tied

together to provide an output OR'ing function. An output pullup resistor can be connected to any available power

supply voltage within the permitted power supply range.

Figure 32. Universal Logic Level Shifter

The two 1 kΩresistors bias the input to half of the power supply voltage. The pull-up resistor should go to the

output logic supply. Due to its wide operating range, the LMC6772 is ideal for the logic level shifting applications.

ONE-SHOT MULTIVIBRATOR

Figure 33. One-Shot Multivibrator

A monostable multivibrator has one stable state in which it can remain indefinitely. It can be triggered externally

to another quasi-stable state. A monostable multivibrator can thus be used to generate a pulse of desired width.

The desired pulse width is set by adjusting the values of C2and R4. The resistor divider of R1and R2can be

used to determine the magnitude of the input trigger pulse. The LMC6772 will change state when V1< V2. Diode

D2provides a rapid discharge path for capacitor C2to reset at the end of the pulse. The diode also prevents the

non-inverting input from being driven below ground.

BI-STABLE MULTIVIBRATOR

Figure 34. Bi-Stable Multivibrator

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A bi-stable multivibrator has two stable states. The reference voltage is set up by the voltage divider of R2and

R3. A pulse applied to the SET terminal will switch the output of the comparator high. The resistor divider of R1,

R4, and R5now clamps the non-inverting input to a voltage greater than the reference voltage. A pulse applied to

RESET will now toggle the output low.

ZERO CROSSING DETECTOR

Figure 35. Zero Crossing Detector

A voltage divider of R4and R5establishes a reference voltage V1at the non-inverting input. By making the series

resistance of R1and R2equal to R5, the comparator will switch when VIN = 0. Diode D1insures that V3never

drops below −0.7V. The voltage divider of R2and R3then prevents V2from going below ground. A small amount

of hysteresis is setup to ensure rapid output voltage transitions.

OSCILLATOR

Figure 36. Square Wave Generator

Figure 36 shows the application of the LMC6772 in a square wave generator circuit. The total hysteresis of the

loop is set by R1, R2and R3. R4and R5provide separate charge and discharge paths for the capacitor C. The

charge path is set through R4and D1. So, the pulse width t1is determined by the RC time constant of R4and C.

Similarly, the discharge path for the capacitor is set by R5and D2. Thus, the time t2between the pulses can be

changed by varying R5, and the pulse width can be altered by R4. The frequency of the output can be changed

by varying both R4and R5.

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Figure 37. Time Delay Generator

The circuit shown above provides output signals at a prescribed time interval from a time reference and

automatically resets the output when the input returns to ground. Consider the case of VIN = 0. The output of

comparator 4 is also at ground. This implies that the outputs of comparators 1, 2, and 3 are also at ground.

When an input signal is applied, the output of comparator 4 swings high and C charges exponentially through R.

This is indicated above. The output voltages of comparators 1, 2, and 3 swtich to the high state when VC1 rises

above the reference voltages VA, VBand VC. A small amount of hysteresis has been provided to insure fast

switching when the RC time constant is chosen to give long delay times.

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REVISION HISTORY

Changes from Revision E (March 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 16

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMC6772AIM ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC67

72AIM

LMC6772AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC67

72AIM

LMC6772AIMM ACTIVE VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 C21

LMC6772AIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 C21

LMC6772AIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 C21

LMC6772AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC67

72AIM

LMC6772BIM ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC67

72BIM

LMC6772BIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC67

72BIM

LMC6772BIMX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMC67

72BIM

LMC6772BIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMC67

72BIM

LMC6772BIN/NOPB LIFEBUY PDIP P 8 40 Green (RoHS

& no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 LMC6772

BIN

LMC6772QMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 AX5A

LMC6772QMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 AX5A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMC6772, LMC6772-Q1 :

•Catalog: LMC6772

•Automotive: LMC6772-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMC6772AIMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMC6772AIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMC6772AIMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMC6772AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMC6772BIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMC6772BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LMC6772QMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMC6772QMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMC6772AIMM VSSOP DGK 8 1000 210.0 185.0 35.0

LMC6772AIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LMC6772AIMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

LMC6772AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LMC6772BIMX SOIC D 8 2500 367.0 367.0 35.0

LMC6772BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

LMC6772QMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LMC6772QMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

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