Document Number : MC33880
Rev. 8.0, 5/2012
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
Configurable Octal Serial Switch
with Serial Peripheral Interface
I/O
The 33880 device is an 8-output hardware configurable high side/
low side switch with 8-bit serial input control using the serial peripheral
interface (SPI). Two of the outputs can be controlled directly via
microcontroller for pulse-width modulation (PWM) applications.
The 33880 controls various inductive or incandescent loads by
directly interfacing with a microcontroller.
The circuit's innovative monitoring and protection features include
very low standby currents, “cascadable” fault reporting, internal 40 V
output clamping for low side configurations, internal -20 V output
clamping for high side configurations, output specific diagnostics, and
independent shutdown of outp uts.
Features
• Designed to operate 5.5 V < VPWR < 24.5 V
• 8-bit SPI for control and fault reporting, 3.3/ 5.0 V compatible
• Outputs are current limited (0.8 A to 2.0 A) to drive incandescent
lamps
• Output voltage clamp is +45 V (typical) (low side drive) and -20 V
(typical) (high side drive) during inducti v e switching
• Internal reverse battery protection on VPWR
• Loss of ground or supply will not energize loads or damag e IC
• Maximum 5.0 μA IPWR standby current at 13 V VPWR up to 95 °C
•R
DS(ON) of 0.55 Ω at 25 °C typical
• Short circuit detect and current limit with autoretry
• Independent over-temperature protection
• 32-pin SOICW has pins 8, 9, 24, and 25 grounded for thermal
performance
Figure 1. 33880 Simplified Application Diagra m
HIGH/LOW SIDE SWITCH
EG SUFFIX (PB-FREE)
98ASB42345B
28-PIN SOICW
33880
ORDERING INFORMATION
Device
(For Tape and Reel, add
an R2 Suffix)
Temperature
Range (TA)Package
MC33880PEG -40°C to 125°C28 SOICW
MC33880PEW 32 SOICW
EW SUFFIX (PB-FREE)
98ARH99137A
32-PIN SOICW
All Output Switches are High- or Low-Side Configurable
VPWR 33880
SPI I/O
PWM
MCU
MOT
High-Side
H-Bridge
Low-Side
5.0 V
5.0 V
VS
D1
D2
D4
D5
D6
D7
S8
D3
EN
VDD
VPWR
GND
CS
SCLK
DI
DO
IN5
IN6
S1
S2
S4
D8
S5
S6
S7
S3
Analog Integrated Circuit Device Data
2Freescale Semiconductor
33880
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
Figure 2. 33880 Simplified Internal Block Diagram
SPI Bit 4
IN5
SPI Bit 0
OV, POR, SLEEP
~50 μA
~50 μA
D8
D7
D4
D3
D2
D5
SPI and
Logic
Interface
Limit
Open/Short Comparator Threshold
~1.5 V Open/Short
Control
Drive
Gate
ThresholdOpen/Short Comparator
Open
Load
Detect
Current
~650 μA
TLIM
+
–
+
–
+
–
+
–
Current
Limit
Gate
Drive
Control Open
Load
Detect
Current
_
+
~650 μA
CS
__
SCLK
DI
DO
~50 μA
EN
VDD
~50 μA
IN5
IN6
Internal
Bias Charge
Pump
Overvoltage
Shutdown/POR
Sleep State
TLIM
Current
_
+
~1.5 V Open/Short
Enable
VPWR
GND
D1
Typical of All 8 Output Drivers
S1
Drain
Outputs
S2
S3
S4
S7
S8
Source
Outputs
D6
S5
S6
Drain
Outputs
Source
Outputs
Analog Integrated Circuit Device Data
Freescale Semiconductor 3
33880
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 28-Pin Connections
Table 1. SOICW 28-Pin Definitions
Pin
Number Pin Name Definition
1GND Digital ground.
2VDD Logic supply voltage. Logic supply mu st be switched off for low current mode (VDD below 3.9 V).
3, 4 S8 Output 8 MOSFET source pins.
5D8 Output 8 MOSFET drain pin.
6S2 Output 2 MOSFET source pin.
7D2 Output 2 MOSFET drain pin.
8S1 Output 1 MOSFET source pin.
9D1 Output 1 MOSFET drain pin.
10 D6 Output 6 MOSFET drain pin.
11 S6 Output 6 MOSFET source pin.
12 IN6 PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
13 EN Enable input. Allows control of outputs. Active high.
14 SCLK SPI control clock input pin.
15 DI SPI control data input pin from MCU to the 33880. Logic [1] activates output.
16 CS SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in.
17 IN5 PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
18 S5 Output 5 MOSFET source pin.
19 D5 Output 5 MOSFET drain pin.
20 D3 Output 3 MOSFET drain pin.
21 S3 Output 3 MOSFET source pin.
22 D4 Output 4 MOSFET drain pin.
23 S4 Output 4 MOSFET source pin.
24 D7 Output 7 MOSFET drain pin.
25, 26 S7 Output 7 MOSFET source pins.
27 VPWR Power supply pin to the 33880. VPWR has internal reverse battery protection.
28 DO SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
28
27
26
25
24
23
22
21
20
19
18
17
16
DO
VPWR
S7
S7
D7
S4
D4
S3
D3
D5
S5
IN5
CS
DI
GND
VDD
S8
S8
D8
S2
D2
S1
D1
D6
S6
IN6
EN
SCLK
Analog Integrated Circuit Device Data
4Freescale Semiconductor
33880
PIN CONNECTIONS
Figure 4. 32-Pin Connections
Table 2. SOICW 32-Pin Definitions
Pin
Number Pin Name Definition
1GND Digital ground.
2VDD Logic supply voltage. Logic supply mu st be switched off for low current mode (VDD below 3.9 V).
3, 4 S8 Output 8 MOSFET source pins.
5D8 Output 8 MOSFETdrain pin.
6S2 Output 2 MOSFET source pin.
7D2 Output 2 MOSFET drain pin.
8, 9, 24, 25 TGND Thermal Ground pins are connected internally to the substrate of the die and are used for heat transfer.
Connect thermal ground pins to the PCB ground and ground plane for heat sinking.
10 S1 Output 1 MOSFET source pin.
11 D1 Output 1 MOSFET drain pin.
12 D6 Output 6 MOSFETdrain pin.
13 S6 Output 6 MOSFET source pin.
14 IN6 PWM direct control input pin for output 6. IN6 is “OR” with SPI bit.
15 EN Enable input. Allows control of outputs. Active high.
16 SCLK SPI control clock input pin.
17 DI SPI control data input pin from MCU to the 33880. Logic [1] activates output.
18 CS SPI control chip select input pin from MCU to the 33880. Logic [0] allows data to be transferred in.
19 IN5 PWM direct control input pin for output 5. IN5 is “OR” with SPI bit.
20 S5 Output 5 MOSFET source pin.
21 D5 Output 5 MOSFET drain pin.
22 D3 Output 3 MOSFET drain pin.
23 S3 Output 3 MOSFET source pin.
26 D4 Output 4 MOSFET drain pin.
27 S4 Output 4 MOSFET source pin.
28 D7 Output 7 MOSFET drain pin.
29, 30 S7 Output 7 MOSFET source pins.
31 VPWR Power supply pin to the 33880. VPWR has internal reverse battery protection.
32 DO SPI control data output pin from the 33880 to the MCU. DO = 0 no fault, DO = 1 specific output has fault.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
DO
VPWR
S7
S7
D7
S4
D4
TGND
TGND
S3
D3
D5
S5
IN5
CS
DI
GND
VDD
S8
S8
D8
S2
D2
TGND
TGND
S1
D1
D6
S6
IN6
EN
SCLK
Analog Integrated Circuit Device Data
Freescale Semiconductor 5
33880
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
VDD Supply Voltage (1) VDD -0.3 to 7.0 VDC
CS, DI, DO, SCLK, IN5, IN6, and EN (1) –-0.3 to 7.0 VDC
VPWR Supply Voltage (1) VPWR -16 to 50 VDC
Drain 1 – 8 (2)
5.0 mA ≤ IOUT ≤ 0.3 A
–-18 to 40 VDC
Source 1 – 8 (3)
5.0 mA ≤ IOUT ≤ 0.3 A
–-28 to 40 VDC
Output Voltage Clamp Low-Side Drive (4) VOC 40 to 55 VDC
Output Voltage Clamp High-Side Drive (4) VOC -15 to -25 VDC
Output Clamp Energy (5) ECLAMP 50 mJ
ESD Voltage (6)
Human Body Model
Machine Model
VESD1
VESD2
±2000
±200
V
Storage Temperature TSTG -55 to 150 °C
Operating Case Temperature TC-40 to 125 °C
Operating Junction Temperature TJ-40 to 150 °C
Maximum Junction Temperature –-40 to 150 °C
Power Dissipation (TA = 25°C) (7)
28 SOIC, Case 751F-05
32 SOIC, Case 1324-02
PD1.3
1.7
W
Thermal Resistance, Junction-to-Ambient, 28 SOIC, Case 751F-05 RθJA 94 °C/W
Thermal Resistance, Junction-to-Ambient, 32 SOIC, Case 1324-02
Thermal Resistance, Junction-to-Thermal Ground Leads, 32 SOIC, Case 1324-02 RθJA
RθJL
70
18
°C/W
Peak Package Reflow Temperature During Reflow (8), (9) TPPRT Note 9 °C
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. Configured as low-side driver with 300 mA load as current limit.
3. Configured as high-side driver with 300 mA load as current limit.
4. With outputs OFF and 10 mA of test current for low-side driver, 30 mA test current for high-side driver.
5. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method.
6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), and ESD2 testing is performed
in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
7. Maximum power dissipation with no heatsink used.
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data
6Freescale Semiconductor
33880
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where app licable, reflect the parameter’s ap proximate average value with VPWR = 13 V, TA = 25°C.
Characteristic Symbol Min Typ Max Unit
POWER INPUT
Supply Voltage Range
Fully Operational VPWR(FO) 5.5 –24.5 V
Supply Current IPWR(ON) –8.0 14 mA
Sleep State Supply Current (VDD and EN = 0 V, VPWR = 16 V)
Temperature = -40°C to 95°C
Temperature = 95°C to 125°C
IPWR(SS) –
–2.0
5.0 5.0
20
μA
Overvoltage Shutdown VOV 25 27 30 V
Overvoltage Shutdown Hysteresis VOV(HYS) 0.15 0.8 2.5 V
Logic Supply Voltage VDD 4.75 –5.25 V
Logic Supply Current IDD 0.5 2.6 4.0 mA
Logic Supply Undervoltage Lockout Threshold VDD(UNVOL) 3.9 4.3 4.7 V
Logic Supply Undervoltage Hysteresis VDD(UNVOL-HYS) 100 150 300 mV
POWER OUTPUT
Drain-to-Source ON Resistance (VPWR = 16 V)
IOUT = 0.25 A, TJ = 125°C
IOUT = 0.25 A, TJ = 25°C
IOUT = 0.25 A, TJ = -40°C
RDS(ON) –
–
–
0.75
0.55
0.45
1.1
0.85
0.80
Ω
Output Self-Limiting Current High-Side and Low-Side Configurations
VPWR = 16 V IOUT(LIM) 0.8 1.4 2.0 A
Output Fault Detect Threshold (10), (11)
Outputs Programmed OFF
VOUTth(F) 1.0 –3.0 V
Output Off Open Load Detect Current (10)
Outputs Programmed OFF
IOCO 0.30 0.55 1.0 mA
Output Clamp Voltage Low-Side Drive
ID = 10 mA VOC(LSD) 40 45 55 V
Output Clamp Voltage High-Side Drive
IS = -30 mA VOC(HSD) -15 -20 -25 V
Output Leakage Current High-Side and Low-Side Configuration
VDD = 0 V, VDS = 16 V IOUT(LKG) –1.0 7.0
μA
Overtemperature Shutdown (11) TLIM 155 –185 °C
Overtemperature Shutdown Hysteresis (11) TLIM(HYST) 5.0 10 15 °C
Notes
10. Output Fault Detect Thresholds with outputs programmed OFF. Output fault detect threshold are the same for output open and shorts.
11. This parameter is guaranteed by design but is not production tested.
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
33880
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
DIGITAL INTERFACE
Input Logic Voltage Thresholds (12) VINLOGIC 0.8 –2.2 V
IN5, IN6, and EN Input Logic Current
IN5, IN6, EN = 0 V IIN5, IN6, EN -10 –10
μA
IN5, IN6, and EN Pull-Down Current
0.8 V to VDD
IIN5, IN6, EN 30 45 100
μA
SCLK, DI, and Tri-State DO Input
0 V to VDD
ISCK, SI, TriSO -10 –10
μA
CS Input Current
CS = VDD
IICS -10 –10
μA
CS Pull-Up Current
CS = 0 V
IICS -30 –-100
μA
DO High-State Output Voltage
IDO-HIGH = -200 μAVDOHIGH VDD - 0.8 – VDD
V
DO Low-State Output Voltage
IDO-HIGH = 1.6 mA VDOLOW – – 0.4 V
Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (13) CIN – – 20 pF
Notes
12. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
13. This parameter is guaranteed by design but is not production tested.
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where app licable, reflect the parameter’s ap proximate average value with VPWR = 13 V, TA = 25°C.
Characteristic Symbol Min Typ Max Unit
Analog Integrated Circuit Device Data
8Freescale Semiconductor
33880
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C unless otherwise
noted. Typical values, where app licable, reflect the parameter’s ap proximate average value with VPWR = 13 V, TA = 25°C.
Characteristic Symbol Min Typ Max Unit
POWER OUTPUT TIMING
Output Slew Rate Low-Side Configuration (14)
RL = 620 Ω
tR0.1 0.5 1.2 V/μs
Output Slew Rate Low-Side Configuration (14)
RL = 620 Ω
tF0.1 0.5 1.2 V/μs
Output Slew Rate High-Side Configuration (14)
RL = 620 Ω
tR0.1 0.3 1.2 V/μs
Output Slew Rate High-Side Configuration (14)
RL = 620 Ω
tF0.1 0.3 1.2 V/μs
Output Turn ON Delay Time, High-Side and Low-Side Configuration (15) tDLY(ON) 1.0 15 50 μs
Output Turn OFF Delay Time, High-Side and Low-Side Configuration (15) tDLY(OFF) 1.0 30 100 μs
Output Fault Delay Time (16) tFAULT 100 –300 μs
DIGITAL INTERFACE TIMING
Recommended Frequency of SPI Operation – – 4.0 6.0 MHz
Required Low State Duration on VDD for Reset (17)
VDD ≤ 0.2 V tRESET –4.0 10
μs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) tLEAD 100 – – ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) tLAG 50 – – ns
DI to Falling Edge of SCLK (Required Setup Time) tDI(su) 16 – – ns
Falling Edge of SCLK to DI (Required Hold Time) tDI(HOLD) 20 – – ns
DI, CS, SCLK Signal Rise Time (18) tR(DI) –5.0 –ns
DI, CS, SCLK Signal Fall Time (18) tF(DI) –5.0 –ns
Time from Falling Edge of CS to DO Low Impedance (19) tDO(EN) – – 60 ns
Time from Rising Edge of CS to DO High Impedance (20) tDO(DIS) – – 60 ns
Time from Rising Edge of SCLK to DO Data Valid (21) tVALID –25 60 ns
Notes
14. Output Rise and Fall time respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
15. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to 90 and 10 percent of initial voltage.
16. Duration of fault before fault bit is set. Duration between access times must be greater than 300 μs to read faults.
17. This parameter is guaranteed by design but is not production tested.
18. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
19. Time required for output status data to be available for use at DO pin.
20. Time required for output status data to be terminated at DO pin
21. Time required to obtain valid data out from DO following the rise of SCLK.
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
33880
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Figure 5. SPI Timing Diagram
Figure 6. Valid Data Delay Time
and Valid Time Test Circui t
Figure 7. Enable and Disable Time Test Circuit
Figure 8. Switching Time Test Circuit
tDO(DIS)
0.7 VDD
0.2 VDD
0.2 VDD
0.7 VDD
0.2 VDD
tLEAD
tDI(SU) tDI(HOLD)
tVALID
tLAG
CS
SCLK
DI
DO
MSB in
MSB out LSB out
0.7 VDD
0.2 VDD
tDO(EN)
DO
CL = 200 pF
VDD = 5.0 V
SCLK 33880
Under
Test
NOTE: CL represents the total capacitance of the test
fixture and probe.
DO
CL = 200 pF
RL = 1.0 kΩ
CS 33880
Under
Test
NOTE: CL represents the total capacitance of the test
fixture and probe.
VDD = 5.0 V VPull-Up = 2.5 V
Output
CL
RL = 620 Ω
VPWR = 13 V
CS 33880
Under
Test
NOTE: CL represents the total capacitance of the test
fixture and probe.
VDD = 5.0 V
Analog Integrated Circuit Device Data
10 Freescale Semiconductor
33880
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Figure 9. Valid Data Delay Time and Valid Time
Waveforms
Figure 10. Enable and Disable Time Waveforms
Figure 11. Turn-ON/OFF Waveforms
(Low-to-High)
tF(DI)
tR(DI)
0.2 VDD
0.7 VDD
0.2 VDD
0.7 VDD
tVALID tr(DO)
VOL
VOH
VOL
VOH
tDLY(HL)
tDLY(LH)
0.2 VDD
0.7 VDD (2.5 V)
0
5.0 V
< 50 ns
50%
< 50 ns
DO
SCLK
(High-to-Low)
DO
90%
tR(DI) tF(DI)
VOH
tSO(DIS)
0
5.0 V
DO
tDO(DIS)
tDO(EN)
tDO(DIS)
tDO(EN)
(T ri-S t ate to Low)
0.7 VDD
0.2 VDD (2.5 V)
< 50 ns
< 50 ns
CS 90%
DO
(Tri-State to High)
10%
10%
90%
10%
VTri-State
VTri-State
90%
tR(DI) tF(DI)
VTri-State
VOH
tSO(DIS)
0
5.0 V
DO
tDO(DIS)
tDO(EN)
tDO(DIS)
tDO(EN)
(Tri-State to Low)
0.7 VDD
0.2 VDD (2.5 V)
< 50 ns
CS 90%
DO
(Tri-State to High)
10%
10%
90%
10%
VTri-State
< 50 ns
Analog Integrated Circuit Device Data
Freescale Semiconductor 11
33880
ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
Figure 12. IPWR vs. Temperature Figure 13. Sleep State IPWR vs. Temperature
Figure 14. Sleep State IPWR vs. VPWR Figure 15. RDS(ON) vs. Temperatu r e @ 250 mA
Figure 16. RDS(ON) vs. V PWR @ 250 mA Figure 17. Current Limit IOUT(LIM) vs. Temperature
0 25 50 100 125-40 75-25
IPWR Current into VPWR Pin (mA)
2
4
6
8
10
12
14
TA, Ambient Temperature (°C)
All Outputs ON
All Outputs OFF
VPWR @ 16 V
0 25 50 100 125-40 75-25
IPWR Current into VPWR Pin (uA)
2
4
6
8
10
12
14
TA, Ambient Temper at ure
0 25 50 100 125-40 75-25
IPWR Current into VPWR Pin (μA)
2
4
6
8
10
12
14
TA, Ambient Temperature (°C)
VPWR @ 16 V
5.0 10 15 20 25
0
IPWR Current into VPWR Pin (μA)
10
20
30
40
50
60
70
VPWR
TA = 25°C
0 25 50 100 125-40 75-25
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TA, Ambient Temperature (°C)
VPWR @ 16 V
RDS(ON) (Ω)
RDS(ON) (Ω)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VPWR (V)
5.0 10 15 20 25
0
VPWR @ 16 V
0 25 50 100 125-40 75-25
IOUT(LIM), Current Limit (A)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
TA, Ambient Temperature (°C)
VPWR @ 16 V
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
33880
ELECTRICAL CHARACTERISTICS
TYPICAL ELECTRICAL CHARACTERISTICS
Figure 18. Open Load Detect Current vs. Temperature Figure 19. Open Load Dete ct Current vs. VPWR
Figure 20. Sleep State Output Leakage vs. VPWR
0 25 50 100 125-40 75-25
IOCO, Open Load (mA)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
TA, Ambient Temperature (°C)
VPWR @ 16 V
High-Side Configuration
5.010152025
0
IOCO Open Load (mA)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VPWR (V)
TA = 25°C
5.010152025
0
IOUT(LKG), Leakage Current (μA)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VPWR (V)
TA = 25°C
Analog Integrated Circuit Device Data
Freescale Semiconductor 13
33880
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33880 is an eight-output hardware configurable power
switch with 8-bit serial control. The 33880 incorporates
SMARTMOS™ 5 technology with CMOS logic, bi polar/MOS
analog circuitry, and independent double diffused DMOS
power output transistors. Many benefits are realized as a
direct result of using this mixed technol ogy. A simplified
internal block diagram of the 33880 is shown in Figure 2,
page 2.
The 33880 device uses high-efficiency updrain power
DMOS output transistors exhibiting low drain-to-source ON
resistance values (RDS(ON) ≤ 0.55 Ω at 25°C) and dense
CMOS control logic. All outputs have independent voltage
clamps to provide fast inductive turn-off and transient
protection. Operational bias currents of less than 4.0 mA on
VDD and 12 mA on VPWR with any combination of outputs ON
are a direct result of using SMARTMOS™ 5 technology.
FUNCTIONAL PIN DESCRIPTION
CHIP SELECT (CS)
The system MCU selects the 33880 to commu nicate
through the use of the CS pin. Whenever the pin is in a logic
low state, data can be transferred from the MCU to the 33880
device and vice versa. Clocked-in data from the MCU is
transferred from the 33880 shift register and latched into the
power outputs on the rising edge of the CS signal. On the
falling edge of the CS signal, output status information is
transferred from the pow er out puts status register into the
device's shift register. The falling edge of CS enables the DO
output driver. Whenever the CS pin goes to a logic low state,
the DO pin output is enabled, thereby allowing information to
be transferred from the 33880 to the MCU. To avoid any
spurious data, it is essential the high-to-low transition of the
CS signal occurs only when SCLK is in a logic low state.
SYSTEM CLOCK (SCLK)
The system clock pin (SCLK) clocks the internal shift
registers of the 33880. The serial data input (DI) is latched
into the input shift register on the falling edge of the SCLK.
The serial data output pin (DO) shifts data out of the shift
register on the rising edge of the SCLK signal. False clocking
of the shift register must be avoided to guarantee validity of
data. It is essential the SCLK pin be in a logic low state
whenever chip select pin (CS) makes any transition. For this
reason, it is recommended the SCLK pin is commanded to a
logic low state when the device is not accessed (CS in logic
high state). When the CS is in a logic high state, any signal at
the SCLK and DI pin is ignored and the DO is tri-stated (high
impedance).
DATA INPUT (DI)
This pin is used for serial instruction data input. DI
information is latched into the input reg ister on the falling
edge of SCLK. A logic high state present on DI will program
a specific output on. The specific output will turn on with the
rising edge of the CS signal. Conversely, a logic low state
present on the DI pin will program the output off. The specific
output will turn off with the rising edge of the CS signal. To
program the eight outputs of the 33880 device on or off, enter
the DI pin beginning with Output 8, followed by Ou tput 7,
Output 6, and so on to Output 1. For each falling edge of the
SCLK while CS is logic low, a data bit instruction (on or off) is
loaded into the shift register per the data bit DI state. Eight
bits of entered information fills the shift register. To preserve
data integrity, do not transition DI as SCLK transitions from a
high to low logic state.
DATA OUTPUT (DO)
The serial data output (DO) pin is the output from the shift
register. Th e DO pin remains tri-state until the CS pin goes to
a logic low state. All faults on the 33880 device are reported
as logic [1] through the DO data pin. Regardless of the
configuration of the driver, open loads and shorted loads are
reported as logic [1]. Conversely, normal operating outputs
with non-faulted loads are repo rted as logic [0]. The first
positive transition of SCLK will make output eight status
available on DO pin. Each successive positive clock will
make the next output status available. The DI/DO shifting of
data follows a first-in-first-out protocol with both input and
output words transferring the most significant bit (MSB) first.
ENABLE (EN)
The EN pin on the 33880 device either enables or disables
the internal charge pump. The EN pin must be high for this
device to enhance the gates of the output drivers, perform
fault detection, and reporting. Active outputs during a low
transition of the EN pin will become active again when the EN
transitions high. If this feature is not required, it is
recommended the EN pin be connected to VDD.
COMMAND INPUT (IN5 AND IN6)
The IN5 and IN6 pins command inputs allowing outputs
five and six to be used in PWM applications. IN5 and IN6 pins
are ORed with the SPI communication input. For SPI control
of outputs five and six, the IN5 and IN6 pins should be
grounded or held low by the microprocessor. In the same
manner, when using the PWM feature the SPI port must
command the outputs off. Maximum PWM frequency for each
output is 2.0 kHz.
Analog Integrated Circuit Device Data
14 Freescale Semiconductor
33880
FUNCTIONAL DESCRIPTION
LOGIC POWER (VDD)
The VDD pin supplies logic power to the 33880 device and
is used for power-on reset (POR). To achieve low standby
current on VPWR supply, power must be removed from the
VDD pin. The device will be in reset with all drivers off when
VDD is below 3.9 VDC.
OPEN DRAIN OUTPUT (D1 – D8)
The D1 – D8 pins are the open drain outputs of the 33880.
For High-Side Drive configurati ons, the drain pins are
connected to battery supply. In Low-Sid e Drive
configurations, the drain pins are connected to the low side of
the load. All outputs may be configured individually as
desired. When Low-Side Drive is used, the 33880 limits the
positive transient for inductive loads to 45 V.
SOURCE OUTPUT (S1 – S8)
The S1 – S8 pins are the source outputs of the 33880. For
High-Side Drive configurations, the source pins are
connected directly to the load. In Low-Side Drive
configurations the source is connected to ground. All outputs
may be configured individually as desired. When High-Side
drive is used, the 33880 will limit the negative transient for
inductive loads to -20 V.
Analog Integrated Circuit Device Data
Freescale Semiconductor 15
33880
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
MCU INTERFACE DESCRIPTION
In operation, the 33880 functions as an eight-output serial
switch serving as a microcontroller (MCU) bus expander and
buffer, with fault management and fault reporting features. In
doing so, the device directly relieves the MCU of the fault
management functions. This device directly interfaces to an
MCU using a Serial Peripheral Interface (SPI) for control and
diagnostic readout. Figure 21 and Figure 24, page 16,
illustrate the basic SPI configuration between an MCU and
one 33880.
Figure 21. SPI Interface with Microcontroller
All inputs are compatible with 5.0 V and 3.3 V CMOS logic
levels and incorporate positive lo gic. When ever an input is
programmed to a logic low state (<0.8 V) the corresponding
output will be OFF. Conversely, whenever an input is
programmed to a logic high state (>2.2 V), the output being
controlled will be ON. Diagnostics are treated in a similar
manner. Outputs with a fault will feedback (via DO) to the
microcontroller as a logic [1] while normal operating outputs
will provide a logic [0].
Figure 22 illustrates the Daisy Chain configuration using
the 33880. Data from the MCU is clocked daisy chain through
each device while the Chip Select (CS) bit is commanded low
by the MCU. During each clock cycle output status from the
daisy chain, the 33880 is being transferred to the MCU via the
Master In Slave Out (MISO) line. On rising edge of CS data
stored in the input register is then transferred to the output
driver.
Figure 22. 33880 SPI System Daisy Chain
Multiple 33880 devices can be controlled in a parallel input
fashion using the SPI. Figure 23 illustrates 24 loads being
controlled by three dedicated para llel MCU ports used for
chip select.
Figure 23. Parallel Input SPI Control
Receive
Buffer
Parallel
Ports
To
Logic
33880
MC68HCxx
Microcontroller
DO
DI
CS
SCLK
MISO
MOSI
Shift Register Shift Register
MC68xx
MCU
with
SPI
Interface
8 Outputs 8 Outputs 8 Outputs
CS
MISO
MOSI
Parallel Port
SCLK
DO DI DO DI DO DI
CS CSSCLK SCLK
33880 33880 33880
DI
SCLK
DO
CS
Parallel
Ports
MOSI
MISO
SCLK
8 Outputs
MC68xx
Microcontroller
SPI
A
B
C
DI
SCLK
DO
CS
8 Outputs
DI
SCLK
DO
CS
8 Outputs
Analog Integrated Circuit Device Data
16 Freescale Semiconductor
33880
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 24. Data Transfer Timing
Analog Integrated Circuit Device Data
Freescale Semiconductor 17
33880
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POWER CONSUMPTION
The 33880 device has been designed with one sleep and
one operational mode. In the sleep mode (VDD ≤ 2.0 V), the
current consumed by the VPWR pin is less than 25 μA. To
place the 33880 in the sleep mode, turn all outputs off, then
remove power from VDD and the EN (enable) input pin. Prior
to removing power from the device, it is recommended all
control inputs from the microcontroller are low. During normal
operation, 4.0 mA will be drawn from the VDD supply and
12 mA from the VPWR supply.
PARALLELING OF OUTPUTS
Using MOSFETs as output switches allows the connection
of any combination of outputs together. RDS(ON) of MOSFETs
have an inherent positive temperature coefficient, providing
balanced current sharing between outputs without
destructive operation. The device can even be operated with
all outputs tied together. This mode of operation may be
desirable in the event the application requires lower power
dissipation or the added capability of switching higher
currents. Performance of parallel operation results in a
corresponding decrease in RDS(ON) while the outputs OFF
open load detect currents and the output current limits
increase correspondingly (by a factor of eight if all outputs are
paralleled). Paralleling outputs from two or more different IC
devices ar e possible but not re commended.
FAULT LOGIC OPERATION
Fault logic of the 33880 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs
faulted, all status bits being received by the MCU will be zero.
When outputs are faulted (off state open circuit or on state
short circuit / overtemperature), the status bits being received
by the MCU will be one. The distinction between open circuit
fault and short circuit / overtemperature is completed via the
command word. For example, when a zero command bit is
sent and a one fault is received in the following word, the fault
is open / sho rt-to-battery for high-side drive or open / short to
ground for low-side drive. In the same manner, when a one
command bit is sent and a one fault is received in the
following word the fault is a short-to-ground / overtemperature
for high-side drive or short-to-battery / overtemperature for
low-side drive. The timing between two write words must be
greater than 300 μs to allow adequate time to sense and
report the proper fault status.
SPI INTEGRITY CHECK
It is recommended that one check the integrity of the SPI
communication with the initial power-up of the VDD and EN
pins. After initial system star t-up or reset, the MCU will write
one 16-bit pattern to the 33880. The first eight bits read by the
MCU will be the fault status of the outputs, while the second
eight bits will be the first byte of the bit pattern. Bus integrity
is confirmed by the MCU receiving the same bit pattern it
sent. Please note that the second byte the MCU sends to the
device is the command byte and will be transferred to the
outputs with rising edge of CS.
OVERTEMPERATURE FAULT
Overtemperature detect and shutdo wn circuits are
specifically incorporated for each individual output. The
shutdown following an overtemperature condition is
independent of the system cl ock or any other logic signal.
Each independent outp ut shuts down at 155°C to 185°C.
When an output shuts down due to an overtemperature fault,
no other outputs are affected. The MCU recognizes the fault
by a one in the fault status register. After the 33880 device
has cooled below the switch poin t temperature and 15°C
hysteresis, the output will activate unless told otherwise by
the MCU via SPI to shut down.
OVERVOLTAGE FAULT
An overvoltage condition on the VPWR pin wi ll cause the
device to shut down all outputs until the overvoltage condition
is removed. When the overvoltage condition is removed, the
outputs will resume their previous state. This device does not
detect an overvoltage on the VDD pin. The overvoltag e
threshold on the VPWR pin is specified as 25 V to 30 V with
1.0 V typical hysteresis. A VPWR overvoltage detect is
global, causing all outputs to be turned OFF.
OUTPUT OFF OPEN LOAD FAULT
An output OFF open load fa ult is the detection and
reporting of an open load when the corresponding output is
disabled (input bit programmed to a logic low state). The
output OFF open load fault is detecte d by comparing the
drain-to-source voltage of the specific MOSFET output to an
internally generated reference. Each output has one
dedicated comparator for this purpose.
An output off open load fault is indicated when the drain-
to-source voltage is less than the output threshold voltage
(VTHRES) of 1.0 V to 3.0 V. Hence, the 33880 will declare the
load open in the OFF state when the VDS is less than 1.0 V.
This device has an internal 650 μA current source
connected from drain to source of the output MOSFET. This
prevents either configuratio n of the driver from having a
floating output. To achieve low sleep mode quiescent
currents, the open load detect current source of each drive r
is switched off when VDD is removed.
During output switching, especially with capacitive loads,
a false output OFF open load fault ma y be triggered. To
prevent this false fault from being reported, an internal fault
filter of 100 μs to 300 μs is incorporated. A false fault
reporting is a function of the load impedance, RDS(ON) , COUT
of the MOSFET, as well as the supply voltage, VPWR. The
rising edge of CS triggers the built-in fault delay timer. The
timer will time out before the fault comparator is enabled and
the fault is detected. Once the condition causing the open
load fault is removed, the device will resume normal
operation. The open load fault however, will be latched in the
output DO register for the MCU to read.
Analog Integrated Circuit Device Data
18 Freescale Semiconductor
33880
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SHORTED LOAD FAULT
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply or an output causing
the device to current limit (linear short).
There are two safety circuits progressively in operation
during load short conditions providin g system protection:
1. The device’s output current is moni tored in an analog
fashion using SENSEFET™ approach and current
limited.
2. The device’s output thermal limit is sensed and when
attained causes only the specific faulted output to shut
down. The output will rema in off until cooled. The
device will then reassert the output automatical ly. The
cycle will continue until the fault is remove or the
command bit instructs the output off.
UNDERVOLTAGE SHUTDOWN
An undervoltage VDD condition will result in the global
shutdown of all outputs. The undervoltage threshold is
between 3.9 V and 4.6 V. When VDD goes below the
threshold, all outputs are tur ned OFF and the Fault Status
(FS) register is cleared. As VDD returns to normal levels, the
FS register will resume normal operation.
An undervoltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5 V
and 9.0 V, the output will operate pe r th e command word.
However, the status as reported by the serial data output
(DO) pin may not be accurate below 9.0 V VPWR. Proper
operation at VPWR voltages below 5.5 V cannot be
guaranteed.
OUTPUT VOLTAGE CLAMP
Each output of the 33880 incorporates an internal voltage
clamp to provide fast turn-off and transient protection of each
output. Each clamp independently limits the drain-to-source
voltage to 45 V for low-side drive configurations and -20 V for
high-side drive configurations (see Figure 25). The total
energy clamped (EJ ) can be calc u l ated by multipl y i ng the
current area under the current curve (IA) times the clamp
voltage (VCL).
Characterization of the output clamps, using a single pulse
non-repetitive method at 0.3 A, indicates the maximum
energy to be 50 mJ at 150°C junction temperature per output.
Figure 25. Output Voltage Clamping
SPI CONFIGURATIONS
The SPI configuration on the 33880 device is consistent
with other devices in the OSS family. This device may be
used in serial SPI or parallel SPI with the 33291 and 33298.
Different SPI configurations may be provided. For more
information, contact Analog Products Division.
REVERSE BATTERY
The 33880 has been designed with reverse battery
protection on the VPWR pin. However, the device does not
protect the load from reverse battery. During the reverse
battery condition, current will flow through the load via the
output MOSFET substrate diode. Under this circumstance
relays may energize and lamps will turn on. If load reverse
battery protection is desired, a diode must be placed in series
with the load.
Current
Area (IA)
Clamp Energy
(EJ = IA x VCL)
Clamp Energy
(EJ = IA x VCL)
Drain Voltage
Source Voltage
Time
Time
Drain-to-Source Clamp
Voltage (VCL = 45 V)
Drain Current
(ID = 0.3 A)
GND
GND
VBAT
Drain-to-Source ON
Voltage (VDS(ON))
Drain-to-Source ON
Voltage (VDS(ON))
Current
Area (I
A
)
Source Current
(IS = 0.3 A)
Source Clamp Voltage
(VCL = -20 V)
Analog Integrated Circuit Device Data
Freescale Semiconductor 19
33880
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
On each SPI communication, an 8-bit command word is sent to the 33880 and an 8-bit fault word is received from the 33880.
The Most Significant Bit (MSB) is sent and recei ve d first (see below).
Command Register Definition:
0 = Output Command Off
1 = Output Command On
Fault Register Definition:
0 = No fault
1 = Fault.
MSB LSB
OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
Table 6. Fault Operation
SERIAL OUTPUT (SO) PINS REPORTS
Overtemperature Fault reported by Serial Output (DO) pin.
Overcurrent DO pin reports short to battery/supply or overcurrent condition.
Output ON Open Load Fault Not reported.
Output OFF Open Load Fault DO pin reports output OFF open load condition.
DEVICE SHUTDOWNS
Overvoltage Total device shutdown at VPWR = 25 V to 30 V. Resumes normal operation with proper voltage.
All outputs assuming the previous st ate upon recovery from overvoltage.
Overtemperature Only the output experiencing an overtemperature fault shuts down. Output assumes previous state
upon recovery from overtemperature.
Analog Integrated Circuit Device Data
20 Freescale Semiconductor
33880
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using “98ASB42345B”. Dimensions shown
are provided for reference ONLY.
Analog Integrated Circuit Device Data
Freescale Semiconductor 21
33880
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
EG SUFFIX (PB-FREE)
28-PIN
PLASTIC PACKAGE
98ASB42345B
REV G
Analog Integrated Circuit Device Data
22 Freescale Semiconductor
33880
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
EW SUFFIX (PB-FREE)
32-PIN
PLASTIC PACKAGE
98ASB42345B
REV B
Analog Integrated Circuit Device Data
Freescale Semiconductor 23
33880
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
EW SUFFIX (PB-FREE)
32-PIN
PLASTIC PACKAGE
98ASB42345B
REV B
Analog Integrated Circuit Device Data
24 Freescale Semiconductor
33880
REVISION HISTORY
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES
4.0 6/2006 • Implemented Revision History page
• Converted to Freescale format and adjusted content to prevailing form and style
5.0 6/2007 • Removed MC33880EG/R2 and MC33880EK/R2 from the ordering information and added
MCZ33880EG/R2 and MCZ33880EW/R2.
• Added Peak Package Reflow Temperature During Reflow (8), (9)
• Updated data sheet to current format.
6.0 5/2008 • Changed 32 pin SOICW, pins 8, 9, 24, 25 from GND to TGND on page 4.
7.0 1/2009 • Corrected Notes for Peak Package Reflow in Maximum Rating Table.
8.0 5/2012 • Removed MCZ33880EG from the ordering information and added MC33880PEG
• Removed MCZ33880EW from the ordering information added MC33880PEW
• Removed MC33880DW and MC33880DWB
• Removed DW and DWB suffix
• Updated Freescale form and style
Document Number: MC33880
Rev. 8.0
5/2012
Information in this document is provide d solely to enable system and software
implementers to use Freescale products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits on the
information in this document .
Freescale reserves the right to make changes without further notice to any products
herein. Freescale makes no warranty, representation, or guarantee regarding the
suitabil i ty of its products for any particular purpose, nor does Freescale assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liabil i ty, including without limitation consequential or incidental
damages. “Typical” paramet ers that may b e pro vided i n Free scale data sheets and/or
specifications can and do vary in dif ferent applicatio ns, and actual performance may
vary over time. All operating pa rameters, including “typicals,” must be validated for
each customer application by customer’s technical experts. Freescale does not convey
any license under its patent rights nor the rights of others. Freescale sells products
pursuant to st andard terms an d conditions of sale, which can be found at the following
address: http://www.reg.net/v2/webservices/Fre escale/Docs/TermsandConditions.htm
Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware,
Energy Ef ficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qor ivva, S tarCore, and
Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a
Package, Processor expert, QorIQ Qonver ge, QUICC Engine, Ready Play,
SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property of their
respective owners .
© 2012 Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support