1M (64K x 16) Static RAM
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 3 8-05226 Rev . ** Revised September 24, 2002
Features
•Very high speed: 55 n s
•Voltage range: 1.65V to 1.95V
•Ultra-low active power
—Typical active current: 0.5 mA @ f = 1 MHz
—Typical active current: 2.5 mA @ f = fMAX
•Ultra-low standby power
•Easy memory expansion with CE1, CE2 and OE features
•Automatic power-down when deselected
•CMOS for optimum speed/power
•Packages offered in a 48-ba ll FBGA and a 44-pi n TSOP
Type II
Functional Description[1]
The CY62127DV18 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The devic e al so ha s
an automatic power-down feature that significantly reduces
power co nsumption by 99% when address es are not togg ling.
The device can be put into st andby mode reduc ing power con-
sumption by more than 99% when deselected Chip Enable 1
(CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and
BLE are HIGH. Th e i np ut/o utpu t p ins (I/O0 throu gh I/O15) a re
placed in a high-impedance state when: deselected Chip En-
able 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are dis abl ed (BHE , BL E HIGH ) o r duri ng a w ri te op er-
ation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2)
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) inpu t LOW . If Byt e Low Enable (BLE ) is LOW , then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written i nto the locati on spe cifie d on the addres s pin s
(A0 through A15).
Reading from the device is accomplished by taking Chip En-
able 1 (CE 1) LO W and Chip Enable 2 (CE2) HIGH and Output
Enable (O E) L OW w hil e fo rci ng the W ri te Enab le (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then dat a from the memor y
location specified by the address pins will appear on I/O0 to
I/O7. If By te High En abl e (BHE) is L OW, then da ta from m em -
ory will app ear on I/O8 to I/O15. See the tru th t able a t the b ack
of this data sheet for a complete description of read and write
modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
64K ×16
RAM ARRAY I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
2048 x 32 x 16
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
0
A
1
A
9
A
10
Power-down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
Logic Block Diagram
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 2 of 13
Pin Configuration[2]
Note:
2. DNU pins are to be connected to VSS or left open.
WE
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
TSOP II (Forward)
12
13
41
44
43
42
16
15 29
30
V
CC
A
15
A
14
A
13
A
12
A
4
A
3
OE
V
SS
A
5
I/O
16
A
2
CE
I/O
3
I/O
1
I/O
2
BHE
CE
A
1
A
0
18
17
20
19
I/O
4
27
28
25
26
22
21 23
24
DNU
V
SS
I/O
7
I/O
5
I/O
6
I/O
8
A
6
A
7
BLE
V
CC
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
A
8
A
9
A
10
A
11
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
V
SS
A
7
I/O
0
BHE
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
326541
D
E
B
A
C
F
G
H
FBGA (Top View)
DNU
V
CC
1
CE
2
DNU
DNU
DNU
DNU
DNU
2
1
NU
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 3 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
.........................................................−0.2V to VCCMAX + 0.2V
DC Voltage Applied to Outputs
in High-Z State[3]....................................−0.2V to VCC + 0.2V
DC Input Voltage[3]................................−0.2V to VCC + 0.2V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ....................................................> 200 mA
Notes:
3. VIL(min.) = -2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Operating Range
Range Ambient
Temperature (T A)V
CC
Industrial −40°C to +85°C 1.65V to 1.95V
Product Portfol io
Product VCC Range(V) Speed
(ns)
Powe r Dissipation
Operating, Icc (mA) Standby, ISB2 (µA)f = 1 MHz f = fMAX
Min. Typ.[4] Max. Typ.[4] Max. Typ.[4] Max. Typ.[4] Max.
CY62127DV18L 1.65 1.8 1.95 55 0.5 1 2.5 5 0.5 3
CY62127DV18LL 55 2.5 5 0.5 2
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 4 of 13
DC Electrical Characteristics (Over the Operating Range)
Capacitance [5]
Thermal Resistance
Parameter Description Test Conditions CY62127DV18-55 UnitMin. Typ.[4] Max.
VOH Output HI GH Volt age IOH = −0.1 mA VCC = 1.65V 1.4 V
VOL Output LO W Voltage IOL = 0.1 mA VCC = 1.65V 0.2 V
VIH Input HIGH Voltage 1.4 VCC +
0.2 V
VIL Input LOW Voltage –0.2 0.4 V
IIX Input Leakage Current GND < VI < VCC –1+1µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1+1µA
ICC VCC Operating Supply Cur-
rent f = fMAX = 1/tRC Vcc = 1.95V , IOUT
= 0mA, CMOS
level
2.5 5 mA
f = 1 MHz 0.5 1
ISB1 Automatic CE Power-down
Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V,
VIN > VCC − 0.2V, VIN < 0.2V, f =
fMAX (Address and Data Only), f
= 0 (OE, WE, BHE and BLE)
L0.53µA
LL 0.5 2
ISB2 Automatic CE Power-down
Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < 0.2V,
VIN > VCC − 0.2 V or V IN < 0.2V, f
= 0, VCC=1.95V
L0.53µA
LL 0.5 2
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz
VCC = VCC(typ) 6pF
COUT Output Capacitance 8 pF
Parameter Description Test Conditions BGA Unit
θJA Thermal Resistance (Junction to
Ambient)[5] S till Air, sold ered on a 3 x 4.5 inch, two -layer
printed circuit bo ard 55 C/W
θJC Thermal Resistance (Junction to
Case)[5] 16 C/W
Note:
5. Tested initially and after any design or proces changes that may affect these parameters.
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 5 of 13
AC Test Loads and Waveforms
Data Retention Characteristics
Data Retention Waveform[7]
Parameter Description Conditions Min. Typ.[4] Max. Unit
VDR VCC for Data Retention 1 1.95 V
ICCDR Data Retention Current VCC = 1V, CE1 > VCC − 0.2V , CE2 <
0.2V, VIN > VCC − 0.2V or VIN < 0.2V L1µA
LL TBD
tCDR[5] Chip Deselect to Dat a Reten-
tion Time 0ns
tR[6] Ope r ati on Rec overy Time tRC ns
Notes:
6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC
Typ
V
CC
UTPUT
R2
C = 30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise Time:
1 V/ns Fall Time:
1 V/ns
L
Parameters 1.8V UNIT
R1 13500 Ω
R2 10800 Ω
R
TH
6000 Ω
V
TH
0.80 V
V
CC(min.)
V
CC(min.)
t
CDR
V
DR
> 1.0V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE .BLE
CE
2
or
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 6 of 13
Switching Characteristics (Over the Operating Range)[8]
Parameter Description CY62127DV18-55 UnitMin. Max.
Read Cycle
tRC Read Cycle Time 55 ns
tAA Address to Data Valid 55 ns
tOHA Data Hold from Address Change 10 ns
tACE CE1 LOW or CE2 HIGH to Data Valid 55 ns
tDOE OE LOW to Data Valid 25 ns
tLZOE OE LOW to Low-Z[9] 5ns
tHZOE OE HIGH to High-Z[9,11] 20 ns
tLZCE CE1 LOW or CE2 HIGH to Low-Z[9] 10 ns
tHZCE CE1 HIGH or CE2 LOW to High-Z[9,11] 20 ns
tPU CE1 LOW or CE2 HIGH to Power-up 0 ns
tPD CE1 HIGH or CE2 LOW to Power-down 55 ns
tDBE BLE/BHE LOW to Data Valid 55 ns
tLZBE[10] BLE/BHE LOW to Low-Z[9] 5ns
tHZBE BLE/BHE HIGH to High-Z[9,11] 20 ns
Write Cycle[12]
tWC Write Cycle Time 55 ns
tSCE CE1 LOW or CE2 HIGH to Write End 45 ns
tAW Address Set-up to Write End 45 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-up to Write Start 0 ns
tPWE WE Pulse Width 40 ns
tBW BLE/BHE LOW to Write End 45 n s
tSD Data Set-up to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z[9,11] 20 ns
tLZWE WE HIGH to Low-Z[9] 10 ns
Notes:
8. Te st con di tio ns assu me si gna l tran siti on time o f 3 ns or less, ti m ing r efe ren ce leve l s of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
10. If both byte enables are toggled together, this value is 10 ns.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/o r BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initia te a
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to th e ed ge o f th e s i g na l t h at
terminates the Write.
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 7 of 13
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
Read Cycle No. 2 (OE Controlled)[14, 15]
Notes:
13. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE 2 = VIH.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
ADDRESS
ATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
t
t
t
t
t
t
HIGH IMPEDANCE
t
t
HIGH
OE
CE
1
I
CC
I
SB
IMPEDANCE
ADDRESS
CE2
VCC
SUPPLY
CURRENT
t
BHE
/
BLE
t
t
DATA OUT
t
RC
ACE
PD
HZCE
HZBE
HZOE
LZBE
DOE
LZOE
LZCE
DBE
PU
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 8 of 13
Write Cycle No. 1 (WE Controlled) [12, 16, 17, 18]
Write Cycle No. 2 (CE1 or CE2 Controlled) [12, 16, 17, 18]
Notes:
16. Data I/O is high-impedance if OE = VIH.
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
t
t
tt tt
t
t
t
DATA
IN
VALID
CE1
ADDRESS
CE2
WE
ATA I/O
OE
BHE/BLE t
DON’T CARE
WC
SCE
SA
AW
PWE
HA
BW
HD
SD
HZOE
t
t
t
tt
t
t
t
DATA
IN
VALID
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
BHE /BLE t
t
DON’T CARE
WC
SCE
HA
AW
SA
PWE
BW
SD HD
HZOE
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 9 of 13
Write Cycle No. 3 (WE Controlled , OE LOW)[17, 18]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17]
Switching Waveforms (continued)
DATA
IN
VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
CE
1
ADDRESS
CE
2
WE
DATA I/O
DON’T CARE
DATA I/O
ADDRESS
t
t
t
tt
t
CE
1
WE
DATA
IN
VALID
t
BHE/BLE
t
CE
2
t
DON’T CARE
WC
SCE
AW HA
PWE
SA
HDSD
BW
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 10 of 13
Ordering Information
Truth Table
CE
1
CE
2
WE OE BHE BLE Input / Outputs Mode Power
H X X X X X High Z Deselect/Power-down Standby(I
SB
)
X L X X X X High Z Deselect/Power-down Standby(I
SB
)
X X X X H H High Z Deselect/Power-down Standby(I
SB
)
L H H L L L Data Out(I/O0
–
I/O15) Read Active(I
CC
)
L H H L H L Data Out(I/O0
–
I/O7);
High Z (I/O8
–
I/O15) Read Active(I
CC
)
L H H L L H High Z (I/O0
–
I/O7);
Data Out(I/O8
–
I/O15) Read Active(I
CC
)
L H H H L H High Z Output Disabled Active(I
CC
)
L H H H H L High Z Output Disabled Active(I
CC
)
L H H H L L High Z Output Disabled Active(I
CC
)
L H L X L L Data In (I/O0
–
I/O15) Write Active(I
CC
)
L H L X H L Data In (I/O0
–
I/O7);
High Z (I/O8
–
I/O15) Write Active(I
CC
)
L H L X L H High Z (I/O0
–
I/O7);
Data In (I/O8
–
I/O15) Write Active(I
CC
)
Speed
(ns) Ordering Code Package
Name Packa ge Type Operating
Range
55 CY62127DV18L-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Industrial
CY62127DV18LL-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm)
CY62127DV18L-55ZI Z44 44-lead TSOP Type II
CY62127DV18LL-55ZI Z44 44-lead TSOP Type II
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 11 of 13
Package Diagrams 48-ball VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Rev. ** Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
44-pin TSOP II Z44
51-85087-A
CY62127DV18
MoBL2®
ADVANCE
INFORMATION
Document #: 38-05226 Re v. ** Page 13 of 13
Document History Page
Document Title: CY62127DV18 MoBL2® 1M (64K x 16) Static RAM
Document Number: 38-052 26
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 11 8006 10/01/02 CDY New Data Sheet
