MB91520 Series
32-bit FR81S Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-04662 Rev. *D Revised June 23, 2016
The MB91520 series is a Cypress 32-bit microcontroller designed for automotive devices. This series contains the FR81S CPU
which is compatible with the FR family.
Note:This series is a composition of the end of the above-mentioned each name of articles of presence, According to Presence of
sub-clock, CSV initial value and LVD initial value. Please see "ORDERING INFORMATION" for details.
Features
FR81S CPU Core
32-bit RISC, load/store architecture, pipeline 5-stage
structure
Maximum operating frequency: 80 MHz (Source oscillation
= 4.0 MHz and 20 multiplied (PLL clock multiplication
system))
General-purpose register : 32 bits × 16 sets
16-bit fixed length instructions (basic instruction),
1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instruction
Bit processing instruction
Barrel shift order etc.
High-level language support instructions
Function entry/exit instructions
Register content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Overhead reduction during branch process
Register interlock function
Easy assembler writing
The support at the built-in / instruction level of the multiplier
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Interrupt (PC/PS saving)
6 cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of
program and data access.
Instruction compatibility with the FR Family
Built-in memory protection function (MPU)
Eight protection areas can be specified commonly for
instructions and the data.
Control access privilege in both privilege mode and
user mode.
Built-in FPU (floating point arithmetic)
IEEE754 compliant
Floating-point register 32-bit × 16 sets
Peripheral Functions
Clock generation (equipped with SSCG function)
Main oscillation (4MHz to 16MHz)
Sub oscillation (32kHz) or none sub oscillation
PLL multiplication rate : 1 to 20 times
Equipped with a 100kHz CR oscillator
Built-in program flash memory capacity
MB91F522:256+64KB
MB91F523:384+64KB
MB91F524:512+64KB
MB91F525:768+64KB
MB91F526:1024+64KB
Flash memory for built-in data (WorkFlash) 64KB
Built-in RAM capacity
Main RAM
MB91F522:48KB
MB91F523:48KB
MB91F524:64KB
MB91F525:96KB
MB91F526:128KB
Backup RAM 8KB
General-purpose ports:
MB91F52xB 44 sets (No sub oscillation), 42 sets (sub
oscillation)
MB91F52xD 56 sets (No sub oscillation), 54 sets (sub
oscillation)
MB91F52xF 76 sets (No sub oscillation), 74 sets (sub
oscillation)
MB91F52xJ 96 sets (No sub oscillation), 94 sets (sub
oscillation)
MB91F52xK 120 sets (No sub oscillation), 118 sets (sub
oscillation)
MB91F52xL 152 sets (No sub oscillation), 150 sets (sub
oscillation)
Included I2C open drain corresponding ports:16 sets
External bus interface
22-bit address, 16-bit data
DMA Controller
Up to 16 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and
software)
A/D converter (successive approximation type)
12-bit resolution : Max.48ch (32ch+16ch)
Conversion time : 1.4μs
Document Number: 002-04662 Rev. *D Page 2 of 289
MB91520 Series
D/A converter (R-2R type)
8-bit resolution : 2ch
External interrupt input: 8 channels × 2 units total
16 channels
Level ("H" / "L"), or edge detection (rising or falling)
enabled
Multi-function serial communication (built-in
transmission/reception FIFO memory) : Max.12 channels
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11
CMOS hysteresis input
< UART (Asynchronous serial interface) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
Parity or no parity is selectable.
Built-in dedicated baud rate generator
An external clock can be used as the transfer clock
Parity, frame, and overrun error detection functions
provided
DMA transfer support
<CSIO (Synchronous serial interface) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
SPI supported; master and slave systems supported;
5 to 16, 20, 24, 32-bit data length can be set.
Built-in dedicated baud rate generator (Master
operation)
An external clock can be entered. (Slave operation)
Overrun error detection function is provided
DMA transfer support
Serial chip select SPI function
<LIN (Asynchronous Serial Interface for LIN) >
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
LIN protocol revision 2.1 supported
Master and slave systems supported
Framing error and overrun error detection
LIN synch break generation and detection; LIN synch
delimiter generation
Built-in dedicated baud rate generator
An external clock can be adjusted by the reload
counter
DMA transfer support
Hard assist function
< I2C >
2 channels ch.3 , ch.4 Standard mode/fast mode
supported.
6 channels ch.5 to ch.8, ch.10, ch.11 Standard mode
supported.
Full-duplex double buffering system, 64-step
transmission FIFO memory, 64-step reception FIFO
memory
Standard mode (Max. 100kbps) / fast mode (Max.
400kbps) supported
DMA transfer supported (for transmission only)
CAN Controller (CAN) : 3 channels
Transfer speed : Up to 1Mbps
128-transmission/reception message buffering :
1 channel (ch.0),
64-transmission/reception message buffering :
2 channels (ch.1 and ch.2)
PPG: 16-bit × Max. 48 channels
LED drive output 4 channels 11ch to 14ch
Reload timer : 16-bit × Max.8 channels
Free-run timer :
16-bit × 3 channels
32-bit × Max 3 channels
Input capture :
16-bit × 4 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
Output compare :
16-bit × 6 channels (linked to the free-run timer)
32-bit × Max 6 channels (linked to the free-run timer)
Waveform generator : 6 channels
Up/Down counter
8/16-bit Up/Down counter × 2 channels
Real-time clock (RTC) (for day, hours, minutes, seconds)
Main or sub oscillation frequency can be selected for
the operation clock
Calibration: Real-time clock (RTC) of the subclock drive
The main clock to sub clock ratio can be corrected by
setting the real-time clock prescaler
Clock Supervisor
Monitoring abnormality (by damaged quartz, etc.) of
suboscillation (32kHz) (dual clock products)
of the outside and main oscillation (4 MHz)
When abnormality is detected, it switches to the CR
clock.
Initial value ON/OFF can be selected by the part
number.
Base timer : Max.2 channels
16-bit timer
Any of four PWM/PPG/PWC/reload timer functions can
be selected and used
As for the PWC function and the reload timer function,
a pair of 16-bit timers can be used as one 32-bit timer
in the cascade mode
CRC generation
Watchdog timer
Hardware watchdog
Software watchdog (possible to set the valid range for
counter clearing)
NMI (non-maskable interrupt)
Interrupt controller
Interrupt request batch read
The interrupt existence from two or more peripherals
can be read by a series of register.
I/O relocation
Peripheral function pins can be reassigned.
Low-power consumption mode
Sleep / Stop / Watch / Sub RUN mode
Stop (power shutdown) / Watch (power shutdown)
mode
Document Number: 002-04662 Rev. *D Page 3 of 289
MB91520 Series
Power-on reset
Low-voltage detection reset (independently monitor the
external power supply and the internal power supply)
The external power supply can select initial value
ON/OFF by the part number.
Device Package : 176/144/120/100/80/64
CMOS 90nm Technology
Power supplies
5V Power supply
The internal 1.2V is generated from 5V with the voltage
step-down circuit
Document Number: 002-04662 Rev. *D Page 4 of 289
MB91520 Series
Contents
1. Product Lineup .......................................................................................................................... 5
2. Pin Assignment ....................................................................................................................... 12
3. Pin Description ........................................................................................................................ 18
4. I/O Circuit Type ....................................................................................................................... 36
5. Handling Precautions .............................................................................................................. 41
6. Handling Devices .................................................................................................................... 45
7. Block Diagram ......................................................................................................................... 48
8. Memory Map ........................................................................................................................... 54
9. I/O Map.................................................................................................................................... 56
10. Interrupt Vector Table ............................................................................................................ 117
11. Electrical Characteristics ....................................................................................................... 141
12. EXAMPLE CHARACTERISTICS .......................................................................................... 201
13. Ordering Information MB91F52xxxB*1 .................................................................................. 204
14. Ordering Information MB91F52xxxC*1 .................................................................................. 211
15. Ordering Information MB91F52xxxD .................................................................................... 218
16. Ordering Information MB91F52xxxE ..................................................................................... 222
17. Package Dimensions ............................................................................................................ 226
18. Errata ..................................................................................................................................... 233
19. Major Changes ...................................................................................................................... 236
Document Number: 002-04662 Rev. *D Page 5 of 289
MB91520 Series
1. Product Lineup
Product lineup comparison 64 pins
MB91F522B
MB91F523B
MB91F524B
MB91F525B
MB91F526B
System Clock
On chip PLL Clock multiple method
Minimum instruction execution time
12.5ns (80MHz)
Flash Capacity (Program)
(256+64)KB
(384+64)KB
(512+64)KB
(768+64)KB
(1024+64)KB
Flash Capacity (Data)
64KB
RAM Capacity
(64+8)KB
(96+8)KB
(128+8)KB
External BUS I/F
(22address/16data/4cs)
None
DMA Transfer
16ch
16-bit Base Timer
None
Free-run Timer
16bit×3ch, 32bit×1ch
Input capture
16bit×4ch, 32bit×5ch
Output Compare
16bit×6ch, 32bit×4ch
16-bit Reload Timer
7ch
PPG
16bit×21ch
Up/down Counter
2ch
Clock Supervisor
Yes
External Interrupt
8ch×2units
A/D converter
12bit×13ch (1unit), 12bit×13ch (1unit)
D/A converter (8bit)
1ch
Multi-Function Serial Interface
8ch*1
CAN
64msg×2ch/128msg×1ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
44 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6ch
NMI request function
Yes
Operation guaranteed temperature (TA)
-40°C to +125°C
Power supply
2.7V to 5.5V *2
Package
LQD064
*1: Only channel 5, channel 6 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 6 of 289
MB91520 Series
Product lineup comparison 80 pins
MB91F522D MB91F523D MB91F524D MB91F525D MB91F526D
System Clock
On chip PLL Clock multiple method
Minimum instruction execution time
12.5ns (80MHz)
Flash Capacity (Program)
(256+64)KB
(384+64)KB
(512+64)KB
(768+64)KB
(1024+64)KB
Flash Capacity (Data)
64KB
RAM Capacity
(48+8)KB
(64+8)KB
(96+8)KB
(128+8)KB
External BUS I/F
(22address/16data/4cs)
None
DMA Transfer
16ch
16-bit Base Timer
1ch
Free-run Timer
16bit×3ch, 32bit×2ch
Input capture
16bit×4ch, 32bit×5ch
Output Compare
16bit×6ch, 32bit×4ch
16-bit Reload Timer
7ch
PPG
16bit×27ch
Up/down Counter
2ch
Clock Supervisor
Yes
External Interrupt
8ch×2units
A/D converter
12bit×16ch (1unit), 12bit×16ch (1unit)
D/A converter (8bit)
1ch
Multi-Function Serial Interface
9ch*1
CAN
64msg×2ch/128msg×1ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
56 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6ch
Operation guaranteed temperature
(TA)
-40°C to +125°C
Power supply
2.7V to 5.5V *2
Package
LQH080
*1: Only channel 5, channel 6 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 7 of 289
MB91520 Series
Product lineup comparison 100 pins
MB91F522F MB91F523F MB91F524F MB91F525F MB91F526F
System Clock
On chip PLL Clock multiple method
Minimum instruction execution time
12.5ns (80MHz)
Flash Capacity (Program)
(256+64)KB
(384+64)KB
(512+64)KB
(768+64)KB
(1024+64)KB
Flash Capacity (Data)
64KB
RAM Capacity
(48+8)KB
(64+8)KB
(96+8)KB
(128+8)KB
External BUS I/F
(22address/16data/4cs)
None
DMA Transfer
16ch
16-bit Base Timer
1ch
Free-run Timer
16bit×3ch, 32bit×3ch
Input capture
16bit×4ch, 32bit×6ch
Output Compare
16bit×6ch, 32bit×6ch
16-bit Reload Timer
8ch
PPG
16bit×34ch
Up/down Counter
2ch
Clock Supervisor
Yes
External Interrupt
8ch×2units
A/D converter
12bit×21ch (1unit), 12bit×16ch (1unit)
D/A converter (8bit)
2ch
Multi-Function Serial Interface
12ch*1
CAN
64msg×2ch/128msg×1ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
76 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6ch
Operation guaranteed temperature
(TA)
-40°C to +125°C
Power supply
2.7V to 5.5V *2
Package
LQI100
*1: Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 8 of 289
MB91520 Series
Product lineup comparison 120 pins
MB91F522J MB91F523J MB91F524J MB91F525J MB91F526J
System Clock
On chip PLL Clock multiple method
Minimum instruction execution time
12.5ns (80MHz)
Flash Capacity (Program)
(256+64)KB
(384+64)KB
(512+64)KB
(768+64)KB
(1024+64)KB
Flash Capacity (Data)
64KB
RAM Capacity
(48+8)KB
(64+8)KB
(96+8)KB
(128+8)KB
External BUS I/F
(22address/16data/4cs)
None
DMA Transfer
16ch
16-bit Base Timer
2ch
Free-run Timer
16bit×3ch, 32bit×3ch
Input capture
16bit×4ch, 32bit×6ch
Output Compare
16bit×6ch, 32bit×6ch
16-bit Reload Timer
8ch
PPG
16bit×38ch
Up/down Counter
2ch
Clock Supervisor
Yes
External Interrupt
8ch×2units
A/D converter
12bit×26ch (1unit), 12bit×16ch (1unit)
D/A converter (8bit)
2ch
Multi-Function Serial Interface
12ch*1
CAN
64msg×2ch/128msg×1ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
96 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6ch
Operation guaranteed temperature (TA)
-40°C to +125°C
Power supply
2.7V to 5.5V *2
Package
LQM120
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 9 of 289
MB91520 Series
Product lineup comparison 144 pins
MB91F522K MB91F523K MB91F524K MB91F525K MB91F526K
System Clock
On chip PLL Clock multiple method
Minimum instruction execution time
12.5ns (80MHz)
Flash Capacity (Program)
(256+64)KB
(384+64)KB
(512+64)KB
(768+64)KB
(1024+64)KB
Flash Capacity (Data)
64KB
RAM Capacity
(48+8)KB
(64+8)KB
(96+8)KB
(128+8)KB
External BUS I/F
(22address/16data/4cs)
Yes
DMA Transfer
16ch
16-bit Base Timer
2ch
Free-run Timer
16bit×3ch, 32bit×3ch
Input capture
16bit×4ch, 32bit×6ch
Output Compare
16bit×6ch, 32bit×6ch
16-bit Reload Timer
8ch
PPG
16bit×44ch
Up/down Counter
2ch
Clock Supervisor
Yes
External Interrupt
8ch×2units
A/D converter
12bit×32ch (1unit), 12bit×16ch (1unit)
D/A converter (8bit)
2ch
Multi-Function Serial Interface
12ch*1
CAN
64msg×2ch/128msg×1ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
120 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6ch
Operation guaranteed temperature (TA)
-40°C to +125°C
Power supply
2.7V to 5.5V *2
Package
LQS144, LQN144
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 10 of 289
MB91520 Series
Product lineup comparison 176 pins
MB91F522L MB91F523L MB91F524L MB91F525L MB91F526L
System Clock
On chip PLL Clock multiple method
Minimum instruction execution time
12.5ns (80MHz)
Flash Capacity (Program)
(256+64)KB
(384+64)KB
(512+64)KB
(768+64)KB
(1024+64)KB
Flash Capacity (Data)
64KB
RAM Capacity
(48+8)KB
(64+8)KB
(96+8)KB
(128+8)KB
External BUS I/F
(22address/16data/4cs)
Yes
DMA Transfer
16ch
16-bit Base Timer
2ch
Free-run Timer
16bit×3ch, 32bit×3ch
Input capture
16bit×4ch, 32bit×6ch
Output Compare
16bit×6ch, 32bit×6ch
16-bit Reload Timer
8ch
PPG
16bit×48ch
Up/down Counter
2ch
Clock Supervisor
Yes
External Interrupt
8ch×2units
A/D converter
12bit×32ch (1unit), 12bit×16ch (1unit)
D/A converter (8bit)
2ch
Multi-Function Serial Interface
12ch*1
CAN
64msg×2ch/128msg×1ch
Hardware Watchdog Timer
Yes
CRC Formation
Yes
Low-voltage detection reset
Yes
Flash Security
Yes
ECC Flash/WorkFlash
Yes
ECC RAM
Yes
Memory Protection Function (MPU)
Yes
Floating point arithmetic (FPU)
Yes
Real Time Clock (RTC)
Yes
General-purpose port (#GPIOs)
152 ports
SSCG
Yes
Sub clock
Yes
CR oscillator
Yes
NMI request function
Yes
OCD (On Chip Debug)
Yes
TPU (Timing Protection Unit)
Yes
Key code register
Yes
Waveform generator
6ch
Operation guaranteed temperature (TA)
-40°C to +125°C
Power supply
2.7V to 5.5V *2
Package
LQP176
*1: Only channel 3 and channel 4 support the I2C (fast mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8, channel 10 and channel 11 support the I2C (standard mode).
*2: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 11 of 289
MB91520 Series
Table for clock supervisor and external low voltage detection reset initial value ON/OFF
Clock
CSV Initial value
LVD Initial value
Function
single
ON
ON
S
OFF
U
OFF
ON
H
OFF
K
Dual
ON
ON
W
OFF
Y
OFF
ON
J
OFF
L
ＭＢ９１Ｆ５２Ｘ□△○
│││└→Ｒｅｖｉｓｉｏｎ：Ｂ, Ｃ, Ｄ, Ｅ
││└─→Ｆｕｎｃｔｉｏｎ：See the table for clock supervisor and external
｜｜ low voltage detection reset initial value ON/OFF.
│└──→ＰＫＧ Ｔｙｐｅ：Ｂ ６４ｐｉｎ
│ Ｄ ８０ ｐｉｎ
│ Ｆ １００ ｐｉｎ
│ Ｊ １２０ ｐｉｎ
│ Ｋ １４４ ｐｉｎ
│ Ｌ １７６ ｐｉｎ
└───→Ｍｅｍｏｒｙ Ｓｉｚｅ：２ ２５６ＫＢ
３ ３８４ＫＢ
４ ５１２ＫＢ
５ ７６８ＫＢ
６ １ＭＢ
Document Number: 002-04662 Rev. *D Page 12 of 289
MB91520 Series
2. Pin Assignment
MB91F52xB
MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
(TOP VIEW)
VCC
P011/WOT/INT3_1
P006/ADTG1_1/INT2_1/TX2(64)
P005/ADTG0_1/INT7_1/RX2(64)
C
VSS
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P126/SIN0_0/INT6_0
DEBUGIF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VSS 1 48 P122/SIN6_0/AN31/OCU8_0/INT9_1
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1 2 47 P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0 3 46 P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1 4 45 P110/TX1(64)/SCS63_0/AN22
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1 5 44 NMIX
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2 6 43
P105/AN17/PPG13_0
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2 7 42
P104/AN16/PPG12_0
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 8 41 P103/AN15/PPG11_0
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0 9 40 P102/AN14/PPG10_0/INT10_0
P036/OCU7_1/TOT5_0/BIN0_0 10 39 AVCC0
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1 11 38 AVRH0
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0 12 37 AVS S 0/AVRL0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0 13 36 P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2 14 35 P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P047/AN45/TRG8_0/TIN3_2/SOT0_1 15 34 P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
P053/AN44/PPG35_0/INT14_1/SCK0_1 16 33 VSS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P087/DAO0/PPG7_0/INT8_0
VCC
●
TOP VIEW
MB91F522B,
MB91F523B,
MB91F524B,
MB91F525B,
MB91F526B
LQFP-64
* In a single clock product, pin 56 and pin 57 are the general-purpose ports.
LQD064
Document Number: 002-04662 Rev. *D Page 13 of 289
MB91520 Series
MB91F52xD
MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
(TOP VIEW)
VCC
P011/WOT/SOT2_1/INT3_1
P006/SCS2_0/ADTG1_1/INT2_1/TX2(64)
P005/SCK2_0/ADTG0_1/INT7_1/RX2(64)
P003/SIN2_0/TIOB1_1/INT3_0
P001/TIOA1_1
C
VSS
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P127/SOT0_0
P126/SIN0_0/INT6_0
DEBUGIF
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VSS 1 60 VSS
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1 2 59 P122/SIN6_0/AN31/OCU8_0/INT9_1
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0 3 58 P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
P026/SCK4_1/PPG26_0/TIN3_0 4 57 P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1 5 56 P114/SCS61_0/AN26/PPG18_0/RTO2_0
P031/SCS42_1/PPG29_0 6 55 P110/TX1(64)/SCS63_0/AN22
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1 7 54 NM IX
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2 8 53 P107/AN19/PPG15_0
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2 9 52
P105/AN17/PPG13_0
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 10 51 P104/AN16/PPG12_0
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0 11 50 P103/AN15/PPG11_0
P036/OCU7_1/TOT5_0/BIN0_0 12 49 P102/AN14/PPG10_0/INT10_0
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1 13 48
P100/AN12/PPG8_0
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0 14 47 AVCC0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0 15 46 AVRH0
P044/SCS9_0/ICU6_1/TRG2_1 16 45 AVS S 0/AVRL0
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2 17 44 P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P047/AN45/TRG8_0/TIN3_2/SOT0_1 18 43 P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P053/AN44/PPG35_0/INT14_1/SCK0_1 19 42 P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
VCC 20 41 VSS
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/AN33/ICU3_2
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P087/DAO0/PPG7_0/INT8_0
VCC
●
TOP VIEW
MB91F522D,
MB91F523D,
MB91F524D,
MB91F525D,
MB91F526D
LQFP-80
* In a single clock product, pin 70 and pin 71 are the general-purpose ports.
LQH080
Document Number: 002-04662 Rev. *D Page 14 of 289
MB91520 Series
MB91F52xF
MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F
(TOP VIEW)
VCC
P011/WOT/SOT2_1/INT3_1
P006/SCS2_0/ADTG1_1/INT2_1
P005/SCK2_0/ADTG0_1/INT7_1
P003/SIN2_0/TIOB1_1/INT3_0
P001/SOT1_0/TIOA1_1
P000/SIN1_0/INT2_0
C
VSS
P144/SCK1_1
P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
P133/TX2(64)
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P130/SCK0_0
P127/SOT0_0
P126/SIN0_0/INT6_0
DEBUGIF
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VSS 175 VSS
P020/SIN3_1/TRG3_0/TIN0_ 2/RTO5_1 274 P 122/SIN6_ 0/AN31/OCU8_0/INT9_1
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0 373 P117/SCS60_0/AN29/PP G21_0/RTO5_0
P025/SOT4_1/PPG25_0/TIN2_ 0 472 P116/SCK6_0/SCL6/AN28/PP G20_0/RTO4_0
P026/SCK4_1/PPG26_0/TIN3_0 571 P 115/RX1_1/SOT6_ 0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P027/SCS40_1/PP G27_0/TOT0_0/RTO3_1 670 P114/SCS61_0/AN26/PPG18_0/RTO2_0
P030/SCS41_1/PP G28_0/TOT1_0 769 P111/RX1(64)/SCS62_0/AN23/INT1_0
P031/SCS42_1/PP G29_0/TOT2_0 868 P110/TX1(64)/SCS63_0/AN22
P032/SCS43_1/PP G30_0/TOT3_0/RTO2_1 967 NMIX
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2 10 66 P107/AN19/PPG15_0
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2 11 65 P106/SCS70_0/AN18/PPG14_0
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0 12 64 P105/SCS71_0/AN17/PPG13_0
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 13 63 P 104/SCS72_0/AN16/P P G12_0
P035/SIN8_0/OCU8_1/TOT4_0/AIN0_0/INT11_0 14 62 P103/SCS73_0/AN15/PPG11_0
P036/SCS8_0/OCU7_1/TOT5_0/BIN0_0 15 61 P102/SIN7_0/AN14/P P G10_0/INT10_0
P037/OCU6_1/TOT6_0/ZIN0_ 0 16 60 P 101/SOT7_0/SDA7/AN13/PPG9_0
P040/PPG23_1/TOT7_ 0/AIN1_0/SIN0_1 17 59 P100/SCK7_0/SCL7/AN12/PPG8_0
P041/SIN9_0/ICU9_1/BIN1_ 0/INT12_0 18 58 AVCC0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0 19 57 AVRH0
P043/ICU7_1/TRG1_1 20 56 AVSS0/AVRL0
P044/SCS9_0/ICU6_1/TRG2_1 21 55 P097/SCK11_0/SCL11/AN11/ICU5_0/PP G17_1
P045/SCK9_0/AN46/ICU5_ 1/TRG3_1/TOT1_2 22 54 P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P047/AN45/TRG8_0/TIN3_2/SOT0_1 23 53 P 095/TX0(128)/SCS11_0/AN9
P053/AN44/PPG35_0/INT14_1/SCK0_1 24 52 P093/TX0_1/SIN11_0/AN7/ICU4_ 2/P P G16_1/ICU3_0/TOT2_1
VCC 25 51 VSS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P070/ICU0_2
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/AN33/ICU3_2
P152/SCS53_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P086/DAO1/PPG6_0
P087/DAO0/PPG7_0/INT8_0
VCC
●
TOP VIEW
MB91F522F,
MB91F523F,
MB91F524F,
MB91F525F,
MB91F526F
LQFP-100
* In a single clock product, pin 86 and pin 87 are the general-purpose ports.
LQI100
Document Number: 002-04662 Rev. *D Page 15 of 289
MB91520 Series
MB91F52xJ
MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J
(TOP VIEW)
VCC
P011/WOT/SOT2_1/TIOA0_0/INT3_1
P010
P007
P006/SCS2_0/ADTG1_1/INT2_1
P005/SCK2_0/ADTG0_1/INT7_1
P003/SIN2_0/TIOB1_1/INT3_0
P002/SCK1_0/TIOB0_1
P001/SOT1_0/TIOA1_1
P000/SIN1_0/TIOA0_1/INT2_0
C
VSS
P144/SCK1_1
P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
P133/TX2(64)
P132/SCS1_0/ADTG1_0
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P130/SCK0_0
P127/SOT0_0
P126/SIN0_0/INT6_0
P125/OCU11_0
DEBUGIF
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
VSS 190 VSS
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1 289 P122/SIN6_0/AN31/OCU8_0/INT9_1
P021/SOT3_1/TRG6_1/TRG4_0 388 P120/AN30/OCU6_0/PPG22_0/INT9_0
P022/SCK3_1/TRG7_1/TRG5_0 487 P 117/SCS60_0/AN29/PPG21_0/RTO5_0
P023/SCS3_ 1/P P G32_0/TIN0_0 586 P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_ 0
P024/SIN4_1/PPG24_0/TIN1_ 0/RTO4_ 1/INT15_ 0 685 P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P025/SOT4_1/PPG25_0/TIN2_0 784 P114/SCS61_0/AN26/PPG18_0/RTO2_0
P026/SCK4_1/PPG26_0/TIN3_0 883 P113/AN25/P PG17_0/RTO1_0
P027/SCS40_ 1/P P G27_0/TOT0_0/RTO3_1 982 P112/AN24/PPG16_0/RTO0_ 0
P030/SCS41_ 1/P P G28_0/TOT1_0 10 81 P111/RX1(64)/SCS62_0/AN23/INT1_0
P031/SCS42_ 1/P P G29_0/TOT2_0 11 80 P110/TX1(64)/SCS63_ 0/AN22
P032/SCS43_ 1/P P G30_0/TOT3_0/RTO2_1 12 79 NMIX
P033/PPG31_0/ICU3_ 3/TIN4_0/RTO1_1/SCK3_2 13 78 P155/AN21
P034/OCU11_1/ICU2_ 3/TIN5_ 0/RTO0_ 1/SOT3_2 14 77 P 154/AN20
P150/SOT8_0/SDA8/OCU10_ 1/TRG6_0/ICU1_3/TIN6_0 15 76 P107/AN19/PPG15_0
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 16 75 P106/SCS70_0/AN18/PPG14_0
P035/SIN8_0/OCU8_1/TOT4_0/AIN0_ 0/INT11_ 0 17 74 P 105/SCS71_0/AN17/P PG13_0
P036/SCS8_ 0/OCU7_1/TOT5_0/BIN0_0 18 73 P104/SCS72_0/AN16/PPG12_0
P037/OCU6_1/TOT6_0/ZIN0_0 19 72 P103/SCS73_0/AN15/PPG11_0
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_ 1 20 71 P 102/SIN7_0/AN14/PPG10_0/INT10_0
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0 21 70 P 101/SOT7_0/SDA7/AN13/PPG9_0
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_ 0 22 69 P 100/SCK7_0/SCL7/AN12/PP G8_0
P043/ICU7_1/TRG1_1 23 68 AVCC0
P044/SCS9_ 0/ICU6_1/TRG2_1 24 67 AVRH0
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_ 2 25 66 AVSS0/AVRL0
P046/ICU4_1/TRG4_1 26 65 P 097/SCK11_ 0/SCL11/AN11/ICU5_0/PPG17_1
P047/AN45/TRG8_0/TIN3_2/SOT0_ 1 27 64 P 096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
P050/TRG5_1/P PG33_0 28 63 P095/TX0(128)/SCS11_0/AN9
P053/AN44/PPG35_0/INT14_1/SCK0_1 29 62 P 093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_ 0/TOT2_ 1
VCC 30 61 VSS
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
P056/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P070/ICU0_2
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P074/SCK4_0/SCL4
P075/SIN3_0/INT4_0
P076/SOT3_0/SDA3
P077/SCK3_0/SCL3
P152/SCS53_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P086/DAO1/PPG6_0
P087/DAO0/PPG7_0/INT8_0
VCC
●
TOP VIEW
MB91F522J,
MB91F523J,
MB91F524J,
MB91F525J,
MB91F526J
LQFP-120
* In a single clock product, pin 102 and pin 103 are the general-purpose ports.
LQM120
Document Number: 002-04662 Rev. *D Page 16 of 289
MB91520 Series
MB91F52xK
MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K
(TOP VIEW)
VCC
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P012/D26/TIOB0_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P010/D24
P007/D23
P006/D22/SCS2_0/ADTG1_1/INT2_1
P005/D21/SCK2_0/ADTG0_1/INT7_1
P004/D20/SOT2_0
P003/D19/SIN2_0/TIOB1_1/INT3_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
P144/SCK1_1
P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
P133/TX2(64)
P132/SCS1_0/ADTG1_0
P131/ADTG0_0
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P130/SCK0_0
P127/SOT0_0
P126/SIN0_0/INT6_0
P125/OCU11_0
P124/OCU10_0
DEBUGIF
VCC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VSS 1108 VSS
P015/D29/TRG0_0 2107 P 123/OCU9_0
P016/D30/TRG1_0 3106 P 122/SIN6_ 0/AN31/OCU8_0/INT9_ 1
P017/D31/TRG2_0 4105 P 121/OCU7_0/PP G23_0
P020/ASX/SIN3_1/TRG3_0/TIN0_ 2/RTO5_1 5104 P120/AN30/OCU6_0/PPG22_0/INT9_ 0
P021/CS0X/SOT3_1/TRG6_1/TRG4_0 6103 P117/SCS60_0/AN29/PP G21_0/RTO5_0
P022/CS1X/SCK3_1/TRG7_1/TRG5_0 7102 P 116/SCK6_0/SCL6/AN28/PPG20_ 0/RTO4_0
P023/RDX/SCS3_1/PPG32_0/TIN0_0 8101 P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
P024/WR0X/SIN4_1/PPG24_0/TIN1_ 0/RTO4_1/INT15_0 9100 P114/SCS61_ 0/AN26/P PG18_0/RTO2_0
P025/WR1X/SOT4_1/PPG25_0/TIN2_0 10 99 P113/AN25/PPG17_0/RTO1_0
P026/A00/SCK4_ 1/P PG26_0/TIN3_ 0 11 98 P112/AN24/P PG16_0/RTO0_ 0
P027/A01/SCS40_1/PPG27_0/TOT0_0/RTO3_1 12 97 P111/RX1(64)/SCS62_0/AN23/INT1_0
P030/A02/SCS41_1/PPG28_0/TOT1_0 13 96 P110/TX1(64)/SCS63_0/AN22
P031/A03/SCS42_1/PPG29_0/TOT2_0 14 95 NMIX
P032/A04/SCS43_1/PPG30_0/TOT3_0/RTO2_1 15 94 P155/AN21
P033/A05/P P G31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_ 2 16 93 P154/AN20
P034/A06/OCU11_1/ICU2_3/TIN5_0/RTO0_ 1/SOT3_2 17 92 P107/AN19/PPG15_0
P150/SOT8_0/SDA8/OCU10_1/TRG6_0/ICU1_3/TIN6_0 18 91 P106/SCS70_0/AN18/PPG14_0
P151/SCK8_0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 19 90 P 105/SCS71_0/AN17/PPG13_0
P035/A07/SIN8_ 0/OCU8_ 1/TOT4_0/AIN0_ 0/INT11_0 20 89 P104/SCS72_ 0/AN16/P PG12_0
P036/A08/SCS8_0/OCU7_1/TOT5_0/BIN0_0 21 88 P103/SCS73_0/AN15/PPG11_0
P037/A09/OCU6_1/TOT6_ 0/ZIN0_ 0 22 87 P102/SIN7_0/AN14/PPG10_0/INT10_0
P040/A10/P P G23_1/TOT7_0/AIN1_0/SIN0_ 1 23 86 P101/SOT7_0/SDA7/AN13/PPG9_0
P041/A11/SIN9_ 0/ICU9_ 1/BIN1_ 0/INT12_0 24 85 P100/SCK7_0/SCL7/AN12/PP G8_0
P042/A12/SOT9_0/AN47/ICU8_ 1/TRG0_1/ZIN1_ 0 25 84 AVCC0
P043/A13/ICU7_1/TRG1_1 26 83 AVRH0
P044/A14/SCS9_0/ICU6_1/TRG2_1 27 82 AVSS0/AVRL0
P045/A15/SCK9_ 0/AN46/ICU5_ 1/TRG3_1/TOT1_ 2 28 81 P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
P046/A16/ICU4_1/TRG4_1 29 80 P 096/RX0(128)/SOT11_0/SDA11/AN10/INT0_ 0
P047/A17/AN45/TRG8_0/TIN3_2/SOT0_ 1 30 79 P095/TX0(128)/SCS11_0/AN9
P050/A18/TRG5_1/PP G33_0 31 78 P094/AN8/ICU4_0/TOT3_1
P051/A19/TRG9_0 32 77 P 093/TX0_1/SIN11_0/AN7/ICU4_ 2/P PG16_1/ICU3_0/TOT2_ 1
P052/A20/P P G34_0/INT14_0 33 76 P 092/AN6/P P G40_1/ICU2_0/TOT0_1
P053/A21/AN44/PP G35_0/INT14_1/SCK0_1 34 75 P091/AN5/P PG41_1/ICU1_0/TIN3_ 1
P054/SYSCLK/PP G36_0 35 74 P090/AN4/ICU0_0/TIN2_1
VCC 36 73 VSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
AVCC1
P057/RDY/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P142/SCK10_0/SCL10/PPG38_0/TIN7_1
P143/SOT10_0/SDA10/PPG39_0/TOT4_1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P070/ICU0_2
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P074/SCK4_0/SCL4
P075/SIN3_0/INT4_0
P076/SOT3_0/SDA3
P077/SCK3_0/SCL3
P152/SCS53_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P080/SCS52_0/PPG0_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P083/SCS50_0/AN2/PPG3_0
P084/SCS51_0/AN3/PPG4_0
P085/PPG5_0
P086/DAO1/PPG6_0
P087/DAO0/PPG7_0/INT8_0
VCC
●
TOP VIEW
MB91F522K,
MB91F523K,
MB91F524K,
MB91F525K,
MB91F526K
LQFP-144
* In a single clock product, pin 121 and pin 122 are the general-purpose ports.
LQS144/LQN144
Document Number: 002-04662 Rev. *D Page 17 of 289
MB91520 Series
MB91F52xL
MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L
(TOP VIEW)
VCC
P014/D28/TIOB1_0
P013/D27/TIOA1_0
P167/PPG35_1
P012/D26/TIOB0_0
P011/WOT/D25/SOT2_1/TIOA0_0/INT3_1
P010/D24
P166/PPG34_1
P007/D23
P006/D22/SCS2_0/ADTG1_1/INT2_1
P165/PPG33_1
P005/D21/SCK2_0/ADTG0_1/INT7_1
P164/PPG32_1
P004/D20/SOT2_0
P003/D19/SIN2_0/TIOB1_1/INT3_0
P002/D18/SCK1_0/TIOB0_1
P001/D17/SOT1_0/TIOA1_1
P000/D16/SIN1_0/TIOA0_1/INT2_0
C
VSS
P144/SCK1_1
P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
P133/TX2(64)
P132/SCS1_0/ADTG1_0
P131/ADTG0_0
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P163/TRG6_2
P162/TRG5_2
P130/SCK0_0
P127/SOT0_0
P126/SIN0_0/INT6_0
P125/OCU11_0
P124/OCU10_0
P161/PPG31_1
P160/PPG30_1
DEBUGIF
VCC
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VSS 1132 VSS
P015/D29/TRG0_0 2131 P 123/OCU9_ 0
P016/D30/TRG1_0 3130 P 197/PPG29_1
P170/PP G36_1 4129 P122/SIN6_ 0/AN 31/OCU8_0/INT9_1
P017/D31/TRG2_0 5128 P 121/OCU7_ 0/PPG23_ 0
P171/PP G37_1 6127 P120/AN30/O CU6_0/P PG22_0/INT9_ 0
P020/ASX/SIN3_1/TRG3_0/TIN0_2/RTO5_1 7126 P 196/FRCK3_1/PPG28_1
P021/CS0X/SOT3_1/TRG6_1/TRG4_0 8125 P117/SCS60_0/AN29/PPG21_0/RTO5_0
P022/CS1X/SCK 3_1/TRG7_1/TRG5_0 9124 P116/SCK6_ 0/SCL6/AN 28/PPG20_ 0/RTO4_0
P023/RDX/SCS3_1/PP G32_0/TIN0_0 10 123 P115/RX1_1/SOT6_ 0/SDA6/AN27/P PG19_0/RTO3_0/INT1_1
P024/WR0X/SIN4_1/PPG24_0/TIN1_0/RTO4_ 1/INT15_0 11 122 P114/SCS61_0/AN26/PP G18_0/RTO2_0
P025/WR1X/SOT4_1/PP G25_0/TIN2_0 12 121 P 195/FRCK4_ 1/PPG27_ 1
P172/PP G38_1 13 120 P194/FRCK5_1/PP G26_1
P026/A00/SCK4_1/PPG26_0/TIN 3_0 14 119 P113/AN25/PPG17_0/RTO 1_0
P027/A01/SCS40_1/PP G27_0/TOT0_ 0/RTO3_1 15 118 P112/AN24/PPG16_0/RTO 0_0
P173/PP G39_1 16 117 P111/RX1(64)/SCS62_0/AN23/INT1_0
P030/A02/SCS41_1/PP G28_0/TOT1_ 0 17 116 P 110/TX1(64)/SCS63_0/AN22
P031/A03/SCS42_1/PP G29_0/TOT2_ 0 18 115 NMIX
P032/A04/SCS43_1/PP G30_0/TOT3_ 0/RTO2_1 19 114 P155/AN21
P033/A05/P PG31_0/ICU3_ 3/TIN4_0/RTO1_1/SCK3_2 20 113 P154/AN 20
P034/A06/OCU11_ 1/ICU2_ 3/TIN5_0/RTO0_1/SOT3_2 21 112 P193/PPG25_1
P150/SOT8_ 0/SDA8/OCU10_ 1/TRG6_0/ICU1_ 3/TIN6_0 22 111 P107/AN19/PP G15_0
P151/SCK8_ 0/SCL8/OCU9_1/TRG7_0/ICU0_3/TIN 7_0/ZIN0_2/DTTI_1 23 110 P 106/SCS70_0/AN18/P PG14_0
P035/A07/SIN8_0/OCU8_1/TOT4_0/A IN0_0/INT11_ 0 24 109 P105/SCS71_ 0/AN17/P PG13_0
P036/A08/SCS8_0/OCU7_1/TOT5_ 0/BIN0_0 25 108 P104/SCS72_ 0/AN16/P PG12_0
P037/A09/OCU6_ 1/TO T6_0/ZIN0_0 26 107 P 103/SCS73_0/AN15/PP G11_0
P174/TRG8_1 27 106 P102/SIN7_ 0/AN14/P PG10_0/INT10_0
P175/TRG9_1 28 105 P101/SOT7_ 0/SDA7/AN13/P PG9_0
P040/A10/P PG23_1/TOT7_0/AIN1_0/SIN0_1 29 104 P100/SCK7_0/SCL7/AN12/P PG8_0
P041/A11/SIN9_0/ICU9_1/BIN1_0/INT12_ 0 30 103 AVCC0
P042/A12/SOT9_0/AN47/ICU 8_1/TRG0_1/ZIN1_0 31 102 AVRH0
P043/A13/ICU7_ 1/TRG1_1 32 101 AVSS0/AVRL0
P044/A14/SCS9_0/ICU6_1/TRG2_1 33 100 P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_ 1
P045/A15/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2 34 99 P096/RX0(128)/SOT11_ 0/SDA11/AN10/INT0_0
P046/A16/ICU4_ 1/TRG4_1 35 98 P095/TX0(128)/SCS11_0/AN9
P176/TRG10_0 36 97 P094/AN 8/ICU4_0/TOT3_1
P047/A17/AN45/TRG8_0/TIN3_ 2/SOT0_1 37 96 P093/TX0_1/SIN11_ 0/AN7/ICU4_ 2/P PG16_1/ICU3_0/TOT2_1
P177/TRG11_0 38 95 P192/PPG24_ 1/TOT1_1
P050/A18/TRG5_1/P PG33_0 39 94 P092/AN6/PP G40_1/ICU2_0/TOT0_ 1
P051/A19/TRG9_0 40 93 P091/AN5/PP G41_1/ICU1_0/TIN3_ 1
P052/A20/P PG34_0/INT14_ 0 41 92 P090/AN4/ICU0_ 0/TIN2_1
P053/A21/AN44/P PG35_0/INT14_ 1/SCK 0_1 42 91 P191/TIN1_1
P054/SYSCLK/P PG36_0 43 90 P190/TIN0_1
VCC 44 89 VSS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
P055/CS2X/SIN10_0/AN43/PPG37_0/TIN4_1
P180/PPG40_0
P181/PPG41_0
P056/CS3X/ICU9_0/PPG0_1/ICU0_1/TIN5_1/DTTI_2
AVCC1
P057/RDY/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P142/SCK10_0/SCL10/PPG38_0/TIN7_1
P143/SOT10_0/SDA10/PPG39_0/TOT4_1
P182/PPG42_0
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P183/PPG43_0
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P184/PPG44_0
P185/PPG45_0
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P070/ICU0_2
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/SOT4_0/SDA4/AN33/ICU3_2
P186/PPG46_0
P187/PPG47_0
P074/SCK4_0/SCL4
P075/SIN3_0/INT4_0
P076/SOT3_0/SDA3
P077/SCK3_0/SCL3
P152/SCS53_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P080/SCS52_0/PPG0_0
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P083/SCS50_0/AN2/PPG3_0
P084/SCS51_0/AN3/PPG4_0
P085/PPG5_0
P086/DAO1/PPG6_0
P087/DAO0/PPG7_0/INT8_0
VCC
●
TOP VIEW
MB91F522L,
MB91F523L,
MB91F524L,
MB91F525L,
MB91F526L
LQFP-176
* In a single clock product, pin 149 and pin 150 are the general-purpose ports.
LQP176
Document Number: 002-04662 Rev. *D Page 18 of 289
MB91520 Series
3. Pin Description
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - - - 2 2
P015
-
A
General-purpose I/O port
D29
-
External bus data bit29 I/O (0)
TRG0_0
-
PPG trigger 0 input (0)
- - - - 3 3
P016
-
A
General-purpose I/O port
D30
-
External bus data bit30 I/O (0)
TRG1_0
-
PPG trigger 1 input (0)
- - - - - 4
P170
-
A
General-purpose I/O port
PPG36_1
-
PPG ch.36 output (1)
- - - - 4 5
P017
-
A
General-purpose I/O port
D31
-
External bus data bit31 I/O (0)
TRG2_0
-
PPG trigger 2 input (0)
- - - - - 6
P171
-
A
General-purpose I/O port
PPG37_1
-
PPG ch.37 output (1)
2 *1 2 *1 2 *1 2 *1 5 7
P020
-
F
General-purpose I/O port
ASX
*2, *3,
*4, *5
- External bus/Address strobe output
SIN3_1 - Multi-function serial ch.3 serial data input
(1)
TRG3_0
-
PPG trigger 3 input (0)
TIN0_2
-
Reload timer ch.0 event input (2)
RTO5_1
-
Waveform generator ch.5 output pin (1)
- - - 3 *1 6 8
P021
-
A
General-purpose I/O port
CS0X
*5
-
External bus chip select 0 output
SOT3_1 - Multi-function serial ch.3 serial data output
(1)
TRG6_1
-
PPG trigger 6 input (1)
TRG4_0
-
PPG trigger 4 input (0)
- - - 4 *1 7 9
P022
-
F
General-purpose I/O port
CS1X *5
-
External bus chip select 1 output
SCK3_1
-
Multi-function serial ch.3 clock I/O (1)
TRG7_1
-
PPG trigger 7 input (1)
TRG5_0
-
PPG trigger 5 input (0)
- - - 5 *1 8 10
P023
-
A
General-purpose I/O port
RDX
*5
-
External bus/Read strobe output
SCS3_1
-
Serial chip select 3 output (1)
PPG32_0
-
PPG ch.32 output (0)
TIN0_0
-
Reload timer ch.0 event input (0)
Document Number: 002-04662 Rev. *D Page 19 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
3 *1 3 *1 3 *1 6 *1 9 11
P024
-
F
General-purpose I/O port
WR0X
*2,
*3, *4, *5
- External bus/Write strobe 0 output
SIN4_1 - Multi-function serial ch.4 serial data input
(1)
PPG24_0
-
PPG ch.24 output (0)
TIN1_0
-
Reload timer ch.1 event input (0)
RTO4_1
-
Waveform generator ch.4 output pin (1)
INT15_0
-
INT15 External interrupt input (0)
- - 4 *1 7 *1 10 12
P025
-
A
General-purpose I/O port
WR1X
*4,
*5
- External bus/Write strobe 1 output
SOT4_1 - Multi-function serial ch.4 serial data output
(1)
PPG25_0
-
PPG ch.25 output (0)
TIN2_0
-
Reload timer ch.2 event input (0)
- - - - - 13
P172
-
A
General-purpose I/O port
PPG38_1
-
PPG ch.38 output (1)
- 4 *1 5 *1 8 *1 11 14
P026
-
F
General-purpose I/O port
A00
*3, *4,
*5
- External bus/Address bit0 output (0)
SCK4_1
-
Multi-function serial ch.4 clock I/O (1)
PPG26_0
-
PPG ch.26 output (0)
TIN3_0
-
Reload timer ch.3 event input (0)
4 *1 5 *1 6 *1 9 *1 12 15
P027
-
A
General-purpose I/O port
A01
*2, *3,
*4, *5
- External bus/Address bit1 output (0)
SCS40_1
-
Serial chip select 40 I/O (1)
PPG27_0
-
PPG ch.27 output (0)
TOT0_0
-
Reload timer ch.0 output (0)
RTO3_1
-
Waveform generator ch.3 output pin (1)
- - - - - 16
P173
-
A
General-purpose I/O port
PPG39_1
-
PPG ch.39 output (1)
- - 7 *1 10 *1 13 17
P030
-
A
General-purpose I/O port
A02 *4, *5
-
External bus/Address bit2 output (0)
SCS41_1
-
Serial chip select 41 output (1)
PPG28_0
-
PPG ch.28 output (0)
TOT1_0
-
Reload timer ch.1 output (0)
- 6 *1 8 *1 11 *1 14 18
P031
-
A
General-purpose I/O port
A03
*3, *4,
*5
- External bus/Address bit3 output (0)
SCS42_1
-
Serial chip select 42 output (1)
PPG29_0
-
PPG ch.29 output (0)
TOT2_0
*3
- Reload timer ch.2 output (0)
Document Number: 002-04662 Rev. *D Page 20 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
5 *1 7 *1 9 *1 12 *1 15 19
P032
-
A
General-purpose I/O port
A04
*2, *3,
*4, *5
- External bus/Address bit4 output (0)
SCS43_1
-
Serial chip select 43 output (1)
PPG30_0
-
PPG ch.30 output (0)
TOT3_0
-
Reload timer ch.3 output (0)
RTO2_1
-
Waveform generator ch.2 output pin (1)
6 *1 8 *1 10 *1 13 *1 16 20
P033
-
A
General-purpose I/O port
A05
*2, *3,
*4, *5
- External bus/Address bit5 output (0)
PPG31_0
-
PPG ch.31 output (0)
ICU3_3
-
Input capture ch.3 input (3)
TIN4_0
-
Reload timer ch.4 event input (0)
RTO1_1
-
Waveform generator ch.1 output pin (1)
SCK3_2
-
Multi-function serial ch.3 clock I/O (2)
7 *1 9 *1 11 *1 14 *1 17 21
P034
-
A
General-purpose I/O port
A06
*2, *3,
*4, *5
- External bus/Address bit6 output (0)
OCU11_1
-
Output compare ch.11 output (1)
ICU2_3
-
Input capture ch.2 input (3)
TIN5_0
-
Reload timer ch.5 event input (0)
RTO0_1
-
Waveform generator ch.0 output pin (1)
SOT3_2 - Multi-function serial ch.3 serial data output
(2)
- - 12 15 18 22
P150
-
F
General-purpose I/O port
SOT8_0/
SDA8
- Multi-function serial ch.8 serial data output
(0)/ I
2
C bus serial data I/O
OCU10_1
-
Output compare ch.10 output (1)
TRG6_0
-
PPG trigger 6 input (0)
ICU1_3
-
Input capture ch.1 input (3)
TIN6_0
-
Reload timer ch.6 event input (0)
8 *1 10
*1 13 16 19 23
P151
-
F
General-purpose I/O port
SCK8_0/
SCL8
*2, *3
- Multi-function serial ch.8 clock I/O (0)/
I
2
C bus serial clock I/O
OCU9_1
-
Output compare ch.9 output (1)
TRG7_0
-
PPG trigger 7 input (0)
ICU0_3
-
Input capture ch.0 input (3)
TIN7_0
-
Reload timer ch.7 event input (0)
ZIN0_2
-
U/D counter ch.0 ZIN input (2)
DTTI_1 - Waveform generator ch.1 input pin (1)
Document Number: 002-04662 Rev. *D Page 21 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
9 *1 11
*1 14 *1 17 *1 20 24
P035
-
I
General-purpose I/O port
A07 *2, *3,
*4, *5
- External bus/Address bit7 output
SIN8_0
*2,
*3
- Multi-function serial ch.8 serial data input
(0)
OCU8_1
-
Output compare ch.8 output (1)
TOT4_0
-
Reload timer ch.4 output (0)
AIN0_0
-
U/D counter ch.0 AIN input (0)
INT11_0
-
INT11 External interrupt input (0)
10
*1
12
*1 15 *1 18 *1 21 25
P036
-
A
General-purpose I/O port
A08
*2, *3,
*4, *5
- External bus/Address bit8 output (0)
SCS8_0
*2, *3
- Serial chip select 8 I/O (0)
OCU7_1
-
Output compare ch.7 output (1)
TOT5_0
-
Reload timer ch.5 output (0)
BIN0_0
-
U/D counter ch.0 BIN input (0)
- - 16 *1 19 *1 22 26
P037
-
A
General-purpose I/O port
A09 *4, *5
-
External bus/Address bit9 output (0)
OCU6_1
-
Output compare ch.6 output (1)
TOT6_0
-
Reload timer ch.6 output (0)
ZIN0_0
-
U/D counter ch.0 ZIN input (0)
- - - - - 27
P174
-
A
General-purpose I/O port
TRG8_1 - PPG trigger 8 input (1)
- - - - - 28
P175
-
A
General-purpose I/O port
TRG9_1
-
PPG trigger 9 input (1)
11
*1
13
*1 17 *1 20 *1 23 29
P040
-
A
General-purpose I/O port
A10
*2, *3,
*4, *5
- External bus/Address bit10 output (0)
PPG23_1
-
PPG ch.23 output (1)
TOT7_0
-
Reload timer ch.7 output (0)
AIN1_0
-
U/D counter ch.1 AIN input (0)
SIN0_1 - Multi-function serial ch.0 serial data input
(1)
12
*1
14
*1 18 *1 21 *1 24 30
P041
-
I
General-purpose I/O port
A11
*2, *3,
*4, *5
- External bus/Address bit11 output (0)
SIN9_0 - Multi-function serial ch.9 serial data input
(0)
ICU9_1
-
Input capture ch.9 input (1)
BIN1_0
-
U/D counter ch.1 BIN input (0)
INT12_0
-
INT12 External interrupt input (0)
Document Number: 002-04662 Rev. *D Page 22 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
13
*1
15
*1 19 *1 22 *1 25 31
P042
-
B
General-purpose I/O port
A12
*2, *3,
*4, *5
- External bus/Address bit12 output
SOT9_0 - Multi-function serial ch.9 serial data output
(0)
AN47
-
ADC analog 47 input
ICU8_1
-
Input capture ch.8 input (1)
TRG0_1
-
PPG trigger 0 input (1)
ZIN1_0
-
U/D counter ch.1 ZIN input (0)
- - 20 *1 23 *1 26 32
P043
-
A
General-purpose I/O port
A13 *4, *5
-
External bus/Address bit13 output (0)
ICU7_1
-
Input capture ch.7 input (1)
TRG1_1
-
PPG trigger 1 input (1)
- 16
*1 21 *1 24 *1 27 33
P044
-
A
General-purpose I/O port
A14
*3, *4,
*5
- External bus/Address bit14 output (0)
SCS9_0
-
Serial chip select 9 I/O (0)
ICU6_1
-
Input capture ch.6 input (1)
TRG2_1
-
PPG trigger 2 input (1)
14
*1
17
*1 22 *1 25 *1 28 34
P045
-
G
General-purpose I/O port
A15
*2, *3,
*4, *5
- External bus/Address bit15 output (0)
SCK9_0
-
Multi-function serial ch.9 clock I/O (0)
AN46
-
ADC analog 46 input
ICU5_1
-
Input capture ch.5 input (1)
TRG3_1
-
PPG trigger 3 input (1)
TOT1_2
-
Reload timer ch.1 output (2)
- - - 26 *1 29 35
P046
-
A
General-purpose I/O port
A16 *5
-
External bus/Address bit16 output (0)
ICU4_1
-
Input capture ch.4 input (1)
TRG4_1
-
PPG trigger 4 input (1)
- - - - - 36
P176
-
A
General-purpose I/O port
TRG10_0
-
PPG trigger 10 input (0)
15
*1
18
*1 23 *1 27 *1 30 37
P047
-
B
General-purpose I/O port
A17
*2, *3,
*4, *5
- External bus/Address bit17 output (0)
AN45
-
ADC analog 45 input
TRG8_0
-
PPG trigger 8 input (0)
TIN3_2
-
Reload timer ch.3 event input (2)
SOT0_1 - Multi-function serial ch.0 serial data output
(1)
- - - - - 38
P177
-
A
General-purpose I/O port
TRG11_0
-
PPG trigger 11 input (0)
Document Number: 002-04662 Rev. *D Page 23 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - - 28 *1 31 39
P050
-
A
General-purpose I/O port
A18 *5
-
External bus/Address bit18 output
TRG5_1
-
PPG trigger 5 input (1)
PPG33_0
-
PPG ch.33 output (0)
- - - - 32 40
P051
-
A
General-purpose I/O port
A19
-
External bus/Address bit19 output
TRG9_0
-
PPG trigger 9 input (0)
- - - - 33 41
P052
-
A
General-purpose I/O port
A20
-
External bus/Address bit20 output
PPG34_0
-
PPG ch.34 output (0)
INT14_0
-
INT14 External interrupt input (0)
16
*1
19
*1 24 *1 29 *1 34 42
P053
-
B
General-purpose I/O port
A21
*2, *3,
*4, *5
- External bus/Address bit21 output
AN44
-
ADC analog 44 input
PPG35_0
-
PPG ch.35 output (0)
INT14_1
-
INT14 External interrupt input (1)
SCK0_1
-
Multi-function serial ch.0 clock I/O (1)
- - - - 35 43
P054
-
A
General-purpose I/O port
SYSCLK
-
External bus/System clock output
PPG36_0
-
PPG ch.36 output (0)
17
*1
22
*1 27 *1 32 *1 38 46
P055
-
G
General-purpose I/O port
CS2X
*2,
*3, *4, *5
- External bus chip select 2 output
SIN10_0 - Multi-function serial ch.10 serial data input
(0)
AN43
-
ADC analog 43 input
PPG37_0
-
PPG ch.37 output (0)
TIN4_1
-
Reload timer ch.4 event input (1)
- - - - - 47
P180
-
A
General-purpose I/O port
PPG40_0
-
PPG ch.40 output (0)
- - - - - 48
P181
-
A
General-purpose I/O port
PPG41_0
-
PPG ch.41 output (0)
- - - 33 *1 39 49
P056
-
A
General-purpose I/O port
CS3X *5
-
External bus chip select 3 output
ICU9_0
-
Input capture ch.9 input (0)
PPG0_1
-
PPG ch.0 output (1)
ICU0_1
-
Input capture ch.0 input (1)
TIN5_1
-
Reload timer ch.5 event input (1)
DTTI_2
-
Waveform generator ch.0-ch.5 input pin (2)
Document Number: 002-04662 Rev. *D Page 24 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
19
*1
24
*1 29 *1 35 *1 41 51
P057
-
G
General-purpose I/O port
RDY
*2, *3,
*4, *5
- External bus/Ready input (0)
SCK10_1
-
Multi-function serial ch.10 clock I/O (1)
AN42
-
ADC analog 42 input
ICU8_0
-
Input capture ch.8 input (0)
TRG0_2
-
PPG trigger 0 input (2)
PPG1_1
-
PPG ch.1 output (1)
ICU1_1
-
Input capture ch.1 input (1)
TIN6_1
-
Reload timer ch.6 event input (1)
- - - - 44 54
P142
-
F
General-purpose I/O port
SCK10_0
/
SCL10
- Multi-function serial ch.10 clock I/O (0)/
I2C bus serial clock I/O
PPG38_0
-
PPG ch.38 output (0)
TIN7_1
-
Reload timer ch.7 event input (1)
- - - - 45 55
P143
-
F
General-purpose I/O port
SOT10_0
/SDA10
- Multi-function serial ch.10 serial data output
(0)/ I
2
C bus serial data I/O
PPG39_0
-
PPG ch.39 output (0)
TOT4_1
-
Reload timer ch.4 output (1)
- - - - - 56
P182
-
A
General-purpose I/O port
PPG42_0
-
PPG ch.42 output (0)
- - 32 38 46 57
P060
-
A
General-purpose I/O port
SCS10_0
-
Serial chip select 10 I/O (0)
PPG2_1
-
PPG ch.2 output (1)
ICU2_1
-
Input capture ch.2 input (1)
TOT5_1
-
Reload timer ch.5 output (1)
INT13_0
-
INT13 External interrupt input (0)
22 27 33 39 47 58
P061
-
B
General-purpose I/O port
SOT10_1 - Multi-function serial ch.10
serial data output (1)
AN41
-
ADC analog 41 input
ICU6_0
-
Input capture ch.6 input (0)
PPG3_1
-
PPG ch.3 output (1)
ICU3_1
-
Input capture ch.3 input (1)
TOT6_1
-
Reload timer ch.6 output (1)
INT13_1
-
INT13 External interrupt input (1)
Document Number: 002-04662 Rev. *D Page 25 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
23 28 34 40 48 59
P062
-
B
General-purpose I/O port
SCS10_1
-
Serial chip select 10 I/O (1)
SCS40_0
-
Serial chip select 40 I/O (0)
AN40
-
ADC analog 40 input
PPG4_1
-
PPG ch.4 output (1)
FRCK0_0
-
Free-run timer 0 clock input (0)
TOT7_1
-
Reload timer ch.7 output (1)
ZIN1_1
-
U/D counter ch.1 ZIN input (1)
- 29 35 41 49 60
P063
-
B
General-purpose I/O port
SCS41_0
-
Serial chip select 41 output (0)
AN39
-
ADC analog 39 input
PPG5_1
-
PPG ch.5 output (1)
FRCK1_0
-
Free-run timer 1 clock input (0)
BIN1_1
-
U/D counter ch.1 BIN input (1)
- - - - - 61
P183
-
A
General-purpose I/O port
PPG43_0
-
PPG ch.43 output (0)
24 30 36 42 50 62
P064
-
B
General-purpose I/O port
SCS42_0
-
Serial chip select 42 output (0)
AN38
-
ADC analog 38 input
FRCK2_0
-
Free-run timer 2 clock input (0)
AIN1_1
-
U/D counter ch.1 AIN input (1)
PPG43_1 - PPG ch.43 output (1)
- - 37 43 51 63
P065
-
A
General-purpose I/O port
SCS43_0
-
Serial chip select 43 output (0)
FRCK3_0
-
Free-run timer 3 clock input (0)
ZIN0_1
-
U/D counter ch.0 ZIN input (1)
PPG44_1
-
PPG ch.44 output (1)
- - - - - 64
P184
-
A
General-purpose I/O port
PPG44_0
-
PPG ch.44 output (0)
- - - - - 65
P185
-
A
General-purpose I/O port
PPG45_0
-
PPG ch.45 output (0)
25 31 38 44 52 66
P066
-
B
General-purpose I/O port
SOT4_2 - Multi-function serial ch.4
serial data output (2)
SCS3_0
-
Serial chip select 3 I/O (0)
AN37
-
ADC analog 37 input
FRCK4_0
-
Free-run timer 4 clock input (0)
BIN0_1
-
U/D counter ch.0 BIN input (1)
- 32 39 45 53 67
P067
-
B
General-purpose I/O port
AN36
-
ADC analog 36 input
FRCK5_0
-
Free-run timer 5 clock input (0)
AIN0_1
-
U/D counter ch.0 AIN input (1)
Document Number: 002-04662 Rev. *D Page 26 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - 40 46 54 68
P070
-
A
General-purpose I/O port
ICU0_2
-
Input capture ch.0 input (2)
26 33 41 47 55 69
P071
-
G
General-purpose I/O port
SCK4_2 - Multi-function serial ch.4
clock I/O (2)
AN35
-
ADC analog 35 input
ICU1_2
-
Input capture ch.1 input (2)
MONCLK - Clock monitor output pin
27 34 42 48 56 70
P072
-
G
General-purpose I/O port
SIN4_0 - Multi-function serial ch.4 serial data input
(0)
AN34
-
ADC analog 34 input
ICU2_2
-
Input capture ch.2 input (2)
INT5_0
-
INT5 External interrupt input (0)
- 35
*3 43 *4 49 57 71
P073
-
D
General-purpose I/O port
SOT4_0/
SDA4
*3, *4
- Multi-function serial ch.4 serial data output
(0)/I
2
C bus serial data I/O
AN33
-
ADC analog 33 input
ICU3_2
-
Input capture ch.3 input (2)
- - - - - 72
P186
-
A
General-purpose I/O port
PPG46_0
-
PPG ch.46 output (0)
- - - - - 73
P187
-
A
General-purpose I/O port
PPG47_0
-
PPG ch.47 output (0)
- - - 50 58 74
P074
-
E
General-purpose I/O port
SCK4_0/
SCL4
- Multi-function serial ch.4 clock I/O (0)/
I
2
C bus serial clock I/O
- - - 51 59 75
P075
-
F
General-purpose I/O port
SIN3_0 - Multi-function serial ch.3 serial data input
(0)
INT4_0
-
INT4 External interrupt input (0)
- - - 52 60 76
P076
-
E
General-purpose I/O port
SOT3_0/
SDA3
- Multi-function serial ch.3 serial data output
(0)/I
2
C bus serial data I/O
- - - 53 61 77
P077
-
E
General-purpose I/O port
SCK3_0/
SCL3
- Multi-function serial ch.3 clock I/O (0)/
I
2
C bus serial clock I/O
- - 44 54 62 78
P152
-
A
General-purpose I/O port
SCS53_0
-
Serial chip select 53 output (0)
28 36 45 55 63 79
P153
-
G
General-purpose I/O port
SCK5_0/
SCL5
- Multi-function serial ch.5 clock I/O (0)/
I
2
C bus serial clock I/O
AN32
-
ADC analog 32 input
FRCK1_1
-
Free-run timer 1 clock input (1)
INT4_1
-
INT4 External interrupt input (1)
Document Number: 002-04662 Rev. *D Page 27 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - - - 64 80
P080
-
A
General-purpose I/O port
SCS52_0
-
Serial chip select 52 output (0)
PPG0_0
-
PPG ch.0 output (0)
29 37 46 56 65 81
P081
-
G
General-purpose I/O port
SOT5_0/
SDA5
- Multi-function serial ch.5 serial data output
(0)/I
2
C bus serial data I/O
AN0
-
ADC analog 0 input
PPG1_0 - PPG ch.1 output (0)
30 38 47 57 66 82
P082
-
G
General-purpose I/O port
SIN5_0 - Multi-function serial ch.5 serial data input
(0)
AN1
-
ADC analog 1 input
PPG2_0
-
PPG ch.2 output (0)
- - - - 67 83
P083
-
B
General-purpose I/O port
SCS50_0
-
Serial chip select 50 I/O (0)
AN2
-
ADC analog 2 input
PPG3_0
-
PPG ch.3 output (0)
- - - - 68 84
P084
-
B
General-purpose I/O port
SCS51_0
-
Serial chip select 51 output (0)
AN3
-
ADC analog 3 input
PPG4_0
-
PPG ch.4 output (0)
- - - - 69 85
P085
-
A
General-purpose I/O port
PPG5_0
-
PPG ch.5 output (0)
- - 48 58 70 86
P086
-
C
General-purpose I/O port
DAO1
-
DAC analog 1 output
PPG6_0
-
PPG ch.6 output (0)
31 39 49 59 71 87
P087
-
C
General-purpose I/O port
DAO0
-
DAC analog 0 output
PPG7_0
-
PPG ch.7 output (0)
INT8_0 - INT8 External interrupt input (0)
- - - - - 90
P190
-
A
General-purpose I/O port
TIN0_1
-
Reload timer ch.0 event input (1)
- - - - - 91
P191
-
A
General-purpose I/O port
TIN1_1
-
Reload timer ch.1 event input (1)
- - - - 74 92
P090
-
B
General-purpose I/O port
AN4
-
ADC analog 4 input
ICU0_0
-
Input capture ch.0 input (0)
TIN2_1
-
Reload timer ch.2 event input (1)
- - - - 75 93
P091
-
B
General-purpose I/O port
AN5
-
ADC analog 5 input
PPG41_1
-
PPG ch.41 output (1)
ICU1_0
-
Input capture ch.1 input (0)
TIN3_1
-
Reload timer ch.3 event input (1)
Document Number: 002-04662 Rev. *D Page 28 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - - - 76 94
P092
-
B
General-purpose I/O port
AN6
-
ADC analog 6 input
PPG40_1
-
PPG ch.40 output (1)
ICU2_0
-
Input capture ch.2 input (0)
TOT0_1
-
Reload timer ch.0 output (1)
- - - - - 95
P192
-
A
General-purpose I/O port
PPG24_1
-
PPG ch.24 output (1)
TOT1_1
-
Reload timer ch.1 output (1)
34
*1
42
*1 52 62 77 96
P093
-
J
General-purpose I/O port
TX0_1
-
CAN transmission data 0 output (1)
SIN11_0 - Multi-function serial ch.11 serial data input
(0)
AN7
-
ADC analog 7 input
ICU4_2
-
Input capture ch.4 input (2)
PPG16_1
-
PPG ch.16 output (1)
ICU3_0
-
Input capture ch.3 input (0)
TOT2_1
*2, *3
- Reload timer ch.2 output (1)
- - - - 78 97
P094
-
B
General-purpose I/O port
AN8
-
ADC analog 8 input
ICU4_0
-
Input capture ch.4 input (0)
TOT3_1
-
Reload timer ch.3 output (1)
- - 53 63 79 98
P095
-
B
General-purpose I/O port
TX0(128)
-
CAN transmission data 0 output
SCS11_0
-
Serial chip select 11 I/O (0)
AN9
-
ADC analog 9 input
35 43 54 64 80 99
P096
-
G
General-purpose I/O port
RX0(128)
-
CAN reception data 0 input
SOT11_0
/
SDA11
- Multi-function serial ch.11 serial data output
(0)/I2C bus serial data I/O
AN10
-
ADC analog 10 input
INT0_0
-
INT0 External interrupt input (0)
36 44 55 65 81 100
P097
-
G
General-purpose I/O port
SCK11_0
/
SCL11
- Multi-function serial ch.11 clock I/O (0)/
I2C bus serial clock I/O
AN11
-
ADC analog 11 input
ICU5_0
-
Input capture ch.5 input (0)
PPG17_1
-
PPG ch.17 output (1)
Document Number: 002-04662 Rev. *D Page 29 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- 48
*1 59 69 85 104
P100
-
G
General-purpose I/O port
SCK7_0/
SCL7
*3
- Multi-function serial ch.7 clock I/O (0)/
I
2
C bus serial clock I/O
AN12
-
ADC analog 12 input
PPG8_0
-
PPG ch.8 output (0)
- - 60 70 86 105
P101
-
G
General-purpose I/O port
SOT7_0/
SDA7
- Multi-function serial ch.7 serial data output
(0)/I
2
C bus serial data I/O
AN13
-
ADC analog 13 input
PPG9_0
-
PPG ch.9 output (0)
40
*1
49
*1 61 71 87 106
P102
-
G
General-purpose I/O port
SIN7_0
*2,
*3
- Multi-function serial ch.7 serial data input
(0)
AN14
-
ADC analog 14 input
PPG10_0
-
PPG ch.10 output (0)
INT10_0 - INT10 External interrupt input (0)
41
*1
50
*1 62 72 88 107
P103
-
H
General-purpose I/O port
SCS73_0
*2, *3
- Serial chip select 73 output (0)
AN15
-
ADC analog 15 input
PPG11_0
-
PPG ch.11 output (0)
42
*1
51
*1 63 73 89 108
P104
-
H
General-purpose I/O port
SCS72_0
*2, *3
- Serial chip select 72 output (0)
AN16
-
ADC analog 16 input
PPG12_0
-
PPG ch.12 output (0)
43
*1
52
*1 64 74 90 109
P105
-
H
General-purpose I/O port
SCS71_0
*2, *3
- Serial chip select 71 output (0)
AN17
-
ADC analog 17 input
PPG13_0
-
PPG ch.13 output (0)
- - 65 75 91 110
P106
-
H
General-purpose I/O port
SCS70_0
-
Serial chip select 70 I/O (0)
AN18
-
ADC analog 18 input
PPG14_0
-
PPG ch.14 output (0)
- 53 66 76 92 111
P107
-
B
General-purpose I/O port
AN19
-
ADC analog 19 input
PPG15_0
-
PPG ch.15 output (0)
- - - - - 112
P193
-
A
General-purpose I/O port
PPG25_1 - PPG ch.25 output (1)
- - - 77 93 113
P154
-
B
General-purpose I/O port
AN20
-
ADC analog 20 input
- - - 78 94 114
P155
-
B
General-purpose I/O port
AN21
-
ADC analog 21 input
Document Number: 002-04662 Rev. *D Page 30 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
44
54
67
79
95
115
NMIX
N
M
Non-masking interrupt input
45 55 68 80 96 116
P110
-
B
General-purpose I/O port
TX1(64)
-
CAN transmission data 1 output
SCS63_0
-
Serial chip select 63 output (0)
AN22
-
ADC analog 22 input
- - 69 81 97 117
P111
-
G
General-purpose I/O port
RX1(64)
-
CAN reception data 1 input
SCS62_0
-
Serial chip select 62 output (0)
AN23
-
ADC analog 23 input
INT1_0
-
INT1 External interrupt input (0)
- - - 82 98 118
P112
-
B
General-purpose I/O port
AN24
-
ADC analog 24 input
PPG16_0
-
PPG ch.16 output (0)
RTO0_0
-
Waveform generator ch. 0 output pin (0)
- - - 83 99 119
P113
-
B
General-purpose I/O port
AN25
-
ADC analog 25 input
PPG17_0
-
PPG ch.17 output (0)
RTO1_0
-
Waveform generator ch. 1 output pin (0)
- - - - - 120
P194
-
A
General-purpose I/O port
FRCK5_1
-
Free-run timer 5 clock input (1)
PPG26_1
-
PPG ch.26 output (1)
- - - - - 121
P195
-
A
General-purpose I/O port
FRCK4_1
-
Free-run timer 4 clock input (1)
PPG27_1
-
PPG ch.27 output (1)
- 56 70 84 100 122
P114
-
B
General-purpose I/O port
SCS61_0
-
Serial chip select 61 output (0)
AN26
-
ADC analog 26 input
PPG18_0
-
PPG ch.18 output (0)
RTO2_0
-
Waveform generator ch.2 output pin (0)
46 57 71 85 101 123
P115
-
G
General-purpose I/O port
RX1_1
-
CAN reception data 1 input (1)
SOT6_0/
SDA6
- Multi-function serial ch.6 serial data output
(0)/I
2
C bus serial data I/O
AN27
-
ADC analog 27 input
PPG19_0
-
PPG ch.19 output (0)
RTO3_0
-
Waveform generator ch.3 output pin (0)
INT1_1
-
INT1 External interrupt input (1)
47 58 72 86 102 124
P116
-
G
General-purpose I/O port
SCK6_0/
SCL6
- Multi-function serial ch.6 clock I/O (0)/
I
2
C bus serial clock I/O
AN28
-
ADC analog 28 input
PPG20_0
-
PPG ch.20 output (0)
RTO4_0
-
Waveform generator ch.4 output pin (0)
Document Number: 002-04662 Rev. *D Page 31 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - 73 87 103 125
P117
-
B
General-purpose I/O port
SCS60_0
-
Serial chip select 60 I/O (0)
AN29
-
ADC analog 29 input
PPG21_0
-
PPG ch.21 output (0)
RTO5_0
-
Waveform generator ch.5 output pin (0)
- - - - - 126
P196
-
A
General-purpose I/O port
FRCK3_1
-
Free-run timer 3 clock input (1)
PPG28_1
-
PPG ch.28 output (1)
- - - 88 104 127
P120
-
B
General-purpose I/O port
AN30
-
ADC analog 30 input
OCU6_0
-
Output compare ch.6 output (0)
PPG22_0
-
PPG ch.22 output (0)
INT9_0
-
INT9 External interrupt input (0)
- - - - 105 128
P121
-
A
General-purpose I/O port
OCU7_0
-
Output compare ch.7 output (0)
PPG23_0 - PPG ch.23 output (0)
48 59 74 89 106 129
P122
-
J
General-purpose I/O port
SIN6_0 - Multi-function serial ch.6 serial data input
(0)
AN31
-
ADC analog 31 input
OCU8_0
-
Output compare ch.8 output (0)
INT9_1
-
INT9 External interrupt input (1)
- - - - - 130
P197
-
A
General-purpose I/O port
PPG29_1
-
PPG ch.29 output (1)
- - - - 107 131
P123
-
A
General-purpose I/O port
OCU9_0
-
Output compare ch.9 output (0)
49
62
77
92
110
134
DEBUGIF
-
L
MDI I/O for debugger (OCD)
- - - - - 135
P160
-
A
General-purpose I/O port
PPG30_1
-
PPG ch.30 output (1)
- - - - - 136
P161
-
A
General-purpose I/O port
PPG31_1
-
PPG ch.31 output (1)
- - - - 111 137
P124
-
A
General-purpose I/O port
OCU10_0
-
Output compare ch.10 output (0)
- - - 93 112 138
P125
-
A
General-purpose I/O port
OCU11_0
-
Output compare ch.11 output (0)
50 63 78 94 113 139
P126
-
F
General-purpose I/O port
SIN0_0 - Multi-function serial ch.0 serial data input
(0)
INT6_0
-
INT6 External interrupt input (0)
- 64 79 95 114 140
P127
-
A
General-purpose I/O port
SOT0_0 - Multi-function serial ch.0 serial data output
(0)
Document Number: 002-04662 Rev. *D Page 32 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - 80 96 115 141
P130
-
F
General-purpose I/O port
SCK0_0
-
Multi-function serial ch.0 clock I/O (0)
- - - - - 142
P162
-
A
General-purpose I/O port
TRG5_2
-
PPG trigger 5 input (2)
- - - - - 143
P163
-
A
General-purpose I/O port
TRG6_2
-
PPG trigger 6 input (2)
51 65 81 97 116 144 MD0 - K Mode pin 0
52
66
82
98
117
145
MD1
-
K
Mode pin 1
53
67
83
99
118
146
X0
-
N
Main clock oscillation input
54
68
84
100
119
147
X1
-
N
Main clock oscillation output
56 70 86 102 121 149
P135
-
A
General-purpose I/O port
DTTI_0
-
Waveform generator ch.0-ch.5 input pin (0)
X1A - O Sub clock oscillation output
57 71 87 103 122 150
P136
-
A
General-purpose I/O port
X0A
-
O
Sub clock oscillation input
58
72
88
104
123
151
RSTX
N
M
External reset input
- - - - 124 152
P131
-
A
General-purpose I/O port
ADTG0_0
-
A/D converter external trigger input 0 (0)
- - - 105 125 153
P132
-
A
General-purpose I/O port
SCS1_0
-
Serial chip select 1 I/O (0)
ADTG1_0
-
A/D converter external trigger input 1 (0)
- - 89 106 126 154
P133
-
A
General-purpose I/O port
TX2(64)
-
CAN transmission data 2 output
- - 90 107 127 155
P134
-
F
General-purpose I/O port
RX2(64)
-
CAN reception data 2 input
SCS1_1
-
Serial chip select 1 I/O (1)
ICU7_0
-
Input capture ch.7 input (0)
INT7_0
-
INT7 External interrupt input (0)
- - 91 108 128 156
P144
-
F
General-purpose I/O port
SCK1_1
-
Multi-function serial ch.1 clock I/O (1)
- - 94 *1 111
*1 131 159
P000
-
F
General-purpose I/O port
D16
*4, *5
-
External bus data bit16 I/O (0)
SIN1_0 - Multi-function serial ch.1 serial data input
(0)
TIOA0_1
*4
- TIOA output of Base timer ch.0 (1)
INT2_0
-
INT2 External interrupt input (0)
- 75
*1 95 *1 112
*1 132 160
P001
-
A
General-purpose I/O port
D17
*3, *4,
*5
- External bus data bit17 I/O
SOT1_0
*3
- Multi-function serial ch.1 serial data output
(0)
TIOA1_1
-
TIOA I/O of Base timer ch.1 (1)
Document Number: 002-04662 Rev. *D Page 33 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
- - - 113
*1 133 161
P002
-
F
General-purpose I/O port
D18 *5
-
External bus data bit18 I/O
SCK1_0
-
Multi-function serial ch.1 clock I/O (0)
TIOB0_1
-
TIOB input of Base timer ch.0 (1)
- 76
*1 96 *1 114
*1 134 162
P003
-
F
General-purpose I/O port
D19
*3, *4,
*5
- External bus data bit19 I/O
SIN2_0 - Multi-function serial ch.2 serial data input
(0)
TIOB1_1
-
TIOB input of Base timer ch.1 (1)
INT3_0
-
INT3 External interrupt input (0)
- - - - 135 163
P004
-
A
General-purpose I/O port
D20
-
External bus data bit20 I/O (0)
SOT2_0 - Multi-function serial ch.2 serial data output
(0)
- - - - - 164
P164
-
A
General-purpose I/O port
PPG32_1
-
PPG ch.32 output (1)
61
*1
77
*1 97 *1 115
*1
136
*1
165
*1
P005
-
F
General-purpose I/O port
D21
*2, *3,
*4, *5
- External bus data bit21 I/O (0)
SCK2_0
*2
- Multi-function serial ch.2 clock I/O (0)
ADTG0_1
-
A/D converter external trigger input 0 (1)
INT7_1
-
INT7 External interrupt input (1)
RX2(64)
*4, *5, *6, *7
- CAN reception data 2 input
- - - - - 166
P165
-
A
General-purpose I/O port
PPG33_1
-
PPG ch.33 output (1)
62
*1
78
*1 98 *1 116
*1
137
*1
167
*1
P006
-
A
General-purpose I/O port
D22
*2, *3,
*4, *5
- External bus data bit22 I/O (0)
SCS2_0
*2
- Serial chip select 2 I/O (0)
ADTG1_1
-
A/D converter external trigger input 1 (1)
INT2_1
-
INT2 External interrupt input (1)
TX2(64)
*4, *5, *6, *7
- CAN transmission data 2 output
- - - 117
*1 138 168
P007
-
A
General-purpose I/O port
D23
*5
-
External bus data bit23 I/O
- - - - - 169
P166
-
A
General-purpose I/O port
PPG34_1
-
PPG ch.34 output (1)
- - - 118
*1 139 170
P010
-
A
General-purpose I/O port
D24 *5
-
External bus data bit24 I/O
Document Number: 002-04662 Rev. *D Page 34 of 289
MB91520 Series
Pin no. Pin
Name Polarity
I/O
circuit
types*8
Function*9
64
80
100
120
144
176
63
*1
79
*1 99 *1 119
*1 140 171
P011
-
A
General-purpose I/O port
WOT
-
RTC output signal
D25
*2, *3,
*4, *5
- External bus data bit25 I/O
SOT2_1
*2
- Multi-function serial ch.2 serial data output
(1)
TIOA0_0
*2, *3, *4
- TIOA output of Base timer ch.0 (0)
INT3_1
-
INT3 External interrupt input (1)
- - - - 141 172
P012
-
A
General-purpose I/O port
D26
-
External bus data bit26 I/O
TIOB0_0
-
TIOB input of Base timer ch.0 (0)
- - - - - 173
P167
-
A
General-purpose I/O port
PPG35_1
-
PPG ch.35 output (1)
- - - - 142 174
P013
-
A
General-purpose I/O port
D27
-
External bus data bit27 I/O
TIOA1_0
-
TIOA I/O of Base timer ch.1 (0)
- - - - 143 175
P014
-
A
General-purpose I/O port
D28
-
External bus data bit28 I/O
TIOB1_0
-
TIOB input of Base timer ch.1 (0)
18 23 28 34 40 50 AVCC1 - - Analog power supply for AD/DA convertor
unit1
39 47 58 68 84 103 AVCC0 - - Analog power supply for AD/DA convertor
unit0
20 25 30 36 42 52 AVRH1 - - Upper limit reference voltage for AD
convertor unit1
38 46 57 67 83 102 AVRH0 - - Upper limit reference voltage for AD
convertor unit0
21 26 31 37 43 53 AVSS1/
AVRL1 - -
GND for AD/DA convertor unit1
Lower limit reference voltage for AD
convertor unit1
37 45 56 66 82 101 AVSS0/
AVRL0 - -
GND for AD/DA convertor unit0
Lower limit reference voltage for AD
convertor unit0
60
74
93
110
130
158
C
-
-
External capacity connection output
-
20
25
30
36
44
VCC - - +5.0V power supply
32
40
50
60
72
88
-
61
76
91
109
133
64
80
100
120
144
176
1
1
1
1
1
1
VSS - - GND
-
21
26
31
37
45
33
41
51
61
73
89
-
60
75
90
108
132
55
69
85
101
120
148
59
73
92
109
129
157
Document Number: 002-04662 Rev. *D Page 35 of 289
MB91520 Series
*1: There is a restriction of pin functions. See "Pin Name" of this table.
*2: not supported in 64pin
*3: not supported in 80pin
*4: not supported in 100pin
*5: not supported in 120pin
*6: not supported in 144pin
*7: not supported in 176pin
*8: For the I/O circuit types, see "I/O CIRCUIT TYPE".
*9: For switching, see "I/O Port" in HARDWARE MANUAL.
Document Number: 002-04662 Rev. *D Page 36 of 289
MB91520 Series
4. I/O Circuit Type
Type
Circuit
Remarks
A
•General-purpose I/O port
•Output 4mA
•Pull-up resistor control 50kΩ
•Automotive input
B
•Analog input, General-purpose I/O port
•Output 4mA
•Pull-up resistor control 50kΩ
•Automotive input
C
•DAC output, General-purpose I/O port
•Output 4mA
•Pull-up resistor control 50kΩ
•Automotive input
Pull-up control
Digital output
Digital output
Standby control
Automotive input
DAC output
Pull-up control
Digital output
Digital output
Standby control
Automotive input
Analog input
Pull-up control
Digital output
Digital output
Standby control
Automotive input
Document Number: 002-04662 Rev. *D Page 37 of 289
MB91520 Series
Type
Circuit
Remarks
D
•I2C Analog input, General-purpose I/O port
•Output 3mA
•Pull-up resistor control 50kΩ
•I2C hysteresis input
E
•I2C,General-purpose I/O port
•Output 3mA
•Pull-up resistor control 50kΩ
•I2C hysteresis input
F
•General-purpose I/O port
•Output 4mA
•Pull-up resistor control 50kΩ
•CMOS hysteresis input
Pull-up control
Digital output
Digital output
Standby control
CMOS-hys input
Pull-up control
Digital output
Digital output
Standby control
I
2
C input
Pull-up control
Digital output
Digital output
Standby control
I
2
C input
Analog input
Document Number: 002-04662 Rev. *D Page 38 of 289
MB91520 Series
Type
Circuit
Remarks
G
•Analog input, General-purpose I/O port
•Output 4mA
•Pull-up resistor control 50kΩ
• CMOS hysteresis input
H
•Analog input, General-purpose I/O port
•Output 12mA
•Pull-up resistor control 50kΩ
•Automotive input
I
• General-purpose I/O port (5V tolerant)
• Output 4mA
• CMOS hysteresis input
Digital output
Digital output
Standby control
CMOS-hys input
Pull-up control
Digital output
Digital output
Standby control
Automotive input
Analog input
Pull-up control
Digital output
Digital output
Standby control
CMOS-hys input
Analog input
Document Number: 002-04662 Rev. *D Page 39 of 289
MB91520 Series
Type
Circuit
Remarks
J
• Analog input, General-purpose I/O port (5V
tolerant)
• Output 4mA
• CMOS hysteresis input
K
•Mode I/O
• CMOS hysteresis input
L
•Open-drain I/O
•Output 25mA (Nch open-drain)
•TTL input
M
• CMOS hysteresis input
•Pull-up resistor 50kΩ
N
•Main oscillation I/O
Standby control
Input
TTL input
Digital output
Control
Mode input
Digital output
Digital output
Standby control
CMOS-hys input
Analog input
CMOS-hys input
Document Number: 002-04662 Rev. *D Page 40 of 289
MB91520 Series
Type
Circuit
Remarks
O
•Sub oscillation I/O
Standby control
Input
Document Number: 002-04662 Rev. *D Page 41 of 289
MB91520 Series
5. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that
must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor
devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may
adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the
device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or
over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current
flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should
be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to
abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large
current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called
latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury
or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to
abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Document Number: 002-04662 Rev. *D Page 42 of 289
MB91520 Series
Code: DS00-00004-2Ea
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection,
and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may
directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are
demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical
devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be
responsible for damages arising from such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount
conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the
board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the
flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to
be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should
conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC
leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to
open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a
ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,
junction strength may be reduced under some conditions of use.
Document Number: 002-04662 Rev. *D Page 43 of 289
MB91520 Series
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures
between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a
silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation
may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the
level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such
cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the
device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
Document Number: 002-04662 Rev. *D Page 44 of 289
MB91520 Series
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If
devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04662 Rev. *D Page 45 of 289
MB91520 Series
6. Handling Devices
This section explains the latch-up prevention and pin processing.
For latch-up prevention
If a voltage higher than VCC or a voltage lower than VSS is applied to an I/O pin, or if a voltage exceeding the ratings is applied
between VCC and VSS pins, a latch-up may occur in CMOS IC. If the latch-up occurs, the power supply current increases
excessively and device elements may be damaged by heat. Take care to prevent any voltage from exceeding the maximum
ratings in device application.
Also, the analog power supply (AVCC, AVRH) and analog input must not be exceed the digital power supply (VCC) when the
power supply to the analog system is turned on or off.
In the correct power-on sequence of the microcontroller, turn on the digital power supply (VCC) and analog power supplies
(AVCC, AVRH) simultaneously. Or, turn on the digital power supply (VCC), and then turn on analog power supplies (AVCC,
AVRH).
Treatment of unused pins
If unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch-up. Connect at
least a 2kΩ resistor to each of the unused pins for pull-up or pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated
in the same way as for the input pins.
Power supply pins
The device is designed to ensure that if the device contains multiple VCC or VSS pins, the pins that should be at the same
potential are interconnected to prevent latch-up or other malfunctions. Further, connect these pins to an external power supply
or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the
total output current standard, etc. As shown in figure 1, all Vss power supply pins must be treated in the similar way. If multiple
Vcc or Vss systems are connected, the device cannot operate correctly even within the guaranteed operating range.
Figure 1 Power Supply Input Pins
The power supply pins should be connected to VCC and VSS pins of this device at the low impedance from the power supply
source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin is recommended
to use as a bypass capacitor between VCC and VSS pins.
Vss
Vss
Vcc
Vcc
Vss
Vcc
Vcc
Vss
Vss
Vcc
Document Number: 002-04662 Rev. *D Page 46 of 289
MB91520 Series
Crystal oscillation circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be designed to lay out X0
and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the
device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
Mode pins (MD1, MD0)
Connect the MD1and MD0 mode pins to the VCC or VSS pin directly. To prevent an erroneous selection of test mode caused by
the noise, reduce the pattern length between each mode pin and VCC or VSS pin on the printed circuit board. Also, use the
low-impedance pin connection.
During power-on
To prevent a malfunction of the voltage step-down circuit built in the device, the voltage rising must be monotonic during
power-on.
Notes during PLL clock operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate
at the free running frequency of the self-oscillator circuit built in the PLL clock. This operation is not guaranteed.
Treatment of A/D converter power supply pins
Connect the pins to have AVCC=AVRH=VCC and AVSS/AVRL=VSS even if the A/D converter is not used.
Notes on using external clock
An external clock is not supported. None of the external direct clock input can be used for both main clock and sub clock.
Power-on sequence of A/D converter analog inputs
Be sure to turn on the digital power supply (Vcc) first, and then turn on the A/D converter power supplies (AVcc, AVRH, AVRL)
and analog inputs (AN0 to AN47). Also, turn off the A/D converter power supplies and analog inputs first, and then turn off the
digital power supply (Vcc). When the AVRH pin voltage is turned on or off, it must not exceed AVCC. Even if a common analog
input pin is used as an input port, its input voltage must not exceed AVcc. (However, the analog power supply and digital power
supply can be turned on or off simultaneously.)
Treatment of C pin
This device contains a voltage step-down circuit. A capacitor must always be connected to the C pin to assure the internal
stabilization of the device. For the standard values, see the "Recommended Operating Conditions" of the latest data sheet.
Note: Please see the latest data sheet for a detailed specification of the operation voltage.
Function switching of a multiplexed port
To switch between the port function and the multiplexed pin function, use the PFR (port function register). However, if a pin is
also used for an external bus, its function is switched by the external bus setting. For details, see " I/O PORTS" in the hardware
manual.
Low-power consumption mode
To transit to the sleep mode, watch mode, stop mode, watch mode(power-off) or stop mode(power-off), follow the procedure
explained in "Activating the sleep mode, watch mode, or stop mode" or "Activating the watch mode (power-off) or stop
mode(power-off)" of " POWER CONSUMPTION CONTROL" in the hardware manual.
Take the following notes when using a monitor debugger.
• Do not set a break point for the low-power consumption transition program.
• Do not execute an operation step for the low-power consumption transition program.
Document Number: 002-04662 Rev. *D Page 47 of 289
MB91520 Series
Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control function, taking care not to
clear its status flag erroneously must be followed.
The program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can access to a single bit only.)
By the Byte, Half-word, or Word access, data is written to the control bits and status flag simultaneously. During this time, take
care not to clear other bits (in this case, the bits of status flag) erroneously.
Note: These points can be ignored because the bit instructions are already taken the points into consideration.
Document Number: 002-04662 Rev. *D Page 48 of 289
MB91520 Series
7. Block Diagram
MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
From Master
To Slave
From Master
To Slave
I / O Port
XBS Crossbar Switch
FR81s CPU core
Instruction Data
On-chip bus lay er 2
Peripheral Bus
Bridge
CAN prescaler
Watchdog timer(SW and HW)
Delay interrupt
Interrupt controller
RTC／W DT1 Calibration
Ｉ/Ｏport setting
Low-power consumption setting register
16 32
Wild register
I / O Port
On-chip bus lay er 1
Debug
Interface
Regulator
Interrupt request batch read
DMA transfer request generate/clear
Real time clock
Clock supervisor
On-chip bus(AHB)
XBS
Clock control （Clock setting,
Main timer, Sub timer, PLL ti mer
）
M P U
32bit Peripheral Bus (APB)
Clock control （divide control）
Bus
performance
counter
16bit Peripheral Bus
BackUp
RAM +8KB
Timing
Protection Unit
PPG(21ch)
Reload timer (7ch)
8bit DA converter (1ch)
External interrupt input(16ch)
32bit Output compare(4ch)
Base timer (1ch)
U/D counter (2ch)
32bit Free-run timer(1ch)
32bit Input capture(5ch)
Multi-function serial interface (8ch)
DMAC
(16 ch)
CAN (3ch)
CRC
Operation mode
register
Wave generator (6ch)
12bit AD converter (13ch + 13ch)
16bit Free-run timer (3ch)
16bit Input capture (4ch)
Power-on reset
CR oscillator
Low-voltage detection
（
External power supply low-voltage detection
）
Reset control register
NMI
Flash
・Main Flash
256K/384K/512K/768K/
1024KB +64KB
RAM
48K/64K/96K/128K
Clock monitor
Bus Bridge (32bit <-> 16bit)
RAM ECC Control(XBS RAM)
Clock /
Bus Bridge
RAM ECC Control
(Bac kUp RAM)
Async Bus Bridge (PCLK1 <-> PCLK2)
Bus Bridge (32bit <-> 16bit)
16bit Output compare (6ch)
Async Bus Bridge (PCLK1 <-> PCLK2)
Low-voltage detection
（Internal power supply low-voltage detection）
RST
NMIX
MD0,MD1,P00
RX,T
FRCK
ICU
OCU
TIOA,TIOB
AIN,BIN,ZI
TIN,TOT
DAO
MONCLK
WOT
INT
TRG,PPG
SOUT,
SIN,
SCK
ADTG,AIN
ICU
FRCK
DTTI,RTO
Document Number: 002-04662 Rev. *D Page 49 of 289
MB91520 Series
MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
From Master
To Slave
From Master
To Slave
I / O Port
XBS Crossbar Switch
FR81s CPU core
Instruction Data
On-chip bus layer 2
Peripheral Bus
Bridge
CAN prescaler
Watchdog timer(SW and HW)
Delay interrupt
Interrupt controller
RTC／W DT1 Calibration
Ｉ/Ｏport setting
Low-power consumption setting register
16 32
Wild register
I / O Port
On-chip bus layer 1
Debug
Interface
Regulator
Interrupt request batch read
DMA transfer request generate/clear
Real time clock
Clock supervisor
On-chip bus(AHB)
XBS
Clock control （Clock setting,
Main timer, Sub timer, PLL timer
）
M P U
32bit Peripheral Bus (APB)
Clock control （divide control）
Bus
performance
counter
16bit Peripheral Bus
BackUp
RAM +8KB
Timing
Protection Unit
PPG(27ch)
Reload timer (7ch)
8bit DA converter (2ch)
External interrupt input(16ch)
32bit Output compare(4ch)
Base timer (1ch)
U/D counter (2ch)
32bit Free-run timer(2ch)
32bit Input capture(5ch)
Multi-function serial interface (9ch)
DMAC
(16 ch)
CAN (3ch)
CRC
Operation mode
register
Wave generator (6ch)
12bit AD converter (21ch + 16ch)
16bit Free-run timer (3ch)
16bit Input capture (4ch)
Power-on reset
CR oscillator
Low-voltage detection
（
External power supply low-voltage detection
）
Reset control register
NMI
Flash
・Main Flash
256K/384K/512K/768K/
1024KB +64KB
RAM
48K/64K/96K/128K
Clock monitor
Bus Bridge (32bit <-> 16bit)
RAM ECC Control(XBS RAM)
Clock /
Bus Bridge
RAM ECC Control
(BackUp RAM)
Async Bus Bridge (PCLK1 <-> PCLK2)
Bus Bridge (32bit <-> 16bit)
16bit Output compare (6ch)
Async Bus Bridge (PCLK1 <-> PCLK2)
Low-voltage detection
（Internal power supply low-voltage detection）
RST
NMIX
MD0,MD1,P00
RX,T
FRCK
ICU
OCU
TIOA,TIOB
AIN,BIN,ZI
TIN,TOT
DAO
MONCLK
WOT
INT
TRG,PPG
SOUT,
SIN,
SCK
ADTG,AIN
ICU
FRCK
DTTI,RTO
Document Number: 002-04662 Rev. *D Page 50 of 289
MB91520 Series
MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F
From Master
To Slave
From Master
To Slave
I / O Port
XBS Crossbar Switch
FR81s CPU core
Instruction Data
On-chip bus layer 2
Peripheral Bus
Bridge
CAN prescaler
Watchdog timer(SW and HW)
Delay interrupt
Interrupt controller
RTC／W DT1 Calibration
Ｉ/Ｏport setting
Low-power consumption setting register
16 32
Wild register
I / O Port
On-chip bus layer 1
Debug Interface
Regulator
Interrupt request batch read
DMA transfer request generate/clear
Real time clock
Clock supervisor
On-chip bus(AHB)
XBS
Clock control （Clock setting,
Main timer, Sub timer, PLL timer
）
M P U
32bit Peripheral Bus (APB)
Clock control （divide control）
Bus
performance
counter
16bit Peripheral Bus
BackUp
RAM +8KB
Timing Protection
Unit
PPG(34ch)
Reload timer (8ch)
8bit DA converter (2ch)
External interrupt input(16ch)
32bit Output compare(6ch)
Base timer (1ch)
U/D counter (2ch)
32bit Free-run timer(3ch)
32bit Input capture(6ch)
Multi-function serial interface (12ch)
DMAC
(16 ch)
CAN (3ch)
CRC
Operation mode
register
Wave generator (6ch)
12bit AD converter (21ch + 16ch)
16bit Free-run timer (3ch)
16bit Input capture (4ch)
Power-on reset
CR oscillator
Low-voltage detection
（
External power supply low-voltage detection
）
Reset control register
NMI
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
RAM
48K/64K/96K/128K
Clock monitor
Bus Bridge (32bit <-> 16bit)
RAM ECC Control(XBS RAM)
Clock / Bus
Bridge
RAM ECC Control
(BackUp RAM)
Async Bus Bridge (PCLK1 <-> PCLK2)
Bus Bridge (32bit <-> 16bit)
16bit Output compare (6ch)
Async Bus Bridge (PCLK1 <-> PCLK2)
Low-voltage detection
（
Internal power supply low-voltage detection
）
RSTX
NMIX
MD0,MD1,P006
RX,TX
FRCK
ICU
OCU
TIOA,TIOB
AIN,BIN,ZIN
TIN,TOT
DAO
MONCLK
WOT
INT
TRG,PPG
SOUT,
SIN,
SCK
ADTG,AIN
ADC enable(ADER)
ICU
FRCK
DTTI,RTO
Document Number: 002-04662 Rev. *D Page 51 of 289
MB91520 Series
MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J
From Master
To Slave
From Master
To Slave
I / O Port
XBS Crossbar Switch
FR81s CPU core
Instruction Data
On-chip bus layer 2
Peripheral Bus
Bridge
CAN prescaler
Watchdog timer(SW and HW)
Delay interrupt
Interrupt controller
RTC／W DT1 Calibration
Ｉ/Ｏport setting
Low-power consumption setting register
16 32
Wild register
I / O Port
On-chip bus layer 1
Debug Interface
Regulator
Interrupt request batch read
DMA transfer request generate/clear
Real time clock
Clock supervisor
On-chip bus(AHB)
XBS
Clock control （Clock setting,
Main timer, Sub timer, PLL timer
）
M P U
32bit Peripheral Bus (APB)
Clock control （divide control）
Bus
performance
counter
16bit Peripheral Bus
BackUp
RAM +8KB
Timing Protection
Unit
PPG(38ch)
Reload timer (8ch)
8bit DA converter (2ch)
External interrupt input(16ch)
32bit Output compare(6ch)
Base timer (2ch)
U/D counter (2ch)
32bit Free-run timer(3ch)
32bit Input capture(6ch)
Multi-function serial interface (12ch)
DMAC
(16 ch)
CAN (3ch)
CRC
Operation mode
register
Wave generator (6ch)
12bit AD converter (26ch + 16ch)
16bit Free-run timer (3ch)
16bit Input capture (4ch)
Power-on reset
CR oscillator
Low-voltage detection
（
External power supply low-voltage detection
）
Reset control register
NMI
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
RAM
48K/64K/96K/128K
Clock monitor
Bus Bridge (32bit <-> 16bit)
RAM ECC Control(XBS RAM)
Clock / Bus
Bridge
RAM ECC Control
(BackUp RAM)
Async Bus Bridge (PCLK1 <-> PCLK2)
Bus Bridge (32bit <-> 16bit)
16bit Output compare (6ch)
Async Bus Bridge (PCLK1 <-> PCLK2)
Low-voltage detection
（
Internal power supply low-voltage detection
）
RSTX
NMIX
MD0,MD1,P006
RX,TX
FRCK
ICU
OCU
TIOA,TIOB
AIN,BIN,ZIN
TIN,TOT
DAO
MONCLK
WOT
INT
TRG,PPG
SOUT,
SIN,
SCK
ADTG,AIN
ADC enable(ADER)
ICU
FRCK
DTTI,RTO
Document Number: 002-04662 Rev. *D Page 52 of 289
MB91520 Series
MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K
From Master
To Slave
From Master
To Slave
I / O Port
XBS Crossbar Switch
FR81s CPU core
Instruction Data
On-chip bus layer 2
External Bus
I / F
Peripheral Bus
Bridge
CAN prescaler
Watchdog timer(SW and HW)
Delay interrupt
Interrupt controller
RTC／W DT1 Calibration
Ｉ/Ｏport setting
Low-power consumption setting register
16 32
Wild register
I / O Port
On-chip bus layer 1
Debug Interface
Regulator
Interrupt request batch read
DMA transfer request generate/clear
Real time clock
Clock supervisor
On-chip bus(AHB)
XBS
Clock control （Clock setting,
Main timer, Sub timer, PLL timer
）
M P U
32bit Peripheral Bus (APB)
Clock control （divide control）
Bus
performance
counter
16bit Peripheral Bus
BackUp
RAM +8KB
Timing Protection
Unit
PPG(44ch)
Reload timer (8ch)
8bit DA converter (2ch)
External interrupt input(16ch)
32bit Output compare(6ch)
Base timer (2ch)
U/D counter (2ch)
32bit Free-run timer(3ch)
32bit Input capture(6ch)
Multi-function serial interface (12ch)
DMAC
(16 ch)
CAN (3ch)
CRC
Operation mode
register
Wave generator (6ch)
12bit AD converter (32ch + 16ch)
16bit Free-run timer (3ch)
16bit Input capture (4ch)
Power-on reset
CR oscillator
Low-voltage detection
（
External power supply low-voltage detection
）
Reset control register
NMI
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
RAM
48K/64K/96K/128K
Clock monitor
Bus Bridge (32bit <-> 16bit)
RAM ECC Control(XBS RAM)
Clock / Bus
Bridge
RAM ECC Control
(BackUp RAM)
Async Bus Bridge (PCLK1 <-> PCLK2)
16bit Output compare (6ch)
Async Bus Bridge (PCLK1 <-> PCLK2)
Low-voltage detection
（
Internal power supply low-voltage detection
）
RSTX
NMIX
MD0,MD1,P006
RX,TX
D,A,
ASX,CS,
RDX,
WRX,
SYSCLK,
RDY
FRCK
ICU
OCU
TIOA,TIOB
AIN,BIN,ZIN
TIN,TOT
DAO
MONCLK
WOT
INT
TRG,PPG
SOUT,
SIN,
SCK
ADTG,AIN
ADC enable(ADER)
ICU
FRCK
DTTI,RTO
Bus Bridge (32bit <-> 16bit)
Document Number: 002-04662 Rev. *D Page 53 of 289
MB91520 Series
MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L
From Master
To Slave
From Master
To Slave
I / O Port
XBS Crossbar Switch
FR81s CPU core
Instruction Data
On-chip bus layer 2
External Bus
I / F
Peripheral Bus
Bridge
CAN prescaler
Watchdog timer(SW and HW)
Delay interrupt
Interrupt controller
RTC／W DT1 Calibration
Ｉ/Ｏport setting
Low-power consumption setting register
16 32
Wild register
I / O Port
On-chip bus layer 1
Debug Interface
Regulator
Interrupt request batch read
DMA transfer request generate/clear
Real time clock
Clock supervisor
On-chip bus(AHB)
XBS
Clock control （Clock setting,
Main timer, Sub timer, PLL timer
）
M P U
32bit Peripheral Bus (APB)
Clock control （divide control）
Bus
performance
counter
16bit Peripheral Bus
BackUp
RAM +8KB
Timing Protection
Unit
PPG(48ch)
Reload timer (8ch)
8bit DA converter (2ch)
External interrupt input(16ch)
32bit Output compare(6ch)
Base timer (2ch)
U/D counter (2ch)
32bit Free-run timer(3ch)
32bit Input capture(6ch)
Multi-function serial interface (12ch)
DMAC
(16 ch)
CAN (3ch)
CRC
Operation mode
register
Wave generator (6ch)
12bit AD converter (32ch + 16ch)
16bit Free-run timer (3ch)
16bit Input capture (4ch)
Power-on reset
CR oscillator
Low-voltage detection
（
External power supply low-voltage detection
）
Reset control register
NMI
Flash
・Main Flash 256K/384K/512K/768K/
1024KB +64KB
・WorkFlash 64KB
RAM
48K/64K/96K/128K
Clock monitor
Bus Bridge (32bit <-> 16bit)
RAM ECC Control(XBS RAM)
Clock / Bus
Bridge
RAM ECC Control
(BackUp RAM)
Async Bus Bridge (PCLK1 <-> PCLK2)
Bus Bridge (32bit <-> 16bit)
16bit Output compare (6ch)
Async Bus Bridge (PCLK1 <-> PCLK2)
Low-voltage detection
（
Internal power supply low-voltage detection
）
RSTX
NMIX
MD0,MD1,P006
RX,TX
D,A,
ASX,CS,
RDX,
WRX,
SYSCLK,
RDY
FRCK
ICU
OCU
TIOA,TIOB
AIN,BIN,ZIN
TIN,TOT
DAO
MONCLK
WOT
INT
TRG,PPG
SOUT,
SIN,
SCK
ADTG,AIN
ADC enable(ADER)
ICU
FRCK
DTTI,RTO
Document Number: 002-04662 Rev. *D Page 54 of 289
MB91520 Series
8. Memory Map
MB91F522, MB91F523, MB91F524
MB91F522
MB91F523
MB91F524
0000
0000H
I/O
0000
0000H
I/O
0000
0000H
I/O
0000
4000H
BackUp RAM (8KB)
0000
4000H
BackUp RAM (8KB)
0000
4000H
BackUp RAM (8KB)
0000
6000H
I/O
0000
6000H
I/O
0000
6000H
I/O
0001
0000H
RAM (48KB)
0001
0000H
RAM (48KB)
0001
0000H
RAM (64KB)
0001
C000H
0001
C000H
0002
0000H
0007
0000H
Flash memory
0007
0000H
0007
0000H
(256+64)KB
Flash memory
Flash memory
(384+64)KB
(512+64)KB
000C
0000H
000E
0000H
0010
0000H
0033
0000H
WorkFlash
0033
0000H
WorkFlash
0033
0000H
WorkFlash
(64KB)
(64KB)
(64KB)
0034
0000H
0034
0000H
0034
0000H
Reserved
Reserved
Reserved
8000
0000H
8000
0000H
8000
0000H
External area
External area
External area
FFFF
FFFFH
FFFF
FFFFH
FFFFH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FFFF
0039
0000H
0039
2000H
0039
0000H
0039
2000H
Interrupt vector
Reset vector
000F
FC00H
0010
0000H
Interrupt vector
Reset vector
000F
FC00H
0010
0000H
Interrupt vector
Reset vector
000F
FC00H
Reserved
Reserved
Document Number: 002-04662 Rev. *D Page 55 of 289
MB91520 Series
MB91F525, MB91F526
MB91F525
MB91F526
0000
0000H
I/O
0000
0000H
I/O
0000
4000H
BackUp RAM (8KB)
0000
4000H
BackUp RAM (8KB)
0000
6000H
I/O
0000
6000H
I/O
0001
0000H
RAM (96KB)
0001
0000H
RAM (128KB)
0002
8000H
0003
0000H
Reserved
Reserved
0007
0000H
0007
0000H
Flash
memory
Flash
memory
(768+64)KB
(1024+64)KB
0014
0000H
0018
0000H
Reserved
Reserved
0033
0000H
WorkFlash
0033
0000H
WorkFlash
(64KB)
(64KB)
0034
0000H
0034
0000H
Reserved
Reserved
8000
0000H
8000
0000H
External area
External area
FFFF
FFFFH
FFFF
FFFFH
0039
0000H
0039
2000H
0039
0000H
0039
2000H
Interrupt vector
Flash
memory
Reset vector
000F
FC00H
0010
0000H
Flash
memory
Interrupt vector
Reset vector
000F
FC00H
0010
0000H
Document Number: 002-04662 Rev. *D Page 56 of 289
MB91520 Series
9. I/O Map
The following I/O map shows the relationship between memory space and registers for peripheral resources.
Legend of I/O Map
Read/Write attribute (R: Read W: Write)
Address
Address offset value/ register name
Block
+0
+1
+2
+3
000090H BT1TMR[R] H
0000000000000000
BT1TMCR[R/W]B,H,W
00000000 00000000
Base timer 1
000094 H - BT1STC[R/W] B
00000000
- -
000098 H BT1PCSR/BT1PRLL[R /W] H
0000000000000000
BT1PDU T/BT1PRLH/BT1DTBF[R/W] H
0000000000000000
00009C H BTSEL[R/W] B
----000 0
- BTSSSR[W] B,H
-------- ------11
0000A0 H ADERH [R/W]B, H, W
00000000 00000000
ADERL [R/W]B, H, W
00000000 00000000
A/D converter
0000A4 H ADCS1 [R/W] B, H,W
00000000
ADCS0 [R/W] B, H,W
00000000
ADCR1 [R] B, H,W
------XX
ADCR0 [R] B, H,W
XXXXX XXX
0000A8 H ADCT1 [R/W] B, H,W
00010000
ADCT0 [R/W] B, H,W
00101100
ADSCH [R/W] B, H,W
---00000
ADECH [R/W] B, H,W
---00000
Data access attribute
B: Byte
H: Half-word
W: Word
(Note)The access by the data
access attribute not described
is disabled.
Initial register value after reset
The initial register value after reset indicates as follows:
· "1": Initial value "1"
· "0": Initial value "0"
· "X": Initial value undefined
· "-": Reserved bit/Undefined bit
· "*": Initial value "0" or "1" according to the setting
Note: The access to addresses not described is disabled.
Document Number: 002-04662 Rev. *D Page 57 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000000H
PDR00 [R/W] B,H,W
XXXXXXXX
PDR01 [R/W] B,H,W
XXXXXXXX
PDR02 [R/W] B,H,W
XXXXXXXX
PDR03 [R/W] B,H,W
XXXXXXXX
Port Data
Register
000004H
PDR04 [R/W] B,H,W
XXXXXXXX
PDR05 [R/W] B,H,W
XXXXXXXX
PDR06 [R/W] B,H,W
XXXXXXXX
PDR07 [R/W] B,H,W
XXXXXXXX
000008H
PDR08 [R/W] B,H,W
XXXXXXXX
PDR09 [R/W] B,H,W
XXXXXXXX
PDR10 [R/W] B,H,W
XXXXXXXX
PDR11 [R/W] B,H,W
XXXXXXXX
00000CH
PDR12 [R/W] B,H,W
XXXXXXXX
PDR13 [R/W] B,H,W
-XXXXXXX
PDR14 [R/W] B,H,W
---XXX--
PDR15 [R/W] B,H,W
--XXXXXX
000010H
― ― ― ―
000014H
― ― ― ―
000018H
PDR16 [R/W] B,H,W
XXXXXXXX
PDR17 [R/W] B,H,W
XXXXXXXX
PDR18 [R/W] B,H,W
XXXXXXXX
PDR19 [R/W] B,H,W
XXXXXXXX
00001CH
to
000034H
― ― ― ― Reserved
000038H
WDTECR0 [R/W]
B,H,W
---00000
― ― ―
Watchdog Timer
[S]
00003CH
WDTCR0 [R/W]
B,H,W
-0--0000
WDTCPR0 [W]
B,H,W
00000000
WDTCR1 [R]
B,H,W
----0110
WDTCPR1 [W]
B,H,W
00000000
000040H
―
―
―
―
Reserved
000044H
DICR [R/W]
B,H,W
-------0
― ― ― Delayed Interrupt
000048H
to
00005CH
― ― ― ― Reserved
000060H
TMRLRA0 [R/W] H
XXXXXXXX XXXXXXXX
TMR0 [R] H
XXXXXXXX XXXXXXXX
Reload Timer 0
000064H
TMRLRB0 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR0 [R/W] B,H,W
00000000 0-000000
000068H
TMRLRA7 [R/W] H
XXXXXXXX XXXXXXXX
TMR7 [R] H
XXXXXXXX XXXXXXXX
Reload Timer 7
00006CH
TMRLRB7 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR7 [R/W] B,H,W
00000000 0-000000
000070H
― FRS8 [R/W] B,H,W
--00--00 --00--00 --00--00
Free-run timer
selection register
8
Document Number: 002-04662 Rev. *D Page 58 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000074H
― FRS9 [R/W] B,H,W
--00--00 --00--00 --00--00
Free-run timer
selection register
9
000078H
― ― ―
OCLS67 [R/W]
B,H,W
----0000
OCU67 Output
level control
register
00007CH
― ― ―
OCLS89 [R/W]
B,H,W
----0000
OCU89 Output
level control
register
000080H
BT0TMR [R] H
00000000 00000000
BT0TMCR [R/W] H
-000--00 -000-000
Base Timer 0
000084H
BT0TMCR2 [R/W] B
-------0
BT0STC [R/W] B
-0-0-0-0 ― ―
000088H
BT0PCSR/BT0PRLL [R/W] H
00000000 00000000
BT0PDUT/BT0PRLH/BT0DTBF [R/W] H
00000000 00000000
00008CH
―
―
―
―
Reserved
000090H
BT1TMR [R] H
00000000 00000000
BT1TMCR [R/W] H
-000--00 -000-000
Base Timer 1
000094H
BT1TMCR2 [R/W] B
-------0
BT1STC [R/W] B
-0-0-0-0 ― ―
000098H
BT1PCSR/BT1PRLL [R/W] H
00000000 00000000
BT1PDUT/BT1PRLH/BT1DTBF [R/W] H
00000000 00000000
00009CH
BTSEL01 [R/W] B
----0000 ― BTSSSR [W] B,H
-------- ------11 Base Timer 0,1
0000A0H
to
0000FCH
― ― ― ― Reserved
000100H
TMRLRA1 [R/W] H
XXXXXXXX XXXXXXXX
TMR1 [R] H
XXXXXXXX XXXXXXXX
Reload Timer 1
000104H
TMRLRB1 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR1 [R/W] B, H,W
00000000 0-000000
000108H
TMRLRA2 [R/W] H
XXXXXXXX XXXXXXXX
TMR2 [R] H
XXXXXXXX XXXXXXXX
Reload Timer 2
00010CH
TMRLRB2 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR2 [R/W] B,H,W
00000000 0-000000
000110H TMRLRA3 [R/W] H
XXXXXXXX XXXXXXXX
TMR3 [R] H
XXXXXXXX XXXXXXXX Reload Timer 3
000114H TMRLRB3 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR3 [R/W] B,H,W
00000000 0-000000
000118H MSCY4 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Input Capture 4,5
Cycle
measurement
data register 45
00011CH
MSCY5 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04662 Rev. *D Page 59 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000120H
OCCP6 [R/W] W
00000000 00000000 00000000 00000000
Output
Compare 6,7
32-bit OCU
000124H
OCCP7 [R/W] W
00000000 00000000 00000000 00000000
000128H
― ―
OCSH67 [R/W]
B,H,W
---0--00
OCSL67 [R/W]
B,H,W
0000--00
00012CH
OCCP8 [R/W] W
00000000 00000000 00000000 00000000
Output
Compare 8,9
32-bit OCU
000130H
OCCP9 [R/W] W
00000000 00000000 00000000 00000000
000134H
― ―
OCSH89 [R/W]
B,H,W
---0--00
OCSL89 [R/W]
B,H,W
0000--00
000138
H
to
0001B4H
― ― ― ― Reserved
0001B8H
EPFR64 [R/W]
B,H,W
-----00-
EPFR65 [R/W]
B,H,W
0000-000
EPFR66 [R/W]
B,H,W
--000000
EPFR67 [R/W]
B,H,W
----0000
Extended port
function register
0001BCH
EPFR68 [R/W]
B,H,W
----0000
EPFR69 [R/W]
B,H,W
----0000
EPFR70 [R/W]
B,H,W
---00000
EPFR71 [R/W]
B,H,W
-0-0-0-0
0001C0H
EPFR72 [R/W]
B,H,W
000000-0
EPFR73 [R/W]
B,H,W
00000000
EPFR74 [R/W]
B,H,W
00000000
EPFR75 [R/W]
B,H,W
00000000
0001C4H
EPFR76 [R/W]
B,H,W
00000000
EPFR77 [R/W]
B,H,W
--000000
EPFR78 [R/W]
B,H,W
------00
EPFR79 [R/W]
B,H,W
00000000
0001C8H
EPFR80 [R/W]
B,H,W
---00000
EPFR81 [R/W]
B,H,W
00000000
EPFR82 [R/W]
B,H,W
00000000
EPFR83 [R/W]
B,H,W
-0000000
0001CCH
EPFR84 [R/W]
B,H,W
00000000
EPFR85 [R/W]
B,H,W
--000000
EPFR86 [R/W]
B,H,W
---00000
EPFR87 [R/W]
B,H,W
------00
0001D0H
EPFR88 [R/W]
B,H,W
-------0
― ― ―
0001D4H
― ― ― ― Reserved
0001D8H
TMRLRA4 [R/W] H
XXXXXXXX XXXXXXXX
TMR4 [R] H
XXXXXXXX XXXXXXXX
Reload Timer 4
0001DCH
TMRLRB4 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR4 [R/W] B, H,W
00000000 0-000000
0001E0
H
to
0001ECH
― ― ― ― Reserved
0001F0H
TMRLRA5 [R/W] H
XXXXXXXX XXXXXXXX
TMR5 [R] H
XXXXXXXX XXXXXXXX
Reload Timer 5
0001F4H
TMRLRB5 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR5 [R/W] B, H,W
00000000 0-000000
Document Number: 002-04662 Rev. *D Page 60 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0001F8H
TMRLRA6 [R/W] H
XXXXXXXX XXXXXXXX
TMR6 [R] H
XXXXXXXX XXXXXXXX
Reload Timer 6
0001FCH
TMRLRB6 [R/W] H
XXXXXXXX XXXXXXXX
TMCSR6 [R/W] B, H,W
00000000 0-000000
000200
H
to
000238H
― ― ― ― Reserved
00023CH
DACR0 [R/W] B,H,W
-------0
DADR0 [R/W] B,H,W
XXXXXXXX
DACR1 [R/W] B,H,W
-------0
DADR1 [R/W] B,H,W
XXXXXXXX DA Converter
000240H
CPCLR3 [R/W] W
11111111 11111111 11111111 11111111
Free-run Timer 3
32-bit FRT
000244H
TCDT3 [R/W] W
00000000 00000000 00000000 00000000
000248H
TCCSH3 [R/W]
B,H,W
0-----00
TCCSL3 [R/W]
B,H,W
-1-00000
― ―
00024CH
CPCLR4 [R/W] W
11111111 11111111 11111111 11111111
Free-run Timer 4
32-bit FRT
000250H
TCDT4 [R/W] W
00000000 00000000 00000000 00000000
000254H
TCCSH4 [R/W]
B,H,W
0-----00
TCCSL4 [R/W]
B,H,W
-1-00000
― ―
000258H
to
0002C0H
― ― ― ― Reserved
0002C4H
to
0002FCH
― ― ― ― Reserved
000300H
to
00030CH
― ― ― ― Reserved
000310H
― ― MPUCR [R/W] H
000000-0 ----0100
MPU [S]
(Only CPU core
can access this
area)
000314H
―
―
―
―
000318H
―
00031CH
― ― ―
000320H
DPVAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000324H
― ― DPVSR [R/W] H
-------- 00000--0
Document Number: 002-04662 Rev. *D Page 61 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000328H
DEAR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
MPU [S]
(Only CPU core
can access this
area)
00032CH
― ― DESR [R/W] H
-------- 00000--0
000330H
PABR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000334H
― ― PACR0 [R/W] H
000000-0 00000--0
000338H
PABR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00033CH
― ― PACR1 [R/W] H
000000-0 00000--0
000340H
PABR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
MPU [S]
(Only CPU core
can access this
area)
000344H
― ― PACR2 [R/W] H
000000-0 00000--0
000348H
PABR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00034CH
― ― PACR3 [R/W] H
000000-0 00000--0
000350H
PABR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000354H
― ― PACR4 [R/W] H
000000-0 00000--0
000358H
PABR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00035CH
― ― PACR5 [R/W] H
000000-0 00000--0
000360H
PABR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
000364H
― ― PACR6 [R/W] H
000000-0 00000--0
000368H
PABR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXX0000
00036CH
― ― PACR7 [R/W] H
000000-0 00000--0
000370H
to
0003ACH
― Reserved [S]
0003B0H
to
0003FCH
― ― ― ― Reserved [S]
Document Number: 002-04662 Rev. *D Page 62 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000400H
ICSEL0 [R/W] B,H,W
-----000
ICSEL1 [R/W] B,H,W
-----000
ICSEL2 [R/W] B,H,W
-------0
ICSEL3 [R/W] B,H,W
-------0
DMA request
generation and
clear
000404H
― ICSEL5 [R/W] B,H,W
-----000
ICSEL6 [R/W] B,H,W
----0000
ICSEL7 [R/W] B,H,W
----0000
000408H
ICSEL8 [R/W] B,H,W
------00
ICSEL9 [R/W] B,H,W
------00
ICSEL10 [R/W]
B,H,W
------00
ICSEL11 [R/W]
B,H,W
-----000
00040CH
―
ICSEL13 [R/W]
B,H,W
------00
ICSEL14 [R/W]
B,H,W
------00
ICSEL15 [R/W]
B,H,W
------00
000410H
ICSEL16 [R/W]
B,H,W
----0000
ICSEL17 [R/W]
B,H,W
------00
ICSEL18 [R/W]
B,H,W
---00000
ICSEL19 [R/W]
B,H,W
-----000
000414H
ICSEL20 [R/W]
B,H,W
-----000
ICSEL21 [R/W]
B,H,W
------00
ICSEL22 [R/W]
B,H,W
------00
ICSEL23 [R/W]
B,H,W
------00
000418H
IRPR0H [R] B,H,W
00------
IRPR0L [R] B,H,W
00------
IRPR1H [R] B,H,W
00------
IRPR1L [R] B,H,W
00------
Interrupt Request
Batch Reading
Register
00041CH
― ― IRPR3H [R] B,H,W
000000--
IRPR3L [R] B,H,W
000000--
000420H
IRPR4H [R] B,H,W
0000----
IRPR4L [R] B,H,W
0000----
IRPR5H [R] B,H,W
0000----
IRPR5L [R] B,H,W
000-----
000424H
IRPR6H [R] B,H,W
--00----
IRPR6L [R] B,H,W
0000----
IRPR7H [R] B,H,W
-0-00---
IRPR7L [R] B,H,W
------00
000428H
IRPR8H [R] B,H,W
--0-----
IRPR8L [R] B,H,W
-00-----
IRPR9H [R] B,H,W
-0------
IRPR9L [R] B,H,W
-0------
00042CH
IRPR10H [R] B,H,W
-0------
IRPR10L [R] B,H,W
-0------
IRPR11H [R] B,H,W
0-------
IRPR11L [R] B,H,W
0-------
000430H
IRPR12H [R] B,H,W
--0000--
IRPR12L [R] B,H,W
----00--
IRPR13H [R] B,H,W
00------
IRPR13L [R] B,H,W
00------
000434H
IRPR14H [R] B,H,W
00000000
IRPR14L [R] B,H,W
00000000
IRPR15H [R] B,H,W
000-----
IRPR15L [R] B,H,W
0000000-
000438H
ICSEL24 [R/W]
B,H,W
------00
ICSEL25 [R/W]
B,H,W
---00000
ICSEL26 [R/W]
B,H,W
-------0
ICSEL27 [R/W]
B,H,W
-------0
DMA request
generation and
clear
00043CH
―
―
―
―
Reserved [S]
Document Number: 002-04662 Rev. *D Page 63 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000440H
ICR00 [R/W] B,H,W
---11111
ICR01 [R/W] B,H,W
---11111
ICR02 [R/W] B,H,W
---11111
ICR03 [R/W] B,H,W
---11111
Interrupt
Controller [S]
000444H
ICR04 [R/W] B,H,W
---11111
ICR05 [R/W] B,H,W
---11111
ICR06 [R/W] B,H,W
---11111
ICR07 [R/W] B,H,W
---11111
000448H
ICR08 [R/W] B,H,W
---11111
ICR09 [R/W] B,H,W
---11111
ICR10 [R/W] B,H,W
---11111
ICR11 [R/W] B,H,W
---11111
00044CH
ICR12 [R/W] B,H,W
---11111
ICR13 [R/W] B,H,W
---11111
ICR14 [R/W] B,H,W
---11111
ICR15 [R/W] B,H,W
---11111
000450H
ICR16 [R/W] B,H,W
---11111
ICR17 [R/W] B,H,W
---11111
ICR18 [R/W] B,H,W
---11111
ICR19 [R/W] B,H,W
---11111
000454H
ICR20 [R/W] B,H,W
---11111
ICR21 [R/W] B,H,W
---11111
ICR22 [R/W] B,H,W
---11111
ICR23 [R/W] B,H,W
---11111
000458H
ICR24 [R/W] B,H,W
---11111
ICR25 [R/W] B,H,W
---11111
ICR26 [R/W] B,H,W
---11111
ICR27 [R/W] B,H,W
---11111
00045CH
ICR28 [R/W] B,H,W
---11111
ICR29 [R/W] B,H,W
---11111
ICR30 [R/W] B,H,W
---11111
ICR31 [R/W] B,H,W
---11111
000460H
ICR32 [R/W] B,H,W
---11111
ICR33 [R/W] B,H,W
---11111
ICR34 [R/W] B,H,W
---11111
ICR35 [R/W] B,H,W
---11111
000464H
ICR36 [R/W] B,H,W
---11111
ICR37 [R/W] B,H,W
---11111
ICR38 [R/W] B,H,W
---11111
ICR39 [R/W] B,H,W
---11111
000468H
ICR40 [R/W] B,H,W
---11111
ICR41 [R/W] B,H,W
---11111
ICR42 [R/W] B,H,W
---11111
ICR43 [R/W] B,H,W
---11111
00046CH
ICR44 [R/W] B,H,W
---11111
ICR45 [R/W] B,H,W
---11111
ICR46 [R/W] B,H,W
---11111
ICR47 [R/W] B,H,W
---11111
000470H
to
00047CH
― ― ― ― Reserved [S]
000480H
RSTRR [R]
B,H,W
XXXX--XX
RSTCR [R/W]
B,H,W
111----0
STBCR [R/W]
B,H,W *
000---11
―
Reset Control [S]
Power Control [S]
*: Writing STBCR
by DMA is
forbidden
000484H
―
―
―
―
Reserved [S]
000488H
DIVR0 [R/W] B,H,W
000-----
DIVR1 [R/W] B,H,W
0001----
DIVR2 [R/W] B,H,W
0011---- ― Clock Control [S]
00048CH
―
―
―
―
Reserved [S]
000490H
IORR0 [R/W] B,H,W
-0000000
IORR1 [R/W] B,H,W
-0000000
IORR2 [R/W] B,H,W
-0000000
IORR3 [R/W] B,H,W
-0000000
DMA request by
peripheral [S]
000494H
IORR4 [R/W] B,H,W
-0000000
IORR5 [R/W] B,H,W
-0000000
IORR6 [R/W] B,H,W
-0000000
IORR7 [R/W] B,H,W
-0000000
000498H
IORR8 [R/W] B,H,W
-0000000
IORR9 [R/W] B,H,W
-0000000
IORR10 [R/W] B,H,W
-0000000
IORR11 [R/W] B,H,W
-0000000
Document Number: 002-04662 Rev. *D Page 64 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
00049CH
IORR12 [R/W] B,H,W
-0000000
IORR13 [R/W] B,H,W
-0000000
IORR14 [R/W] B,H,W
-0000000
IORR15 [R/W] B,H,W
-0000000
DMA request by
peripheral [S]
0004A0H
―
―
―
―
Reserved
0004A4H
CANPRE [R/W]
B,H,W
---00000
― ― ― CAN prescaler
0004A8H
― ― CSCFG[R/W]B,H,W
---0----
CMCFG[R/W]B,H,W
00000000
Clock monitor
control register
0004ACH
ADERH0[R/W] B,H
11111111 11111111
ADERL0[R/W] B,H
11111111 11111111
Analog input
control register 0
0004B0H
― ADERL1[R/W] B,H
11111111 11111111
Analog input
control register 1
0004B4H
― ― ― ― Reserved
0004B8H
CUCR0 [R/W] B,H,W
-------- ---0--00
CUTD0 [R/W] B,H,W
10000000 00000000
RTC/WDT1
calibration
0004BCH
CUTR0 [R] B,H,W
-------- 00000000 00000000 00000000
0004C0H
―
―
―
―
0004C4H
CUCR1 [R/W] B,H,W
-------- ---0--00
CUTD1 [R/W] B,H,W
11000011 01010000
0004C8H
CUTR1 [R] B,H,W
-------- 00000000 00000000 00000000
0004CCH
to
00050CH
― ― ― ― Reserved
000510H
CSELR [R/W] B,H,W
001---00
CMONR [R] B,H,W
001---00
MTMCR [R/W]
B,H,W
00001111
STMCR [R/W] B,H,W
0000-111
Clock Control [S]
000514H
PLLCR [R/W] B,H,W
-------- 11110000
CSTBR [R/W] B,H,W
-0000000
PTMCR [R/W] B,H,W
00------
000518H
― ―
CPUAR [R/W] B,H,W
0----XXX ― Reset Control [S]
00051CH
―
―
―
―
Reserved [S]
000520H
CCPSSELR [R/W]
B,H,W
-------0
― ―
CCPSDIVR [R/W]
B,H,W
-000-000
Clock Control 2
[S]
000524H
―
CCPLLFBR [R/W]
B,H,W
-0000000
CCSSFBR0 [R/W]
B,H,W
--000000
CCSSFBR1 [R/W]
B,H,W
---00000
000528H
―
CCSSCCR0 [R/W]
B,H,W
----0000
CCSSCCR1 [R/W] H,W
000----- --------
Document Number: 002-04662 Rev. *D Page 65 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
00052CH
―
CCCGRCR0 [R/W]
B,H,W
00----00
CCCGRCR1 [R/W]
B,H,W
00000000
CCCGRCR2 [R/W]
B,H,W
00000000
Clock Control 2
[S]
000530H
CCRTSELR [R/W]
B,H,W
0------0
―
CCPMUCR0 [R/W]
B,H,W
0-----00
CCPMUCR1 [R/W]
B,H,W
0--00000
000534H
to
00054CH
― ― ― ― Reserved
000550H
EIRR0 [R/W] B,H,W
XXXXXXXX
ENIR0 [R/W] B,H,W
00000000
ELVR0 [R/W] B,H,W
00000000 00000000
External Interrupt
(INT0 to 7)
000554H
EIRR1 [R/W] B,H,W
XXXXXXXX
ENIR1 [R/W] B,H,W
00000000
ELVR1 [R/W] B,H,W
00000000 00000000
External Interrupt
(INT8 to 15)
000558
H
―
―
―
―
Reserved
00055CH
― ― WTDR [R/W] H
00000000 00000000
Real Time Clock
(RTC)
000560H
― WTCRH [R/W] B
------00
WTCRM [R/W] B,H
00000000
WTCRL [R/W] B,H
----00-0
000564H
― WTBRH [R/W] B
--XXXXXX
WTBRM [R/W] B
XXXXXXXX
WTBRL [R/W] B
XXXXXXXX
000568H
WTHR [R/W] B,H
---00000
WTMR [R/W] B,H
--000000
WTSR [R/W] B
--000000 ―
00056CH
― CSVCR [R/W] B
000111-- ― ― Clock Supervisor
000570H
to
00057CH
― ― ― ― Reserved
000580H
REGSEL [R/W]
B,H,W
0110011-
― ― ―
Regulator Control
/ Low Voltage
Detection
000584H
LVD5R [R/W]
B,H,W
-------1
LVD5F [R/W]
B,H,W
00000001
LVD [R/W]
B,H,W
01000--0
―
000588H
to
00058CH
― ― ― ― Reserved
000590H
PMUSTR [R/W]
B,H,W
0-----1X
PMUCTLR [R/W]
B,H,W
0-00----
PWRTMCTL [R/W]
B,H,W
-----011
―
PMU
000594H
PMUINTF0 [R/W]
B,H,W
00000000
PMUINTF1 [R/W]
B,H,W
00000000
PMUINTF2 [R/W]
B,H,W
0000----
―
000598H
― ― ― ―
Document Number: 002-04662 Rev. *D Page 66 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
00059CH
to
0005BCH
― ― ― ― Reserved
0005C0H
to
0005FCH
― ― ― ― Reserved
000600H
ASR0 [R/W] W
00000000 00000000 -------- 1111-001
External Bus
Interface [S]
000604H
ASR1 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000608H
ASR2 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
00060CH
ASR3 [R/W] W
XXXXXXXX XXXXXXXX -------- XXXX-XX0
000610H
to
00063CH
― ― ― ― Reserved [S]
000640H
ACR0 [R/W] W
-------- -------- -------- 01--00--
External Bus
Interface [S]
000644H
ACR1 [R/W] W
-------- -------- -------- XX--XX--
000648H
ACR2 [R/W] W
-------- -------- -------- XX--XX--
00064CH
ACR3 [R/W] W
-------- -------- -------- XX--XX--
000650H
to
00067CH
― ― ― ― Reserved [S]
000680H
AWR0 [R/W] W
----1111 00000000 11110000 00000-0- External Bus
Interface [S]
000684H
AWR1 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000688H
AWR2 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X- External Bus
Interface [S]
00068CH
AWR3 [R/W] W
----XXXX XXXXXXXX XXXXXXXX XXXXX-X-
000690H
to
0006FCH
― ― ― ― Reserved [S]
000700H
to
00070CH
― ― ― ― Reserved
Document Number: 002-04662 Rev. *D Page 67 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000710H
BPCCRA [R/W] B
00000000
BPCCRB [R/W] B
00000000
BPCCRC [R/W] B
00000000 ―
Bus Performance
Counter
000714H
BPCTRA [R/W] W
00000000 00000000 00000000 00000000
000718H
BPCTRB [R/W] W
00000000 00000000 00000000 00000000
00071CH
BPCTRC [R/W] W
00000000 00000000 00000000 00000000
000720H
to
0007F8H
― ― ― ― Reserved
0007FCH
BMODR [R] B, H, W
XXXXXXXX ― ― ― Mode Register
000800H
to
00083CH
― ― ― ― Reserved [S]
000840H
FCTLR [R/W] H
-0--1000 0--0---- ― FSTR [R/W] B
-----001
Flash Memory
Register [S]
000844H
to
000854H
― ― ― ― Reserved [S]
000858H
― ― WREN [R/W] H
00000000 00000000 Wild Register [S]
00085CH
to
00087CH
― ― ― ― Reserved [S]
000880H
WRAR00 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild Register [S]
000884H
WRDR00 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000888H
WRAR01 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00088CH
WRDR01 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000890H
WRAR02 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild Register [S]
000894H
WRDR02 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000898H
WRAR03 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
00089CH
WRDR03 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04662 Rev. *D Page 68 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0008A0H
WRAR04 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Wild Register [S]
0008A4H
WRDR04 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008A8H
WRAR05 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ACH
WRDR05 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B0H
WRAR06 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008B4H
WRDR06 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008B8H
WRAR07 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008BCH
WRDR07 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008C0H
WRAR08 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008C4H
WRDR08 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008C8H
WRAR09 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008CCH
WRDR09 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008D0H
WRAR10 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008D4H
WRDR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008D8H
WRAR11 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008DCH
WRDR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E0H
WRAR12 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008E4H
WRDR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008E8H
WRAR13 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008ECH
WRDR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0008F0H
WRAR14 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
Document Number: 002-04662 Rev. *D Page 69 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0008F4H
WRDR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Wild Register [S]
0008F8H
WRAR15 [R/W] W
-------- --XXXXXX XXXXXXXX XXXXXX--
0008FCH
WRDR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000900H
TPUUNLOCK [R/W] W
00000000 00000000 00000000 00000000
Time Protection
Unit [S]
000904H
TPULST [R] B,H,W
-------0 ―
TPUVST [R/W]
B,H,W
-----000
―
000908H
TPUCFG [R/W] B,H,W
-------0 0-000000 -------- -------0
00090CH
TPUTIR [R] B,H,W
00000000 ― ― ―
000910H
TPUTST [R] B,H,W
00000000 ― ― ―
000914H
TPUTIE [R/W] B,H,W
00000000 ― ― ―
000918H
TPUTMID [R] B,H,W
00000000 00000000 00000000 00000000
00091CH
to
00092CH
― ― ― ―
000930H
TPUTCN00 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000934H
TPUTCN01 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000938H
TPUTCN02 [R/W] B,H,W
000000-- 00000000 00000000 00000000
00093CH
TPUTCN03 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000940H
TPUTCN04 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000944H
TPUTCN05 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000948H
TPUTCN06 [R/W] B,H,W
000000-- 00000000 00000000 00000000
00094CH
TPUTCN07 [R/W] B,H,W
000000-- 00000000 00000000 00000000
000950H
TPUTCN10 [R/W]
B,H,W
---00000
― ― ―
Document Number: 002-04662 Rev. *D Page 70 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000954H
TPUTCN11 [R/W]
B,H,W
---00000
― ― ―
Time Protection
Unit [S]
000958H
TPUTCN12 [R/W]
B,H,W
---00000
― ― ―
00095CH
TPUTCN13 [R/W]
B,H,W
---00000
― ― ―
000960H
TPUTCN14 [R/W]
B,H,W
---00000
― ― ―
000964H
TPUTCN15 [R/W]
B,H,W
---00000
― ― ―
000968H
TPUTCN16 [R/W]
B,H,W
---00000
― ― ―
00096CH
TPUTCN17 [R/W]
B,H,W
---00000
― ― ―
000970H
TPUTCC0 [R] B,H,W
-------- 00000000 00000000 00000000
000974H
TPUTCC1 [R] B,H,W
-------- 00000000 00000000 00000000
000978H
TPUTCC2 [R] B,H,W
-------- 00000000 00000000 00000000
00097CH
TPUTCC3 [R] B,H,W
-------- 00000000 00000000 00000000
000980H
TPUTCC4 [R] B,H,W
-------- 00000000 00000000 00000000
000984H
TPUTCC5 [R] B,H,W
-------- 00000000 00000000 00000000
000988H
TPUTCC6 [R] B,H,W
-------- 00000000 00000000 00000000
00098CH
TPUTCC7 [R] B,H,W
-------- 00000000 00000000 00000000
000990H
to
0009FCH
― ― ― ―
000A00H
to
000BECH
― ― ― ― Reserved
000BF0H
HSCFR [R/W] B,H,W
-------- ------00 00000000 00000000
OCDU
000BF4H
― ― ― ―
Document Number: 002-04662 Rev. *D Page 71 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000BF8H
― ― MBR [R/W] B,H,W
00------ XXXXXXXX
OCDU
000BFCH
― ― UER [W] B,H,W
-------- -------X
000C00H
DCCR0 [R/W] W
0----000 --00--00 00000000 0-000000
DMA
Controller
[S]
000C04H
DCSR0 [R/W] H
0------- -----000
DTCR0 [R/W] H
00000000 00000000
000C08H
DSAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C0CH
DDAR0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C10H
DCCR1 [R/W] W
0----000 --00--00 00000000 0-000000
000C14H
DCSR1 [R/W] H
0------- -----000
DTCR1 [R/W] H
00000000 00000000
000C18H
DSAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C1CH
DDAR1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C20H
DCCR2 [R/W] W
0----000 --00--00 00000000 0-000000
000C24H
DCSR2 [R/W] H
0------- -----000
DTCR2 [R/W] H
00000000 00000000
000C28H
DSAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C2CH
DDAR2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C30H
DCCR3 [R/W] W
0----000 --00--00 00000000 0-000000
000C34H
DCSR3 [R/W] H
0------- -----000
DTCR3 [R/W] H
00000000 00000000
000C38H
DSAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C3CH
DDAR3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C40H
DCCR4 [R/W] W
0----000 --00--00 00000000 0-000000
000C44H
DCSR4 [R/W] H
0------- -----000
DTCR4 [R/W] H
00000000 00000000
000C48H
DSAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04662 Rev. *D Page 72 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000C4CH
DDAR4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMA
Controller
[S]
000C50H
DCCR5 [R/W] W
0----000 --00--00 00000000 0-000000
000C54H
DCSR5 [R/W] H
0------- -----000
DTCR5 [R/W] H
00000000 00000000
000C58H
DSAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C5CH
DDAR5 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C60H
DCCR6 [R/W] W
0----000 --00--00 00000000 0-000000
000C64H
DCSR6 [R/W] H
0------- -----000
DTCR6 [R/W] H
00000000 00000000
000C68H
DSAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C6CH
DDAR6 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C70H
DCCR7 [R/W] W
0----000 --00--00 00000000 0-000000
000C74H
DCSR7 [R/W] H
0------- -----000
DTCR7 [R/W] H
00000000 00000000
000C78H
DSAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C7CH
DDAR7 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C80H
DCCR8 [R/W] W
0----000 --00--00 00000000 0-000000
000C84H
DCSR8 [R/W] H
0------- -----000
DTCR8 [R/W] H
00000000 00000000
000C88H
DSAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C8CH
DDAR8 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C90H
DCCR9 [R/W] W
0----000 --00--00 00000000 0-000000
000C94H
DCSR9 [R/W] H
0------- -----000
DTCR9 [R/W] H
00000000 00000000
000C98H
DSAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000C9CH
DDAR9 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04662 Rev. *D Page 73 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000CA0H
DCCR10 [R/W] W
0----000 --00--00 00000000 0-000000
DMA
Controller
[S]
000CA4H
DCSR10 [R/W] H
0------- -----000
DTCR10 [R/W] H
00000000 00000000
000CA8H
DSAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CACH
DDAR10 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CB0H
DCCR11 [R/W] W
0----000 --00--00 00000000 0-000000
000CB4H
DCSR11 [R/W] H
0------- -----000
DTCR11 [R/W] H
00000000 00000000
000CB8H
DSAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CBCH
DDAR11 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CC0H
DCCR12 [R/W] W
0----000 --00--00 00000000 0-000000
000CC4H
DCSR12 [R/W] H
0------- -----000
DTCR12 [R/W] H
00000000 00000000
000CC8H
DSAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CCC
H
DDAR12 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CD0H
DCCR13 [R/W] W
0----000 --00--00 00000000 0-000000
000CD4H
DCSR13 [R/W] H
0------- -----000
DTCR13 [R/W] H
00000000 00000000
000CD8H
DSAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CDC
H
DDAR13 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CE0H
DCCR14 [R/W] W
0----000 --00--00 00000000 0-000000
000CE4H
DCSR14 [R/W] H
0------- -----000
DTCR14 [R/W] H
00000000 00000000
000CE8H
DSAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CECH
DDAR14 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04662 Rev. *D Page 74 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000CF0H
DCCR15 [R/W] W
0----000 --00--00 00000000 0-000000
DMA
Controller
[S]
000CF4H
DCSR15 [R/W] H
0------- -----000
DTCR15 [R/W] H
00000000 00000000
000CF8H
DSAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000CFCH
DDAR15 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000D00H
to
000DF0H
― ― ― ― Reserved [S]
000DF4H
― ― DNMIR [R/W] B
0------0
DILVR [R/W] B
---11111 DMA
Controller
[S]
000DF8H
DMACR[R/W] W
0------- -------- 0------- --------
000DFCH
― ― ― ― Reserved [S]
000E00H
DDR00 [R/W] B,H,W
00000000
DDR01 [R/W] B,H,W
00000000
DDR02 [R/W] B,H,W
00000000
DDR03 [R/W] B,H,W
00000000 Data Direction
Register
000E04H
DDR04 [R/W] B,H,W
00000000
DDR05 [R/W] B,H,W
00000000
DDR06 [R/W] B,H,W
00000000
DDR07 [R/W] B,H,W
00000000
000E08H
DDR08 [R/W] B,H,W
00000000
DDR09 [R/W] B,H,W
00000000
DDR10 [R/W] B,H,W
00000000
DDR11 [R/W] B,H,W
00000000
Data Direction
Register
000E0CH
DDR12 [R/W] B,H,W
00000000
DDR13 [R/W] B,H,W
-0000000
DDR14 [R/W] B,H,W
---000--
DDR15 [R/W] B,H,W
--000000
000E10H
―
―
―
―
000E14H
―
―
―
―
000E18H
DDR16 [R/W] B,H,W
00000000
DDR17 [R/W] B,H,W
00000000
DDR18 [R/W] B,H,W
00000000
DDR19 [R/W] B,H,W
00000000
000E1CH
―
―
―
―
Reserved
000E20H
PFR00 [R/W] B,H,W
00000000
PFR01 [R/W] B,H,W
00000000
PFR02 [R/W] B,H,W
00000000
PFR03 [R/W] B,H,W
00000000
Port Function
Register
000E24H
PFR04 [R/W] B,H,W
00000000
PFR05 [R/W] B,H,W
00000000
PFR06 [R/W] B,H,W
00000000
PFR07 [R/W] B,H,W
00000000
000E28H
PFR08 [R/W] B,H,W
00000000
PFR09 [R/W] B,H,W
00000000
PFR10 [R/W] B,H,W
00000000
PFR11 [R/W] B,H,W
00000000
000E2CH
PFR12 [R/W] B,H,W
00000000
PFR13 [R/W] B,H,W
-0000000
PFR14 [R/W] B,H,W
---000--
PFR15 [R/W] B,H,W
--000000
000E30H
―
―
―
―
000E34H
―
―
―
―
000E38H
PFR16 [R/W] B,H,W
00000000
PFR17 [R/W] B,H,W
00000000
PFR18 [R/W] B,H,W
00000000
PFR19 [R/W] B,H,W
00000000
Document Number: 002-04662 Rev. *D Page 75 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000E3CH
―
―
―
―
Reserved
000E40H
PDDR00 [R] B,H,W
XXXXXXXX
PDDR01 [R] B,H,W
XXXXXXXX
PDDR02 [R] B,H,W
XXXXXXXX
PDDR03 [R] B,H,W
XXXXXXXX
Port Direct
Read Register
000E44H
PDDR04 [R] B,H,W
XXXXXXXX
PDDR05 [R] B,H,W
XXXXXXXX
PDDR06 [R] B,H,W
XXXXXXXX
PDDR07 [R] B,H,W
XXXXXXXX
000E48H
PDDR08 [R] B,H,W
XXXXXXXX
PDDR09 [R] B,H,W
XXXXXXXX
PDDR10 [R] B,H,W
XXXXXXXX
PDDR11 [R] B,H,W
XXXXXXXX
000E4CH
PDDR12 [R] B,H,W
XXXXXXXX
PDDR13 [R] B,H,W
-XXXXXXX
PDDR14 [R] B,H,W
---XXX--
PDDR15 [R] B,H,W
--XXXXXX
000E50H
―
―
―
―
000E54H
―
―
―
―
000E58H
PDDR16 [R] B,H,W
XXXXXXXX
PDDR17 [R] B,H,W
XXXXXXXX
PDDR18 [R] B,H,W
XXXXXXXX
PDDR19 [R] B,H,W
XXXXXXXX
000E5CH
―
―
―
―
Reserved
000E60H
EPFR00 [R/W]
B,H,W
00000000
EPFR01 [R/W]
B,H,W
-0-0-000
EPFR02 [R/W]
B,H,W
----0000
EPFR03 [R/W]
B,H,W
---000-0
Extended Port
Function Register
000E64H
EPFR04 [R/W]
B,H,W
----00-0
EPFR05 [R/W]
B,H,W
----0000
EPFR06 [R/W]
B,H,W
----000-
EPFR07 [R/W]
B,H,W
---00000
000E68H
EPFR08 [R/W]
B,H,W
---00000
EPFR09 [R/W]
B,H,W
-----00-
EPFR10 [R/W]
B,H,W
----0000
EPFR11 [R/W]
B,H,W
----0000
000E6CH
EPFR12 [R/W]
B,H,W
----0000
EPFR13 [R/W]
B,H,W
------00
EPFR14 [R/W]
B,H,W
------00
EPFR15 [R/W]
B,H,W
-----000
000E70H
―
―
―
―
000E74H
―
―
―
―
000E78H
― ―
EPFR26 [R/W]
B,H,W
00000000
EPFR27 [R/W]
B,H,W
---0----
000E7CH
EPFR28 [R/W]
B,H,W
--000-0-
EPFR29 [R/W]
B,H,W
00000000
― ―
000E80H
―
EPFR33 [R/W]
B,H,W
-----00-
EPFR34 [R/W]
B,H,W
-----00-
EPFR35 [R/W]
B,H,W
---00000
000E84H
EPFR36 [R/W]
B,H,W
----000-
― ― ―
000E88H
― ―
EPFR42 [R/W]
B,H,W
------00
EPFR43 [R/W]
B,H,W
0--0000-
000E8CH
EPFR44 [R/W]
B,H,W
-00---0-
EPFR45 [R/W]
B,H,W
-0000000
― ―
000E90H
―
―
―
―
Document Number: 002-04662 Rev. *D Page 76 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000E94H
―
―
―
―
Extended Port
Function Register
000E98H
EPFR56 [R/W]
B,H,W
-----0-0
EPFR57 [R/W]
B,H,W
----00-0
EPFR58 [R/W]
B,H,W
----00-0
EPFR59 [R/W]
B,H,W
----00-0
000E9CH
EPFR60 [R/W]
B,H,W
----00-0
EPFR61 [R/W]
B,H,W
-----00-
EPFR62 [R/W]
B,H,W
-----00-
EPFR63 [R/W]
B,H,W
---0000-
000EA0H
to
000EBCH
― ― ― ― Reserved
000EC0H
PPER00 [R/W]
B,H,W
00000000
PPER01 [R/W]
B,H,W
00000000
PPER02 [R/W]
B,H,W
00000000
PPER03 [R/W]
B,H,W
00000000
Port Pull
-
up/down
Enable Register
000EC4H
PPER04 [R/W]
B,H,W
00000000
PPER05 [R/W]
B,H,W
00000000
PPER06 [R/W]
B,H,W
00000000
PPER07 [R/W]
B,H,W
00000000
000EC8H
PPER08 [R/W]
B,H,W
00000000
PPER09 [R/W]
B,H,W
00000000
PPER10 [R/W]
B,H,W
00000000
PPER11 [R/W]
B,H,W
00000000
000ECCH
PPER12 [R/W]
B,H,W
00000000
PPER13 [R/W]
B,H,W
-0000000
PPER14 [R/W]
B,H,W
---000--
PPER15 [R/W]
B,H,W
--000000
000ED0H
―
―
―
―
000ED4H
―
―
―
―
000ED8H
PPER16 [R/W]
B,H,W
00000000
PPER17 [R/W]
B,H,W
00000000
PPER18 [R/W]
B,H,W
00000000
PPER19 [R/W]
B,H,W
00000000
000EDCH
to
000F3CH
― ― ― ― Reserved
000F40H
PORTEN [R/W]
B,H,W
-------0
― ― ― Port Enable
Register
000F44H
KEYCDR [R/W] H
00000000 00000000 ― ―
KeyCodeRegister
000F48H
to
000F64H
― ― ― ― Reserved
000F68H
MSCY6 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input
Capture 6,7
Cycle
measurement
data register 67
000F6CH
MSCY7 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Document Number: 002-04662 Rev. *D Page 77 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000F70H
RCRH0 [W] H,W
XXXXXXXX
RCRL0 [W] B,H,W
XXXXXXXX
UDCRH0 [R] H,W
00000000
UDCRL0 [R] B,H,W
00000000 Up/Down
Counter 0
000F74H
CCR0 [R/W] B,H
00000000 -0001000 ― CSR0 [R/W] B
00000000
000F78H
to
000F7CH
― ― ― ― Reserved
000F80H
RCRH1 [W] H,W
XXXXXXXX
RCRL1 [W] B,H,W
XXXXXXXX
UDCRH1 [R] H,W
00000000
UDCRL1 [R] B,H,W
00000000 Up/Down
Counter 1
000F84H
CCR1 [R/W] B,H
00000000 -0001000 ― CSR1 [R/W] B
00000000
000F88H
― ―
MSCH45 [R]
B,H,W
00000000
MSCL45 [R/W]
B,H,W
------00
Input C
apture 4,5
32-bit ICU
Cycle and pulse
width
measurement
control 45
000F8CH
― ―
MSCH67 [R]
B,H,W
00000000
MSCL67 [R/W]
B,H,W
------00
Input Capture 6,7
32-bit ICU
Cycle and pulse
width
measurement
control 67
000F90H
OCCP10 [R/W] W
00000000 00000000 00000000 00000000
Output Compare
10,11
32-bit OCU
000F94H
OCCP11 [R/W] W
00000000 00000000 00000000 00000000
000F98H
― ―
OCSH1011 [R/W]
B,H,W
---0--00
OCSL1011 [R/W]
B,H,W
0000--00
Output Compare
10,11
32-bit OCU
000F9CH
―
―
―
OCLS1011 [R/W]
B,H,W
----0000
OCU1011
Output level
control register
000FA0H
CPCLR5 [R/W] W
11111111 11111111 11111111 11111111
Free-run Timer 5
32-bit FRT
000FA4H
TCDT5 [R/W] W
00000000 00000000 00000000 00000000
000FA8H
TCCSH5
[R/W]B,H,W
0-----00
TCCSL5 [R/W]B,H,W
-1-00000 ― ―
000FACH
to
000FCCH
― ― ― ― Reserved
Document Number: 002-04662 Rev. *D Page 78 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
000FD0H
IPCP4 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Input
Capture 4,5
32-bit ICU
000FD4H
IPCP5 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000FD8H
― ―
LSYNS1 [R/W]
B,H,W
00000000
ICS45 [R/W] B,H,W
00000000
000FDCH
IPCP6 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Input
Capture 6,7
32-bit ICU
000FE0H
IPCP7 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000FE4H
― ― ― ICS67 [R/W] B,H,W
00000000
000FE8H
IPCP8 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Input
Capture 8,9
32-bit ICU
000FECH
IPCP9 [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000FF0H
― ― ― ICS89 [R/W] B,H,W
00000000
000FF4H
MSCY8 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Input
Capture 8,9
32-bit ICU
Cycle
measurement
data register 89
000FF8H
MSCY9 [R] H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000FFCH
― ― MSCH89 [R] B,H,W
00000000
MSCL89 [R/W]
B,H,W
------00
Cycle and pulse
width
measurement
control 89
001000H
SACR [R/W] B,H,W
-------0
PICD [R/W] B,H,W
----0011
― ― Clock Control
001004H
to
00112CH
― ― ― ― Reserved
001130H ― ― ― CRCCR [R/W] B,H,W
-0000000
CRC calculation
unit
001134H CRCINIT [R/W] B,H,W
11111111 11111111 11111111 11111111
001138H CRCIN [R/W] B,H,W
00000000 00000000 00000000 00000000
00113CH
CRCR [R] B,H,W
11111111 11111111 11111111 11111111
001140H
to
0011FCH
― ― ― ― Reserved
Document Number: 002-04662 Rev. *D Page 79 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001200H
TCGS [R/W] B,H,W
------00 ― ― TCGSE [R/W] B,H,W
-----000
16-bit Free-run
timer
synchronous
activation
001204H
CPCLRB0/CPCLR0 [W] H,W
11111111 11111111
TCDT0 [R/W] H,W
00000000 00000000 16-bit Free-run
Timer 0
001208H
TCCS0 [R/W] B,H,W
00000000 01000000 ----0000 --------
00120CH
CPCLRB1/CPCLR1 [W] H,W
11111111 11111111
TCDT1 [R/W] H,W
00000000 00000000 16-bit Free-run
Timer 1
001210H
TCCS1 [R/W] B,H,W
00000000 01000000 ----0000 --------
001214H
CPCLRB2/CPCLR2 [W] H,W
11111111 11111111
TCDT2 [R/W] H,W
00000000 00000000 16-bit Free-run
Timer 2
001218H
TCCS2 [R/W] B,H,W
00000000 01000000 ----0000 --------
00121CH
to
001230H
― ― ― ― Reserved
001234H
FRS0 [R/W] B,H,W
-------- --00--00 --00--00 --00--00
16-bit Free-run
timer selection
001238H
― FRS1 [R/W] B,H,W
--00--00 --00--00
00123CH
FRS2 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
001240H
FRS3 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
001244H
FRS4 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
001248H
―
―
―
―
Reserved
00124CH
OCCPB0/OCCP0 [R/W] H,W
00000000 00000000
OCCPB1/OCCP1 [R/W] H,W
00000000 00000000 16-bit Output
compare 0/1
001250H
OCS01 [R/W] B,H,W
-110--00 00001100 ―
OCMOD01 [R/W]
B,H,W
------00
001254H
OCCPB2/OCCP2 [R/W] H,W
00000000 00000000
OCCPB3/OCCP3 [R/W] H,W
00000000 00000000 16-bit Output
compare 2/3
001258H
OCS23 [R/W] B,H,W
-110--00 00001100 ―
OCMOD23 [R/W]
B,H,W
------00
Document Number: 002-04662 Rev. *D Page 80 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
00125CH
OCCPB4/OCCP4 [R/W] H,W
00000000 00000000
OCCPB5/OCCP5 [R/W] H,W
00000000 00000000 16-bit Output
compare 4/5
001260H
OCS45 [R/W] B,H,W
-110--00 00001100 ―
OCMOD45 [R/W]
B,H,W
------00
001264H
to
001278H
― ― ― ― Reserved
00127CH
IPCP0 [R] H,W
00000000 00000000
IPCP1 [R] H,W
00000000 00000000 16-bit Input
capture 0/1
001280H
ICS01 [R/W] B,H,W
------00 00000000 ― LSYNS [R/W] B,H,W
----0000
001284H
IPCP2 [R] H,W
00000000 00000000
IPCP3 [R] H,W
00000000 00000000 16-bit Input
capture 2/3
001288H
ICS23 [R/W] B,H,W
------00 00000000 ― ―
00128CH
to
001298H
― ― ― ― Reserved
00129CH
― ― ― ― Reserved
0012A0H
TMRR0 [R/W] H,W
00000000 00000001
TMRR1 [R/W] H,W
00000000 00000001
Waveform
generator
0/1/2
0012A4H
TMRR2 [R/W] H,W
00000000 00000001 ― ―
0012A8H
DTSCR0 [R/W]
B,H,W
00000000
DTSCR1 [R/W]
B,H,W
00000000
DTSCR2 [R/W]
B,H,W
00000000
―
0012ACH
― DTIR0 [R/W] B,H,W
000000-- ―
DTMNS0 [R/W]
B,H,W
00---000
0012B0H
―
SIGCR10 [R/W]
B,H,W
00000000
―
SIGCR20 [R/W]
B,H,W
000000-1
0012B4H
PICS0 [R/W] B,H,W
000000-- -------- -------- --------
0012B8H
to
0012CCH
― ― ― ― Reserved
0012D0H
FRS5 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
16-bit Free-run
timer selection
A/D activation
compare
Document Number: 002-04662 Rev. *D Page 81 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0012D4H
FRS6 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
16-bit Free-run
timer selection
A/D activation
compare
0012D8H
FRS7 [R/W] B,H,W
--00--00 --00--00 --00--00 --00--00
0012DCH
to
0012FCH
― ― ― ― Reserved
001300H
― Reserved
001304H
ADTSS0[R/W]
B,H,W
-------0
― ― ―
12-bit A/D
converter 1/2 unit
001308H
ADTSE0[R/W] B,H,W
00000000 00000000 00000000 00000000
00130CH
ADCOMP0/ADCOMPB0[R/W] H,W
00000000 00000000
ADCOMP1/ADCOMPB1[R/W] H,W
00000000 00000000
12-bit A/D
converter 1/2 unit
001310H
ADCOMP2/ADCOMPB2[R/W] H,W
00000000 00000000
ADCOMP3/ADCOMPB3[R/W] H,W
00000000 00000000
001314H
ADCOMP4/ADCOMPB4[R/W] H,W
00000000 00000000
ADCOMP5/ADCOMPB5[R/W] H,W
00000000 00000000
001318H
ADCOMP6/ADCOMPB6[R/W] H,W
00000000 00000000
ADCOMP7/ADCOMPB7[R/W] H,W
00000000 00000000
00131CH
ADCOMP8/ADCOMPB8[R/W] H,W
00000000 00000000
ADCOMP9/ADCOMPB9[R/W] H,W
00000000 00000000
001320H
ADCOMP10/ADCOMPB10[R/W] H,W
00000000 00000000
ADCOMP11/ADCOMPB11[R/W] H,W
00000000 00000000
001324H
ADCOMP12/ADCOMPB12[R/W] H,W
00000000 00000000
ADCOMP13/ADCOMPB13[R/W] H,W
00000000 00000000
001328H
ADCOMP14/ADCOMPB14[R/W] H,W
00000000 00000000
ADCOMP15/ADCOMPB15[R/W] H,W
00000000 00000000
00132CH
ADCOMP16/ADCOMPB16[R/W] H,W
00000000 00000000
ADCOMP17/ADCOMPB17[R/W] H,W
00000000 00000000
001330H
ADCOMP18/ADCOMPB18[R/W] H,W
00000000 00000000
ADCOMP19/ADCOMPB19[R/W] H,W
00000000 00000000
001334H
ADCOMP20/ADCOMPB20[R/W] H,W
00000000 00000000
ADCOMP21/ADCOMPB21[R/W] H,W
00000000 00000000
001338H
ADCOMP22/ADCOMPB22[R/W] H,W
00000000 00000000
ADCOMP23/ADCOMPB23[R/W] H,W
00000000 00000000
00133CH
ADCOMP24/ADCOMPB24[R/W] H,W
00000000 00000000
ADCOMP25/ADCOMPB25[R/W] H,W
00000000 00000000
001340H
ADCOMP26/ADCOMPB26[R/W] H,W
00000000 00000000
ADCOMP27/ADCOMPB27[R/W] H,W
00000000 00000000
Document Number: 002-04662 Rev. *D Page 82 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001344H
ADCOMP28/ADCOMPB28[R/W] H,W
00000000 00000000
ADCOMP29/ADCOMPB29[R/W] H,W
00000000 00000000
12-bit A/D
converter 1/2 unit
001348H
ADCOMP30/ADCOMPB30[R/W] H,W
00000000 00000000
ADCOMP31/ADCOMPB31[R/W] H,W
00000000 00000000
00134CH
ADTCS0[R/W] B,H,W
00000000 0010----
ADTCS1[R/W] B,H,W
00000000 0010----
001350H
ADTCS2[R/W] B,H,W
00000000 0010----
ADTCS3[R/W] B,H,W
00000000 0010----
001354H
ADTCS4[R/W] B,H,W
00000000 0010----
ADTCS5[R/W] B,H,W
00000000 0010----
001358H
ADTCS6[R/W] B,H,W
00000000 0010----
ADTCS7[R/W] B,H,W
00000000 0010----
00135CH
ADTCS8[R/W] B,H,W
00000000 0010----
ADTCS9[R/W] B,H,W
00000000 0010----
001360H
ADTCS10[R/W] B,H,W
00000000 0010----
ADTCS11[R/W] B,H,W
00000000 0010----
001364H
ADTCS12[R/W] B,H,W
00000000 0010----
ADTCS13[R/W] B,H,W
00000000 0010----
001368H
ADTCS14[R/W] B,H,W
00000000 0010----
ADTCS15[R/W] B,H,W
00000000 0010----
00136CH
ADTCS16[R/W] B,H,W
00000000 0010----
ADTCS17[R/W] B,H,W
00000000 0010----
001370H
ADTCS18[R/W] B,H,W
00000000 0010----
ADTCS19[R/W] B,H,W
00000000 0010----
001374H
ADTCS20[R/W] B,H,W
00000000 0010----
ADTCS21[R/W] B,H,W
00000000 0010----
001378H
ADTCS22[R/W] B,H,W
00000000 0010----
ADTCS23[R/W] B,H,W
00000000 0010----
00137CH
ADTCS24[R/W] B,H,W
00000000 0010----
ADTCS25[R/W] B,H,W
00000000 0010----
001380H
ADTCS26[R/W] B,H,W
00000000 0010----
ADTCS27[R/W] B,H,W
00000000 0010----
001384H
ADTCS28[R/W] B,H,W
00000000 0010----
ADTCS29[R/W] B,H,W
00000000 0010----
001388H
ADTCS30[R/W] B,H,W
00000000 0010----
ADTCS31[R/W] B,H,W
00000000 0010----
00138CH
ADTCD0[R] B,H,W
10--0000 00000000
ADTCD1[R] B,H,W
10--0000 00000000
001390H
ADTCD2[R] B,H,W
10--0000 00000000
ADTCD3[R] B,H,W
10--0000 00000000
Document Number: 002-04662 Rev. *D Page 83 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001394H
ADTCD4[R] B,H,W
10--0000 00000000
ADTCD5[R] B,H,W
10--0000 00000000
12-bit A/D
converter 1/2 unit
001398H
ADTCD6[R] B,H,W
10--0000 00000000
ADTCD7[R] B,H,W
10--0000 00000000
00139CH
ADTCD8[R] B,H,W
10--0000 00000000
ADTCD9[R] B,H,W
10--0000 00000000
0013A0H
ADTCD10[R] B,H,W
10--0000 00000000
ADTCD11[R] B,H,W
10--0000 00000000
0013A4H
ADTCD12[R] B,H,W
10--0000 00000000
ADTCD13[R] B,H,W
10--0000 00000000
0013A8H
ADTCD14[R] B,H,W
10--0000 00000000
ADTCD15[R] B,H,W
10--0000 00000000
0013ACH
ADTCD16[R] B,H,W
10--0000 00000000
ADTCD17[R] B,H,W
10--0000 00000000
0013B0H
ADTCD18[R] B,H,W
10--0000 00000000
ADTCD19[R] B,H,W
10--0000 00000000
0013B4H
ADTCD20[R] B,H,W
10--0000 00000000
ADTCD21[R] B,H,W
10--0000 00000000
0013B8H
ADTCD22[R] B,H,W
10--0000 00000000
ADTCD23[R] B,H,W
10--0000 00000000
0013BCH
ADTCD24[R] B,H,W
10--0000 00000000
ADTCD25[R] B,H,W
10--0000 00000000
0013C0H
ADTCD26[R] B,H,W
10--0000 00000000
ADTCD27[R] B,H,W
10--0000 00000000
0013C4H
ADTCD28[R] B,H,W
10--0000 00000000
ADTCD29[R] B,H,W
10--0000 00000000
0013C8H
ADTCD30[R] B,H,W
10--0000 00000000
ADTCD31[R] B,H,W
10--0000 00000000
0013CCH
ADTECS0[R/W] B,H,W
-------0 ---00000
ADTECS1[R/W] B,H,W
-------0 ---00000
0013D0H
ADTECS2[R/W] B,H,W
-------0 ---00000
ADTECS3[R/W] B,H,W
-------0 ---00000
0013D4H
ADTECS4[R/W] B,H,W
-------0 ---00000
ADTECS5[R/W] B,H,W
-------0 ---00000
0013D8H
ADTECS6[R/W] B,H,W
-------0 ---00000
ADTECS7[R/W] B,H,W
-------0 ---00000
0013DCH
ADTECS8[R/W] B,H,W
-------0 ---00000
ADTECS9[R/W] B,H,W
-------0 ---00000
0013E0H
ADTECS10[R/W] B,H,W
-------0 ---00000
ADTECS11[R/W] B,H,W
-------0 ---00000
0013E4H
ADTECS12[R/W] B,H,W
-------0 ---00000
ADTECS13[R/W] B,H,W
-------0 ---00000
Document Number: 002-04662 Rev. *D Page 84 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0013E8H
ADTECS14[R/W] B,H,W
-------0 ---00000
ADTECS15[R/W] B,H,W
-------0 ---00000
12-bit A/D
converter 1/2 unit
0013ECH
ADTECS16[R/W] B,H,W
-------0 ---00000
ADTECS17[R/W] B,H,W
-------0 ---00000
0013F0H
ADTECS18[R/W] B,H,W
-------0 ---00000
ADTECS19[R/W] B,H,W
-------0 ---00000
0013F4H
ADTECS20[R/W] B,H,W
-------0 ---00000
ADTECS21[R/W] B,H,W
-------0 ---00000
0013F8H
ADTECS22[R/W] B,H,W
-------0 ---00000
ADTECS23[R/W] B,H,W
-------0 ---00000
0013FCH
ADTECS24[R/W] B,H,W
-------0 ---00000
ADTECS25[R/W] B,H,W
-------0 ---00000
001400H
ADTECS26[R/W] B,H,W
-------0 ---00000
ADTECS27[R/W] B,H,W
-------0 ---00000
001404H
ADTECS28[R/W] B,H,W
-------0 ---00000
ADTECS29[R/W] B,H,W
-------0 ---00000
001408H
ADTECS30[R/W] B,H,W
-------0 ---00000
ADTECS31[R/W] B,H,W
-------0 ---00000
00140CH
ADRCUT0[R/W] B,H,W
----0000 00000000
ADRCLT0[R/W] B,H,W
----0000 00000000
001410H
ADRCUT1[R/W] B,H,W
----0000 00000000
ADRCLT1[R/W] B,H,W
----0000 00000000
001414H
ADRCUT2[R/W] B,H,W
----0000 00000000
ADRCLT2[R/W] B,H,W
----0000 00000000
001418H
ADRCUT3[R/W] B,H,W
----0000 00000000
ADRCLT3[R/W] B,H,W
----0000 00000000
00141CH
ADRCCS0[R/W]
B,H,W
00000000
ADRCCS1[R/W]
B,H,W
00000000
ADRCCS2[R/W]
B,H,W
00000000
ADRCCS3[R/W]
B,H,W
00000000
001420H
ADRCCS4[R/W]
B,H,W
00000000
ADRCCS5[R/W]
B,H,W
00000000
ADRCCS6[R/W]
B,H,W
00000000
ADRCCS7[R/W]
B,H,W
00000000
001424H
ADRCCS8[R/W]
B,H,W
00000000
ADRCCS9[R/W]
B,H,W
00000000
ADRCCS10[R/W]
B,H,W
00000000
ADRCCS11[R/W]
B,H,W
00000000
001428H
ADRCCS12[R/W]
B,H,W
00000000
ADRCCS13[R/W]
B,H,W
00000000
ADRCCS14[R/W]
B,H,W
00000000
ADRCCS15[R/W]
B,H,W
00000000
00142CH
ADRCCS16[R/W]
B,H,W
00000000
ADRCCS17[R/W]
B,H,W
00000000
ADRCCS18[R/W]
B,H,W
00000000
ADRCCS19[R/W]
B,H,W
00000000
001430H
ADRCCS20[R/W]
B,H,W
00000000
ADRCCS21[R/W]
B,H,W
00000000
ADRCCS22[R/W]
B,H,W
00000000
ADRCCS23[R/W]
B,H,W
00000000
Document Number: 002-04662 Rev. *D Page 85 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001434H
ADRCCS24[R/W]
B,H,W
00000000
ADRCCS25[R/W]
B,H,W
00000000
ADRCCS26[R/W]
B,H,W
00000000
ADRCCS27[R/W]
B,H,W
00000000
12-bit A/D
converter 1/2 unit
001438H
ADRCCS28[R/W]
B,H,W
00000000
ADRCCS29[R/W]
B,H,W
00000000
ADRCCS30[R/W]
B,H,W
00000000
ADRCCS31[R/W]
B,H,W
00000000
00143CH
ADRCOT0[R] B,H,W
00000000 00000000 00000000 00000000
001440H
ADRCIF0[R,W] B,H,W
00000000 00000000 00000000 00000000
001444H
ADSCANS0[R/W]
B,H,W
000-----
― ― ―
001448H
ADNCS0[R/W]
B,H,W
0-000-00
ADNCS1[R/W]
B,H,W
0-000-00
ADNCS2[R/W]
B,H,W
0-000-00
ADNCS3[R/W]
B,H,W
0-000-00
00144CH
ADNCS4[R/W]
B,H,W
0-000-00
ADNCS5[R/W]
B,H,W
0-000-00
ADNCS6[R/W]
B,H,W
0-000-00
ADNCS7[R/W]
B,H,W
0-000-00
001450H
ADNCS8[R/W]
B,H,W
0-000-00
ADNCS9[R/W]
B,H,W
0-000-00
ADNCS10[R/W]
B,H,W
0-000-00
ADNCS11[R/W]
B,H,W
0-000-00
001454H
ADNCS12[R/W]
B,H,W
0-000-00
ADNCS13[R/W]
B,H,W
0-000-00
ADNCS14[R/W]
B,H,W
0-000-00
ADNCS15[R/W]
B,H,W
0-000-00
001458H
ADPRTF0[R] B,H,W
00000000 00000000 00000000 00000000
00145CH
ADEOCF0[R] B,H,W
11111111 11111111 11111111 11111111
001460H
ADCS0[R] B,H,W
0------- --------
ADCH0[R] B,H,W
---00000
ADMD0[R/W] B,H,W
0---0000
001464H
ADSTPCS0[R/W]
B,H,W
00000000
ADSTPCS1[R/W]
B,H,W
00000000
ADSTPCS2[R/W]
B,H,W
00000000
ADSTPCS3[R/W]
B,H,W
00000000
001468H
ADSTPCS4[R/W]
B,H,W
00000000
ADSTPCS5[R/W]
B,H,W
00000000
ADSTPCS6[R/W]
B,H,W
00000000
ADSTPCS7[R/W]
B,H,W
00000000
00146CH
―
12-bit A/D
converter 2/2 unit
001470H
ADTSS1[R/W]
B,H,W
-------0
― ― ―
001474H
ADTSE1[R/W] B,H,W
-------- -------- 00000000 00000000
001478H
ADCOMP32/ADCOMPB32[R/W] H,W
00000000 00000000
ADCOMP33/ADCOMPB33[R/W] H,W
00000000 00000000
Document Number: 002-04662 Rev. *D Page 86 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
00147CH
ADCOMP34/ADCOMPB34[R/W] H,W
00000000 00000000
ADCOMP35/ADCOMPB35[R/W] H,W
00000000 00000000
12-bit A/D
converter 2/2 unit
001480H
ADCOMP36/ADCOMPB36[R/W] H,W
00000000 00000000
ADCOMP37/ADCOMPB37[R/W] H,W
00000000 00000000
001484H
ADCOMP38/ADCOMPB38[R/W] H,W
00000000 00000000
ADCOMP39/ADCOMPB39[R/W] H,W
00000000 00000000
001488H
ADCOMP40/ADCOMPB40[R/W] H,W
00000000 00000000
ADCOMP41/ADCOMPB41[R/W] H,W
00000000 00000000
00148CH
ADCOMP42/ADCOMPB42[R/W] H,W
00000000 00000000
ADCOMP43/ADCOMPB43[R/W] H,W
00000000 00000000
001490H
ADCOMP44/ADCOMPB44[R/W] H,W
00000000 00000000
ADCOMP45/ADCOMPB45[R/W] H,W
00000000 00000000
001494H
ADCOMP46/ADCOMPB46[R/W] H,W
00000000 00000000
ADCOMP47/ADCOMPB47[R/W] H,W
00000000 00000000
001498H
to
0014B4H
― ― ― ― Reserved
0014B8H
ADTCS32[R/W] B,H,W
00000000 0010----
ADTCS33[R/W] B,H,W
00000000 0010----
12-bit A/D
converter 2/2 unit
0014BCH
ADTCS34[R/W] B,H,W
00000000 0010----
ADTCS35[R/W] B,H,W
00000000 0010----
0014C0H
ADTCS36[R/W] B,H,W
00000000 0010----
ADTCS37[R/W] B,H,W
00000000 0010----
0014C4H
ADTCS38[R/W] B,H,W
00000000 0010----
ADTCS39[R/W] B,H,W
00000000 0010----
0014C8H
ADTCS40[R/W] B,H,W
00000000 0010----
ADTCS41[R/W] B,H,W
00000000 0010----
0014CCH
ADTCS42[R/W] B,H,W
00000000 0010----
ADTCS43[R/W] B,H,W
00000000 0010----
0014D0H
ADTCS44[R/W] B,H,W
00000000 0010----
ADTCS45[R/W] B,H,W
00000000 0010----
0014D4H
ADTCS46[R/W] B,H,W
00000000 0010----
ADTCS47[R/W] B,H,W
00000000 0010----
0014D8H
to
0014F4H
― ― ― ― Reserved
0014F8H
ADTCD32[R] B,H,W
10--0000 00000000
ADTCD33[R] B,H,W
10--0000 00000000 12-bit A/D
converter 2/2 unit
0014FCH
ADTCD34[R] B,H,W
10--0000 00000000
ADTCD35[R] B,H,W
10--0000 00000000
Document Number: 002-04662 Rev. *D Page 87 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001500H
ADTCD36[R] B,H,W
10--0000 00000000
ADTCD37[R] B,H,W
10--0000 00000000
12-bit A/D
convert
er 2/2 unit
001504H
ADTCD38[R] B,H,W
10--0000 00000000
ADTCD39[R] B,H,W
10--0000 00000000
001508H
ADTCD40[R] B,H,W
10--0000 00000000
ADTCD41[R] B,H,W
10--0000 00000000
00150CH
ADTCD42[R] B,H,W
10--0000 00000000
ADTCD43[R] B,H,W
10--0000 00000000
001510H
ADTCD44[R] B,H,W
10--0000 00000000
ADTCD45[R] B,H,W
10--0000 00000000
001514H
ADTCD46[R] B,H,W
10--0000 00000000
ADTCD47[R] B,H,W
10--0000 00000000
001518H
to
001534H
― ― ― ― Reserved
001538H
ADTECS32[R/W] B,H,W
-------0 ----0000
ADTECS33[R/W] B,H,W
-------0 ----0000
12-bit A/D
converter 2/2 unit
00153CH
ADTECS34[R/W] B,H,W
-------0 ----0000
ADTECS35[R/W] B,H,W
-------0 ----0000
001540H
ADTECS36[R/W] B,H,W
-------0 ----0000
ADTECS37[R/W] B,H,W
-------0 ----0000
001544H
ADTECS38[R/W] B,H,W
-------0 ----0000
ADTECS39[R/W] B,H,W
-------0 ----0000
001548H
ADTECS40[R/W] B,H,W
-------0 ----0000
ADTECS41[R/W] B,H,W
-------0 ----0000
00154CH
ADTECS42[R/W] B,H,W
-------0 ----0000
ADTECS43[R/W] B,H,W
-------0 ----0000
001550H
ADTECS44[R/W] B,H,W
-------0 ----0000
ADTECS45[R/W] B,H,W
-------0 ----0000
001554H
ADTECS46[R/W] B,H,W
-------0 ----0000
ADTECS47[R/W] B,H,W
-------0 ----0000
001558H
to
001574H
― ― ― ― Reserved
001578H
ADRCUT4[R/W] B,H,W
----0000 00000000
ADRCLT4[R/W] B,H,W
----0000 00000000
12-bit A/D
converter 2/2 unit
00157CH
ADRCUT5[R/W] B,H,W
----0000 00000000
ADRCLT5[R/W] B,H,W
----0000 00000000
001580H
ADRCUT6[R/W] B,H,W
----0000 00000000
ADRCLT6[R/W] B,H,W
----0000 00000000
001584H
ADRCUT7[R/W] B,H,W
----0000 00000000
ADRCLT7[R/W] B,H,W
----0000 00000000
Document Number: 002-04662 Rev. *D Page 88 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001588H
ADRCCS32[R/W]
B,H,W
00000000
ADRCCS33[R/W]
B,H,W
00000000
ADRCCS34[R/W]
B,H,W
00000000
ADRCCS35[R/W]
B,H,W
00000000
12-bit A/D
converter 2/2 unit
00158CH
ADRCCS36[R/W]
B,H,W
00000000
ADRCCS37[R/W]
B,H,W
00000000
ADRCCS38[R/W]
B,H,W
00000000
ADRCCS39[R/W]
B,H,W
00000000
001590H
ADRCCS40[R/W]
B,H,W
00000000
ADRCCS41[R/W]
B,H,W
00000000
ADRCCS42[R/W]
B,H,W
00000000
ADRCCS43[R/W]
B,H,W
00000000
001594H
ADRCCS44[R/W]
B,H,W
00000000
ADRCCS45[R/W]
B,H,W
00000000
ADRCCS46[R/W]
B,H,W
00000000
ADRCCS47[R/W]
B,H,W
00000000
001598H
to
0015A4H
― ― ― ― Reserved
0015A8H
ADRCOT1 [R] B,H,W
-------- -------- 00000000 00000000
12-bit A/D
converter 2/2 unit
0015ACH
ADRCIF1 [R,W] B,H,W
-------- -------- 00000000 00000000
0015B0H
ADSCANS1 [R/W]
B,H,W
000-----
― ― ―
0015B4H
ADNCS16 [R/W]
B,H,W
0-000-00
ADNCS17 [R/W]
B,H,W
0-000-00
ADNCS18 [R/W]
B,H,W
0-000-00
ADNCS19 [R/W]
B,H,W
0-000-00
0015B8H
ADNCS20 [R/W]
B,H,W
0-000-00
ADNCS21 [R/W]
B,H,W
0-000-00
ADNCS22 [R/W]
B,H,W
0-000-00
ADNCS23 [R/W]
B,H,W
0-000-00
0015BCH
― ― ― ―
0015C0H
― ― ― ―
0015C4H
ADPRTF1 [R] B,H,W
-------- -------- 00000000 00000000
12-bit A/D
converter 2/2 unit
0015C8H
ADEOCF1 [R] B,H,W
-------- -------- 11111111 11111111
0015CCH
ADCS1 [R] B,H,W
0------- --------
ADCH1 [R] B,H,W
---00000
ADMD1 [R/W] B,H,W
0---0000
0015D0H
ADSTPCS8 [R/W]
B,H,W
00000000
ADSTPCS9 [R/W]
B,H,W
00000000
ADSTPCS10 [R/W]
B,H,W
00000000
ADSTPCS11 [R/W]
B,H,W
00000000
0015D4H
to
00174CH
― ― ― ― Reserved
Document Number: 002-04662 Rev. *D Page 89 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001750H
SCR0/(IBCR0)[R/W]
B,H,W
0--00000
SMR0[R/W]
B,H,W
000-00-0
SSR0[R/W]
B,H,W
0-000011
ESCR0/(IBSR0)[R/W
] B,H,W
00000000
Multi-UART0
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
001754H
― /(RDR10/(TDR10))[R/W] B,H,W
-------- -------- *3
RDR00/(TDR00)[R/W] B,H,W
-------0 00000000 *1
001758H
SACSR0[R/W] B,H,W
0----000 00000000
STMR0[R] B,H,W
00000000 00000000
00175CH
STMCR0[R/W] B,H,W
00000000 00000000
― /(SCSCR0/SFUR0)[R/W] B,H,W
-------- -------- *3 *4
001760H
― /(SCSTR30)/
(LAMSR0)
[R/W] B,H,W
--------
*3
― /(SCSTR20)/
(LAMCR0)
[R/W] B,H,W
--------
*3
― /(SCSTR10)
/(SFLR10)
[R/W] B,H,W
--------
*3
― /(SCSTR00)/
(SFLR00)
[R/W] B,H,W
--------
*3
001764H
―
― /(SCSFR20)
[R/W] B,H,W
-------- *3
― /(SCSFR10)
[R/W] B,H,W
-------- *3
― /(SCSFR00)
[R/W] B,H,W
-------- *3
001768H
―/(TBYTE30)/
(LAMESR0)
[R/W] B,H,W
-------- *3
―/(TBYTE20)
/(LAMERT0)
[R/W] B,H,W
-------- *3
―/(TBYTE10)/
(LAMIER0)
[R/W] B,H,W
-------- *3
TBYTE00/(LAMRID0)
/
(LAMTID0)
[R/W] B,H,W
00000000
00176CH
BGR0[R/W] H, W
00000000 00000000
― /(ISMK0)
[R/W] B,H,W
-------- *2
― /(ISBA0)
[R/W] B,H,W
-------- *2
001770H
FCR10[R/W]
B,H,W
---00100
FCR00[R/W]
B,H,W
-0000000
FBYTE0[R/W] B,H,W
00000000 00000000
001774H
FTICR0[R/W] B,H,W
00000000 00000000 ― ―
001778H
SCR1/(IBCR1) [R/W]
B,H,W
0--00000
SMR1[R/W] B,H,W
000-00-0
SSR1[R/W] B,H,W
0-000011
ESCR1/(IBSR1)[R/W
] B,H,W
00000000
Multi-UART1
00177CH
― /(RDR11/(TDR11))[R/W] B,H,W
-------- -------- *3
RDR01/(TDR01)[R/W] B,H,W
-------0 00000000 *1
001780H
SACSR1[R/W] B,H,W
0----000 00000000
STMR1[R] B,H,W
00000000 00000000
Multi-UART1
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
001784H
STMCR1[R/W] B,H,W
00000000 00000000
― /(SCSCR1/SFUR1)[R/W] B,H,W
-------- -------- *3 *4
001788H
― /(SCSTR31)/
(LAMSR1)
[R/W] B,H,W
--------
*3
― /(SCSTR21)/
(LAMCR1)
[R/W] B,H,W
--------
*3
― /(SCSTR11)/
(SFLR11)
[R/W] B,H,W
--------
*3
― /(SCSTR01)/
(SFLR01)
[R/W] B,H,W
--------
*3
00178CH
―
― /(SCSFR21)[R/W]
B,H,W
-------- *3
― /(SCSFR11)
[R/W] B,H,W
-------- *3
― /(SCSFR01)
[R/W] B,H,W
-------- *3
Document Number: 002-04662 Rev. *D Page 90 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001790H
―/(TBYTE31)/
(LAMESR1)
[R/W] B,H,W
-------- *3
―/(TBYTE21)/
(LAMERT1)
[R/W] B,H,W
-------- *3
―/(TBYTE11)/
(LAMIER1)
[R/W] B,H,W
-------- *3
TBYTE01/(LAMRID1)
/
(LAMTID1)
[R/W] B,H,W
00000000
Multi-UART1
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
001794H
BGR1[R/W] H,W
00000000 00000000
― /(ISMK1)[R/W]
B,H,W
-------- *2
― /(ISBA1)[R/W]
B,H,W
-------- *2
001798H
FCR11[R/W]
B,H,W
---00100
FCR01[R/W]
B,H,W
-0000000
FBYTE1[R/W] B,H,W
00000000 00000000
00179CH
FTICR1[R/W] B,H,W
00000000 00000000 ― ―
0017A0H
SCR2/(IBCR2)[R/W]
B,H,W
0--00000
SMR2[R/W] B,H,W
000-00-0
SSR2[R/W] B,H,W
0-000011
ESCR2/(IBSR2)[R/W
] B,H,W
00000000
Multi-UART2
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
0017A4H
― /(RDR12/(TDR12))[R/W] B,H,W
-------- -------- *3
RDR02/(TDR02)[R/W] B,H,W
-------0 00000000 *1
0017A8H
SACSR2[R/W] B,H,W
0----000 00000000
STMR2[R] B,H,W
00000000 00000000
0017ACH
STMCR2[R/W] B,H,W
00000000 00000000
― /(SCSCR2/SFUR2)[R/W] B,H,W
-------- -------- *3 *4
0017B0H
― /(SCSTR32)/
(LAMSR2)
[R/W] B,H,W
--------
*3
― /(SCSTR22)/
(LAMCR2)
[R/W] B,H,W
--------
*3
― /(SCSTR12)/
(SFLR12)
[R/W] B,H,W
--------
*3
― /(SCSTR02)/
(SFLR02)
[R/W] B,H,W
--------
*3
0017B4H
―
― /(SCSFR22)
[R/W] B,H,W
-------- *3
― /(SCSFR12)
[R/W] B,H,W
-------- *3
― /(SCSFR02)
[R/W] B,H,W
-------- *3
0017B8H
―/(TBYTE32)/
(LAMESR2)
[R/W] B,H,W
-------- *3
―/(TBYTE22)/
(LAMERT2)
[R/W] B,H,W
-------- *3
―/(TBYTE12)/
(LAMIER2)
[R/W] B,H,W
-------- *3
TBYTE02/(LAMRID2)
/
(LAMTID2)
[R/W] B,H,W
00000000
0017BCH
BGR2[R/W] H, W
00000000 00000000
― /(ISMK2)[R/W]
B,H,W
-------- *2
― /(ISBA2)[R/W]
B,H,W
-------- *2
0017C0H
FCR12[R/W]
B,H,W
---00100
FCR02[R/W]
B,H,W
-0000000
FBYTE2[R/W] B,H,W
00000000 00000000
Multi-UART2
0017C4H
FTICR2[R/W] B,H,W
00000000 00000000 ― ―
Document Number: 002-04662 Rev. *D Page 91 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0017C8H
SCR3/(IBCR3) [R/W]
B,H,W
0--00000
SMR3[R/W] B,H,W
000-00-0
SSR3[R/W] B,H,W
0-000011
ESCR3/(IBSR3)[R/W
] B,H,W
00000000
Multi-UART3
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
0017CCH
― /(RDR13/(TDR13))[R/W] B,H,W
-------- -------- *3
RDR03/(TDR03)[R/W] B,H,W
-------0 00000000 *1
0017D0H
SACSR3[R/W] B,H,W
0----000 00000000
STMR3[R] B,H,W
00000000 00000000
0017D4H
STMCR3[R/W] B,H,W
00000000 00000000
― /(SCSCR3/SFUR3)[R/W] B,H,W
-------- -------- *3 *4
0017D8H
― /(SCSTR33)/
(LAMSR3)
[R/W] B,H,W
--------
*3
― /(SCSTR23)/
(LAMCR3)
[R/W] B,H,W
--------
*3
― /(SCSTR13)/
(SFLR13)
[R/W] B,H,W
--------
*3
― /(SCSTR03)/
(SFLR03)
[R/W] B,H,W
--------
*3
0017DCH
―
― /(SCSFR23)
[R/W] B,H,W
-------- *3
― /(SCSFR13)
[R/W] B,H,W
-------- *3
― /(SCSFR03)
[R/W] B,H,W
-------- *3
0017E0H
―/(TBYTE33)/
(LAMESR3)
[R/W] B,H,W
-------- *3
―/(TBYTE23)/
(LAMERT3)
[R/W] B,H,W
-------- *3
―/(TBYTE13)/
(LAMIER3)
[R/W] B,H,W
-------- *3
TBYTE03/(LAMRID3)
/
(LAMTID3)
[R/W] B,H,W
00000000
0017E4H
BGR3[R/W] H, W
00000000 00000000
― /(ISMK3)[R/W]
B,H,W
--------
*2
― /(ISBA3)[R/W]
B,H,W
--------
*2
0017E8H
FCR13[R/W]
B,H,W
---00100
FCR03[R/W]
B,H,W
-0000000
FBYTE3[R/W] B,H,W
00000000 00000000
0017ECH
FTICR3[R/W] B,H,W
00000000 00000000 ― ―
0017F0H
SCR4/(IBCR4) [R/W]
B,H,W
0--00000
SMR4[R/W] B,H,W
000-00-0
SSR4[R/W] B,H,W
0-000011
ESCR4/(IBSR4)[R/W
] B,H,W
00000000
Multi-UART4
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately aft
er
reset.
0017F4H
― /(RDR14/(TDR14))[R/W] B,H,W
-------- -------- *3
RDR04/(TDR04)[R/W] B,H,W
-------0 00000000 *1
0017F8H
SACSR4[R/W] B,H,W
0----000 00000000
STMR4[R] B,H,W
00000000 00000000
0017FCH
STMCR4[R/W] B,H,W
00000000 00000000
― /(SCSCR4/SFUR4)[R/W] B,H,W
-------- -------- *3 *4
001800H
― /(SCSTR34)/
(LAMSR4)
[R/W] B,H,W
--------
*3
― /(SCSTR24)/
(LAMCR4)
[R/W] B,H,W
--------
*3
― /(SCSTR14)/
(SFLR14)
[R/W] B,H,W
--------
*3
― /(SCSTR04)/
(SFLR04)
[R/W] B,H,W
--------
*3
Document Number: 002-04662 Rev. *D Page 92 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001804H
―
― /(SCSFR24)
[R/W] B,H,W
-------- *3
― /(SCSFR14)
[R/W] B,H,W
-------- *3
― /(SCSFR04)
[R/W] B,H,W
-------- *3 Multi-UART4
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
001808H
―/(TBYTE34)/
(LAMESR4)
[R/W] B,H,W
-------- *3
―/(TBYTE24)/
(LAMERT4)
[R/W] B,H,W
-------- *3
―/(TBYTE14)/
(LAMIER4)
[R/W] B,H,W
-------- *3
TBYTE04/(LAMRID4)
/
(LAMTID4)
[R/W] B,H,W
00000000
00180CH
BGR4[R/W] H, W
00000000 00000000
― /(ISMK4)[R/W]
B,H,W
--------
*2
― /(ISBA4)[R/W]
B,H,W
--------
*2
001810H
FCR14[R/W]
B,H,W
---00100
FCR04[R/W]
B,H,W
-0000000
FBYTE4[R/W] B,H,W
00000000 00000000
001814H
FTICR4[R/W] B,H,W
00000000 00000000 ― ―
001818H
SCR5/(IBCR5) [R/W]
B,H,W
0--00000
SMR5[R/W] B,H,W
000-00-0
SSR5[R/W] B,H,W
0-000011
ESCR5/(IBSR5)[R/W
] B,H,W
00000000
Multi-UART5
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately af
ter
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
00181CH
― /(RDR15/(TDR15))[R/W] B,H,W
-------- -------- *3
RDR05/(TDR05)[R/W] B,H,W
-------0 00000000 *1
001820H
SACSR5[R/W] B,H,W
0----000 00000000
STMR5[R] B,H,W
00000000 00000000
001824H
STMCR5[R/W] B,H,W
00000000 00000000
― /(SCSCR5/SFUR5)[R/W] B,H,W
-------- -------- *3 *4
001828H
― /(SCSTR35)/
(LAMSR5)
[R/W] B,H,W
--------
*3
― /(SCSTR25)/
(LAMCR5)
[R/W] B,H,W
--------
*3
― /(SCSTR15)/
(SFLR15)
[R/W] B,H,W
--------
*3
― /(SCSTR05)/
(SFLR05)
[R/W] B,H,W
--------
*3
00182CH
―
― /(SCSFR25)
[R/W] B,H,W
-------- *3
― /(SCSFR15)
[R/W] B,H,W
-------- *3
― /(SCSFR05)
[R/W] B,H,W
-------- *3
001830H
―/(TBYTE35)/
(LAMESR5)
[R/W] B,H,W
-------- *3
―/(TBYTE25)/
(LAMERT5)
[R/W] B,H,W
-------- *3
―/(TBYTE15)/
(LAMIER5)
[R/W] B,H,W
-------- *3
TBYTE05/(LAMRID5)
/
(LAMTID5)
[R/W] B,H,W
00000000
001834H
BGR5[R/W] H, W
00000000 00000000
― /(ISMK5)[R/W]
B,H,W
--------
*2
― /(ISBA5)[R/W]
B,H,W
--------
*2
001838H
FCR15[R/W]
B,H,W
---00100
FCR05[R/W]
B,H,W
-0000000
FBYTE5[R/W] B,H,W
00000000 00000000
00183CH
FTICR5[R/W] B,H,W
00000000 00000000 ― ―
Document Number: 002-04662 Rev. *D Page 93 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001840H
SCR6/(IBCR6) [R/W]
B,H,W
0--00000
SMR6[R/W] B,H,W
000-00-0
SSR6[R/W] B,H,W
0-000011
ESCR6/(IBSR6)[R/W
] B,H,W
00000000
Multi-UART6
001844H
― /(RDR16/(TDR16))[R/W] B,H,W
-------- -------- *3
RDR06/(TDR06)[R/W] B,H,W
-------0 00000000 *1
Multi-UART6
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
001848H
SACSR6[R/W] B,H,W
0----000 00000000
STMR6[R] B,H,W
00000000 00000000
00184CH
STMCR6[R/W] B,H,W
00000000 00000000
― /(SCSCR6/SFUR6)[R/W] B,H,W
-------- -------- *3 *4
001850H
― /(SCSTR36)/
(LAMSR6)
[R/W] B,H,W
--------
*3
― /(SCSTR26)/
(LAMCR6)
[R/W] B,H,W
--------
*3
― /(SCSTR16)/
(SFLR16)
[R/W] B,H,W
--------
*3
― /(SCSTR06)/
(SFLR06)
[R/W] B,H,W
--------
*3
001854H
―
― /(SCSFR26)
[R/W] B,H,W
-------- *3
― /(SCSFR16)
[R/W] B,H,W
-------- *3
― /(SCSFR06)
[R/W] B,H,W
-------- *3
001858H
―/(TBYTE36)/
(LAMESR6)
[R/W] B,H,W
-------- *3
―/(TBYTE26)/
(LAMERT6)
[R/W] B,H,W
-------- *3
―/(TBYTE16)/
(LAMIER6)
[R/W] B,H,W
-------- *3
TBYTE06/(LAMRID6)
/
(LAMTID6)
[R/W] B,H,W
00000000
00185CH
BGR6[R/W] H, W
00000000 00000000
― /(ISMK6)[R/W]
B,H,W
-------- *2
― /(ISBA6)[R/W]
B,H,W
-------- *2
001860H
FCR16[R/W]
B,H,W
---00100
FCR06[R/W]
B,H,W
-0000000
FBYTE6[R/W] B,H,W
00000000 00000000
001864H
FTICR6[R/W] B,H,W
00000000 00000000 ― ―
001868H
SCR7/(IBCR7) [R/W]
B,H,W
0--00000
SMR7[R/W] B,H,W
000-00-0
SSR7[R/W] B,H,W
0-000011
ESCR7/(IBSR7)[R/W
] B,H,W
00000000
Multi-UART7
*1: Byte access is
possible only for
access
to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
00186CH
― /(RDR17/(TDR17))[R/W] B,H,W
-------- -------- *3
RDR07/(TDR07)[R/W] B,H,W
-------0 00000000 *1
001870H
SACSR7[R/W] B,H,W
0----000 00000000
STMR7[R] B,H,W
00000000 00000000
001874H
STMCR7[R/W] B,H,W
00000000 00000000
― /(SCSCR7/SFUR7)[R/W] B,H,W
-------- -------- *3 *4
Document Number: 002-04662 Rev. *D Page 94 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001878H
― /(SCSTR37)/
(LAMSR7)
[R/W] B,H,W
--------
*3
― /(SCSTR27)/
(LAMCR7)
[R/W] B,H,W
--------
*3
― /(SCSTR17)/
(SFLR17)
[R/W] B,H,W
--------
*3
― /(SCSTR07)/
(SFLR07)
[R/W] B,H,W
--------
*3
Multi-UART7
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
00187CH
―
― /(SCSFR27)
[R/W] B,H,W
-------- *3
― /(SCSFR17)
[R/W] B,H,W
-------- *3
― /(SCSFR07)
[R/W] B,H,W
-------- *3
001880H
―/(TBYTE37)/
(LAMESR7)
[R/W] B,H,W
-------- *3
―/(TBYTE27)/
(LAMERT7)
[R/W] B,H,W
-------- *3
―/(TBYTE17)/
(LAMIER7)
[R/W] B,H,W
-------- *3
TBYTE07/(LAMRID7)
/
(LAMTID7)
[R/W] B,H,W
00000000
001884H
BGR7[R/W] H, W
00000000 00000000
― /(ISMK7)[R/W]
B,H,W
--------
*2
― /(ISBA7)[R/W]
B,H,W
--------
*2
Multi-UART7
001888H
FCR17[R/W]
B,H,W
---00100
FCR07[R/W]
B,H,W
-0000000
FBYTE7[R/W] B,H,W
00000000 00000000
00188CH
FTICR7[R/W] B,H,W
00000000 00000000 ― ―
001890H
SCR8/(IBCR8) [R/W]
B,H,W
0--00000
SMR8[R/W] B,H,W
000-00-0
SSR8[R/W] B,H,W
0-000011
ESCR8/(IBSR8)[R/W
] B,H,W
00000000
Multi-UART8
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
001894H
― /(RDR18/(TDR18))[R/W] B,H,W
-------- -------- *3
RDR08/(TDR08)[R/W] B,H,W
-------0 00000000 *1
001898H
SACSR8[R/W] B,H,W
0----000 00000000
STMR8[R] B,H,W
00000000 00000000
00189CH
STMCR8[R/W] B,H,W
00000000 00000000
― /(SCSCR8/SFUR8)[R/W] B,H,W
-------- -------- *3 *4
0018A0H
― /(SCSTR38)/
(LAMSR8)
[R/W] B,H,W
--------
*3
― /(SCSTR28)/
(LAMCR8)
[R/W] B,H,W
--------
*3
― /(SCSTR18)/
(SFLR18)
[R/W] B,H,W
--------
*3
― /(SCSTR08)/
(SFLR08)
[R/W] B,H,W
--------
*3
0018A4H
―
― /(SCSFR28)
[R/W] B,H,W
-------- *3
― /(SCSFR18)
[R/W] B,H,W
-------- *3
― /(SCSFR08)
[R/W] B,H,W
-------- *3
0018A8H
―/(TBYTE38)/
(LAMESR8)
[R/W] B,H,W
-------- *3
―/(TBYTE28)/
(LAMERT8)
[R/W] B,H,W
-------- *3
―/(TBYTE18)/
(LAMIER8)
[R/W] B,H,W
-------- *3
TBYTE08/(LAMRID8)
/
(LAMTID8)
[R/W] B,H,W
00000000
0018ACH
BGR8[R/W] H,W
00000000 00000000
― /(ISMK8)[R/W]
B,H,W
-------- *2
― /(ISBA8)[R/W]
B,H,W
-------- *2
Document Number: 002-04662 Rev. *D Page 95 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0018B0H
FCR18[R/W]
B,H,W
---00100
FCR08[R/W]
B,H,W
-0000000
FBYTE8[R/W] B,H,W
00000000 00000000
Multi-UART8
0018B4H
FTICR8[R/W] B,H,W
00000000 00000000 ― ―
0018B8H
SCR9/(IBCR9) [R/W]
B,H,W
0--00000
SMR9[R/W] B,H,W
000-00-0
SSR9[R/W] B,H,W
0-000011
ESCR9/(IBSR9)[R/W
] B,H,W
00000000
Multi-UART9
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
0018BCH
― /(RDR19/(TDR19))[R/W] B,H,W
-------- -------- *3
RDR09/(TDR09)[R/W] B,H,W
-------0 00000000 *1
0018C0H
SACSR9[R/W] B,H,W
0----000 00000000
STMR9[R] B,H,W
00000000 00000000
0018C4H
STMCR9[R/W] B,H,W
00000000 00000000
― /(SCSCR9/SFUR9)[R/W] B,H,W
-------- -------- *3 *4
0018C8H
― /(SCSTR39)/
(LAMSR9)
[R/W] B,H,W
--------
*3
― /(SCSTR29)/
(LAMCR9)
[R/W] B,H,W
--------
*3
― /(SCSTR19)/
(SFLR19)
[R/W] B,H,W
--------
*3
― /(SCSTR09)/
(SFLR09)
[R/W] B,H,W
--------
*3
0018CCH
―
― /(SCSFR29)
[R/W] B,H,W
-------- *3
― /(SCSFR19)
[R/W] B,H,W
-------- *3
― /(SCSFR09)
[R/W] B,H,W
-------- *3
0018D0H
―/(TBYTE39)/
(LAMESR9)
[R/W] B,H,W
-------- *3
―/(TBYTE29)/
(LAMERT9)
[R/W] B,H,W
-------- *3
―/(TBYTE19)/
(LAMIER9)
[R/W] B,H,W
-------- *3
TBYTE09/(LAMRID9)
/
(LAMTID9)
[R/W] B,H,W
00000000
0018D4H
BGR9[R/W] H, W
00000000 00000000
― /(ISMK9)[R/W]
B,H,W
-------- *2
― /(ISBA9)[R/W]
B,H,W
-------- *2
0018D8H
FCR19[R/W]
B,H,W
---00100
FCR09[R/W]
B,H,W
-0000000
FBYTE9[R/W] B,H,W
00000000 00000000
0018DCH
FTICR9[R/W] B,H,W
00000000 00000000 ― ―
0018E0H
SCR10/(IBCR10)
[R/W] B,H,W
0--00000
SMR10[R/W] B,H,W
000-00-0
SSR10[R/W] B,H,W
0-000011
ESCR10/(IBSR10)
[R/W] B,H,W
00000000
Multi-UART10
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
0018E4H
― /(RDR110/(TDR110))[R/W] B,H,W
-------- -------- *3
RDR010/(TDR010)[R/W] B,H,W
-------0 00000000 *1
0018E8H
SACSR10[R/W] B,H,W
0----000 00000000
STMR10[R] B,H,W
00000000 00000000
0018ECH
STMCR10[R/W] B,H,W
00000000 00000000
― /(SCSCR10/SFUR10)[R/W] B,H,W
-------- -------- *3 *4
Document Number: 002-04662 Rev. *D Page 96 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0018F0H
― /(SCSTR310)/
(LAMSR10)
[R/W] B,H,W
--------
*3
― /(SCSTR210)/
(LAMCR10)
[R/W] B,H,W
--------
*3
― /(SCSTR110)/
(SFLR110)[R/W]
B,H,W
--------
*3
― /(SCSTR010)/
(SFLR010)[R/W]
B,H,W
--------
*3
Multi-UART10
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
0018F4H
―
― /(SCSFR210)
[R/W] B,H,W
-------- *3
― /(SCSFR110)
[R/W] B,H,W
-------- *3
― /(SCSFR010)
[R/W] B,H,W
-------- *3
0018F8H
―/(TBYTE310)/
(LAMESR10)
[R/W] B,H,W
-------- *3
―/(TBYTE210)/
(LAMERT10)
[R/W] B,H,W
-------- *3
―/(TBYTE110)/
(LAMIER10)
[R/W] B,H,W
-------- *3
TBYTE010/(LAMRID
10)/(LAMTID10)
[R/W] B,H,W
00000000
0018FCH
BGR10[R/W] H, W
00000000 00000000
― /(ISMK10)[R/W]
B,H,W
--------
*2
― /(ISBA10)[R/W]
B,H,W
--------
*2
001900H
FCR110[R/W]
B,H,W
---00100
FCR010[R/W]
B,H,W
-0000000
FBYTE10[R/W] B,H,W
00000000 00000000
001904H
FTICR10[R/W] B,H,W
00000000 00000000 ― ―
001908H
SCR11/(IBCR11)
[R/W] B,H,W
0--00000
SMR11[R/W] B,H,W
000-00-0
SSR11[R/W] B,H,W
0-000011
ESCR11/(IBSR11)
[R/W] B,H,W
00000000
Multi-UART11
*1: Byte access is
possible only for
access to lower 8
bits.
*2: Reserved
because I2C
mode is not set
immediately after
reset.
*3: Reserved
because CSIO
mode is not set
immediately after
reset.
*4: Reserved
because LIN2.1
mode is not set
immediately after
reset.
00190CH
― /(RDR111/(TDR111))[R/W] B,H,W
-------- -------- *3
RDR011/(TDR011)[R/W] B,H,W
-------0 00000000 *1
001910H
SACSR11[R/W] B,H,W
0----000 00000000
STMR11[R] B,H,W
00000000 00000000
001914H
STMCR11[R/W] B,H,W
00000000 00000000
― /(SCSCR11/SFUR11)[R/W] B,H,W
-------- -------- *3 *4
001918H
― /(SCSTR311)/
(LAMSR11)
[R/W] B,H,W
--------
*3
― /(SCSTR211)/
(LAMCR11)
[R/W] B,H,W
--------
*3
― /(SCSTR111)/
(SFLR111)[R/W]
B,H,W
--------
*3
― /(SCSTR011)/
(SFLR011)[R/W]
B,H,W
--------
*3
00191CH
―
― /(SCSFR211)
[R/W] B,H,W
-------- *3
― /(SCSFR111)
[R/W] B,H,W
-------- *3
― /(SCSFR011)
[R/W] B,H,W
-------- *3
001920H
―/(TBYTE311)/
(LAMESR11)
[R/W] B,H,W
--------
*3
―/(TBYTE211)/
(LAMERT11)
[R/W] B,H,W
--------
*3
―/(TBYTE111)/
(LAMIER11)
[R/W] B,H,W
--------
*3
TBYTE011/(LAMRID
11)/(LAMTID11)
[R/W] B,H,W
00000000
001924H
BGR11[R/W] H, W
00000000 00000000
― /(ISMK11)[R/W]
B,H,W
-------- *2
― /(ISBA11)[R/W]
B,H,W
-------- *2
Document Number: 002-04662 Rev. *D Page 97 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001928H
FCR111[R/W]
B,H,W
---00100
FCR011[R/W]
B,H,W
-0000000
FBYTE11[R/W] B,H,W
00000000 00000000
Multi-UART11
00192CH
FTICR11[R/W] B,H,W
00000000 00000000 ― ―
001930H
to
0019D8H
― ― ― ― Reserved
0019DCH
―
GATEC0 [R/W]
B,H,W
------00
―
GATEC2 [R/W]
B,H,W
------00
PPG GATE
control
0019E0H
―
GATEC4 [R/W]
B,H,W
------00
― ―
0019E4H
― ― ― ― Reserved
0019E8H
GTRS0 [R/W] B,H,W
-0000000 -0000000
GTRS1 [R/W] B,H,W
-0000000 -0000000
PPG
controller
0019ECH
GTRS2 [R/W] B,H,W
-0000000 -0000000
GTRS3 [R/W] B,H,W
-0000000 -0000000
0019F0H
GTRS4 [R/W] B,H,W
-0000000 -0000000
GTRS5 [R/W] B,H,W
-0000000 -0000000
0019F4H
GTRS6 [R/W] B,H,W
-0000000 -0000000
GTRS7 [R/W] B,H,W
-0000000 -0000000
0019F8H
GTRS8 [R/W] B,H,W
-0000000 -0000000
GTRS9 [R/W] B,H,W
-0000000 -0000000
PPG
controller
0019FCH
GTRS10 [R/W] B,H,W
-0000000 -0000000
GTRS11 [R/W] B,H,W
-0000000 -0000000
001A00H
GTRS12 [R/W] B,H,W
-0000000 -0000000
GTRS13 [R/W] B,H,W
-0000000 -0000000
001A04H
GTRS14 [R/W] B,H,W
-0000000 -0000000
GTRS15 [R/W] B,H,W
-0000000 -0000000
001A08H
GTRS16 [R/W] B,H,W
-0000000 -0000000
GTRS17 [R/W] B,H,W
-0000000 -0000000
001A0CH
GTRS18 [R/W] B,H,W
-0000000 -0000000
GTRS19 [R/W] B,H,W
-0000000 -0000000
001A10H
GTRS20 [R/W] B,H,W
-0000000 -0000000
GTRS21 [R/W] B,H,W
-0000000 -0000000
001A14H
GTRS22 [R/W] B,H,W
-0000000 -0000000
GTRS23 [R/W] B,H,W
-0000000 -0000000
001A18H
to
001A2CH
― ― ― ― Reserved
Document Number: 002-04662 Rev. *D Page 98 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001A30H
― ― ― ―
Reserved
001A34H
― ― ― ―
001A38H
GTREN0 [R/W] H,W
00000000 00000000
GTREN1 [R/W] H,W
00000000 00000000 PPG
controller
001A3CH
GTREN2 [R/W] H,W
00000000 00000000 ― ―
001A40H
PCN0 [R/W] B,H,W
00000000 000000-0
PCSR0 [W] H,W
XXXXXXXX XXXXXXXX
PPG0
* for
communication
001A44H
PDUT0 [W] H,W
XXXXXXXX XXXXXXXX
PTMR0 [R] H,W
11111111 11111111
001A48H
PCN200 [R/W] B,H,W
--000000 -----110
PSDR0 [R/W] H,W
00000000 00000000
001A4CH
PTPC0 [R/W] H,W
00000000 00000000
PCMDWD0 [R/W] B,H,W
-------- ----0000
001A50H
PHCSR0 [W] H,W
XXXXXXXX XXXXXXXX
PLCSR0 [W] H,W
XXXXXXXX XXXXXXXX
001A54H
PHDUT0 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT0 [W] H,W
XXXXXXXX XXXXXXXX
001A58H
PCMDDT0 [R/W] H,W
00000000 00000000 ― ―
001A5CH
PCN1 [R/W] B,H,W
00000000 000000-0
PCSR1 [W] H,W
XXXXXXXX XXXXXXXX PPG1
* for
communication
001A60H
PDUT1 [W] H,W
XXXXXXXX XXXXXXXX
PTMR1 [R] H,W
11111111 11111111
001A64H
PCN201 [R/W] B,H,W
--000000 -----110
PSDR1 [R/W] H,W
00000000 00000000
PPG1
* for
communication
001A68H
PTPC1 [R/W] H,W
00000000 00000000
PCMDWD1 [R/W] B,H,W
-------- ----0000
001A6CH
PHCSR1 [W] H,W
XXXXXXXX XXXXXXXX
PLCSR1 [W] H,W
XXXXXXXX XXXXXXXX
001A70H
PHDUT1 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT1 [W] H,W
XXXXXXXX XXXXXXXX
001A74H
PCMDDT1 [R/W] H,W
00000000 00000000 ― ―
001A78H
PCN2 [R/W] B,H,W
00000000 000000-0
PCSR2 [W] H,W
XXXXXXXX XXXXXXXX PPG2
* for
communication
001A7CH
PDUT2 [W] H,W
XXXXXXXX XXXXXXXX
PTMR2 [R] H,W
11111111 11111111
Document Number: 002-04662 Rev. *D Page 99 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001A80H
PCN202 [R/W] B,H,W
--000000 -----110
PSDR2 [R/W] H,W
00000000 00000000
PPG2
* for
communication
001A84H
PTPC2 [R/W] H,W
00000000 00000000
PCMDWD2 [R/W] B,H,W
-------- ----0000
001A88H
PHCSR2 [W] H,W
XXXXXXXX XXXXXXXX
PLCSR2 [W] H,W
XXXXXXXX XXXXXXXX
001A8CH
PHDUT2 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT2 [W] H,W
XXXXXXXX XXXXXXXX
001A90H
PCMDDT2 [R/W] H,W
00000000 00000000 ― ―
001A94H
PCN3 [R/W] B,H,W
00000000 000000-0
PCSR3 [W] H,W
XXXXXXXX XXXXXXXX
PPG3
* for
communication
001A98H
PDUT3 [W] H,W
XXXXXXXX XXXXXXXX
PTMR3 [R] H,W
11111111 11111111
001A9CH
PCN203 [R/W] B,H,W
--000000 -----110
PSDR3 [R/W] H,W
00000000 00000000
001AA0H
PTPC3 [R/W] H,W
00000000 00000000
PCMDWD3 [R/W] B,H,W
-------- ----0000
001AA4H
PHCSR3 [W] H,W
XXXXXXXX XXXXXXXX
PLCSR3 [W] H,W
XXXXXXXX XXXXXXXX
001AA8H
PHDUT3 [W] H,W
XXXXXXXX XXXXXXXX
PLDUT3 [W] H,W
XXXXXXXX XXXXXXXX
001AACH
PCMDDT3 [R/W] H,W
00000000 00000000 ― ―
001AB0H
PCN4 [R/W] B,H,W
00000000 000000-0
PCSR4 [W] H,W
XXXXXXXX XXXXXXXX
PPG4 001AB4H
PDUT4 [W] H,W
XXXXXXXX XXXXXXXX
PTMR4 [R] H,W
11111111 11111111
001AB8H
PCN204 [R/W] B,H,W
--000000 -----110
PSDR4 [R/W] H,W
00000000 00000000
001ABCH
PTPC4 [R/W] H,W
00000000 00000000 ― ― PPG4
001AC0H
PCN5 [R/W] B,H,W
00000000 000000-0
PCSR5 [W] H,W
XXXXXXXX XXXXXXXX
PPG5
001AC4H
PDUT5 [W] H,W
XXXXXXXX XXXXXXXX
PTMR5 [R] H,W
11111111 11111111
001AC8H
PCN205 [R/W] B,H,W
--000000 -----110
PSDR5 [R/W] H,W
00000000 00000000
001ACCH
PTPC5 [R/W] H,W
00000000 00000000
― ―
Document Number: 002-04662 Rev. *D Page 100 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001AD0H
PCN6 [R/W] B,H,W
00000000 000000-0
PCSR6 [W] H,W
XXXXXXXX XXXXXXXX
PPG6
001AD4H
PDUT6 [W] H,W
XXXXXXXX XXXXXXXX
PTMR6 [R] H,W
11111111 11111111
001AD8H
PCN206 [R/W] B,H,W
--000000 -----110
PSDR6 [R/W] H,W
00000000 00000000
001ADCH
PTPC6 [R/W] H,W
00000000 00000000 ― ―
001AE0H
PCN7 [R/W] B,H,W
00000000 000000-0
PCSR7 [W] H,W
XXXXXXXX XXXXXXXX
PPG7
001AE4H
PDUT7 [W] H,W
XXXXXXXX XXXXXXXX
PTMR7 [R] H,W
11111111 11111111
001AE8H
PCN207 [R/W] B,H,W
--000000 -----110
PSDR7 [R/W] H,W
00000000 00000000
001AECH
PTPC7 [R/W] H,W
00000000 00000000 ― ―
001AF0H
PCN8 [R/W] B,H,W
00000000 000000-0
PCSR8 [W] H,W
XXXXXXXX XXXXXXXX
PPG8
001AF4H
PDUT8 [W] H,W
XXXXXXXX XXXXXXXX
PTMR8 [R] H,W
11111111 11111111
001AF8H
PCN208 [R/W] B,H,W
--000000 -----110
PSDR8 [R/W] H,W
00000000 00000000
001AFCH
PTPC8 [R/W] H,W
00000000 00000000 ― ―
001B00H
PCN9 [R/W] B,H,W
00000000 000000-0
PCSR9 [W] H,W
XXXXXXXX XXXXXXXX
PPG9
001B04H
PDUT9 [W] H,W
XXXXXXXX XXXXXXXX
PTMR9 [R] H,W
11111111 11111111
001B08H
PCN209 [R/W] B,H,W
--000000 -----110
PSDR9 [R/W] H,W
00000000 00000000
001B0CH
PTPC9 [R/W] H,W
00000000 00000000
― ―
001B10H
PCN10 [R/W] B,H,W
00000000 000000-0
PCSR10 [W] H,W
XXXXXXXX XXXXXXXX
PPG10
001B14H
PDUT10 [W] H,W
XXXXXXXX XXXXXXXX
PTMR10 [R] H,W
11111111 11111111
001B18H
PCN210 [R/W] B,H,W
--000000 -----110
PSDR10 [R/W] H,W
00000000 00000000
PPG10
001B1CH
PTPC10 [R/W] H,W
00000000 00000000 ― ―
001B20H
PCN11 [R/W] B,H,W
00000000 000000-0
PCSR11 [W] H,W
XXXXXXXX XXXXXXXX PPG11
Document Number: 002-04662 Rev. *D Page 101 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001B24H
PDUT11 [W] H,W
XXXXXXXX XXXXXXXX
PTMR11 [R] H,W
11111111 11111111
PPG11 001B28H
PCN211 [R/W] B,H,W
--000000 -----110
PSDR11 [R/W] H,W
00000000 00000000
001B2CH
PTPC11 [R/W] H,W
00000000 00000000 ― ―
001B30H
PCN12 [R/W] B,H,W
00000000 000000-0
PCSR12 [W] H,W
XXXXXXXX XXXXXXXX
PPG12
001B34H
PDUT12 [W] H,W
XXXXXXXX XXXXXXXX
PTMR12 [R] H,W
11111111 11111111
001B38H
PCN212 [R/W] B,H,W
--000000 -----110
PSDR12 [R/W] H,W
00000000 00000000
001B3CH
PTPC12 [R/W] H,W
00000000 00000000 ― ―
001B40H
PCN13 [R/W] B,H,W
00000000 000000-0
PCSR13 [W] H,W
XXXXXXXX XXXXXXXX
PPG13
001B44H
PDUT13 [W] H,W
XXXXXXXX XXXXXXXX
PTMR13 [R] H,W
11111111 11111111
001B48H
PCN213 [R/W] B,H,W
--000000 -----110
PSDR13 [R/W] H,W
00000000 00000000
001B4CH
PTPC13 [R/W] H,W
00000000 00000000 ― ―
001B50H
PCN14 [R/W] B,H,W
00000000 000000-0
PCSR14 [W] H,W
XXXXXXXX XXXXXXXX
PPG14
001B54H
PDUT14 [W] H,W
XXXXXXXX XXXXXXXX
PTMR14 [R] H,W
11111111 11111111
001B58H
PCN214 [R/W] B,H,W
--000000 -----110
PSDR14 [R/W] H,W
00000000 00000000
001B5CH
PTPC14 [R/W] H,W
00000000 00000000
― ―
001B60H
PCN15 [R/W] B,H,W
00000000 000000-0
PCSR15 [W] H,W
XXXXXXXX XXXXXXXX
PPG15
001B64H
PDUT15 [W] H,W
XXXXXXXX XXXXXXXX
PTMR15 [R] H,W
11111111 11111111
001B68H
PCN215 [R/W] B,H,W
--000000 -----110
PSDR15 [R/W] H,W
00000000 00000000
001B6CH
PTPC15 [R/W] H,W
00000000 00000000 ― ―
001B70H
PCN16 [R/W] B,H,W
00000000 000000-0
PCSR16 [W] H,W
XXXXXXXX XXXXXXXX
PPG16
001B74H
PDUT16 [W] H,W
XXXXXXXX XXXXXXXX
PTMR16 [R] H,W
11111111 11111111
Document Number: 002-04662 Rev. *D Page 102 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001B78H
PCN216 [R/W] B,H,W
--000000 -----110
PSDR16 [R/W] H,W
00000000 00000000
PPG16
001B7CH
PTPC16 [R/W] H,W
00000000 00000000 ― ―
001B80H
PCN17 [R/W] B,H,W
00000000 000000-0
PCSR17 [W] H,W
XXXXXXXX XXXXXXXX
PPG17
001B84H
PDUT17 [W] H,W
XXXXXXXX XXXXXXXX
PTMR17 [R] H,W
11111111 11111111
001B88H
PCN217 [R/W] B,H,W
--000000 -----110
PSDR17 [R/W] H,W
00000000 00000000
001B8CH
PTPC17 [R/W] H,W
00000000 00000000 ― ―
001B90H
PCN18 [R/W] B,H,W
00000000 000000-0
PCSR18 [W] H,W
XXXXXXXX XXXXXXXX
PPG18
001B94H
PDUT18 [W] H,W
XXXXXXXX XXXXXXXX
PTMR18 [R] H,W
11111111 11111111
001B98H
PCN218 [R/W] B,H,W
--000000 -----110
PSDR18 [R/W] H,W
00000000 00000000
001B9CH
PTPC18 [R/W] H,W
00000000 00000000
― ―
001BA0H
PCN19 [R/W] B,H,W
00000000 000000-0
PCSR19 [W] H,W
XXXXXXXX XXXXXXXX
PPG19
001BA4H
PDUT19 [W] H,W
XXXXXXXX XXXXXXXX
PTMR19 [R] H,W
11111111 11111111
001BA8H
PCN219 [R/W] B,H,W
--000000 -----110
PSDR19 [R/W] H,W
00000000 00000000
001BACH
PTPC19 [R/W] H,W
00000000 00000000
― ―
001BB0H
PCN20 [R/W] B,H,W
00000000 000000-0
PCSR20 [W] H,W
XXXXXXXX XXXXXXXX
PPG20
001BB4H
PDUT20 [W] H,W
XXXXXXXX XXXXXXXX
PTMR20 [R] H,W
11111111 11111111
001BB8H
PCN220 [R/W] B,H,W
--000000 -----110
PSDR20 [R/W] H,W
00000000 00000000
001BBCH
PTPC20 [R/W] H,W
00000000 00000000 ― ―
001BC0H
PCN21 [R/W] B,H,W
00000000 000000-0
PCSR21 [W] H,W
XXXXXXXX XXXXXXXX
PPG21
001BC4H
PDUT21 [W] H,W
XXXXXXXX XXXXXXXX
PTMR21 [R] H,W
11111111 11111111
001BC8H
PCN221 [R/W] B,H,W
--000000 -----110
PSDR21 [R/W] H,W
00000000 00000000
Document Number: 002-04662 Rev. *D Page 103 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001BCCH
PTPC21 [R/W] H,W
00000000 00000000
― ― PPG21
001BD0H
PCN22 [R/W] B,H,W
00000000 000000-0
PCSR22 [W] H,W
XXXXXXXX XXXXXXXX
PPG22
001BD4H
PDUT22 [W] H,W
XXXXXXXX XXXXXXXX
PTMR22 [R] H,W
11111111 11111111
001BD8H
PCN222 [R/W] B,H,W
--000000 -----110
PSDR22 [R/W] H,W
00000000 00000000
001BDCH
PTPC22 [R/W] H,W
00000000 00000000
― ―
001BE0H
PCN23 [R/W] B,H,W
00000000 000000-0
PCSR23 [W] H,W
XXXXXXXX XXXXXXXX
PPG23
001BE4H
PDUT23 [W] H,W
XXXXXXXX XXXXXXXX
PTMR23 [R] H,W
11111111 11111111
001BE8H
PCN223 [R/W] B,H,W
--000000 -----110
PSDR23 [R/W] H,W
00000000 00000000
001BECH
PTPC23 [R/W] H,W
00000000 00000000
― ―
001BF0H
PCN24 [R/W] B,H,W
00000000 000000-0
PCSR24 [W] H,W
XXXXXXXX XXXXXXXX
PPG24
001BF4H
PDUT24 [W] H,W
XXXXXXXX XXXXXXXX
PTMR24 [R] H,W
11111111 11111111
001BF8H
PCN224 [R/W] B,H,W
--000000 -----110
PSDR24 [R/W] H,W
00000000 00000000
001BFCH
PTPC24 [R/W] H,W
00000000 00000000
― ―
001C00H
PCN25 [R/W] B,H,W
00000000 000000-0
PCSR25 [W] H,W
XXXXXXXX XXXXXXXX
PPG25
001C04H
PDUT25 [W] H,W
XXXXXXXX XXXXXXXX
PTMR25 [R] H,W
11111111 11111111
001C08H
PCN225 [R/W] B,H,W
--000000 -----110
PSDR25 [R/W] H,W
00000000 00000000
001C0CH
PTPC25 [R/W] H,W
00000000 00000000
― ―
001C10H
PCN26 [R/W] B,H,W
00000000 000000-0
PCSR26 [W] H,W
XXXXXXXX XXXXXXXX
PPG26
001C14H
PDUT26 [W] H,W
XXXXXXXX XXXXXXXX
PTMR26 [R] H,W
11111111 11111111
001C18H
PCN226 [R/W] B,H,W
--000000 -----110
PSDR26 [R/W] H,W
00000000 00000000
001C1CH
PTPC26 [R/W] H,W
00000000 00000000
― ―
001C20H
PCN27 [R/W] B,H,W
00000000 000000-0
PCSR27 [W] H,W
XXXXXXXX XXXXXXXX PPG27
Document Number: 002-04662 Rev. *D Page 104 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001C24H
PDUT27 [W] H,W
XXXXXXXX XXXXXXXX
PTMR27 [R] H,W
11111111 11111111 PPG27
001C28H
PCN227 [R/W] B,H,W
--000000 -----110
PSDR27 [R/W] H,W
00000000 00000000
001C2CH
PTPC27 [R/W] H,W
00000000 00000000 ― ― PPG27
001C30H
PCN28 [R/W] B,H,W
00000000 000000-0
PCSR28 [W] H,W
XXXXXXXX XXXXXXXX
PPG28
001C34H
PDUT28 [W] H,W
XXXXXXXX XXXXXXXX
PTMR28 [R] H,W
11111111 11111111
001C38H
PCN228 [R/W] B,H,W
--000000 -----110
PSDR28 [R/W] H,W
00000000 00000000
001C3CH
PTPC28 [R/W] H,W
00000000 00000000 ― ―
001C40H
PCN29 [R/W] B,H,W
00000000 000000-0
PCSR29 [W] H,W
XXXXXXXX XXXXXXXX
PPG29
001C44H
PDUT29 [W] H,W
XXXXXXXX XXXXXXXX
PTMR29 [R] H,W
11111111 11111111
001C48H
PCN229 [R/W] B,H,W
--000000 -----110
PSDR29 [R/W] H,W
00000000 00000000
001C4CH
PTPC29 [R/W] H,W
00000000 00000000
― ―
001C50H
PCN30 [R/W] B,H,W
00000000 000000-0
PCSR30 [W] H,W
XXXXXXXX XXXXXXXX
PPG30
001C54H
PDUT30 [W] H,W
XXXXXXXX XXXXXXXX
PTMR30 [R] H,W
11111111 11111111
001C58H
PCN230 [R/W] B,H,W
--000000 -----110
PSDR30 [R/W] H,W
00000000 00000000
001C5CH
PTPC30 [R/W] H,W
00000000 00000000
― ―
001C60H
PCN31 [R/W] B,H,W
00000000 000000-0
PCSR31 [W] H,W
XXXXXXXX XXXXXXXX
PPG31
001C64H
PDUT31 [W] H,W
XXXXXXXX XXXXXXXX
PTMR31 [R] H,W
11111111 11111111
001C68H
PCN231 [R/W] B,H,W
--000000 -----110
PSDR31 [R/W] H,W
00000000 00000000
001C6CH
PTPC31 [R/W] H,W
00000000 00000000 ― ―
001C70H
PCN32 [R/W] B,H,W
00000000 000000-0
PCSR32 [W] H,W
XXXXXXXX XXXXXXXX
PPG32
001C74H
PDUT32 [W] H,W
XXXXXXXX XXXXXXXX
PTMR32 [R] H,W
11111111 11111111
Document Number: 002-04662 Rev. *D Page 105 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001C78H
PCN232 [R/W] B,H,W
--000000 -----110
PSDR32 [R/W] H,W
00000000 00000000
PPG32
001C7CH
PTPC32 [R/W] H,W
00000000 00000000 ― ―
001C80H
PCN33 [R/W] B,H,W
00000000 000000-0
PCSR33 [W] H,W
XXXXXXXX XXXXXXXX
PPG33
001C84H
PDUT33 [W] H,W
XXXXXXXX XXXXXXXX
PTMR33 [R] H,W
11111111 11111111
001C88H
PCN233 [R/W] B,H,W
--000000 -----110
PSDR33 [R/W] H,W
00000000 00000000 PPG33
001C8CH
PTPC33 [R/W] H,W
00000000 00000000
― ―
001C90H
PCN34 [R/W] B,H,W
00000000 000000-0
PCSR34 [W] H,W
XXXXXXXX XXXXXXXX
PPG34
001C94H
PDUT34 [W] H,W
XXXXXXXX XXXXXXXX
PTMR34 [R] H,W
11111111 11111111
001C98H
PCN234 [R/W] B,H,W
--000000 -----110
PSDR34 [R/W] H,W
00000000 00000000
001C9CH
PTPC34 [R/W] H,W
00000000 00000000
― ―
001CA0H
PCN35 [R/W] B,H,W
00000000 000000-0
PCSR35 [W] H,W
XXXXXXXX XXXXXXXX
PPG35
001CA4H
PDUT35 [W] H,W
XXXXXXXX XXXXXXXX
PTMR35 [R] H,W
11111111 11111111
001CA8H
PCN235 [R/W] B,H,W
--000000 -----110
PSDR35 [R/W] H,W
00000000 00000000
001CACH
PTPC35 [R/W] H,W
00000000 00000000
― ―
001CB0H
PCN36 [R/W] B,H,W
00000000 000000-0
PCSR36 [W] H,W
XXXXXXXX XXXXXXXX
PPG36
001CB4H
PDUT36 [W] H,W
XXXXXXXX XXXXXXXX
PTMR36 [R] H,W
11111111 11111111
001CB8H
PCN236 [R/W] B,H,W
--000000 -----110
PSDR36 [R/W] H,W
00000000 00000000
001CBCH
PTPC36 [R/W] H,W
00000000 00000000
― ―
001CC0H
PCN37 [R/W] B,H,W
00000000 000000-0
PCSR37 [W] H,W
XXXXXXXX XXXXXXXX
PPG37
001CC4H
PDUT37 [W] H,W
XXXXXXXX XXXXXXXX
PTMR37 [R] H,W
11111111 11111111
001CC8H
PCN237 [R/W] B,H,W
--000000 -----110
PSDR37 [R/W] H,W
00000000 00000000
Document Number: 002-04662 Rev. *D Page 106 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001CCC
H
PTPC37 [R/W] H,W
00000000 00000000 ― ― PPG37
001CD0H
PCN38 [R/W] B,H,W
00000000 000000-0
PCSR38 [W] H,W
XXXXXXXX XXXXXXXX
PPG38
001CD4H
PDUT38 [W] H,W
XXXXXXXX XXXXXXXX
PTMR38 [R] H,W
11111111 11111111
001CD8H
PCN238 [R/W] B,H,W
--000000 -----110
PSDR38 [R/W] H,W
00000000 00000000
001CDC
H
PTPC38 [R/W] H,W
00000000 00000000
― ―
001CE0H
PCN39 [R/W] B,H,W
00000000 000000-0
PCSR39 [W] H,W
XXXXXXXX XXXXXXXX PPG39
001CE4H
PDUT39 [W] H,W
XXXXXXXX XXXXXXXX
PTMR39 [R] H,W
11111111 11111111
PPG39
001CE8H
PCN239 [R/W] B,H,W
--000000 -----110
PSDR39 [R/W] H,W
00000000 00000000
001CECH
PTPC39 [R/W] H,W
00000000 00000000
― ―
001CF0H
PCN40 [R/W] B,H,W
00000000 000000-0
PCSR40 [W] H,W
XXXXXXXX XXXXXXXX
PPG40
001CF4H
PDUT40 [W] H,W
XXXXXXXX XXXXXXXX
PTMR40 [R] H,W
11111111 11111111
001CF8H
PCN240 [R/W] B,H,W
--000000 -----110
PSDR40 [R/W] H,W
00000000 00000000
001CFCH
PTPC40 [R/W] H,W
00000000 00000000
― ―
001D00H
PCN41 [R/W] B,H,W
00000000 000000-0
PCSR41 [W] H,W
XXXXXXXX XXXXXXXX
PPG41
001D04H
PDUT41 [W] H,W
XXXXXXXX XXXXXXXX
PTMR41 [R] H,W
11111111 11111111
001D08H
PCN241 [R/W] B,H,W
--000000 -----110
PSDR41 [R/W] H,W
00000000 00000000
001D0CH
PTPC41 [R/W] H,W
00000000 00000000
― ―
001D10H
PCN42 [R/W] B,H,W
00000000 000000-0
PCSR42 [W] H,W
XXXXXXXX XXXXXXXX
PPG42
001D14H
PDUT42 [W] H,W
XXXXXXXX XXXXXXXX
PTMR42 [R] H,W
11111111 11111111
001D18H
PCN242 [R/W] B,H,W
--000000 -----110
PSDR42 [R/W] H,W
00000000 00000000
001D1CH
PTPC42 [R/W] H,W
00000000 00000000
― ―
Document Number: 002-04662 Rev. *D Page 107 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001D20H
PCN43 [R/W] B,H,W
00000000 000000-0
PCSR43 [W] H,W
XXXXXXXX XXXXXXXX
PPG43
001D24H
PDUT43 [W] H,W
XXXXXXXX XXXXXXXX
PTMR43 [R] H,W
11111111 11111111
001D28H
PCN243 [R/W] B,H,W
--000000 -----110
PSDR43 [R/W] H,W
00000000 00000000
001D2CH
PTPC43 [R/W] H,W
00000000 00000000 ― ―
001D30H
PCN44 [R/W] B,H,W
00000000 000000-0
PCSR44 [W] H,W
XXXXXXXX XXXXXXXX
PPG44
001D34H
PDUT44 [W] H,W
XXXXXXXX XXXXXXXX
PTMR44 [R] H,W
11111111 11111111
001D38H
PCN244 [R/W] B,H,W
--000000 -----110
PSDR44 [R/W] H,W
00000000 00000000
001D3CH
PTPC44 [R/W] H,W
00000000 00000000 ― ―
001D40H
PCN45 [R/W] B,H,W
00000000 000000-0
PCSR45 [W] H,W
XXXXXXXX XXXXXXXX
PPG45
001D44H
PDUT45 [W] H,W
XXXXXXXX XXXXXXXX
PTMR45 [R] H,W
11111111 11111111
001D48H
PCN245 [R/W] B,H,W
--000000 -----110
PSDR45 [R/W] H,W
00000000 00000000
001D4CH
PTPC45 [R/W] H,W
00000000 00000000 ― ―
001D50H
PCN46 [R/W] B,H,W
00000000 000000-0
PCSR46 [W] H,W
XXXXXXXX XXXXXXXX
PPG46
001D54H
PDUT46 [W] H,W
XXXXXXXX XXXXXXXX
PTMR46 [R] H,W
11111111 11111111
001D58H
PCN246 [R/W] B,H,W
--000000 -----110
PSDR46 [R/W] H,W
00000000 00000000
001D5CH
PTPC46 [R/W] H,W
00000000 00000000
― ―
001D60H
PCN47 [R/W] B,H,W
00000000 000000-0
PCSR47 [W] H,W
XXXXXXXX XXXXXXXX
PPG47
001D64H
PDUT47 [W] H,W
XXXXXXXX XXXXXXXX
PTMR47 [R] H,W
11111111 11111111
001D68H
PCN247 [R/W] B,H,W
--000000 -----110
PSDR47 [R/W] H,W
00000000 00000000
001D6CH
PTPC47 [R/W] H,W
00000000 00000000 ― ―
Document Number: 002-04662 Rev. *D Page 108 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
001D70H
to
001FFCH
― ― ― ― Reserved
002000H
CTRLR0 [R/W] B,H,W
-------- 000-0001
STATR0 [R/W] B,H,W
-------- 00000000
CAN0
(128msb)
002004H
ERRCNT0 [R] B,H,W
00000000 00000000
BTR0 [R/W] B,H,W
-0100011 00000001
002008H
INTR0 [R] B,H,W
00000000 00000000
TESTR0 [R/W] B,H,W
-------- X00000--
00200CH
BRPER0 [R/W] B,H,W
-------- ----0000 ― ―
002010H
IF1CREQ0 [R/W] B,H,W
0------- 00000001
IF1CMSK0 [R/W] B,H,W
-------- 00000000
002014H
IF1MSK20 [R/W] B,H,W
11-11111 11111111
IF1MSK10 [R/W] B,H,W
11111111 11111111
002018H
IF1ARB20 [R/W] B,H,W
00000000 00000000
IF1ARB10 [R/W] B,H,W
00000000 00000000
00201CH
IF1MCTR0 [R/W] B,H,W
00000000 0---0000 ― ―
002020H
IF1DTA10 [R/W] B,H,W
00000000 00000000
IF1DTA20 [R/W] B,H,W
00000000 00000000
002024H
IF1DTB10 [R/W] B,H,W
00000000 00000000
IF1DTB20 [R/W] B,H,W
00000000 00000000
002028H
― ― ― ―
00202CH
― ― ― ―
002030H,
002034H
Reserved(IF1 data mirror)
002038H
― ― ― ―
00203CH
― ― ― ―
002040H
IF2CREQ0 [R/W] B,H,W
0------- 00000001
IF2CMSK0 [R/W] B,H,W
-------- 00000000
002044H
IF2MSK20 [R/W] B,H,W
11-11111 11111111
IF2MSK10 [R/W] B,H,W
11111111 11111111
002048H
IF2ARB20 [R/W] B,H,W
00000000 00000000
IF2ARB10 [R/W] B,H,W
00000000 00000000
00204CH
IF2MCTR0 [R/W] B,H,W
00000000 0---0000 ― ―
002050H
IF2DTA10 [R/W] B,H,W
00000000 00000000
IF2DTA20 [R/W] B,H,W
00000000 00000000
Document Number: 002-04662 Rev. *D Page 109 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
002054H
IF2DTB10 [R/W] B,H,W
00000000 00000000
IF2DTB20 [R/W] B,H,W
00000000 00000000
CAN0
(128msb)
002058H
― ― ― ―
00205CH
― ― ― ―
002060H,
002064H
Reserved(IF2 data mirror)
002068H
to
00207CH
―
002080H
TREQR20 [R] B,H,W
00000000 00000000
TREQR10 [R] B,H,W
00000000 00000000
002084H
TREQR40 [R] B,H,W
00000000 00000000
TREQR30 [R] B,H,W
00000000 00000000
002088H
TREQR60 [R] B,H,W
00000000 00000000
TREQR50 [R] B,H,W
00000000 00000000
00208CH
TREQR80 [R] B,H,W
00000000 00000000
TREQR70 [R] B,H,W
00000000 00000000
002090H
NEWDT20 [R] B,H,W
00000000 00000000
NEWDT10 [R] B,H,W
00000000 00000000
002094H
NEWDT40 [R] B,H,W
00000000 00000000
NEWDT30 [R] B,H,W
00000000 00000000
002098H
NEWDT60 [R] B,H,W
00000000 00000000
NEWDT50 [R] B,H,W
00000000 00000000
00209CH
NEWDT80 [R] B,H,W
00000000 00000000
NEWDT70 [R] B,H,W
00000000 00000000
0020A0H
INTPND20 [R] B,H,W
00000000 00000000
INTPND10 [R] B,H,W
00000000 00000000
0020A4H
INTPND40 [R] B,H,W
00000000 00000000
INTPND30 [R] B,H,W
00000000 00000000
0020A8H
INTPND60 [R] B,H,W
00000000 00000000
INTPND50 [R] B,H,W
00000000 00000000
0020ACH
INTPND80 [R] B,H,W
00000000 00000000
INTPND70 [R] B,H,W
00000000 00000000
0020B0H
MSGVAL20 [R] B,H,W
00000000 00000000
MSGVAL10 [R] B,H,W
00000000 00000000
0020B4H
MSGVAL40 [R] B,H,W
00000000 00000000
MSGVAL30 [R] B,H,W
00000000 00000000
0020B8H
MSGVAL60 [R] B,H,W
00000000 00000000
MSGVAL50 [R] B,H,W
00000000 00000000
Document Number: 002-04662 Rev. *D Page 110 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0020BCH
MSGVAL80 [R] B,H,W
00000000 00000000
MSGVAL70 [R] B,H,W
00000000 00000000
CAN0
(128msb)
0020C0H
to
0020FCH
―
002100H
CTRLR1 [R/W] B,H,W
-------- 000-0001
STATR1 [R/W] B,H,W
-------- 00000000
CAN1
(64msb)
002104H
ERRCNT1 [R] B,H,W
00000000 00000000
BTR1 [R/W] B,H,W
-0100011 00000001
002108H
INTR1 [R] B,H,W
00000000 00000000
TESTR1 [R/W] B,H,W
-------- X00000--
00210CH
BRPER1 [R/W] B,H,W
-------- ----0000
― ―
002110H IF1CREQ1 [R/W] B,H,W
0------- 00000001
IF1CMSK1 [R/W] B,H,W
-------- 00000000
002114H IF1MSK21 [R/W] B,H,W
11-11111 11111111
IF1MSK11 [R/W] B,H,W
11111111 11111111
002118H IF1ARB21 [R/W] B,H,W
00000000 00000000
IF1ARB11 [R/W] B,H,W
00000000 00000000
00211CH
IF1MCTR1 [R/W] B,H,W
00000000 0---0000 ― ―
002120H
IF1DTA11 [R/W] B,H,W
00000000 00000000
IF1DTA21 [R/W] B,H,W
00000000 00000000
002124H
IF1DTB11 [R/W] B,H,W
00000000 00000000
IF1DTB21 [R/W] B,H,W
00000000 00000000
002128H
― ― ― ―
00212CH
― ― ― ―
002130H,
002134H
Reserved (IF1 data mirror)
CAN1
(64msb)
002138H
― ― ― ―
00213CH
― ― ― ―
002140H
IF2CREQ1 [R/W] B,H,W
0------- 00000001
IF2CMSK1 [R/W] B,H,W
-------- 00000000
002144H
IF2MSK21 [R/W] B,H,W
11-11111 11111111
IF2MSK11 [R/W] B,H,W
11111111 11111111
002148H
IF2ARB21 [R/W] B,H,W
00000000 00000000
IF2ARB11 [R/W] B,H,W
00000000 00000000
00214CH
IF2MCTR1 [R/W] B,H,W
00000000 0---0000 ― ―
Document Number: 002-04662 Rev. *D Page 111 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
002150H
IF2DTA11 [R/W] B,H,W
00000000 00000000
IF2DTA21 [R/W] B,H,W
00000000 00000000
CAN1
(64msb)
002154H
IF2DTB11 [R/W] B,H,W
00000000 00000000
IF2DTB21 [R/W] B,H,W
00000000 00000000
002158H
― ― ― ―
00215CH
― ― ― ―
002160H,
002164H
Reserved (IF2 data mirror)
002168H
to
00217CH
―
002180H
TREQR21 [R] B,H,W
00000000 00000000
TREQR11 [R] B,H,W
00000000 00000000
002184H
TREQR41 [R] B,H,W
00000000 00000000
TREQR31 [R] B,H,W
00000000 00000000
002188H
― ― ― ―
00218CH
― ― ― ―
002190H
NEWDT21 [R] B,H,W
00000000 00000000
NEWDT11 [R] B,H,W
00000000 00000000
002194H
NEWDT41 [R] B,H,W
00000000 00000000
NEWDT31 [R] B,H,W
00000000 00000000
002198H
― ― ― ―
00219CH
― ― ― ―
0021A0H
INTPND21 [R] B,H,W
00000000 00000000
INTPND11 [R] B,H,W
00000000 00000000
0021A4H
INTPND41 [R] B,H,W
00000000 00000000
INTPND31 [R] B,H,W
00000000 00000000
0021A8H
― ― ― ―
0021ACH
― ― ― ―
0021B0H
MSGVAL21 [R] B,H,W
00000000 00000000
MSGVAL11 [R] B,H,W
00000000 00000000
0021B4H
MSGVAL41 [R] B,H,W
00000000 00000000
MSGVAL31 [R] B,H,W
00000000 00000000
0021B8H
― ― ― ―
0021BCH
― ― ― ―
Document Number: 002-04662 Rev. *D Page 112 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
0021C0H
to
0021FCH
― CAN1
(64msb)
002200H
CTRLR2 [R/W] B,H,W
-------- 000-0001
STATR2 [R/W] B,H,W
-------- 00000000
CAN2
(64msb)
002204H
ERRCNT2 [R] B,H,W
00000000 00000000
BTR2 [R/W] B,H,W
-0100011 00000001
002208H
INTR2 [R] B,H,W
00000000 00000000
TESTR2 [R/W] B,H,W
-------- X00000--
00220CH
BRPER2 [R/W] B,H,W
-------- ----0000 ―
002210H
IF1CREQ2 [R/W] B,H,W
0------- 00000001
IF1CMSK2 [R/W] B,H,W
-------- 00000000
002214H
IF1MSK22 [R/W] B,H,W
11-11111 11111111
IF1MSK12 [R/W] B,H,W
11111111 11111111
002218H
IF1ARB22 [R/W] B,H,W
00000000 00000000
IF1ARB12 [R/W] B,H,W
00000000 00000000
00221CH
IF1MCTR2 [R/W] B,H,W
00000000 0---0000 ―
002220H
IF1DTA12 [R/W] B,H,W
00000000 00000000
IF1DTA22 [R/W] B,H,W
00000000 00000000
002224H
IF1DTB12 [R/W] B,H,W
00000000 00000000
IF1DTB22 [R/W] B,H,W
00000000 00000000
002228H
― ― ― ―
00222CH
― ― ― ―
002230H,
002234H
Reserved (IF1 data mirror)
002238H
― ― ― ―
00223CH
― ― ― ―
002240H
IF2CREQ2 [R/W] B,H,W
0------- 00000001
IF2CMSK2 [R/W] B,H,W
-------- 00000000
002244H
IF2MSK22 [R/W] B,H,W
11-11111 11111111
IF2MSK12 [R/W] B,H,W
11111111 11111111
002248H
IF2ARB22 [R/W] B,H,W
00000000 00000000
IF2ARB12 [R/W] B,H,W
00000000 00000000
CAN2
(64msb)
00224CH
IF2MCTR2 [R/W] B,H,W
00000000 0---0000 ―
002250H
IF2DTA12 [R/W] B,H,W
00000000 00000000
IF2DTA22 [R/W] B,H,W
00000000 00000000
Document Number: 002-04662 Rev. *D Page 113 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
002254H
IF2DTB12 [R/W] B,H,W
00000000 00000000
IF2DTB22 [R/W] B,H,W
00000000 00000000
CAN2
(64msb)
002258H
― ― ― ―
00225CH
― ― ― ―
002260H,
002264H
Reserved (IF2 data mirror)
002268H
to
00227CH
―
002280H
TREQR22 [R] B,H,W
00000000 00000000
TREQR12 [R] B,H,W
00000000 00000000
002284H
TREQR42 [R] B,H,W
00000000 00000000
TREQR32 [R] B,H,W
00000000 00000000
002288H
― ― ― ―
00228CH
― ― ― ―
002290H
NEWDT22 [R] B,H,W
00000000 00000000
NEWDT12 [R] B,H,W
00000000 00000000
002294H
NEWDT42 [R] B,H,W
00000000 00000000
NEWDT32 [R] B,H,W
00000000 00000000
002298H
― ― ― ―
00229CH
― ― ― ―
0022A0H
INTPND22 [R] B,H,W
00000000 00000000
INTPND12 [R] B,H,W
00000000 00000000
0022A4H
INTPND42 [R] B,H,W
00000000 00000000
INTPND32 [R] B,H,W
00000000 00000000
0022A8H
― ― ― ―
0022ACH
― ― ― ―
0022B0H
MSGVAL22 [R] B,H,W
00000000 00000000
MSGVAL12 [R] B,H,W
00000000 00000000
0022B4H
MSGVAL42 [R] B,H,W
00000000 00000000
MSGVAL32 [R] B,H,W
00000000 00000000
0022B8H
― ― ― ―
0022BCH
― ― ― ―
0022C0H
to
0022FCH
―
Document Number: 002-04662 Rev. *D Page 114 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
002300H
DFCTLR [R/W] B,H,W
-0------ -------- ― DFSTR [R/W] B,H,W
-----001 WorkFlash
002304H
― ― ― ―
002308H
FLIFCTLR [R/W]
B,H,W
---0--00
―
FLIFFER1 [R/W]
B,H,W
--------
FLIFFER2 [R/W]
B,H,W
--------
Flash /
WorkFlash
00230CH
to
0023FCH
― Reserved
002400H
SEEARX [R] B,H,W
-0000000 00000000
DEEARX [R] B,H,W
-0000000 00000000
XBS RAM
ECC control
002404H
EECSRX [R/W]
B,H,W
----00--
― EFEARX [R/W] B,H,W
-0000000 00000000
002408H
― EFECRX [R/W] B,H,W
-------0 00000000 00000000
00240CH
to
002FFCH
― Reserved
003000H
SEEARA [R] B,H,W
-----000 00000000
DEEARA [R] B,H,W
-----000 00000000
Backup RAM
ECC control
003004H
EECSRA [R/W]
B,H,W
----00--
― EFEARA [R/W] B,H,W
-----000 00000000
003008H
― EFECRA [R/W] B,H,W
-------0 00000000 00000000
00300CH
TEAR0X[R] B,H,W
000----- -------- -0000000 00000000
RAM/ diagnosis
XBS RAM
003010H
TEAR1X[R] B,H,W
000----- -------- -0000000 00000000
003014H
TEAR2X[R] B,H,W
000----- -------- -0000000 00000000
003018H
TAEARX [R/W] B,H,W
-1111111 11111111
TASARX [R/W] B,H,W
-0000000 00000000
00301CH
TFECRX [R/W]
B,H,W
----0000
TICRX [R/W]
B,H,W
----0000
TTCRX [R/W] B,H,W
------00 00001100
003020H
TSRCRX [W]
B,H,W
0-------
― ―
TKCCRX [R/W]
B,H,W
00----00
003024H
to
00302CH
― Reserved
Document Number: 002-04662 Rev. *D Page 115 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
003030H
TEAR0A[R] B,H,W
000----- -------- -----000 00000000
RAM/ diagnosis
Backup RAM
003034H
TEAR1A[R] B,H,W
000----- -------- -----000 00000000
003038H
TEAR2A[R] B,H,W
000----- -------- -----000 00000000
00303CH
TAEARA[R/W] B,H,W
-----111 11111111
TASARA[R/W] B,H,W
-----000 00000000
003040H
TFECRA [R/W]
B,H,W
----0000
TICRA [R/W]
B,H,W
----0000
TTCRA [R/W] B,H,W
------00 00001100 RAM/ diagnosis
Backup RAM
003044H
TSRCRA [R/W]
B,H,W
0-------
― ―
TKCCRA [R/W]
B,H,W
00----00
003048H
to
0030FCH
― Reserved
003100H
BUSDIGSR0[R/W] H,W
00000000 0-----00
BUSDIGSR1[R/W] H,W
00000000 0-----00
BUS diagnosis
003104H
BUSDIGSR2[R/W] H,W
00000000 0-----00
BUSTSTR0[R/W] H,W
00--0000 00000000
003108H
BUSADR0 [R] W
00000000 00000000 00000000 00000000
00310CH
BUSADR1 [R] W
00000000 00000000 00000000 00000000
003110H BUSADR2 [R] W
00000000 00000000 00000000 00000000
003114H ― ― BUSDIGSR3[R/W] H,W
00000000 0-----00
003118H BUSDIGSR4[R/W] H,W
00000000 0-----00
BUSTSTR1[R/W] H,W
00--000- 00000000
00311CH
― ― ― ―
003120H
BUSADR3 [R] W
00000000 00000000 00000000 00000000
003124H
BUSADR4 [R] W
00000000 00000000 00000000 00000000
003128H
to
003FFCH
― Reserved
004000H
to
005FFCH
Backup-RAM Backup RAM
area
Document Number: 002-04662 Rev. *D Page 116 of 289
MB91520 Series
Address
Address offset value / Register name
Block
+0 +1 +2 +3
006000H
to
00EFFCH
― ― ― ― Reserved
00F000H
to
00FEFCH
― ― ― ― Reserved [S]
00FF00H
DSUCR [R/W] B,H,W
-------- -------0 ― ― OCDU [S]
00FF04H
to
00FF0CH
― Reserved [S]
00FF10H
PCSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCDU [S]
00FF14H
PSSR [R/W] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCDU [S]
00FF18H
to
00FFF4H
― Reserved [S]
00FFF8H
EDIR1 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
OCDU [S]
00FFFCH
EDIR0 [R] B,H,W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
[S]: It is a system register. The illegal instruction exception (data access error) is generated in these registers in the user mode
when reading and writing to it.
Document Number: 002-04662 Rev. *D Page 117 of 289
MB91520 Series
10. Interrupt Vector Table
This list shows the assignments of interrupt factors and interrupt vectors/interrupt control registers.
Interrupt vector
64 pins
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
Reset
0
0
-
3FCH
000FFFFCH
-
System reserved
1
1
-
3F8H
000FFFF8H
-
System reserved
2
2
-
3F4H
000FFFF4H
-
System reserved
3
3
-
3F0H
000FFFF0H
-
System reserved
4
4
-
3ECH
000FFFECH
-
FPU exception
5
5
-
3E8H
000FFFE8H
-
Exception of instruction access protection violation
6
6
-
3E4H
000FFFE4H
-
Exception of data access protection violation
7
7
-
3E0H
000FFFE0H
-
Data access error interrupt
8
8
-
3DCH
000FFFDCH
-
INTE instruction
9
9
-
3D8H
000FFFD8H
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
NMI request
15 0F 15 (FH)
Fixed 3C0H 000FFFC0H -
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00
3BCH
000FFFBCH
0
External interrupt 8-15
17 11 ICR01 3B8H 000FFFB8H 1*7
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 3/6/7
19
13
ICR03
3B0H
000FFFB0H
3*2
Multi-function serial interface ch.0 (reception
completed)
20 14 ICR04 3ACH 000FFFACH 4*1
Multi-function serial interface ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
21 15 ICR05 3A8H 000FFFA8H 5*1
-
22
16
ICR06
3A4H
000FFFA4H
-*6
-
23
17
ICR07
3A0H
000FFFA0H
-*6
-
24
18
ICR08
39CH
000FFF9CH
-*6
-
25
19
ICR09
398H
000FFF98H
-*6
Multi-function serial interface
ch.3 (reception completed)
26 1A ICR10 394H 000FFF94H 10*1
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
ch.3 (transmission completed)
27 1B ICR11 390H 000FFF90H 11
Document Number: 002-04662 Rev. *D Page 118 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
Multi-function serial interface
ch.4 (reception completed)
28 1C ICR12 38CH 000FFF8CH 12*1
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
29 1D ICR13 388H 000FFF88H 13
Multi-function serial interface
ch.5 (reception completed)
30 1E ICR14 384H 000FFF84H 14*1
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
31 1F ICR15 380H 000FFF80H 15
Multi-function serial interface
ch.6 (reception completed)
32 20 ICR16 37CH 000FFF7CH 16*1
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
33 21 ICR17 378H 000FFF78H 17
CAN0
34
22
ICR18
374H
000FFF74H
-
CAN1
35 23 ICR19 370H 000FFF70H -
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
36 24 ICR20 36CH 000FFF6CH -
Up/down counter 0
Up/down counter 1
Real time clock
37
25
ICR21
368H
000FFF68H
-
-
38
26
ICR22
364H
000FFF64H
-*6
16-bit Free-run timer 0 (0 detection) /
(compare clear)
39 27 ICR23 360H 000FFF60H 23
PPG 1/10/11/20/30/31
40 28 ICR24 35CH 000FFF5CH 24*3
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/23/43
41 29 ICR25 358H 000FFF58H 25*3
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/24/35
42
2A
ICR26
354H
000FFF54H
26*3
PPG 7/16/17/27/37
43
2B
ICR27
350H
000FFF50H
27*3
PPG 19
44
2C
ICR28
34CH
000FFF4CH
28*3
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
45
2D
ICR29
348H
000FFF48H
29
Main timer
46 2E ICR30 344H 000FFF44H 30
Sub timer
PLL timer
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Document Number: 002-04662 Rev. *D Page 119 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
Clock calibration unit (sub oscillation)
47 2F ICR31 340H 000FFF40H 31*1,*4
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/10/11/14/15/16/17/22/27/28/31
48 30 ICR32 33CH 000FFF3CH 32
Clock calibration unit (CR oscillation)
49 31 ICR33 338H 000FFF38H 33
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
50 32 ICR34 334H 000FFF34H 34*5
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
51
33
ICR35
330H
000FFF30H
35
32-bit ICU6 (fetching/measurement)
52 34 ICR36 32CH 000FFF2CH 36*1
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
Multi-function serial interface
ch.10 (transmission completed)
53 35 ICR37 328H 000FFF28H 37
32-bit ICU8 (fetching/measurement)
54 36 ICR38 324H 000FFF24H 38*1
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
55 37 ICR39 320H 000FFF20H 39
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
56 38 ICR40 31CH 000FFF1CH 40
Multi-function serial interface
ch.11 (transmission completed)
32-bit ICU5 (fetching/measurement)
57 39 ICR41 318H 000FFF18H 41
A/D converter
32/34/35/37/38/40/41/42/43/44/45/46/47
32-bit OCU7/11 (match)
58
3A
ICR42
314H
000FFF14H
42
32-bit OCU8/9 (match)
59
3B
ICR43
310H
000FFF10H
43
-
60
3C
ICR44
30CH
000FFF0CH
-*6
-
61 3D ICR45 308H 000FFF08H -
-
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS
TM
*
8
)
64 40 - 2FCH 000FFEFCH -
System reserved
(Used for REALOS)
65 41 - 2F8H 000FFEF8H -
Document Number: 002-04662 Rev. *D Page 120 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
Used with the INT instruction
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
*8: REALOS is a trademark of Cypress.
Document Number: 002-04662 Rev. *D Page 121 of 289
MB91520 Series
80 pins
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
Reset
0
0
-
3FCH
000FFFFCH
-
System reserved
1
1
-
3F8H
000FFFF8H
-
System reserved
2
2
-
3F4H
000FFFF4H
-
System reserved
3
3
-
3F0H
000FFFF0H
-
System reserved
4
4
-
3ECH
000FFFECH
-
FPU exception
5
5
-
3E8H
000FFFE8H
-
Exception of instruction access protection
violation
6 6 - 3E4H 000FFFE4H -
Exception of data access protection violation
7
7
-
3E0H
000FFFE0H
-
Data access error interrupt
8
8
-
3DCH
000FFFDCH
-
INTE instruction
9
9
-
3D8H
000FFFD8H
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
NMI request
15 0F 15 (FH)
Fixed 3C0H 000FFFC0H -
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00
3BCH
000FFFBCH
0
External interrupt 8-15
17 11 ICR01 3B8H 000FFFB8H 1*7
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 3/6/7
19
13
ICR03
3B0H
000FFFB0H
3*2
Multi-function serial interface
ch.0 (reception completed)
20 14 ICR04 3ACH 000FFFACH 4*1
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
21 15 ICR05 3A8H 000FFFA8H 5*1
-
22
16
ICR06
3A4H
000FFFA4H
-*6
-
23
17
ICR07
3A0H
000FFFA0H
-*6
Multi-function serial interface
ch.2 (reception completed)
24 18 ICR08 39CH 000FFF9CH 8*1
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
25 19 ICR09 398H 000FFF98H 9*1
Multi-function serial interface
ch.3 (reception completed)
26 1A ICR10 394H 000FFF94H 10*1
Multi-function serial interface
ch.3 (status)
Multi-function serial interface
ch.3 (transmission completed)
27 1B ICR11 390H 000FFF90H 11
Document Number: 002-04662 Rev. *D Page 122 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
Multi-function serial interface
ch.4 (reception completed)
28 1C ICR12 38CH 000FFF8CH 12*1
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
29 1D ICR13 388H 000FFF88H 13
Multi-function serial interface
ch.5 (reception completed)
30 1E ICR14 384H 000FFF84H 14*1
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
31 1F ICR15 380H 000FFF80H 15
Multi-function serial interface
ch.6 (reception completed)
32 20 ICR16 37CH 000FFF7CH 16*1
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
33 21 ICR17 378H 000FFF78H 17
CAN0
34
22
ICR18
374H
000FFF74H
-
CAN1
35 23 ICR19 370H 000FFF70H -
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
36 24 ICR20 36CH 000FFF6CH -
Up/down counter 0
Up/down counter 1
Real time clock
37
25
ICR21
368H
000FFF68H
-
-
38
26
ICR22
364H
000FFF64H
-*6
16-bit Free-run timer 0 (0 detection) /
(compare clear)
39 27 ICR23 360H 000FFF60H 23
PPG 1/10/11/20/30/31
40 28 ICR24 35CH 000FFF5CH 24*3
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/23/43
41 29 ICR25 358H 000FFF58H 25*3
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/15/24/35
42
2A
ICR26
354H
000FFF54H
26*3
PPG 7/16/17/26/27/37
43
2B
ICR27
350H
000FFF50H
27*3
PPG 8/18/19/29
44
2C
ICR28
34CH
000FFF4CH
28*3
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
45
2D
ICR29
348H
000FFF48H
29
Main timer
46 2E ICR30 344H 000FFF44H 30
Sub timer
PLL timer
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Document Number: 002-04662 Rev. *D Page 123 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
Clock calibration unit
(sub oscillation)
47 2F ICR31 340H 000FFF40H 31*1,*4
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/10/11/12/14/15/16/17/19/22/26/27/28/31
48 30 ICR32 33CH 000FFF3CH 32
Clock calibration unit (CR oscillation)
49 31 ICR33 338H 000FFF38H 33
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
50 32 ICR34 334H 000FFF34H 34*5
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 5
51 33 ICR35 330H 000FFF30H 35*5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
52 34 ICR36 32CH 000FFF2CH 36*1
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
Multi-function serial interface
ch.10 (transmission completed)
53 35 ICR37 328H 000FFF28H 37
32-bit ICU8 (fetching/measurement)
54 36 ICR38 324H 000FFF24H 38*1
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
55 37 ICR39 320H 000FFF20H 39
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
56 38 ICR40 31CH 000FFF1CH 40
Multi-function serial interface
ch.11 (transmission completed)
32-bit ICU5 (fetching/measurement)
57 39 ICR41 318H 000FFF18H 41
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/
47
32-bit OCU7/11 (match)
58
3A
ICR42
314H
000FFF14H
42
32-bit OCU8/9 (match)
59
3B
ICR43
310H
000FFF10H
43
-
60
3C
ICR44
30CH
000FFF0CH
-*6
Base timer 1 IRQ0
61 3D ICR45 308H 000FFF08H 45
Base timer 1 IRQ1
-
-
DMAC
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62 3E ICR46 304H 000FFF04H -
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
Document Number: 002-04662 Rev. *D Page 124 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decimal
System reserved
(Used for REALOS)
64 40 - 2FCH 000FFEFCH -
System reserved
(Used for REALOS)
65 41 - 2F8H 000FFEF8H -
Used with the INT instruction
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Document Number: 002-04662 Rev. *D Page 125 of 289
MB91520 Series
100 pins
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Reset
0
0
-
3FCH
000FFFFCH
-
System reserved
1
1
-
3F8H
000FFFF8H
-
System reserved
2
2
-
3F4H
000FFFF4H
-
System reserved
3
3
-
3F0H
000FFFF0H
-
System reserved
4
4
-
3ECH
000FFFECH
-
FPU exception
5
5
-
3E8H
000FFFE8H
-
Exception of instruction access protection
violation
6 6 - 3E4H 000FFFE4H
-
Exception of data access protection violation
7
7
-
3E0H
000FFFE0H
-
Data access error interrupt
8
8
-
3DCH
000FFFDCH
-
INTE instruction
9
9
-
3D8H
000FFFD8H
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
NMI request
15 0F 15 (FH)
Fixed 3C0H 000FFFC0H
-
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00
3BCH
000FFFBCH
0
External interrupt 8-15
17 11 ICR01 3B8H 000FFFB8H
1*7
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 2/3/6/7
19
13
ICR03
3B0H
000FFFB0H
3*2
Multi-function serial interface
ch.0 (reception completed)
20 14 ICR04 3ACH 000FFFACH
4*1
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
21 15 ICR05 3A8H 000FFFA8H
5*1
Multi-function serial interface
ch.1 (reception completed)
22 16 ICR06 3A4H 000FFFA4H
6*1
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
23 17 ICR07 3A0H 000FFFA0H
7*1
Multi-function serial interface
ch.2 (reception completed)
24 18 ICR08 39CH 000FFF9CH
8*1
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
25 19 ICR09 398H 000FFF98H
9*1
Multi-function serial interface
ch.3 (reception completed)
26 1A ICR10 394H 000FFF94H
10*1
Multi-function serial interface
ch.3 (status)
Document Number: 002-04662 Rev. *D Page 126 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Multi-function serial interface
ch.3 (transmission completed)
27 1B ICR11 390H 000FFF90H
11
Multi-function serial interface
ch.4 (reception completed)
28 1C ICR12 38CH 000FFF8CH
12*1
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
29 1D ICR13 388H 000FFF88H
13
Multi-function serial interface
ch.5 (reception completed)
30 1E ICR14 384H 000FFF84H
14*1
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
31 1F ICR15 380H 000FFF80H
15
Multi-function serial interface
ch.6 (reception completed)
32 20 ICR16 37CH 000FFF7CH
16*1
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
33 21 ICR17 378H 000FFF78H
17
CAN0
34
22
ICR18
374H
000FFF74H
-
CAN1
35 23 ICR19 370H 000FFF70H
-
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
36 24 ICR20 36CH 000FFF6CH
-
Up/down counter 0
Up/down counter 1
Real time clock
37
25
ICR21
368H
000FFF68H
-
Multi-function serial interface
ch.7 (reception completed)
38 26 ICR22 364H 000FFF64H
22*1
Multi-function serial interface
ch.7 (status)
16-bit Free-running timer 0 (0 detection) /
(compare clear)
39 27 ICR23 360H 000FFF60H
23
Multi-function serial interface
ch.7 (transmission completed)
PPG 1/10/11/20/21/30/31
40 28 ICR24 35CH 000FFF5CH
24*3
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/23/32/43
41 29 ICR25 358H 000FFF58H
25*3
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/35/44
42
2A
ICR26
354H
000FFF54H
26*3
PPG 6/7/16/17/26/27/37
43
2B
ICR27
350H
000FFF50H
27*3
PPG 8/9/18/19/28/29
44
2C
ICR28
34CH
000FFF4CH
28*3
Document Number: 002-04662 Rev. *D Page 127 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Multi-function serial interface
ch.8 (reception completed)
45 2D ICR29 348H 000FFF48H
29*1
Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
46 2E ICR30 344H 000FFF44H
30
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
47 2F ICR31 340H 000FFF40H
31*1,
*4
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/9/10/11/12/13/14/15/16
17/18/19/22/23/26/27/28/29/31
48 30 ICR32 33CH 000FFF3CH
32
Clock calibration unit (CR oscillation)
49 31 ICR33 338H 000FFF38H
33
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
50 32 ICR34 334H 000FFF34H
34*5
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
51 33 ICR35 330H 000FFF30H
35*5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
52 34 ICR36 32CH 000FFF2CH
36*1
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
53 35 ICR37 328H 000FFF28H
37
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
54 36 ICR38 324H 000FFF24H
38*1
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
55 37 ICR39 320H 000FFF20H
39
WG dead timer underflow 0/1/2
WG dead timer reload 0/1/2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
56 38 ICR40 31CH 000FFF1CH
40
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *D Page 128 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
32-bit ICU5 (fetching/measurement)
57 39 ICR41 318H 000FFF18H
41
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/
47
32-bit OCU 6/7/10/11 (match)
58
3A
ICR42
314H
000FFF14H
42
32-bit OCU 8/9 (match)
59
3B
ICR43
310H
000FFF10H
43
-
60 3C ICR44 30CH 000FFF0CH
44
-
Base timer 1 IRQ0
61 3D ICR45 308H 000FFF08H
45
Base timer 1 IRQ1
-
-
DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS)
64 40 - 2FCH 000FFEFCH
-
System reserved
(Used for REALOS)
65 41 - 2F8H 000FFEF8H
-
Used with the INT instruction
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Document Number: 002-04662 Rev. *D Page 129 of 289
MB91520 Series
120 pins
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Reset
0
0
-
3FCH
000FFFFCH
-
System reserved
1
1
-
3F8H
000FFFF8H
-
System reserved
2
2
-
3F4H
000FFFF4H
-
System reserved
3
3
-
3F0H
000FFFF0H
-
System reserved
4
4
-
3ECH
000FFFECH
-
FPU exception
5
5
-
3E8H
000FFFE8H
-
Exception of instruction access protection violation
6
6
-
3E4H
000FFFE4H
-
Exception of data access protection violation
7
7
-
3E0H
000FFFE0H
-
Data access error interrupt
8
8
-
3DCH
000FFFDCH
-
INTE instruction
9
9
-
3D8H
000FFFD8H
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
NMI request
15 0F 15 (FH)
Fixed 3C0H 000FFFC0H
-
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00
3BCH
000FFFBCH
0
External interrupt 8-15
17 11 ICR01 3B8H 000FFFB8H
1*7
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 2/3/6/7
19
13
ICR03
3B0H
000FFFB0H
3*2
Multi-function serial interface
ch.0 (reception completed)
20 14 ICR04 3ACH 000FFFACH
4*1
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
21 15 ICR05 3A8H 000FFFA8H
5*1
Multi-function serial interface
ch.1 (reception completed)
22 16 ICR06 3A4H 000FFFA4H
6*1
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
23 17 ICR07 3A0H 000FFFA0H
7*1
Multi-function serial interface
ch.2 (reception completed)
24 18 ICR08 39CH 000FFF9CH
8*1
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
25 19 ICR09 398H 000FFF98H
9*1
Multi-function serial interface
ch.3 (reception completed)
26 1A ICR10 394H 000FFF94H
10*1
Multi-function serial interface
ch.3 (status)
Document Number: 002-04662 Rev. *D Page 130 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Multi-function serial interface
ch.3 (transmission completed)
27 1B ICR11 390H 000FFF90H
11
Multi-function serial interface
ch.4 (reception completed)
28 1C ICR12 38CH 000FFF8CH
12*1
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
29 1D ICR13 388H 000FFF88H
13
Multi-function serial interface
ch.5 (reception completed)
30 1E ICR14 384H 000FFF84H
14*1
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
31 1F ICR15 380H 000FFF80H
15
Multi-function serial interface
ch.6 (reception completed)
32 20 ICR16 37CH 000FFF7CH
16*1
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
33 21 ICR17 378H 000FFF78H
17
CAN0
34
22
ICR18
374H
000FFF74H
-
CAN1
35 23 ICR19 370H 000FFF70H
-
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
36 24 ICR20 36CH 000FFF6CH
-
Up/down counter 0
Up/down counter 1
Real time clock
37
25
ICR21
368H
000FFF68H
-
Multi-function serial interface
ch.7 (reception completed)
38 26 ICR22 364H 000FFF64H
22*1
Multi-function serial interface
ch.7 (status)
16-bit Free-run timer 0 (0 detection) /
(compare clear)
39 27 ICR23 360H 000FFF60H
23
Multi-function serial interface
ch.7 (transmission completed)
PPG 0/1/10/11/20/21/30/31
40 28 ICR24 35CH 000FFF5CH
24*3
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/22/23/32/33/43
41 29 ICR25 358H 000FFF58H
25*3
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/35/44
42
2A
ICR26
354H
000FFF54H
26*3
PPG 6/7/16/17/26/27/37
43
2B
ICR27
350H
000FFF50H
27*3
PPG 8/9/18/19/28/29
44
2C
ICR28
34CH
000FFF4CH
28*3
Document Number: 002-04662 Rev. *D Page 131 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Multi-function serial interface
ch.8 (reception completed)
45 2D ICR29 348H 000FFF48H
29*1 Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
46 2E ICR30 344H 000FFF44H
30
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
47 2F ICR31 340H 000FFF40H
31*1, *4
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/7/9/10/11/12/13/14/15/16/
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
48 30 ICR32 33CH 000FFF3CH
32
Clock calibration unit ( CR oscillation)
49 31 ICR33 338H 000FFF38H
33
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
50 32 ICR34 334H 000FFF34H
34*5
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
51 33 ICR35 330H 000FFF30H
35*5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
52 34 ICR36 32CH 000FFF2CH
36*1
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
53 35 ICR37 328H 000FFF28H
37
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
54 36 ICR38 324H 000FFF24H
38*1
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
55 37 ICR39 320H 000FFF20H
39
WG dead timer underflow 0/1/2
WG dead timer reload 0/1/2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
56 38 ICR40 31CH 000FFF1CH
40
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *D Page 132 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
32-bit ICU5 (fetching/measurement)
57 39 ICR41 318H 000FFF18H
41
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
32-bit OCU 6/7/10/11 (match)
58
3A
ICR42
314H
000FFF14H
42
32-bit OCU 8/9 (match)
59
3B
ICR43
310H
000FFF10H
43
-
60 3C ICR44 30CH 000FFF0CH
44
-
Base timer 1 IRQ0
61 3D ICR45 308H 000FFF08H
45
Base timer 1 IRQ1
-
-
DMAC0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS)
64 40 - 2FCH 000FFEFCH
-
System reserved
(Used for REALOS)
65 41 - 2F8H 000FFEF8H
-
Used with the INT instruction
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Document Number: 002-04662 Rev. *D Page 133 of 289
MB91520 Series
144 pins
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decim
al
Reset
0
0
-
3FCH
000FFFFCH
-
System reserved
1
1
-
3F8H
000FFFF8H
-
System reserved
2
2
-
3F4H
000FFFF4H
-
System reserved
3
3
-
3F0H
000FFFF0H
-
System reserved
4
4
-
3ECH
000FFFECH
-
FPU exception
5
5
-
3E8H
000FFFE8H
-
Exception of instruction access protection
violation
6 6 - 3E4H 000FFFE4H -
Exception of data access protection violation
7
7
-
3E0H
000FFFE0H
-
Data access error interrupt
8
8
-
3DCH
000FFFDCH
-
INTE instruction
9
9
-
3D8H
000FFFD8H
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
NMI request
15 0F 15 (FH)
Fixed 3C0H 000FFFC0H -
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00
3BCH
000FFFBCH
0
External interrupt 8-15
17 11 ICR01 3B8H 000FFFB8H 1*7
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 2/3/6/7
19
13
ICR03
3B0H
000FFFB0H
3*2
Multi-function serial interface
ch.0 (reception completed)
20 14 ICR04 3ACH 000FFFACH 4*1
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
21 15 ICR05 3A8H 000FFFA8H 5*1
Multi-function serial interface
ch.1 (reception completed)
22 16 ICR06 3A4H 000FFFA4H 6*1
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
23 17 ICR07 3A0H 000FFFA0H 7*1
Multi-function serial interface
ch.2 (reception completed)
24 18 ICR08 39CH 000FFF9CH 8*1
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
25 19 ICR09 398H 000FFF98H 9*1
Multi-function serial interface
ch.3 (reception completed)
26 1A ICR10 394H 000FFF94H 10*1
Multi-function serial interface
ch.3 (status)
Document Number: 002-04662 Rev. *D Page 134 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decim
al
Multi-function serial interface
ch.3 (transmission completed)
27 1B ICR11 390H 000FFF90H 11
Multi-function serial interface
ch.4 (reception completed)
28 1C ICR12 38CH 000FFF8CH 12*1
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
29 1D ICR13 388H 000FFF88H 13
Multi-function serial interface
ch.5 (reception completed)
30 1E ICR14 384H 000FFF84H 14*1
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
31 1F ICR15 380H 000FFF80H 15
Multi-function serial interface
ch.6 (reception completed)
32 20 ICR16 37CH 000FFF7CH 16*1
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
33 21 ICR17 378H 000FFF78H 17
CAN0
34
22
ICR18
374H
000FFF74H
-
CAN1
35 23 ICR19 370H 000FFF70H -
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
36 24 ICR20 36CH 000FFF6CH -
Up/down counter 0
Up/down counter 1
Real time clock
37
25
ICR21
368H
000FFF68H
-
Multi-function serial interface
ch.7 (reception completed)
38 26 ICR22 364H 000FFF64H 22*1
Multi-function serial interface
ch.7 (status)
16-bit Free-run timer 0 (0 detection) /
(compare clear)
39 27 ICR23 360H 000FFF60H 23
Multi-function serial interface
ch.7 (transmission completed)
PPG 0/1/10/11/20/21/30/31/40/41
40 28 ICR24 35CH 000FFF5CH 24*3
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/22/23/32/33/43
41 29 ICR25 358H 000FFF58H 25*3
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/34/35/44
42
2A
ICR26
354H
000FFF54H
26*3
PPG 6/7/16/17/26/27/36/37
43
2B
ICR27
350H
000FFF50H
27*3
PPG 8/9/18/19/28/29/38/39
44
2C
ICR28
34CH
000FFF4CH
28*3
Document Number: 002-04662 Rev. *D Page 135 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decim
al
Multi-function serial interface
ch.8 (reception completed)
45 2D ICR29 348H 000FFF48H 29*1 Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
46 2E ICR30 344H 000FFF44H 30
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
47 2F ICR31 340H 000FFF40H 31*1, *4
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
48 30 ICR32 33CH 000FFF3CH 32
Clock calibration unit ( CR oscillation)
49 31 ICR33 338H 000FFF38H 33
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
50 32 ICR34 334H 000FFF34H 34*5
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
51 33 ICR35 330H 000FFF30H 35*5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU 6 (fetching/measurement)
52 34 ICR36 32CH 000FFF2CH 36*1
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
53 35 ICR37 328H 000FFF28H 37
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
54 36 ICR38 324H 000FFF24H 38*1
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
55 37 ICR39 320H 000FFF20H 39
WG dead timer underflow 0 / 1/ 2
WG dead timer reload 0 / 1/ 2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
56 38 ICR40 31CH 000FFF1CH 40
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *D Page 136 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexa
decim
al
32-bit ICU5 (fetching/measurement)
57 39 ICR41 318H 000FFF18H 41
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/47
32-bit OCU 6/7/10/11 (match)
58
3A
ICR42
314H
000FFF14H
42
32-bit OCU8/9 (match)
59
3B
ICR43
310H
000FFF10H
43
Base timer 0 IRQ0
60 3C ICR44 30CH 000FFF0CH 44
Base timer 0 IRQ1
Base timer 1 IRQ0
61 3D ICR45 308H 000FFF08H 45
Base timer 1 IRQ1
-
-
DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS)
64 40 - 2FCH 000FFEFCH -
System reserved
(Used for REALOS)
65 41 - 2F8H 000FFEF8H -
Used with the INT instruction
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Document Number: 002-04662 Rev. *D Page 137 of 289
MB91520 Series
176 pins
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Reset
0
0
-
3FCH
000FFFFCH
-
System reserved
1
1
-
3F8H
000FFFF8H
-
System reserved
2
2
-
3F4H
000FFFF4H
-
System reserved
3
3
-
3F0H
000FFFF0H
-
System reserved
4
4
-
3ECH
000FFFECH
-
FPU exception
5
5
-
3E8H
000FFFE8H
-
Exception of instruction access protection
violation
6 6 - 3E4H 000FFFE4H
-
Exception of data access protection violation
7
7
-
3E0H
000FFFE0H
-
Data access error interrupt
8
8
-
3DCH
000FFFDCH
-
INTE instruction
9
9
-
3D8H
000FFFD8H
-
Instruction break
10
0A
-
3D4H
000FFFD4H
-
System reserved
11
0B
-
3D0H
000FFFD0H
-
System reserved
12
0C
-
3CCH
000FFFCCH
-
System reserved
13
0D
-
3C8H
000FFFC8H
-
Exception of invalid instruction
14
0E
-
3C4H
000FFFC4H
-
NMI request
15 0F 15 (FH)
Fixed 3C0H 000FFFC0H
-
Error generation during internal bus diagnosis
XBS RAM double-bit error generation
Backup RAM double-bit error generation
TPU violation
External interrupt 0-7
16
10
ICR00
3BCH
000FFFBCH
0
External interrupt 8-15
17 11 ICR01 3B8H 000FFFB8H
1*7
External low-voltage detection interrupt
Reload timer 0/1/4/5
18
12
ICR02
3B4H
000FFFB4H
2*2
Reload timer 2/3/6/7
19
13
ICR03
3B0H
000FFFB0H
3*2
Multi-function serial interface
ch.0 (reception completed)
20 14 ICR04 3ACH 000FFFACH
4*1
Multi-function serial interface
ch.0 (status)
Multi-function serial interface
ch.0 (transmission completed)
21 15 ICR05 3A8H 000FFFA8H
5*1
Multi-function serial interface
ch.1 (reception completed)
22 16 ICR06 3A4H 000FFFA4H
6*1
Multi-function serial interface
ch.1 (status)
Multi-function serial interface
ch.1 (transmission completed)
23 17 ICR07 3A0H 000FFFA0H
7*1
Multi-function serial interface
ch.2 (reception completed)
24 18 ICR08 39CH 000FFF9CH
8*1
Multi-function serial interface
ch.2 (status)
Multi-function serial interface
ch.2 (transmission completed)
25 19 ICR09 398H 000FFF98H 9*1
Multi-function serial interface
ch.3 (reception completed)
26 1A ICR10 394H 000FFF94H 10*1
Multi-function serial interface
ch.3 (status)
Document Number: 002-04662 Rev. *D Page 138 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Multi-function serial interface
ch.3 (transmission completed)
27 1B ICR11 390H 000FFF90H 11
Multi-function serial interface
ch.4 (reception completed)
28 1C ICR12 38CH 000FFF8CH
12*1
Multi-function serial interface
ch.4 (status)
Multi-function serial interface
ch.4 (transmission completed)
29 1D ICR13 388H 000FFF88H 13
Multi-function serial interface
ch.5 (reception completed)
30 1E ICR14 384H 000FFF84H 14*1
Multi-function serial interface
ch.5 (status)
Multi-function serial interface
ch.5 (transmission completed)
31 1F ICR15 380H 000FFF80H 15
Multi-function serial interface
ch.6 (reception completed)
32 20 ICR16 37CH 000FFF7CH
16*1
Multi-function serial interface
ch.6 (status)
Multi-function serial interface
ch.6 (transmission completed)
33 21 ICR17 378H 000FFF78H 17
CAN0
34
22
ICR18
374H
000FFF74H
-
CAN1
35 23 ICR19 370H 000FFF70H -
RAM diagnosis end
RAM initialization completion
Error generation during RAM diagnosis
Backup RAM diagnosis end
Backup RAM initialization completion
Error generation during Backup RAM diagnosis
CAN2
36 24 ICR20 36CH 000FFF6CH
-
Up/down counter 0
Up/down counter 1
Real time clock
37
25
ICR21
368H
000FFF68H
-
Multi-function serial interface
ch.7 (reception completed)
38 26 ICR22 364H 000FFF64H 22*1
Multi-function serial interface
ch.7 (status)
16-bit Free-run timer 0 (0 detection) /
(compare clear)
39 27 ICR23 360H 000FFF60H 23
Multi-function serial interface
ch.7 (transmission completed)
PPG 0/1/10/11/20/21/30/31/40/41
40 28 ICR24 35CH 000FFF5CH
24*3
16-bit Free-run timer 1 (0 detection) /
(compare clear)
PPG 2/3/12/13/22/23/32/33/43
41 29 ICR25 358H 000FFF58H 25*3
16-bit Free-run timer 2 (0 detection) /
(compare clear)
PPG 4/5/14/15/24/25/34/35/44/45
42
2A
ICR26
354H
000FFF54H
26*3
PPG 6/7/16/17/26/27/36/37/46/47
43
2B
ICR27
350H
000FFF50H
27*3
PPG 8/9/18/19/28/29/38/39
44
2C
ICR28
34CH
000FFF4CH
28*3
Document Number: 002-04662 Rev. *D Page 139 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
Multi-function serial interface
ch.8 (reception completed)
45 2D ICR29 348H 000FFF48H 29*1 Multi-function serial interface
ch.8 (status)
16-bit ICU 0 (fetching) / 16-bit ICU 1 (fetching)
Main timer
46 2E ICR30 344H 000FFF44H 30
Sub timer
PLL timer
Multi-function serial interface
ch.8 (transmission completed)
16-bit ICU 2 (fetching) /16-bit ICU 3 (fetching)
Clock calibration unit (sub oscillation)
47 2F ICR31 340H 000FFF40H 31*1,
*4
Multi-function serial interface
ch.9 (reception completed)
Multi-function serial interface
ch.9 (status)
A/D converter
0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15/16
17/18/19/20/21/22/23/24/25/26/27/28/29/30/31
48 30 ICR32 33CH 000FFF3CH
32
Clock calibration unit (CR oscillation)
49 31 ICR33 338H 000FFF38H 33
Multi-function serial interface
ch.9 (transmission completed)
16-bit OCU 0 (match) / 16-bit OCU 1 (match)
32-bit Free-run timer 4
50 32 ICR34 334H 000FFF34H 34*5
16-bit OCU 2 (match) / 16-bit OCU 3 (match)
32-bit Free-run timer 3/5
51 33 ICR35 330H 000FFF30H 35*5
16-bit OCU 4 (match) / 16-bit OCU 5 (match)
32-bit ICU6 (fetching/measurement)
52 34 ICR36 32CH 000FFF2CH
36*1
Multi-function serial interface
ch.10 (reception completed)
Multi-function serial interface
ch.10 (status)
32-bit ICU7 (fetching/measurement)
53 35 ICR37 328H 000FFF28H 37
Multi-function serial interface
ch.10 (transmission completed)
32-bit ICU8 (fetching/measurement)
54 36 ICR38 324H 000FFF24H 38*1
Multi-function serial interface
ch.11 (reception completed)
Multi-function serial interface
ch.11 (status)
32-bit ICU9 (fetching/measurement)
55 37 ICR39 320H 000FFF20H 39
WG dead timer underflow 0/1/2
WG dead timer reload 0/1/2
WG DTTI 0
32-bit ICU4 (fetching/measurement)
56 38 ICR40 31CH 000FFF1CH
40
Multi-function serial interface
ch.11 (transmission completed)
Document Number: 002-04662 Rev. *D Page 140 of 289
MB91520 Series
Interrupt factor
Interrupt number
Interrupt
level Offset
Default
address for
TBR
RN
Decimal
Hexadecimal
32-bit ICU5 (fetching/measurement)
57 39 ICR41 318H 000FFF18H 41
A/D converter
32/33/34/35/36/37/38/39/40/41/42/43/44/45/46/
47
32-bit OCU 6/7/10/11 (match)
58
3A
ICR42
314H
000FFF14H
42
32-bit OCU 8/9 (match)
59
3B
ICR43
310H
000FFF10H
43
Base timer 0 IRQ0
60 3C ICR44 30CH 000FFF0CH
44
Base timer 0 IRQ1
Base timer 1 IRQ0
61 3D ICR45 308H 000FFF08H 45
Base timer 1 IRQ1
-
-
DMAC 0/1/2/3/4/5/6/7/8/9/10/11/12/13/14/15
62
3E
ICR46
304H
000FFF04H
-
Delay interrupt
63
3F
ICR47
300H
000FFF00H
-
System reserved
(Used for REALOS)
64 40 - 2FCH 000FFEFCH
-
System reserved
(Used for REALOS)
65 41 - 2F8H 000FFEF8H
-
Used with the INT instruction
66
|
255
42
|
FF
-
2F4H
|
000H
000FFEF4H
|
000FFC00H
-
Note: It does not support a DMA transfer request caused by an interrupt generated from a peripheral to which no
RN (Resource Number) is assigned.
*1: It does not support a DMA transfer by the status of the multi-function serial interface and I2C reception.
*2: Reload timer ch.4 to ch.7 do not support a DMA transfer by the interrupt.
*3: PPG ch.24 to ch.47 do not support a DMA transfer by the interrupt.
*4: The clock calibration unit does not support a DMA transfer by the interrupt.
*5: 32-bit Free-run timer ch.3, ch.4 and ch.5 do not support a DMA transfer by the interrupt.
*6: There is no resource corresponding to the interrupt level.
*7: It does not support a DMA transfer by the external low-voltage detection interrupt.
Document Number: 002-04662 Rev. *D Page 141 of 289
MB91520 Series
11. Electrical Characteristics
Absolute Maximum Ratings
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage *1,*2
VCC
VSS-0.3
VSS+6.0
V
Analog power supply voltage *1,*2 AVCC VSS-0.3 VSS+6.0 V AVRH ≤ AVCC ≤
VCC
Analog reference voltage *1
AVRH
VSS-0.3
VSS+6.0
V
AVRH ≤ AVCC
Input voltage *1
VI
VSS-0.3
VCC+0.3
V
Analog pin input voltage *1
VIA5
VSS-0.3
VCC+0.3
V
Output voltage *1
Vo
VSS-0.3
VCC+0.3
V
Maximum clamp current
ICLAMP
-
4.0
mA
*6
To t a l maximum clamp current
Σ|ICLAMP|
-
20
mA
*6
"L" level maximum output current *3
IOL1
-
15
mA
IOL2
-
30
mA
"L" level average output current *4
IOL AV1
-
4
mA
*9
IOL AV2
-
12
mA
*10
"L" level total output current *5
ΣIOL1
-
100
mA
ΣIOL2
-
120
mA
"H" level maximum output current*3
IOH1
-
-15
mA
IOH2
-
-30
mA
"H" level average output current*4
IOHAV1
-
-4
mA
*9
IOHAV2
-
-12
mA
*10
"H" level total output current *5
ΣIOH1
-
-100
mA
ΣIOH2
-
-120
mA
Power
consumption
TA: -40°C to +105°C
PD
-
882
mW
*8
TA: -40°C to +125°C
-
675
mW
*8
Operating temperature TA
-40
+105
°C
-40
+125
°C
*7
Storage temperature
Ts t g
-55
+150
°C
*1: These parameters are based on the condition that VSS=AVSS=0.0V
*2: Caution must be taken that AVCC, AVRH do not exceed VCC upon power-on and under other circumstances.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the corresponding pins for
a 10 ms period. The average value is the operation current × the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding pins.
*6: · Corresponding pins: all general-purpose ports except P035, 041, 093, 122.
· Use within recommended operating conditions.
· Use at DC voltage (current).
· The + B signal should always be applied by connecting a limiting resistor between the + B signal and the microcontroller.
· The value of the limiting resistor should be set so that the current input to the microcontroller pin does not exceed rated
values at any time regardless of instantaneously or constantly when the + B signal is input.
· Note that when the microcontroller drive current is low, such as in the low power consumption modes, the + B input potential
can increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
· Note that if the + B signal is input when the microcontroller is off (not fixed at 0 V), since the power is supplied through the
pin, the microcontroller may operate incompletely.
· Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset may not
function in the power supply voltage.
· Do not leave + B input pins open.
*7: When it is used under this condition, contact your sales representative.
Document Number: 002-04662 Rev. *D Page 142 of 289
MB91520 Series
*8: It is a standard when four-layer substrate is used.
*9: Corresponding pins: General-purpose ports other than those of P103, P104, P105 and P106.
*10: Corresponding pins: General-purpose ports of P103, P104, P105 and P106.
Sample Recommended Circuit
MB91520 series
+B input (12 to 16V)
Protective diode
Limiting resistor current
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Recommended operating conditions
(VSS=AVSS=0.0V)
Parameter Symbol
Value
Unit Remarks
Min Max
Power supply voltage VCC,
AVCC
4.5 5.5 V
Recommended operation
guarantee range (When 5.0V is
used)
3.0 3.6 V
Recommended operation
guarantee range (When 3.3V is
used)
2.7
5.5
V
Operation guarantee range*1
Smoothing capacitor *2 CS 4.7
(tolerance within ±50%) µF
Use a ceramic capacitor or a
capacitor that has the similar
frequency characteristics. Use a
capacitor with a capacitance
greater than CS as the smoothing
capacitor on the VCC pin.
Operating temperature TA
-40
+105
°C
-40
+125
°C
*3
*1: When it is used outside recommended operation guarantee range (range of the operation guarantee),contact your sales
representative.
The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed
operation voltage, as these detection levels are below the minimum guaranteed MCU operation voltage. Below the
Document Number: 002-04662 Rev. *D Page 143 of 289
MB91520 Series
minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
*2: See the following diagram for details on the connection of smoothing capacitor CS.
*3: When it is used under this condition, contact your sales representative.
· C Pin Connection Diagram
CS
C
VSS
AVSS
VSS
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other
than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with
respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application
under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04662 Rev. *D Page 144 of 289
MB91520 Series
DC Characteristics
(TA: -40°C to +105°C, VCC= AVcc=5.0V±10%/3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power
supply
current
ICC5
VCC
Operating frequency FCP=80MHz,
Fcpp=40MHz, at normal operation
- 60 80 mA
Operating frequency FCP=80MHz,
Fcpp=40MHz, at Flash write
- 70 90 mA
Operating frequency FCP=80MHz,
Fcpp=40MHz, at Flash erase
- 70 90 mA
Operating frequency FCP=64MHz,
Fcpp=32MHz, at normal operation
- 54 71 mA
Operating frequency FCP=64MHz,
Fcpp=32MHz, at Flash write
- 64 81 mA
Operating frequency FCP=64MHz,
Fcpp=32MHz, at Flash erase
- 64 81 mA
Operating frequency FCP=48MHz,
Fcpp=24MHz, at normal operation
- 46 62 mA
Operating frequency FCP=48MHz,
Fcpp=24MHz, at Flash write
- 56 72 mA
Operating frequency FCP=48MHz,
Fcpp=24MHz, at Flash erase
- 56 72 mA
ICCS5 Operating frequency FCP=80MHz,
Fcpp=40MHz, at CPU sleep mode
- 45 61 mA
ICCBS5 Operating frequency FCP=80MHz,
Fcpp=40MHz, at bus sleep mode
- 23 51 mA
ICCT5 Watch
mode
When using crystal
4MHz TA=+25°C
*
- 1500 2610
µA
When using built-in
CR clock 50kHz
TA=+25°C
*
- 450 2000
When using sub
clock 32kHz
TA=+25°C
*
- 460 2000
ICCH5
Stop mode
TA=+25°C*
-
450
2000
µA
ICCT52
Watch
mode
(power off)
When using crystal
4MHz TA=+25°C
*
- 1100 1300
µA
LVD/
RTC
operation,
Backup
RAM
8KB
retention
When using built-in
CR clock 50kHz ,
TA=+25°C
*
- 77 267
When using sub
clock 32kHz
TA=+25°C
*
- 100 285
ICCH52 Stop mode
(power off) TA=+25°C* - 74 265 µA
Backup
RAM 8KB
retention
Document Number: 002-04662 Rev. *D Page 145 of 289
MB91520 Series
(TA: -40°C to +125°C, VCC= AVcc=5.0V±10%/3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power
supply
current
ICC5
VCC
Operating frequency FCP=80MHz,
Fcpp=40MHz, at normal operation
- 60 102 mA
Operating frequency FCP=80MHz,
Fcpp=40MHz, at Flash write
- 70 115 mA
Operating frequency FCP=80MHz,
Fcpp=40MHz, at Flash erase
- 70 115 mA
Operating frequency FCP=64MHz,
Fcpp=32MHz, at normal operation
- 54 92 mA
Operating frequency FCP=64MHz,
Fcpp=32MHz, at Flash write
- 64 105 mA
Operating frequency FCP=64MHz,
Fcpp=32MHz, at Flash erase
- 64 105 mA
Operating frequency FCP=48MHz,
Fcpp=24MHz, at normal operation
- 46 82 mA
Operating frequency FCP=48MHz,
Fcpp=24MHz, at Flash write
- 56 95 mA
Operating frequency FCP=48MHz,
Fcpp=24MHz, at Flash erase
- 56 95 mA
ICCS5 Operating frequency FCP=80MHz,
Fcpp=40MHz, at CPU sleep mode
- 45 82 mA
ICCBS5 Operating frequency FCP=80MHz,
Fcpp=40MHz, at bus sleep mode
- 23 72 mA
ICCT5 Watch
mode
When using crystal
4MHz TA=+25°C
*
- 1500 2610
µA
When using built-in
CR clock 50kHz
TA=+25°C
*
- 450 2000
When using sub
clock 32kHz
TA=+25°C
*
- 460 2000
ICCH5
Stop mode
TA=+25°C*
-
450
2000
µA
ICCT52
Watch
mode
(power off)
When using crystal
4MHz TA=+25°C
*
- 1100 1300
µA
LVD/
RTC
operation
,
Backup
RAM
8KB
retention
When using built-in
CR clock 50kHz ,
TA=+25°C
*
- 77 267
When using sub
clock 32kHz
TA=+25°C
*
-
100
285
ICCH52 Stop mode
(power off) TA=+25°C* - 74 265 µA
Backup
RAM
8KB
retention
Document Number: 002-04662 Rev. *D Page 146 of 289
MB91520 Series
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/Vcc=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Typ Max
Input leak
current
IIL All input pins VCC=AVCC=5.5V
VSS<VI<VCC
-5 - 5 µA
Input
capacitance 1 CIN1
Other than
VCC,VSS,
AVCC, AVSS,
C
- - 5 15 pF
Pull-up
resistance
RUP1 RSTX, NMIX
VCC=5.0V±10%
25
-
100
kΩ
Vcc=3.3V±0.3V
45
-
140
RUP2 P073,074
076,077
VCC=5.0V±10%
25
-
60
Vcc=3.3V±0.3V
33
-
90
RUP3
Port pin other
than P035,
041,073,074,
076,077,093,
122
VCC=5.0V±10%
25
-
100
kΩ
Vcc=3.3V±0.3V 45 - 140
“H” level
output voltage
VOH1 Normal output
pin
Vcc=4.5V
IOH=-4.0mA
VCC
-0.5
- VCC V
Vcc=3.0V
IOH=-2.0mA
VOH2 P073,074,076,
077
Vcc=4.5V
IOH=-3.0mA
VCC
-0.5
- VCC V I
2
C pin
output
VOH3 P103 to 106
Vcc=4.5V
IOH=-12.0mA
VCC
-0.5 - VCC V
Vcc=3.0V
IOH=-8.0mA
“L” level
output voltage
VOL1 Normal output
pin
Vcc=4.5V
IOL=4.0mA
0 - 0.4 V
Vcc=3.0V
IOL=2.0mA
VOL2 P073,074,076,
077
Vcc=4.5V
IOL=3.0mA
0 - 0.4 V I
2
C pin
output
VOL3 P103 to 106
Vcc=4.5V
IOL=12.0mA
0 - 0.4 V
Vcc=3.0V
IOL=8.0mA
Document Number: 002-04662 Rev. *D Page 147 of 289
MB91520 Series
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Typ Max
“H” level
input voltage
VIH1
P000,002,003,
005,020,022,
024,026,150,
151,035,041,
045,055,057,
071-077,081,
082,093,096,
097,100-102,
111,115,116,
122,126,130,
134,142,143,
144,153
CMOS
hysteresis input
level
0.7×
VCC - VCC V
VIH3 Port other than
VIH1
Automotive input
level
0.8×
VCC
- VCC V
VIH5 RSTX,NMIX,M
D0,MD1
CMOS
hysteresis input
level
0.8×
VCC - VCC V
VIHT DEBUGIF TTL input level 2 - VCC V
“L” level
input voltage
VIL1
P000,002,003,
005,020,022,
024,026,150,
151,035,041,
045,055,057,
071-077,081,
082,093,096,
097,100-102,
111,115,116,
122,126,130,
134,142,143,
144,153
CMOS
hysteresis input
level
Vss - 0.3×
VCC V
VIL3 Port other than
VIH1
Automotive
input level
Vss - 0.5×
VCC
V
VIL5 RSTX,NMIX,M
D0,MD1
CMOS
hysteresis input
level
Vss - 0.2×
VCC V
VILT DEBUGIF TTL input level Vss - 0.8 V
*: It is a standard in BRAMSC (Backup RAM sleep control bit)=1(Enter the state of the sleep at the standby mode) condition.
Document Number: 002-04662 Rev. *D Page 148 of 289
MB91520 Series
AC Characteristics
(1) Main Clock Timing
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS =AVSS=0.0V)
Parameter Symbol Pin
name Conditions
Value
Unit Remarks
Min Typ Max
Source oscillation
clock frequency
FC X0, X1
-
- 4 16 MHz
Source oscillation
clock cycle time
tCYL X0, X1 62.5 250 - ns
Internal operating
clock frequency*1
FCP
-
2
-
80
MHz
CPU clock
FCPP 1 40 Peripheral bus
clock
FCPT
1 40
External bus clock
(When VCC=5.0V is
used)
*2
1 32
External bus clock
(When VCC=3.3V is
used)
Internal operating
clock cycle time*1
tCP
-
12.5
-
500
ns
CPU clock
tCPP 25 1000 Peripheral bus
clock
tCPT
25 1000
External bus clock
(When VCC=5.0V is
used)
31.25 1000
External bus clock
(When VCC=3.3V is
used)
CAN PLL jitter
(during lock) tPJ - -10 - 10 ns
FCP=80MHz
(4MHzMultiplied
by 20)
Built-in CR
oscillation
frequency
FCCR - 50 100 150 kHz
*1: The maximum / minimum value is defined when using the main clock and PLL clock.
*2: Please use it with external load capacity 12pF or less for VCC=3.3V±0.3V (40MHz operation).
X0,X1 clock timing
X0
tCYL
Document Number: 002-04662 Rev. *D Page 149 of 289
MB91520 Series
CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20, 000 cycles.
t1 t2 t3
t1
PLL output
Ideal clock
Deviation time
Slow
Fast
t2 t3
tn-1 tn
tn-1
tn
Document Number: 002-04662 Rev. *D Page 150 of 289
MB91520 Series
(1-2) Sub clock timing
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin
name Conditions
Value
Unit Remarks
Min Typ Max
Source oscillation clock
frequency
FCL X0A, X1A
-
- 32.7
68
- kHz
Source oscillation clock
cycle time
tLCYL X0A, X1A - 30.5
2
- µs
X0A,X1A clock timing
X0A
t
LCYL
Document Number: 002-04662 Rev. *D Page 151 of 289
MB91520 Series
Guaranteed operation range
Internal operation clock frequency vs. Power supply voltage
Internal operation clock frequency F
CP
(MHz)
80
4
2
2.7
5.5
Power supply voltage V
CC
(V)
MB91F52x guaranteed operation
range
PLL
guaranteed operation
range
4.5
MB91F52x recommended guaranteed
operation range
Note: The power supply voltage, which is the low-voltage detection setting voltage or lower, is in the reset
state.
Document Number: 002-04662 Rev. *D Page 152 of 289
MB91520 Series
Oscillation clock frequency vs. Internal operation clock frequency
Internal operation clock frequency
Main Clock
PLL clock
Multiplied
by 1
Multiplied
by 2
Multiplied
by 3
Multiplied
by 4
...
Multiplied
by 19
Multiplied
by 20
Oscillation
clock frequency
4MHz 2MHz 4MHz 8MHz 12MHz 16MHz ... 76MHz 80MHz
Example of oscillation circuit
X1
X0
R=0Ω
C2=10pF
C1=10pF
4MHz
Note: As to the product with its clock supervisor’s initial value is “ON”, when the oscillator is unable to start
within 20ms from the stop state the clock supervisor will detect the oscillation stop. As a result, the CPU
moves to the fail safe operation.
Design your print circuit board so that the oscillator can start oscillation within 20ms. Moreover, it is
recommended to be designed after the match evaluation of the circuit is requested to the departure
pendulum maker when the oscillation circuit is composed.
Document Number: 002-04662 Rev. *D Page 153 of 289
MB91520 Series
AC characteristics are specified by the following measurement reference voltage values.
Input Signal Waveform Output Signal Waveform
Hysteresis Input Pin (Automotive)
0.5Vcc
0.8Vcc
Output Pin
0.8V
2.4V
Hysteresis Input Pin (CMOS schmitt)
0.3Vcc
0.7Vcc
Document Number: 002-04662 Rev. *D Page 154 of 289
MB91520 Series
(2) Reset Input
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin
name Conditions
Value
Unit Remarks
Min Max
Reset input time
tRSTL RSTX –
10 – µs When normal
operation
Oscillation time of
oscillator* +100
– µs At Stop mode
At Power-on
*2
100
–
µs
At Watch mode
Width for reset
input removal
1 – µs
*1: The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90%. For
crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is
between several hundred μs and several ms, and for an external clock, the time is 0 ms.
*2: In case of using MB91F52xxxD or MB91F52xxxE and corresponding to note in (3) Power-on Conditions of next
subsection, assert RSTX with power-on.
RSTX
0.2 vcc
0.2 vcc
tRSTL
At Stop mode
0.2 V
CC
100 μs
RSTX
X0
90% of
amplitude
Internal operation
clock
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction
execution
Internal reset
0.2 V
CC
t
RSTL
Document Number: 002-04662 Rev. *D Page 155 of 289
MB91520 Series
(3) Power-on Conditions
(3-1) [MB9152xxxB/MB9152xxxC/MB9152xxxD]
(TA: -40°C to +125°C, VSS=0.0V)
Parameter Symbol Pin
name Conditions
Value
Unit Remarks
Min Typ Max
Level detection
voltage
– VCC – 2.024 2.2 2.376
V
Level detection
hysteresis width
– VCC – – 100 – mV
Level detection time – – – – – 30 µs *1
Power off time tOFF VCC – 50 – – ms *2
Power ramp rate dV/dt VCC VCC:
0.2V to 2.376V
– – 4 mV/µs *3
C pin voltage at
Power-on
– C – – – 60 mV *4
*1: This spec is at 4mV/µs of power ramp rate. If the power ramp rate is faster than 4mV/µs, there is the possibility to
generate or release after the power supply voltage has exceeded the detection voltage range.
*2: Vcc must be held below 0.2V for a minimum period of tOFF.
*3: Power-on can detect by satisfying power ramp rate when power off time is not satisfied.
*4: C-pin voltage is below 60 mV when VCC is turned on again.
Note:
When using MB91F52xxxB/C, either *2 or *3 or *4 must be satisfied. When neither *2 nor *3 nor *4 can be
satisfied, use MB91F52xxxD and assert external reset (RSTX) at power-up and at any brownout event.
Power off time, Power ramp rate, C pin voltage at Power-on
VCC
t
OFF
0.2V
0.2V
dV/dt
C pin
=60mV
≤60mV
Document Number: 002-04662 Rev. *D Page 156 of 289
MB91520 Series
(3-2) [MB9152xxxE]
(TA: -40°C to +125°C, VSS=0.0V)
Parameter Symbol Pin
name Conditions
Value
Unit Remarks
Min Typ Max
Level detection
voltage
– VCC – 2.024 2.2 2.376
V
Level detection
hysteresis width
– VCC – – 100 – mV
Level detection time – – – – – 30 µs *1
Power off time
tOFF1 VCC Vcc ≤ 0.2V 50 – – ms *2
tOFF2 VCC Vcc ≤ 1.3V 100 – – µs *4
Power ramp rate
dV/dt VCC
VCC:
0.2V to 2.376V
(tOFF1
<
50ms )
– – 50 mV/µs *3
dV/dt VCC
VCC:
1.3V to 2.376V
(tOFF2 ≥ 100µs)
– – 1000 mV/µs *4
C pin voltage at
Power-on
– C – – – 60 mV *5
Maximum ramp rate
guaranteed to not
generate power-on
reset
|dV/dt| Vcc
VCC:
Between 2.4V and
4.5V
– – 50 mV/µs *6
*1: The specified level detection time applies only for power ramp rate of 1000mV/µs or less.
*2: Vcc must be held below 0.2V for a minimum period of tOFF1.
*3: Power-on can detect by satisfying power ramp rate when tOFF1 is not satisfied.
*4: Vcc must be held below 1.3V for a minimum period of tOFF2.
Power ramp rate must be 1000mV/µs or less from 1.3V to 2.376V.
Power-on can detect by satisfying power ramp rate and power off time.
*5: C-pin voltage is below 60 mV when VCC is turned on again.
*6: This specification is specified the power supply fluctuation after power on detection. When VCC voltage is
between 2.4V and 4.5V, the power supply fluctuation is below 50mV/us, the detection of power-on is suppressed.
The power-on does not detect in any power fluctuation between 4.5V and 5.5V.
Note: When using MB91F52xxxE, either *2 or *3 or *4 or *5 must be satisfied. When neither *2 nor *3 nor *4 nor *5
can be satisfied, assert external reset (RSTX) at power-up and at any brownout event.
Power off time, Power ramp rate, C pin voltage at Power-on
VCC
t
OFF1
0.2V
0.2V
dV/dt
C pin
=60mV
50ms
50mV/us
*2
*3
*5
*4
VCC
t
OFF2
1.3V
1.3V
100us
dV/dt
2.376V
VCC
VCC
≤60mV
Document Number: 002-04662 Rev. *D Page 157 of 289
MB91520 Series
Maximum ramp rate guaranteed to not generate power-on reset
VCC
2.4V
|dV/dt|
5.5V
|dV/dt|
4.5V
Document Number: 002-04662 Rev. *D Page 158 of 289
MB91520 Series
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR : MD0=0, SMR: SCINV=0, SCR:SPI=0
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Serial clock cycle
time tSCYC SCK0 to SCK11
-
4tCPP - ns
Internal shift
clock mode
output pin :
CL=50pF
SCK ↓ →
SOT delay time tSLOVI
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
-30 30 ns
SCK3 , SCK4
SOT3 , SOT4
-300 300 ns
Valid SIN →
SCK ↑ setup time tIVSHI
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
34 - ns
SCK3 , SCK4
SIN3 , SIN4
300 - ns
SCK ↑ →
Valid SIN hold time tSHIXI SCK0 to SCK11
SIN0 to SIN11 0 - ns
Serial clock
"H"pulse width tSHSL
SCK0 to SCK11
-
tCPP+10 - ns
External shift
clock mode
output pin:
CL=50pF
Serial clock
"L" pulse width tSLSH 2tCPP-1
0 - ns
SCK ↓ →
SOT delay time tSLOVE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
- 33 ns
SCK3 , SCK4
SOT3 , SOT4
- 300 ns
Valid SIN →
SCK ↑ setup time tIVSHE
SCK0 to SCK11
SIN0 to SIN11
10 - ns
SCK ↑ →
Valid SIN hold time tSHIXE 20 - ns
SCK fall time tF SCK0 to SCK11 - 5 ns
SCK rise time tR SCK0 to SCK11 - 5 ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and
ch.4 with maximum baud rate 400kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *D Page 159 of 289
MB91520 Series
Internal shift clock mode
2.4V
2.4V
0.8V
0.8V
SINx
SOTx
SCKx
t
SCYC
t
SLOVI
t
SHIXI
t
IVSHI
0.8V
V
IH1
V
IL1
V
IH1
V
IL1
External shift clock mode
2.4V
V
IH1
0.8V
SINx
SOTx
SCKx
t
SLSH
t
SLOVE
t
SHIXE
t
IVSHE
t
SHSL
V
IL1
t
F
t
R
V
IH1
V
IL1
V
IH1
V
IL1
V
IH1
V
IL1
Document Number: 002-04662 Rev. *D Page 160 of 289
MB91520 Series
(4-1-2) Bit setting: SMR: MD2=0, SMR: MD1=1, SMR : MD0=0, SMR: SCINV=1, SCR:SPI=0
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Serial clock cycle
time tSCYC SCK0 to SCK11
-
4tCPP - ns
Internal shift
clock mode
output pin :
CL=50pF
SCK ↑ →
SOT delay time tSHOVI
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
-30 30 ns
SCK3 , SCK4
SOT3 , SOT4
-300 300 ns
Valid SIN →
SCK ↓ setup time tIVSLI
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
34 - ns
SCK3 , SCK4
SIN3, SIN4
300 - ns
SCK ↓ →
Valid SIN hold time tSLIXI SCK0 to SCK11
SIN0 to SIN11 0 - ns
Serial clock
"H"pulse width tSHSL
SCK0 to SCK11
-
tCPP+10 - ns
External shift
clock mode
output pin:
CL=50pF
Serial clock
"L" pulse width tSLSH 2tCPP-1
0 - ns
SCK ↑ →
SOT delay time tSHOVE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
- 33 ns
SCK3 , SCK4
SOT3 , SOT4
- 300 ns
Valid SIN →
SCK ↓ setup time tIVSLE
SCK0 to SCK11
SIN0 to SIN11
10 - ns
SCK ↓ →
Valid SIN hold time tSLIXE 20 - ns
SCK fall time tF SCK0 to SCK11 - 5 ns
SCK rise time tR SCK0 to SCK11 - 5 ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and
ch.4 with maximum baud rate 400kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *D Page 161 of 289
MB91520 Series
Internal shift clock mode
2.4V
0.8V
2.4V
0.8V
SINx
SOTx
SCKx
t
SCYC
t
SHOVI
t
SLIXI
t
IVSLI
2.4V
V
IH1
V
IL1
V
IH1
V
IL1
External shift clock mode
2.4V
V
IH1
0.8V
SINx
SOTx
SCKx
t
SHSL
t
SHOVE
t
SLIXE
t
IVSLE
t
SLSH
V
IL1
t
R
t
F
V
IH1
V
IL1
V
IH1
V
IL1
V
IH1
V
IL1
Document Number: 002-04662 Rev. *D Page 162 of 289
MB91520 Series
(4-1-3) Bit setting: SMR : MD2=0, SMR:MD1=1, SMR : MD0=0, SMR:SCINV=0, SCR:SPI=1
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Serial clock cycle time tSCYC SCK0 to SCK11
-
4tCPP - ns
Internal shift clock
mode output pin :
CL=50pF
SCK ↑ →
SOT delay time tSHOVI
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
-30 30 ns
SCK3 , SCK4
SOT3 , SOT4
-300 300 ns
Valid SIN →
SCK ↓ setup time tIVSLI
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
34 - ns
SCK3 , SCK4
SIN3 , SIN4
300 - ns
SCK ↓ →
Valid SIN hold time tSLIXI SCK0 to SCK11
SIN0 to SIN11 0 - ns
SOT→SCK↓
delay time tSOVLI SCK0 to SCK11
SOT0 to SOT11
2tCPP
-30 - ns
Serial clock
"H"pulse width tSHSL
SCK0 to SCK11
-
tCPP+
10 - ns
External shift clock
mode output pin:
CL=50pF
Serial clock
"L" pulse width tSLSH 2tCPP
-10 - ns
SCK ↑ →
SOT delay time tSHOVE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
- 33 ns
SCK3 , SCK4
SOT3 , SOT4
- 300 ns
Valid SIN →
SCK ↓ setup time tIVSHE
SCK0 to SCK11
SIN0 to SIN11
10 - ns
SCK ↓ →
Valid SIN hold time tSLIXE 20 - ns
SCK fall time tF SCK0 to SCK11 - 5 ns
SCK rise time tR SCK0 to SCK11 - 5 ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum
baud rate 400kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *D Page 163 of 289
MB91520 Series
Internal shift clock mode
t
SCYC
t
SHOVI
t
SOVLI
t
SLIXI
t
IVSLI
2.4V
2.4V
0.8V
0.8V
VIH
VIL
VIH
VIL
2.4V
0.8V
0.8V
SCKx
SOTx
SINx
External shift clock mode
tSLSH tSHSL
tSHOVE
tR
tF
tSLIXE
tIVSLE
2.4V
0.8V
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IL
2.4V
0.8V
SCKx
*
SOTx
SINx
*: It writes in the TDR register and, then, it changes.
tIVSHE
Document Number: 002-04662 Rev. *D Page 164 of 289
MB91520 Series
(4-1-4) Bit setting: SMR : MD2=0, SMR:MD1=1, SMR : MD0=0, SMR:SCINV=1, SCR:SPI=1
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Serial clock cycle
time tSCYC SCK0 to SCK11
-
4tCPP - ns
Internal shift clock
mode output pin :
CL=50pF
SCK↓→
SOT delay time tSLOVI
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
-30 30 ns
SCK3 , SCK4
SOT3 , SOT4
-300 300 ns
Valid SIN →
SCK↑setup time tIVSHI
SCK0 to SCK2,
SCK5 to SCK11
SIN0 to SIN2,
SIN5 to SIN11
34 - ns
SCK3 , SCK4
SIN3 , SIN4
300 - ns
SCK↑→
Valid SIN hold time tSHIXI SCK0 to SCK11
SIN0 to SIN11 0 - ns
SOT→SCK↑
delay time tSOVHI SCK0 to SCK11
SOT0 to SOT11 2tCPP-30 - ns
Serial clock
"H"pulse width tSHSL
SCK0 to SCK11
-
tCPP+10 - ns
External shift clock
mode output pin:
CL=50pF
Serial clock
"L" pulse width tSLSH 2tCPP-10 - ns
SCK↓→
SOT delay time tSLOVE
SCK0 to SCK2,
SCK5 to SCK11
SOT0 to SOT2,
SOT5 to SOT11
- 33 ns
SCK3 , SCK4
SOT3 , SOT4
- 300 ns
Valid SIN →
SCK↑setup time tIVSHE
SCK0 to SCK11
SIN0 to SIN11
10 - ns
SCK↑→
Valid SIN hold time tSHIXE 20 - ns
SCK fall time tF SCK0 to SCK11 - 5 ns
SCK rise time tR SCK0 to SCK11 - 5 ns
Notes:
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum bard rate is limited by internal operation clock used and other parameters. Please use ch.3 and ch.4 with maximum
baud rate 400kbps or less.
See Hardware Manual for details.
Document Number: 002-04662 Rev. *D Page 165 of 289
MB91520 Series
Internal shift clock mode
t
SCYC
t
SLOVI
t
SOVHI
t
SHIXI
t
IVSHI
2.4V 2.4V
2.4V
0.8V
0.8V
V
IH
V
IL
V
IH
V
IL
2.4V
0.8V
SCKx
SOTx
SINx
External shift clock mode
*: It writes in the TDR register and, then, it changes.
t
SLSH
t
SHSL
t
SLOVE
t
R
t
F
t
SHIXE
t
IVSHE
2.4V
0.8V
V
IH
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IL
2.4V
0.8V
SCKx
*
SOTx
SINx
t
F
Document Number: 002-04662 Rev. *D Page 166 of 289
MB91520 Series
(4-1-5) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "H" : SMR,SCSFR:SCINV=0,
Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL=1
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↓→SCK↓
setup time tCSSI
SCK1, SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
tCSSU-50
*1
tCSSU+0
*1 ns
Internal shift
clock mode
output pin :
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSSU-50
*1
tCSSU+300
*1 ns
SCK↑→SCS↑
hold time tCSHI
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSHD-10
*2
tCSHD+50
*2 ns
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSHD-300
*2
tCSHD+50
*2 ns
SCS
deselect time tCSDI
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSDS-50
*3
tCSDS+50
*3 ns
Document Number: 002-04662 Rev. *D Page 167 of 289
MB91520 Series
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↓→SCK↓
setup time tCSSE
SCK1 to SCK11
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP+30 - ns
External shift
clock mode
output pin:
CL=50pF
SCK↑→SCS↑
hold time tCSHE
+0 - ns
SCS
deselect time tCSDE
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
3tCPP+30 - ns
SCS↓→SOT
delay time tDSE
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 , SOT2 ,
SOT5 to SOT11
- 40 ns
SCS3,
SCS40 to SCS43
SOT3 , SOT4
- 300 ns
SCS↑→SOT
delay time tDEE
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 to SOT11
- +0 - ns
External shift
clock mode
output pin:
CL=50pF
SCK↓→SCS↓
clock switch
time
tSCC
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP-10 3tCPP+50 ns Internal shift
clock mode
Round operation
output pin:
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
3tCPP-300 3tCPP+50 ns
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
Document Number: 002-04662 Rev. *D Page 168 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
External shift clock mode
SCK input
SOT
(SPI=0)
SOT
(SPI=1)
tCSSE
SCS input
tCSHE
t
CSDE
tDSE
tDEE
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
Internal shift clock mode
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
tCSSI
SCS output
tCSHI
tCSDI
Document Number: 002-04662 Rev. *D Page 169 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "H"
,Serial chip select Inactive level "H"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
SCSy output
SCK output
SCSx output
tSCC
Document Number: 002-04662 Rev. *D Page 170 of 289
MB91520 Series
(4-1-6) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "L" : SMR,SCSFR:SCINV=1,
Serial chip select Inactive level "H" : SCSCR,SCSFR:CSLVL=1
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↓→SCK↑
setup time tCSSI
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
tCSSU-50
*1
tCSSU+0
*1 ns
Internal shift
clock mode
output pin :
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSSU-50
*1
tCSSU+300
*1 ns
SCK↓→SCS↑
hold time tCSHI
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSHD-10
*2
tCSHD+50
*2 ns
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSHD-300
*2
tCSHD+50
*2 ns
SCS
deselect time tCSDI
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSDS-50
*3
tCSDS+50
*3 ns
Document Number: 002-04662 Rev. *D Page 171 of 289
MB91520 Series
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↓→SCK↑
setup time tCSSE
SCK1 to SCK11
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP+30 - ns
External shift
clock mode
output pin:
CL=50pF
SCK↓→SCS↑
hold time tCSHE
+0 - ns
SCS
deselect time tCSDE
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
3tCPP+30 - ns
SCS↓→SOT
delay time tDSE
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 , SOT2,
SOT5 to SOT11
- 40 ns
SCS3,
SCS40 to SCS43
SOT3 , SOT4
- 300 ns
SCS↑→SOT
delay time tDEE
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 to SOT11
- +0 - ns
External shift
clock mode
output pin:
CL=50pF
SCK↑→SCS↓
clock switch
time
tSCC
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP-10
3tCPP+50 ns
Internal shift
clock mode
Round
operation
output pin:
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
3tCPP-300 3tCPP+50 ns
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1,*2, and *3
Document Number: 002-04662 Rev. *D Page 172 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
tCSSI
SCS output
tCSHI
tCSDI
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
External shift clock mode
SCK input
SOT
(SPI=0)
SOT
(SPI=1)
tCSSE
SCS input
t
CSHE
tCSDE
tDSE
tDEE
Document Number: 002-04662 Rev. *D Page 173 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "H"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
SCSy output
SCK output
SCSx output
tSCC
Document Number: 002-04662 Rev. *D Page 174 of 289
MB91520 Series
(4-1-7) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used : SCSCR:CSEN=1,
Serial clock output mark level "H" : SMR,SCSFR:SCINV=0,
Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL=0
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↑→SCK↓
setup time tCSSI
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
tCSSU-50
*1
tCSSU+0
*1 ns
Internal shift
clock mode
output pin :
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSSU-50
*1
tCSSU+30
0
*1
ns
SCK↑→SCS↓
hold time tCSHI
SCK1 to SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSHD-10
*2
tCSHD+50
*2 ns
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSHD-300
*2
tCSHD+50
*2 ns
SCS
deselect time tCSDI
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSDS-50
*3
tCSDS+50
*3 ns
Document Number: 002-04662 Rev. *D Page 175 of 289
MB91520 Series
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↑→SCK↓
setup time tCSSE
SCK1 to SCK11
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP+3
0
- ns
External shift
clock mode
output pin:
CL=50pF
SCK↑→SCS↓
hold time tCSHE
+0 - ns
SCS
deselect time tCSDE
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
3tCPP+3
0
- ns
SCS↑→SOT
delay time tDSE
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 , SOT2,
SOT5 to SOT11
- 40 ns
SCS3 ,
SCS40 to SCS43
SOT3 , SOT4
- 300 ns
SCS↓→SOT
delay time tDEE
SCS1 to ~SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 to SOT11
- +0 - ns
External shift
clock mode
output pin:
CL=50pF
SCK↓→SCS↑
clock switch
time
tSCC
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP-10 3tCPP+5
0 ns Internal shift
clock mode
Round operation
output pin:
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
3tCPP-30
0
3tCPP+5
0 ns
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
Document Number: 002-04662 Rev. *D Page 176 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
tCSSI
SCS output
t
CSHI
tCSDI
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
External shift clock mode
SCK input
SOT
(SPI=0)
SOT
(SPI=1)
tCSSE
SCS input
tCSHE
tCSDE
tDSE
tDEE
Document Number: 002-04662 Rev. *D Page 177 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "H",
Serial chip select Inactive level "L"
Internal shift clock mode , Example of switching clock by round operation (x,y=0,1,2,3)
SCSy output
SCK output
SCSx output
tSCC
Document Number: 002-04662 Rev. *D Page 178 of 289
MB91520 Series
(4-1-8) Bit setting: SMR:MD2=0, SMR:MD1=1, SMR:MD0=0,
When Serial chip select is used: SCSCR:CSEN=1,
Serial clock output mark level "L" : SMR,SCSFR:SCINV=1,
Serial chip select Inactive level "L" : SCSCR,SCSFR:CSLVL=0
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↑→SCK↑
setup time tCSSI
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
tCSSU-50
*1
tCSSU+0
*1 ns
Internal shift
clock mode
output pin :
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSSU-50
*1
tCSSU+300
*1 ns
SCK↓→SCS↓
hold time tCSHI
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSHD-10
*2
tCSHD+50
*2 ns
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
tCSHD-300
*2
tCSHD+50
*2 ns
SCS
deselect time tCSDI
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
tCSDS-50
*3
tCSDS+50
*3 ns
Document Number: 002-04662 Rev. *D Page 179 of 289
MB91520 Series
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
SCS↑→SCK↑
setup time tCSSE
SCK1 to SCK11
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP+30 - ns
External shift
clock mode
output pin:
CL=50pF
SCK↓→SCS↓
hold time tCSHE
+0 - ns
SCS
deselect time tCSDE
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
3tCPP+30 - ns
SCS↑→SOT
delay time tDSE
SCS1 , SCS2,
SCS50~SCS53,
SCS60~SCS63,
SCS70~SCS73,
SCS8~SCS11
SOT1 , SOT2,
SOT5~SOT11
- 40 ns
SCS3 ,
SCS40~SCS43
SOT3 ,SOT4
- 300 ns
SCS↓→SOT
delay time tDEE
SCS1 to SCS3,
SCS40 to SCS43,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
SOT1 to SOT11
- +0 - ns
External shift
clock mode
output pin:
CL=50pF
SCK↑→SCS↑
clock switch
time
tSCC
SCK1 , SCK2,
SCK5 to SCK11
SCS1 , SCS2,
SCS50 to SCS53,
SCS60 to SCS63,
SCS70 to SCS73,
SCS8 to SCS11
-
3tCPP-10
3tCPP+50
ns
Internal shift
clock mode
Round operation
output pin:
CL=50pF
SCK3 , SCK4
SCS3 ,
SCS40 to SCS43
3tCPP-300 3tCPP+50
*1: tCSSU =SCSTR:CSSU7-0×Serial chip select timing operating clock
*2: tCSHD=SCSTR:CSHD7-0×Serial chip select timing operating clock
*3: tCSDS=SCSTR:CSDS15-0×Serial chip select timing operating clock
Regardless of the deselect time setting, once after the serial chip select pin becomes inactive, it will take
at least five peripheral bus clock cycles to be active again
Please see the hardware manual for details of above-mentioned *1,*2, and *3.
Document Number: 002-04662 Rev. *D Page 180 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode
SCK output
SOT
(SPI=0)
SOT
(SPI=1)
tCSSI
SCS output
tCSHI
tCSDI
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Slave mode
SCK input
SOT
(SPI=0)
SOT
(SPI=1)
tCSSE
SCS input
tCSHE
tCSDE
tDSE
tDEE
Document Number: 002-04662 Rev. *D Page 181 of 289
MB91520 Series
When Serial chip select is used , Serial clock output mark level "L",
Serial chip select Inactive level "L"
Master mode, Example of switching clock by round operation (x,y=0,1,2,3)
SCSy output
SCK output
SCSx output
tSCC
Document Number: 002-04662 Rev. *D Page 182 of 289
MB91520 Series
(4-2) UART (Asynchronous serial interface) timing
Bit setting: SMR : MD2=0, SMR:MD1=0, SMR : MD0=0
Bit setting: SMR : MD2=0, SMR:MD1=0, SMR : MD0=1
When external clock is selected (BGR:EXT=1)
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Serial clock
"L" pulse width tSLSH
SCK0 to SCK11 -
tCPP+10 - ns
output pin:
CL=50pF
Serial clock
"H"pulse width tSHSL tCPP+10 - ns
SCK fall time tF - 5 ns
SCK rise time tR - 5 ns
When external clock is selected
SCK
t
SHSL
V
IL
V
IH
V
IH
tR
t
SLSH
tF
V
IL
V
IH
V
IL
Document Number: 002-04662 Rev. *D Page 183 of 289
MB91520 Series
(4-3) LIN Interface (v2.1)( Asynchronous Serial Interface for LIN (v2.1)) timing
Bit setting: SMR : MD2=0, SMR:MD1=1, SMR : MD0=1
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Serial clock
"L" pulse width tSLSH
SCK0 to SCK11 -
tCPP+10 - ns
output pin:
CL=50pF
Serial clock
"H"pulse width tSHSL tCPP+10 - ns
SCK fall time tF - 5 ns
SCK rise time tR - 5 ns
When external clock is selected
SCK
t
SHSL
V
IL
V
IH
V
IH
tR
t
SLSH
tF
V
IL
VIH
V
IL
Document Number: 002-04662 Rev. *D Page 184 of 289
MB91520 Series
(4-4) I2C timing
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symb
ol Pin name Conditions
Standard mode Fast mode*3
Unit Remarks
Min Max Min Max
SCL clock frequency fSCL SCK3 to
SCK11
CL=50pF
R = (VP/IOL) *1
0 100 0 400 kHz
Repeat "start" condition
hold time
SDA ↓ → SCL ↓
tHDSTA
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
4.0 – 0.6 – μs
Period of "L" for SCL
clock tLOW
SCK3 to
SCK11,
(SCL)
4.7 – 1.3 – μs
Period of "H" for SCL
clock tHIGH
SCK3 to
SCK11,
(SCL)
4.0 – 0.6 – μs
Repeat "start" condition
setup time
SCL ↑ → SDA ↓
tSUSTA
SCK3 to
SCK11,
(SCL)
4.7 – 0.6 – μs
Data hold time
SCL ↓ → SDA ↓ ↑ tHDDAT
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
0 3.45*2 0 0.9*3 μs
Data setup time
SDA ↓ ↑ → SCL ↑ tSUDAT
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
250 – 100 – ns
"Stop" condition setup
time
SCL ↑ → SDA ↑
tSUSTO
SOT3 to
SOT11,
(SDA)
SCK3 to
SCK11,
(SCL)
4.0 – 0.6 – μs
Bus-free time between
"stop" condition and
"start" condition
tBUF – 4.7 – 1.3 – μs
Noise filter tSP – – 2tCPP*4 – 2tCPP*4 – ns
Notes: Only ch.3 and ch.4 are standard mode/fast mode correspondence. In ch.5-ch.8, ch.10, and ch.11, only a standard mode is
correspondences.
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA output lines,
respectively.
Vp shows that the power-supply voltage of the pull-up resistor and IOL shows the VOL guarantee current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3: A fast mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of
Document Number: 002-04662 Rev. *D Page 185 of 289
MB91520 Series
"tSUDAT ≥ 250 ns".
*4: tCPP is the peripheral clock cycle time. Adjust the clock of the bus in the surrounding to 8MHz or more when use I2C.
・I2C timing
SDA
SCL
t
HDSTA
t
LOW
t
HDDAT
t
SUDAT
t
HIGH
t
SUSTA
t
HDSTA
t
SP
t
BUF
t
SUSTO
Document Number: 002-04662 Rev. *D Page 186 of 289
MB91520 Series
(5) Timer input timing
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Input pulse width tTIW H,
tTIWL
TIN0 to TIN7
ICU0 to ICU9
FRCK0 to FRCK5
TIOA0, TIOA1,
TIOB0, TIOB1,
AIN0, AIN1,
BIN0, BIN1,
ZIN0, ZIN1
– 4tCPP – ns
Timer input timing
V
IH
V
IL
t
TIWL
t
TIWH
V
IL
TINx,
ICUx,
FRCKx,
TIOAx,TIOBx
AINx,BINx,ZINx
V
IH
(6) Trigger input timing
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Input pulse width tTRGH,
tTRGL
INT0 to
INT15,
A DT G,
RX0,
RX1,
RX2
–
5tCPP – ns
1 – μs At stop mode
Trigger input timing
VIH
VIL
ADTG
tTRGL
tTRGH
VIL
INTx
RXx
VIH
Document Number: 002-04662 Rev. *D Page 187 of 289
MB91520 Series
(7) NMI input timing
(TA: -40°C to +125°C, VCC= AVCC=5.0V ± 10%/VCC=AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name Conditions
Value
Unit Remarks
Min Max
Input pulse width tNMIL NMIX – 4tCPP – ns
NMIX input timing
V
IH5
NMIX
t
NMIL
V
IH5
V
IL5
V
IL5
(8) Low voltage detection (External low-voltage detection)
(TA: -40°C to +125°C, VSS=AVSS=0.0V)
Parameter Symbol Pin
name Conditions
Value
Unit Remarks
Min Typ Max
Power supply
voltage range
VDP5
VCC
- 2.7 - 5.5 V
Detection
voltage*3 VDL *1 -8%
LVD5F
_SEL
[3:0]
+8% V
LVD5F_SEL[3:0] are
programmable.
Refer to the
hardware manual.
Hysteresis width VHYS
-
- 0.1 - V When power-supply
voltage rises
Low voltage
detection time
Td - - - 30 µs
Power supply
voltage regulation
- VCC - -2 - 2 V/ms *2
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2: Please suppress the change of the power supply within the range of the power-supply voltage regulation to do a low voltage
detection by detecting voltage (VDL).
*3: The initial detection voltage of the external low voltage detection is 2.8V±8% (2.576V to 3.024V).
This LVD setting cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation
voltage, as this detection level is below the minimum guaranteed MCU operation voltage (2.7V).
Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 188 of 289
MB91520 Series
(9) Low voltage detection (Internal low-voltage detection)
(TA: -40°C to +125°C, VSS=AVSS=0.0V)
Parameter Symbol Pin
name Conditions
Value
Unit Remarks
Min Typ Max
Power supply
voltage range
VRDP5
-
- 0.6 - 1.4 V
Detection
voltage*2 VRDL *1 0.8 0.9 1.0 V
When
power-supply
voltage falls
Hysteresis width VRHYS
-
- 0.1 - V
When
power-supply
voltage rises
Low voltage
detection time
- - - - 30 µs
*1: If the fluctuation of the power supply is faster than the low voltage detection time, there is a possibility to generate or release
after the power supply voltage has exceeded the detection voltage range.
*2: The detection voltage of the internal low voltage detection is 0.9V±0.1V.
This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage,
as this detection level is below the minimum guaranteed MCU operation voltage.
Below the minimum guaranteed MCU operation voltage, MCU operations are not guaranteed with the exception of LVD.
(10) External bus I/F (synchronous mode) timing
(TA: -40°C to +105°C, VCC=AVCC=5.0V±10%/VCC= AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
(external load capacitance 50pF)
Parameter Symbol Pin name
Value
Unit Remarks
Min
Max
Cycle time tCYC SYSCLK
25
- ns
VCC=5.0V±10%*1
31.25
VCC=3.3V±0.3V
ASX delay time tCHASL,
tCHASH
SYSCLK
ASX
0.5 18 ns
CS0X to CS3X
delay time
tCHCSL,
tCHCSH
SYSCLK
CS0X to
CS3X
0.5 18 ns
A00 to A21
delay time
tCHAV,
tCHAX
SYSCLK
A00 to A21
0.5 18 ns
RDX delay
time
tCHRL,
tCHRH
SYSCLK
RDX
0.5 18 ns
RDX
minimum pulse
tRLRH RDX tCYC×
2 - 20
- ns RWT=1, set RWT to 1 or more.*2
Data setup →
RDX↑time
tDSRH
RDX
D16 to D31
18+tCYC - ns Same as above
RDX↑→
data hold
tRHDH 0 - ns
Document Number: 002-04662 Rev. *D Page 189 of 289
MB91520 Series
Parameter Symbol Pin name
Value
Unit Remarks
Min
Max
WRnX delay
time
tCHWL,
tCHWH
SYSCLK
WR0X,
WR1X
0.5 18 ns
WRnX
minimum pulse
tWLWH WR0X,
WR1X
tCYC - 10 - ns WWT=0 *2
SYSCLK↑→
data output
time
tCHDV
SYSCLK
D16 to D31
0.5 18 ns
SYSCLK↑→
data hold time
tCHDX - 18 ns Set WRCS to 1 or more.
SYSCLK↑→
address output
time
tCHMAV
SYSCLK
D16 to D31
0.5 18 ns
SYSCLK↑→
address hold
time
tCHMAX - 18 ns
In multiplex mode, set as follows:
Set CSWR and CSRD to 2 or
more.
ASCY must satisfy the following
conditions because of setting
ADCY > ASCY and protocol
violation prevention.
ADCY +1 ≤ ACS + CSRD
ADCY +1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
See Hardware Manual for details.
*1: Please use it with external load capacity 12pF or less for VCC=3.3V±0.3V (40MHz operation).
*2: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated
value.
Document Number: 002-04662 Rev. *D Page 190 of 289
MB91520 Series
External bus I/F (synchronous mode, read operation, and multiplex mode) timing
Valid Address Read Data
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
RDX
D16~D31
tCHASL tCHASH
tCHCSL tCHCSH
tCHRL tCHRH
tCHMAX
tRHDH
tCYC
tDSRH
tRLRH
t4
CSRD=2
ADCY=1
RWT=1
tCHMAV
ASCY=0
ACS=0 RDCS=0
External bus I/F (synchronous mode, read operation, and split mode) timing
Valid Address
Read Data
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
RDX
A00~A21
D16~D31
tCHCSH
tCHRL tCHRH
tCHAV tCHAX
tRHDH
tDSRH
tRLRH
t4
CSRD=0
RWT=1
tCHCSL
tCYC
ACS=0 RDCS=0
tCHASL tCHASH
ASCY=0
CS0X to CS3X
CS0X to CS3X
CS0X to CS3X
D16 to D31
D16 to D31
A00 to A21
Document Number: 002-04662 Rev. *D Page 191 of 289
MB91520 Series
External bus I/F (synchronous mode, write operation, and multiplex mode) timing
Valid Address Write Data
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
WR0X~WR1X
D16~D31
tCHASL tCHASH
t
CYC
tCHCSL tCHCSH
tCHWL tCHWH
tCHDV tCHDX
tWLWH
ADCY=1
CSWR=2
t4
WRCS=1
tCHMAV
WWT=0
ACS=0
ASCY=0
External bus I/F (synchronous mode, write operation, and split mode) timing
Valid Address
Write Data
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
WR0X~WR1X
A00~A21
D16~D31
tCHCSH
tCHWL tCHWH
tCHAV tCHAX
tCHDX
tWLWH
CSWR=0
t4
WRCS=1
tCHDV
tCHASL
t
CYC
tCHASH
ASCY=0
tCHCSL
ACS=0
WWT=0
CS0X to CS3X
WR0X to WR1X
D16 to D31
CS0X to CS3X
WR0X to WR1X
D16 to D31
A00 to A21
Document Number: 002-04662 Rev. *D Page 192 of 289
MB91520 Series
(11) External bus I/F (asynchronous mode) timing
(TA: -40°C to +105°C, VCC=AVCC=5.0V±10%/VCC= AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
(external load capacitance 50pF)
Parameter Symbol Pin name
Value
Unit Remarks
Min Max
Cycle time tCYC SYSCLK
25
- ns
VCC=5.0V±10%
*1
31.25 VCC=3.3V±0.3V
Address setup
→
RDX↑time
tASRH
RDX
A00 to A21
2×tCYC - 12 2×tCYC +
12
ns RWT=1,
set RWT to 1 or more.
*2
RDX↑→
Address hold
tRHAH tCYC - 12 tCYC + 12 ns Set RDCS to 1 or more.
Data setup
→
RDX↑time
tDSRH
RDX
D16 to D31
18 +
tCYC
- ns RWT=1,
set RWT to 1 or more.
RDX↑
→
Data hold
tRHDH 0 - ns
Address setup
→
WRnX↑time
tASWH WR0X to
WR1X
A00 to A21
tCYC - 12 tCYC + 12 ns WWT=0 *2
WRnX↑
→
Address hold
tWHAH tCYC - 12 tCYC + 12 ns Set WRCS to 1 or more.
Data setup
→
WRnX↑time
tDSWH WR0X to
WR1X
D16 to D31
tCYC - 16 tCYC + 16 ns WWT=0 *2
WRnX↑→
Data hold
tWHDH tCYC - 16 tCYC +
16
ns Set WRCS to 1 or more.
Address setup →
ASX↑time
tMASASH
ASX
D16 to D31
tCYC-16 tCYC+ 16 ns ASCY=0
ASX↑
→Address
hold
tMASHAH tCYC-16 tCYC + 16 ns
In multiplex mode, set as follows:
Set CSWR and CSRD to 2 or
more.
ASCY must satisfy the following
conditions because of setting
ADCY > ASCY and protocol
violation prevention.
ADCY +1 ≤ ACS + CSRD
ADCY +1 ≤ ACS + CSWR
ASCY + 1 ≤ ACS + CSRD
ASCY + 1 ≤ ACS + CSWR
See Hardware Manual for details.
*1: Please use it with external load capacity 12pF or less for VCC=3.3V±0.3V (40MHz operation).
*2: If the bus is expanded by automatic wait insertion or RDY input, add time (tCYC × the number of expanded cycles) to the rated
value.
Document Number: 002-04662 Rev. *D Page 193 of 289
MB91520 Series
External bus I/F (asynchronous mode, read operation, and multiplex mode) Timing
Valid Address
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
RDX
D16~D31
CSRD=2
ADCY=1
t4
Read Data
RWT=1
tRHDH
tDSRH
t5
RDCS=1
tMASASH tMASHAH
ACS=0
ASCY=0
tCYC
External bus I/F (asynchronous mode, read operation, and split mode) Timing
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
RDX
A00~A21
D16~D31
CSRD=0
t4
Read Data
Valid Address
RWT=1
tRHDH
tDSRH
t5
RDCS=1
tASRH tRHAH
ACS=0
ASCY=0
t
CYC
CS0X to CS3X
D16 to D31
A00 to A21
CS0X to CS3X
D16 to D31
Document Number: 002-04662 Rev. *D Page 194 of 289
MB91520 Series
External bus I/F (asynchronous mode, write operation, and multiplex mode) Timing
Valid Address Write Data
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
WR0X~WR1X
D16~D31
WRCS=1
ADCY=1
t4
CSWR=2
tMASASH tMASHAH tDSWH tWHDH
ASCY=0
ACS=0
WWT=0
tCYC
External bus I/F (Asynchronous mode, write operation, and split mode) Timing
Valid Address
Write Data
t1 t2 t3
SYSCLK
ASX
CS0X~CS3X
WR0X~WR1X
A00~A21
D16~D31
WRCS=1
t4
CSWR=0
tASWH tWHAH
tDSWH tWHDH
ASCY=0
ACS=0
WWT=0
t
CYC
CS0X to CS3X
D16 to D31
CS0X to CS3X
D16 to D31
A00 to A21
WR0X to WR1X
CS0X to CS3X
WR0X to WR1X
Document Number: 002-04662 Rev. *D Page 195 of 289
MB91520 Series
(12) External bus I/F (ready) Timing
(TA: -40°C to +105°C, VCC=AVCC=5.0V ± 10%/VCC= AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
(external load capacitance 50pF)
Parameter Symbol Pin name
Value
Unit Remarks
Min
Max
Cycle time tCYC SYSCLK 50 - ns If using RDY, set SYSCLK
to 20 MHz or less.
RDY setup time →
SYSCLK↑
tRDYS SYSCLK,
RDY
28 - ns
SYSCLK↑→
RDY hold time
tRDYH SYSCLK,
RDY
0 - ns
External bus I/F (ready) Timing
t3 t4 t5
SYSCLK
ASX
CS0X~CS3X
RDX
RDY tRDYS tRDYH
t6
RWT=2
CSRD=2
ASCY=0
ACS=0 RDCS=0
t1 t2
tCYC
Auto wait cycle
Added cycle by RDY
Document Number: 002-04662 Rev. *D Page 196 of 289
MB91520 Series
A/D Converter
(1) 12-bit A/D Converter Electrical Characteristics
(TA: -40°C to +125°C, VCC=AVCC=5.0V ± 10%/VCC= AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol Pin name
Value
Unit Remarks
Min Typ Max
Resolution - - - - 12 bit
Total error - - - - ±12 LSB
Linearity error - - - - ± 4.0 LSB
Differential linearity
error
- - - - ± 1.9 LSB
Zero transition voltage VOT AN0 to AN47 AVRL-
11.5LSB
- AVRL+
12.5LSB
V 1LSB=
(VFST-VOT)/
4094
Full-scale transition
voltage
VFST AN0 to AN47 AVRH-
13.5LSB
- AVRH+
10.5LSB
V
Sampling time tSMP - 0.7 - - µs *1
Compare time tCMP - 0.7 - - µs *1
A/D conversion time tCNV - 1.4 - - µs *1
Analog port input
current
IAIN AN0 to AN47 -1.0 - +1.0 µA VAVS S ≤
VAIN ≤ VAVCC
Analog input voltage VAIN AN0 to AN47 AVRL - AVRH V
Reference voltage
AVRH AVRH 3.0 - 5.5 V
AVRL AVSS/
AVRL
- 0.0 - V
Power supply current
IA
AVCC*3
- 0.47 0.63 mA Per unit
TA: +105°C
- 0.47 0.7 mA Per unit
TA: +125°C
IAH - - 2.5 µA *2
IR
AVRH
- 1 1.96 mA Per unit
IRH - - 1.6 µA *2
Variation between
channels
- AN0 to AN47 - - 4 LSB
*1: Time for each channel.
*2: Power supply current (VCC = AVCC = 5.0 V) is specified if A/D converter is not operating and CPU is stopped.
*3: The power supply current described only current value on A/D converter.
The total AVcc current value must be calculated the power supply current for A/D converter and D/A converter.
(Note) Please use the clock of 0.5MHz-20MHz for the output clock of A/D converter to guarantee accuracy.
Document Number: 002-04662 Rev. *D Page 197 of 289
MB91520 Series
(2) Definition of A/D Converter Terms
Resolution : Analog variation that is recognized by an A/D converter.
Linearity error : Deviation of the actual conversion characteristics from a straight line that connects
the zero transition point ("0000 0000 0000"← →"0000 0000 0001") to the full-scale
transition point ("1111 1111 1110"← →"1111 1111 1111").
Differential linearity
error
: Deviation of the input voltage from the ideal value that is required to change the
output code by LSB.
FFF
H
FFE
H
FFD
H
004
H
003
H
002
H
001
H
AVSS
(AVRL)
AVRH AVSS
(AVRL)
AVRH
N + 1
N
N - 1
N - 2
V
OT
(actual measurement value)
{1 LSB × (N - 1)
+ V
OT
}
Actual conversion
characteristics
V
FST
(actual
measurement
value)
V
NT
(actual
measurement value)
Actual conversion
characteristics
Ideal characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Ideal
characteristics
Digital output
Digital output
Analog input
Linearity error Differential linearity error
Analog input
V
NT
(actual measurement value)
V
(N + 1) T
(actual measurement
value)
Linearity error of digital output N =
VNT - {1LSB × (N - 1) + VOT}
[LSB]
1LSB
Differential linearity error of digital output N = V(N + 1) T - VNT - 1 LSB [LSB]
1LSB
1LSB =
VFST - VOT
[V]
4094
VOT : Voltage at which the digital output changes from “000H” to “001 H”.
VFST : Voltage at which the digital output changes from “FFE H” to “FFF H”.
Document Number: 002-04662 Rev. *D Page 198 of 289
MB91520 Series
(3) Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling period for analog voltages may not be sufficient. In this case, it is
recommended to connect the capacitor (approx. 0.1 μF) to the analog input pin.
Analog input circuit model
R
C
12bit A/D
1.9kΩ (Max)
8.30pF (Max)
(4.5V ≤ AVCC ≤ 5.5V)
4.3kΩ (Max)
8.30pF (Max)
(3.0V ≤ AVCC ≤ 3.6V)
Note: Listed values must be considered as reference values.
R
C
Analog input
Comparator
During sampling: ON
Document Number: 002-04662 Rev. *D Page 199 of 289
MB91520 Series
Flash memory
(1) Electrical Characteristics
Parameter
Value
Unit Remarks
Min
Typ
Max
Sector erase time
– 200 800 ms 8 Kbytes sector*
1
,
excluding internal preprogramming time
– 300 1100 ms 8 Kbytes sector*
1
,
including internal preprogramming time
– 400 2000 ms 64 Kbytes sector*
1
,
excluding internal preprogramming time
– 700 3700 ms 64 Kbytes sector*
1
,
including internal preprogramming time
8-bit writing time – 9 288 µs Exclusive of overhead time at
system level*
1
16-bit writing time – 12 384 µs Exclusive of overhead time at
system level*
1
ECC writing time – 9 288 µs Exclusive of overhead time at
system level*
1
Erase cycle*2/
Data retain time
1,000 cycles/
20 years,
10,000 cycles/
10 years,
100,000 cycles/
5 years
– – – Average TA=+85°C*3
*1: The guaranteed value for erasure up to 100,000 cycles.
*2: Number of erase cycles for each sector.
*3: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into
normalized value at + 85°C).
(2) Notes
While the Flash memory is written or erased, shutdown of the external power (Vcc) is prohibited.
In the application system where Vcc might be shut down while writing or erasing, be sure to turn the power off by using an external
voltage detection function.
To put it concretely, after the external power supply voltage falls below the detection
voltage (VDL*), hold Vcc at 2.7V or more within the duration calculated by the following expression:
Td*[µs] + (period of PCLK [µs] × 257) + 50 [µs]
*: See “4.AC Characteristics (8) Low-voltage detection (External low-voltage detection) ”
Document Number: 002-04662 Rev. *D Page 200 of 289
MB91520 Series
D/A converter
(TA:-40°C to +125°C, VCC=AVCC=5.0V±10%/VCC= AVCC=3.3V±0.3V, VSS=AVSS=0.0V)
Parameter Symbol
Pin
name
Condition
Value
Unit Remarks
Min
Typ
Max
Resolution
-
-
–
–
–
8
bit
Differential linearity
error
- - – – – ± 3.0 LSB
Conversion time - -
–
0.47
0.58
0.69
µs
CL=20
–
2.37
2.90
3.43
µs
CL=100
Output impedance Ro DA0,
DA1
– 3.1 3.8 4.5 kΩ
Power supply current
*1
IA AVCC – – 475 580 µA Each
channel
IAH AVCC – – – 7.5 µA
When
powerdown
Each
channel
*1: The power supply current described only current value on D/A converter.
The total AVcc current value must be calculated the power supply current for D/A converter and A/D converter.
Document Number: 002-04662 Rev. *D Page 201 of 289
MB91520 Series
12. EXAMPLE CHARACTERISTICS
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
MB91F526
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MB91520 Series
MB91F526
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MB91520 Series
MB91F526
Document Number: 002-04662 Rev. *D Page 204 of 289
MB91520 Series
13. Ordering Information MB91F52xxxB*1
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526LWBPMC
Yes
ON
ON
LQP・176 pin,
Plastic
MB91F526LYBPMC
OFF
MB91F526LJBPMC
OFF
ON
MB91F526LLBPMC
OFF
MB91F525LWBPMC
ON
ON
MB91F525LYBPMC
OFF
MB91F525LJBPMC
OFF
ON
MB91F525LLBPMC
OFF
MB91F524LWBPMC
ON
ON
MB91F524LYBPMC
OFF
MB91F524LJBPMC
OFF
ON
MB91F524LLBPMC
OFF
MB91F523LWBPMC
ON
ON
MB91F523LYBPMC
OFF
MB91F523LJBPMC
OFF
ON
MB91F523LLBPMC
OFF
MB91F522LWBPMC
ON
ON
MB91F522LYBPMC
OFF
MB91F522LJBPMC
OFF
ON
MB91F522LLBPMC
OFF
MB91F526LSBPMC
None
ON
ON
MB91F526LUBPMC
OFF
MB91F526LHBPMC
OFF
ON
MB91F526LKBPMC
OFF
MB91F525LSBPMC
ON
ON
MB91F525LUBPMC
OFF
MB91F525LHBPMC
OFF
ON
MB91F525LKBPMC
OFF
MB91F524LSBPMC
ON
ON
MB91F524LUBPMC
OFF
MB91F524LHBPMC
OFF
ON
MB91F524LKBPMC
OFF
MB91F523LSBPMC
ON
ON
MB91F523LUBPMC
OFF
MB91F523LHBPMC
OFF
ON
MB91F523LKBPMC
OFF
MB91F522LSBPMC
ON
ON
MB91F522LUBPMC
OFF
MB91F522LHBPMC
OFF
ON
MB91F522LKBPMC
OFF
Document Number: 002-04662 Rev. *D Page 205 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526KWBPMC
Yes
ON
ON
LQS・144 pin,
(Lead pitch 0.5mm)
Plastic
MB91F526KYBPMC
OFF
MB91F526KJBPMC
OFF
ON
MB91F526KLBPMC
OFF
MB91F525KWBPMC
ON
ON
MB91F525KYBPMC
OFF
MB91F525KJBPMC
OFF
ON
MB91F525KLBPMC
OFF
MB91F524KWBPMC
ON
ON
MB91F524KYBPMC
OFF
MB91F524KJBPMC
OFF
ON
MB91F524KLBPMC
OFF
MB91F523KWBPMC
ON
ON
MB91F523KYBPMC
OFF
MB91F523KJBPMC
OFF
ON
MB91F523KLBPMC
OFF
MB91F522KWBPMC
ON
ON
MB91F522KYBPMC
OFF
MB91F522KJBPMC
OFF
ON
MB91F522KLBPMC
OFF
MB91F526KSBPMC
None
ON
ON
MB91F526KUBPMC
OFF
MB91F526KHBPMC
OFF
ON
MB91F526KKBPMC
OFF
MB91F525KSBPMC
ON
ON
MB91F525KUBPMC
OFF
MB91F525KHBPMC
OFF
ON
MB91F525KKBPMC
OFF
MB91F524KSBPMC
ON
ON
MB91F524KUBPMC
OFF
MB91F524KHBPMC
OFF
ON
MB91F524KKBPMC
OFF
MB91F523KSBPMC
ON
ON
MB91F523KUBPMC
OFF
MB91F523KHBPMC
OFF
ON
MB91F523KKBPMC
OFF
MB91F522KSBPMC
ON
ON
MB91F522KUBPMC
OFF
MB91F522KHBPMC
OFF
ON
MB91F522KKBPMC
OFF
Document Number: 002-04662 Rev. *D Page 206 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526KWBPMC1
Yes
ON
ON
LQN・144 pin,
(Lead pitch 0.4mm)
Plastic
MB91F526KYBPMC1
OFF
MB91F526KJBPMC1
OFF
ON
MB91F526KLBPMC1
OFF
MB91F525KWBPMC1
ON
ON
MB91F525KYBPMC1
OFF
MB91F525KJBPMC1
OFF
ON
MB91F525KLBPMC1
OFF
MB91F524KWBPMC1
ON
ON
MB91F524KYBPMC1
OFF
MB91F524KJBPMC1
OFF
ON
MB91F524KLBPMC1
OFF
MB91F523KWBPMC1
ON
ON
MB91F523KYBPMC1
OFF
MB91F523KJBPMC1
OFF
ON
MB91F523KLBPMC1
OFF
MB91F522KWBPMC1
ON
ON
MB91F522KYBPMC1
OFF
MB91F522KJBPMC1
OFF
ON
MB91F522KLBPMC1
OFF
MB91F526KSBPMC1
None
ON
ON
MB91F526KUBPMC1
OFF
MB91F526KHBPMC1
OFF
ON
MB91F526KKBPMC1
OFF
MB91F525KSBPMC1
ON
ON
MB91F525KUBPMC1
OFF
MB91F525KHBPMC1
OFF
ON
MB91F525KKBPMC1
OFF
MB91F524KSBPMC1
ON
ON
MB91F524KUBPMC1
OFF
MB91F524KHBPMC1
OFF
ON
MB91F524KKBPMC1
OFF
MB91F523KSBPMC1
ON
ON
MB91F523KUBPMC1
OFF
MB91F523KHBPMC1
OFF
ON
MB91F523KKBPMC1
OFF
MB91F522KSBPMC1
ON
ON
MB91F522KUBPMC1
OFF
MB91F522KHBPMC1
OFF
ON
MB91F522KKBPMC1
OFF
Document Number: 002-04662 Rev. *D Page 207 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526JWBPMC
Yes
ON
ON
LQM・120 pin,
Plastic
MB91F526JYBPMC
OFF
MB91F526JJBPMC
OFF
ON
MB91F526JLBPMC
OFF
MB91F525JWBPMC
ON
ON
MB91F525JYBPMC
OFF
MB91F525JJBPMC
OFF
ON
MB91F525JLBPMC
OFF
MB91F524JWBPMC
ON
ON
MB91F524JYBPMC
OFF
MB91F524JJBPMC
OFF
ON
MB91F524JLBPMC
OFF
MB91F523JWBPMC
ON
ON
MB91F523JYBPMC
OFF
MB91F523JJBPMC
OFF
ON
MB91F523JLBPMC
OFF
MB91F522JWBPMC
ON
ON
MB91F522JYBPMC
OFF
MB91F522JJBPMC
OFF
ON
MB91F522JLBPMC
OFF
MB91F526JSBPMC
None
ON
ON
MB91F526JUBPMC
OFF
MB91F526JHBPMC
OFF
ON
MB91F526JKBPMC
OFF
MB91F525JSBPMC
ON
ON
MB91F525JUBPMC
OFF
MB91F525JHBPMC
OFF
ON
MB91F525JKBPMC
OFF
MB91F524JSBPMC
ON
ON
MB91F524JUBPMC
OFF
MB91F524JHBPMC
OFF
ON
MB91F524JKBPMC
OFF
MB91F523JSBPMC
ON
ON
MB91F523JUBPMC
OFF
MB91F523JHBPMC
OFF
ON
MB91F523JKBPMC
OFF
MB91F522JSBPMC
ON
ON
MB91F522JUBPMC
OFF
MB91F522JHBPMC
OFF
ON
MB91F522JKBPMC
OFF
Document Number: 002-04662 Rev. *D Page 208 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526FWBPMC
Yes
ON
ON
LQI・100 pin,
Plastic
MB91F526FYBPMC
OFF
MB91F526FJBPMC
OFF
ON
MB91F526FLBPMC
OFF
MB91F525FWBPMC
ON
ON
MB91F525FYBPMC
OFF
MB91F525FJBPMC
OFF
ON
MB91F525FLBPMC
OFF
MB91F524FWBPMC
ON
ON
MB91F524FYBPMC
OFF
MB91F524FJBPMC
OFF
ON
MB91F524FLBPMC
OFF
MB91F523FWBPMC
ON
ON
MB91F523FYBPMC
OFF
MB91F523FJBPMC
OFF
ON
MB91F523FLBPMC
OFF
MB91F522FWBPMC
ON
ON
MB91F522FYBPMC
OFF
MB91F522FJBPMC
OFF
ON
MB91F522FLBPMC
OFF
MB91F526FSBPMC
None
ON
ON
MB91F526FUBPMC
OFF
MB91F526FHBPMC
OFF
ON
MB91F526FKBPMC
OFF
MB91F525FSBPMC
ON
ON
MB91F525FUBPMC
OFF
MB91F525FHBPMC
OFF
ON
MB91F525FKBPMC
OFF
MB91F524FSBPMC
ON
ON
MB91F524FUBPMC
OFF
MB91F524FHBPMC
OFF
ON
MB91F524FKBPMC
OFF
MB91F523FSBPMC
ON
ON
MB91F523FUBPMC
OFF
MB91F523FHBPMC
OFF
ON
MB91F523FKBPMC
OFF
MB91F522FSBPMC
ON
ON
MB91F522FUBPMC
OFF
MB91F522FHBPMC
OFF
ON
MB91F522FKBPMC
OFF
Document Number: 002-04662 Rev. *D Page 209 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526DWBPMC
Yes
ON
ON
LQH・80 pin,
Plastic
MB91F526DYBPMC
OFF
MB91F526DJBPMC
OFF
ON
MB91F526DLBPMC
OFF
MB91F525DWBPMC
ON
ON
MB91F525DYBPMC
OFF
MB91F525DJBPMC
OFF
ON
MB91F525DLBPMC
OFF
MB91F524DWBPMC
ON
ON
MB91F524DYBPMC
OFF
MB91F524DJBPMC
OFF
ON
MB91F524DLBPMC
OFF
MB91F523DWBPMC
ON
ON
MB91F523DYBPMC
OFF
MB91F523DJBPMC
OFF
ON
MB91F523DLBPMC
OFF
MB91F522DWBPMC
ON
ON
MB91F522DYBPMC
OFF
MB91F522DJBPMC
OFF
ON
MB91F522DLBPMC
OFF
MB91F526DSBPMC
None
ON
ON
MB91F526DUBPMC
OFF
MB91F526DHBPMC
OFF
ON
MB91F526DKBPMC
OFF
MB91F525DSBPMC
ON
ON
MB91F525DUBPMC
OFF
MB91F525DHBPMC
OFF
ON
MB91F525DKBPMC
OFF
MB91F524DSBPMC
ON
ON
MB91F524DUBPMC
OFF
MB91F524DHBPMC
OFF
ON
MB91F524DKBPMC
OFF
MB91F523DSBPMC
ON
ON
MB91F523DUBPMC
OFF
MB91F523DHBPMC
OFF
ON
MB91F523DKBPMC
OFF
MB91F522DSBPMC
ON
ON
MB91F522DUBPMC
OFF
MB91F522DHBPMC
OFF
ON
MB91F522DKBPMC
OFF
Document Number: 002-04662 Rev. *D Page 210 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526BWBPMC1
Yes
ON
ON
LQD・64 pin,
Plastic
MB91F526BYBPMC1
OFF
MB91F526BJBPMC1
OFF
ON
MB91F526BLBPMC1
OFF
MB91F525BWBPMC1
ON
ON
MB91F525BYBPMC1
OFF
MB91F525BJBPMC1
OFF
ON
MB91F525BLBPMC1
OFF
MB91F524BWBPMC1
ON
ON
MB91F524BYBPMC1
OFF
MB91F524BJBPMC1
OFF
ON
MB91F524BLBPMC1
OFF
MB91F523BWBPMC1
ON
ON
MB91F523BYBPMC1
OFF
MB91F523BJBPMC1
OFF
ON
MB91F523BLBPMC1
OFF
MB91F522BWBPMC1
ON
ON
MB91F522BYBPMC1
OFF
MB91F522BJBPMC1
OFF
ON
MB91F522BLBPMC1
OFF
MB91F526BSBPMC1
None
ON
ON
MB91F526BUBPMC1
OFF
MB91F526BHBPMC1
OFF
ON
MB91F526BKBPMC1
OFF
MB91F525BSBPMC1
ON
ON
MB91F525BUBPMC1
OFF
MB91F525BHBPMC1
OFF
ON
MB91F525BKBPMC1
OFF
MB91F524BSBPMC1
ON
ON
MB91F524BUBPMC1
OFF
MB91F524BHBPMC1
OFF
ON
MB91F524BKBPMC1
OFF
MB91F523BSBPMC1
ON
ON
MB91F523BUBPMC1
OFF
MB91F523BHBPMC1
OFF
ON
MB91F523BKBPMC1
OFF
MB91F522BSBPMC1
ON
ON
MB91F522BUBPMC1
OFF
MB91F522BHBPMC1
OFF
ON
MB91F522BKBPMC1
OFF
*1: It is only supported for customers who have already adopted it now. We do not recommend adopting new products.
*2: For details of the package, see "■ PACKAGE DIMENSIONS ".
Document Number: 002-04662 Rev. *D Page 211 of 289
MB91520 Series
14. Ordering Information MB91F52xxxC*1
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526LWCPMC
Yes
ON
ON
LQP・176 pin,
Plastic
MB91F526LYCPMC
OFF
MB91F526LJCPMC
OFF
ON
MB91F526LLCPMC
OFF
MB91F525LWCPMC
ON
ON
MB91F525LYCPMC
OFF
MB91F525LJCPMC
OFF
ON
MB91F525LLCPMC
OFF
MB91F524LWCPMC
ON
ON
MB91F524LYCPMC
OFF
MB91F524LJCPMC
OFF
ON
MB91F524LLCPMC
OFF
MB91F523LWCPMC
ON
ON
MB91F523LYCPMC
OFF
MB91F523LJCPMC
OFF
ON
MB91F523LLCPMC
OFF
MB91F522LWCPMC
ON
ON
MB91F522LYCPMC
OFF
MB91F522LJCPMC
OFF
ON
MB91F522LLCPMC
OFF
MB91F526LSCPMC
None
ON
ON
MB91F526LUCPMC
OFF
MB91F526LHCPMC
OFF
ON
MB91F526LKCPMC
OFF
MB91F525LSCPMC
ON
ON
MB91F525LUCPMC
OFF
MB91F525LHCPMC
OFF
ON
MB91F525LKCPMC
OFF
MB91F524LSCPMC
ON
ON
MB91F524LUCPMC
OFF
MB91F524LHCPMC
OFF
ON
MB91F524LKCPMC
OFF
MB91F523LSCPMC
ON
ON
MB91F523LUCPMC
OFF
MB91F523LHCPMC
OFF
ON
MB91F523LKCPMC
OFF
MB91F522LSCPMC
ON
ON
MB91F522LUCPMC
OFF
MB91F522LHCPMC
OFF
ON
MB91F522LKCPMC
OFF
Document Number: 002-04662 Rev. *D Page 212 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526KWCPMC
Yes
ON
ON
LQS・144 pin,
(Lead pitch 0.5mm)
Plastic
MB91F526KYCPMC
OFF
MB91F526KJCPMC
OFF
ON
MB91F526KLCPMC
OFF
MB91F525KWCPMC
ON
ON
MB91F525KYCPMC
OFF
MB91F525KJCPMC
OFF
ON
MB91F525KLCPMC
OFF
MB91F524KWCPMC
ON
ON
MB91F524KYCPMC
OFF
MB91F524KJCPMC
OFF
ON
MB91F524KLCPMC
OFF
MB91F523KWCPMC
ON
ON
MB91F523KYCPMC
OFF
MB91F523KJCPMC
OFF
ON
MB91F523KLCPMC
OFF
MB91F522KWCPMC
ON
ON
MB91F522KYCPMC
OFF
MB91F522KJCPMC
OFF
ON
MB91F522KLCPMC
OFF
MB91F526KSCPMC
None
ON
ON
MB91F526KUCPMC
OFF
MB91F526KHCPMC
OFF
ON
MB91F526KKCPMC
OFF
MB91F525KSCPMC
ON
ON
MB91F525KUCPMC
OFF
MB91F525KHCPMC
OFF
ON
MB91F525KKCPMC
OFF
MB91F524KSCPMC
ON
ON
MB91F524KUCPMC
OFF
MB91F524KHCPMC
OFF
ON
MB91F524KKCPMC
OFF
MB91F523KSCPMC
ON
ON
MB91F523KUCPMC
OFF
MB91F523KHCPMC
OFF
ON
MB91F523KKCPMC
OFF
MB91F522KSCPMC
ON
ON
MB91F522KUCPMC
OFF
MB91F522KHCPMC
OFF
ON
MB91F522KKCPMC
OFF
Document Number: 002-04662 Rev. *D Page 213 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526KWCPMC1
Yes
ON
ON
LQN・144 pin,
(Lead pitch 0.4mm)
Plastic
MB91F526KYCPMC1
OFF
MB91F526KJCPMC1
OFF
ON
MB91F526KLCPMC1
OFF
MB91F525KWCPMC1
ON
ON
MB91F525KYCPMC1
OFF
MB91F525KJCPMC1
OFF
ON
MB91F525KLCPMC1
OFF
MB91F524KWCPMC1
ON
ON
MB91F524KYCPMC1
OFF
MB91F524KJCPMC1
OFF
ON
MB91F524KLCPMC1
OFF
MB91F523KWCPMC1
ON
ON
MB91F523KYCPMC1
OFF
MB91F523KJCPMC1
OFF
ON
MB91F523KLCPMC1
OFF
MB91F522KWCPMC1
ON
ON
MB91F522KYCPMC1
OFF
MB91F522KJCPMC1
OFF
ON
MB91F522KLCPMC1
OFF
MB91F526KSCPMC1
None
ON
ON
MB91F526KUCPMC1
OFF
MB91F526KHCPMC1
OFF
ON
MB91F526KKCPMC1
OFF
MB91F525KSCPMC1
ON
ON
MB91F525KUCPMC1
OFF
MB91F525KHCPMC1
OFF
ON
MB91F525KKCPMC1
OFF
MB91F524KSCPMC1
ON
ON
MB91F524KUCPMC1
OFF
MB91F524KHCPMC1
OFF
ON
MB91F524KKCPMC1
OFF
MB91F523KSCPMC1
ON
ON
MB91F523KUCPMC1
OFF
MB91F523KHCPMC1
OFF
ON
MB91F523KKCPMC1
OFF
MB91F522KSCPMC1
ON
ON
MB91F522KUCPMC1
OFF
MB91F522KHCPMC1
OFF
ON
MB91F522KKCPMC1
OFF
Document Number: 002-04662 Rev. *D Page 214 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526JWCPMC
Yes
ON
ON
LQM・120 pin,
Plastic
MB91F526JYCPMC
OFF
MB91F526JJCPMC
OFF
ON
MB91F526JLCPMC
OFF
MB91F525JWCPMC
ON
ON
MB91F525JYCPMC
OFF
MB91F525JJCPMC
OFF
ON
MB91F525JLCPMC
OFF
MB91F524JWCPMC
ON
ON
MB91F524JYCPMC
OFF
MB91F524JJCPMC
OFF
ON
MB91F524JLCPMC
OFF
MB91F523JWCPMC
ON
ON
MB91F523JYCPMC
OFF
MB91F523JJCPMC
OFF
ON
MB91F523JLCPMC
OFF
MB91F522JWCPMC
ON
ON
MB91F522JYCPMC
OFF
MB91F522JJCPMC
OFF
ON
MB91F522JLCPMC
OFF
MB91F526JSCPMC
None
ON
ON
MB91F526JUCPMC
OFF
MB91F526JHCPMC
OFF
ON
MB91F526JKCPMC
OFF
MB91F525JSCPMC
ON
ON
MB91F525JUCPMC
OFF
MB91F525JHCPMC
OFF
ON
MB91F525JKCPMC
OFF
MB91F524JSCPMC
ON
ON
MB91F524JUCPMC
OFF
MB91F524JHCPMC
OFF
ON
MB91F524JKCPMC
OFF
MB91F523JSCPMC
ON
ON
MB91F523JUCPMC
OFF
MB91F523JHCPMC
OFF
ON
MB91F523JKCPMC
OFF
MB91F522JSCPMC
ON
ON
MB91F522JUCPMC
OFF
MB91F522JHCPMC
OFF
ON
MB91F522JKCPMC
OFF
Document Number: 002-04662 Rev. *D Page 215 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526FWCPMC
Yes
ON
ON
LQI・100 pin,
Plastic
MB91F526FYCPMC
OFF
MB91F526FJCPMC
OFF
ON
MB91F526FLCPMC
OFF
MB91F525FWCPMC
ON
ON
MB91F525FYCPMC
OFF
MB91F525FJCPMC
OFF
ON
MB91F525FLCPMC
OFF
MB91F524FWCPMC
ON
ON
MB91F524FYCPMC
OFF
MB91F524FJCPMC
OFF
ON
MB91F524FLCPMC
OFF
MB91F523FWCPMC
ON
ON
MB91F523FYCPMC
OFF
MB91F523FJCPMC
OFF
ON
MB91F523FLCPMC
OFF
MB91F522FWCPMC
ON
ON
MB91F522FYCPMC
OFF
MB91F522FJCPMC
OFF
ON
MB91F522FLCPMC
OFF
MB91F526FSCPMC
None
ON
ON
MB91F526FUCPMC
OFF
MB91F526FHCPMC
OFF
ON
MB91F526FKCPMC
OFF
MB91F525FSCPMC
ON
ON
MB91F525FUCPMC
OFF
MB91F525FHCPMC
OFF
ON
MB91F525FKCPMC
OFF
MB91F524FSCPMC
ON
ON
MB91F524FUCPMC
OFF
MB91F524FHCPMC
OFF
ON
MB91F524FKCPMC
OFF
MB91F523FSCPMC
ON
ON
MB91F523FUCPMC
OFF
MB91F523FHCPMC
OFF
ON
MB91F523FKCPMC
OFF
MB91F522FSCPMC
ON
ON
MB91F522FUCPMC
OFF
MB91F522FHCPMC
OFF
ON
MB91F522FKCPMC
OFF
Document Number: 002-04662 Rev. *D Page 216 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526DWCPMC
Yes
ON
ON
LQH・80 pin,
Plastic
MB91F526DYCPMC
OFF
MB91F526DJCPMC
OFF
ON
MB91F526DLCPMC
OFF
MB91F525DWCPMC
ON
ON
MB91F525DYCPMC
OFF
MB91F525DJCPMC
OFF
ON
MB91F525DLCPMC
OFF
MB91F524DWCPMC
ON
ON
MB91F524DYCPMC
OFF
MB91F524DJCPMC
OFF
ON
MB91F524DLCPMC
OFF
MB91F523DWCPMC
ON
ON
MB91F523DYCPMC
OFF
MB91F523DJCPMC
OFF
ON
MB91F523DLCPMC
OFF
MB91F522DWCPMC
ON
ON
MB91F522DYCPMC
OFF
MB91F522DJCPMC
OFF
ON
MB91F522DLCPMC
OFF
MB91F526DSCPMC
None
ON
ON
MB91F526DUCPMC
OFF
MB91F526DHCPMC
OFF
ON
MB91F526DKCPMC
OFF
MB91F525DSCPMC
ON
ON
MB91F525DUCPMC
OFF
MB91F525DHCPMC
OFF
ON
MB91F525DKCPMC
OFF
MB91F524DSCPMC
ON
ON
MB91F524DUCPMC
OFF
MB91F524DHCPMC
OFF
ON
MB91F524DKCPMC
OFF
MB91F523DSCPMC
ON
ON
MB91F523DUCPMC
OFF
MB91F523DHCPMC
OFF
ON
MB91F523DKCPMC
OFF
MB91F522DSCPMC
ON
ON
MB91F522DUCPMC
OFF
MB91F522DHCPMC
OFF
ON
MB91F522DKCPMC
OFF
Document Number: 002-04662 Rev. *D Page 217 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*2
MB91F526BWCPMC1
Yes
ON
ON
LQD・64 pin,
Plastic
MB91F526BYCPMC1
OFF
MB91F526BJCPMC1
OFF
ON
MB91F526BLCPMC1
OFF
MB91F525BWCPMC1
ON
ON
MB91F525BYCPMC1
OFF
MB91F525BJCPMC1
OFF
ON
MB91F525BLCPMC1
OFF
MB91F524BWCPMC1
ON
ON
MB91F524BYCPMC1
OFF
MB91F524BJCPMC1
OFF
ON
MB91F524BLCPMC1
OFF
MB91F523BWCPMC1
ON
ON
MB91F523BYCPMC1
OFF
MB91F523BJCPMC1
OFF
ON
MB91F523BLCPMC1
OFF
MB91F522BWCPMC1
ON
ON
MB91F522BYCPMC1
OFF
MB91F522BJCPMC1
OFF
ON
MB91F522BLCPMC1
OFF
MB91F526BSCPMC1
None
ON
ON
MB91F526BUCPMC1
OFF
MB91F526BHCPMC1
OFF
ON
MB91F526BKCPMC1
OFF
MB91F525BSCPMC1
ON
ON
MB91F525BUCPMC1
OFF
MB91F525BHCPMC1
OFF
ON
MB91F525BKCPMC1
OFF
MB91F524BSCPMC1
ON
ON
MB91F524BUCPMC1
OFF
MB91F524BHCPMC1
OFF
ON
MB91F524BKCPMC1
OFF
MB91F523BSCPMC1
ON
ON
MB91F523BUCPMC1
OFF
MB91F523BHCPMC1
OFF
ON
MB91F523BKCPMC1
OFF
MB91F522BSCPMC1
ON
ON
MB91F522BUCPMC1
OFF
MB91F522BHCPMC1
OFF
ON
MB91F522BKCPMC1
OFF
*1: It is only supported for customers who have already adopted it now. We do not recommend adopting new products.
*2: For details of the package, see "■ PACKAGE DIMENSIONS ".
Document Number: 002-04662 Rev. *D Page 218 of 289
MB91520 Series
15. Ordering Information MB91F52xxxD
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526LWDPMC
Yes
ON
ON
LQP・176 pin,
Plastic
MB91F526LJDPMC
OFF
ON
MB91F525LWDPMC
ON
ON
MB91F525LJDPMC
OFF
ON
MB91F524LWDPMC
ON
ON
MB91F524LJDPMC
OFF
ON
MB91F523LWDPMC
ON
ON
MB91F523LJDPMC
OFF
ON
MB91F522LWDPMC
ON
ON
MB91F522LJDPMC
OFF
ON
MB91F526LSDPMC
None
ON
ON
MB91F526LHDPMC
OFF
ON
MB91F525LSDPMC
ON
ON
MB91F525LHDPMC
OFF
ON
MB91F524LSDPMC
ON
ON
MB91F524LHDPMC
OFF
ON
MB91F523LSDPMC
ON
ON
MB91F523LHDPMC
OFF
ON
MB91F522LSDPMC
ON
ON
MB91F522LHDPMC
OFF
ON
MB91F526KWDPMC
Yes
ON
ON
LQS・144 pin,
(Lead pitch 0.5mm)
Plastic
MB91F526KJDPMC
OFF
ON
MB91F525KWDPMC
ON
ON
MB91F525KJDPMC
OFF
ON
MB91F524KWDPMC
ON
ON
MB91F524KJDPMC
OFF
ON
MB91F523KWDPMC
ON
ON
MB91F523KJDPMC
OFF
ON
MB91F522KWDPMC
ON
ON
MB91F522KJDPMC
OFF
ON
MB91F526KSDPMC
None
ON
ON
MB91F526KHDPMC
OFF
ON
MB91F525KSDPMC
ON
ON
MB91F525KHDPMC
OFF
ON
MB91F524KSDPMC
ON
ON
MB91F524KHDPMC
OFF
ON
MB91F523KSDPMC
ON
ON
MB91F523KHDPMC
OFF
ON
MB91F522KSDPMC
ON
ON
MB91F522KHDPMC
OFF
ON
Document Number: 002-04662 Rev. *D Page 219 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526KWDPMC1
Yes
ON
ON
LQN・144 pin,
(Lead pitch 0.4mm)
Plastic
MB91F526KJDPMC1
OFF
ON
MB91F525KWDPMC1
ON
ON
MB91F525KJDPMC1
OFF
ON
MB91F524KWDPMC1
ON
ON
MB91F524KJDPMC1
OFF
ON
MB91F523KWDPMC1
ON
ON
MB91F523KJDPMC1
OFF
ON
MB91F522KWDPMC1
ON
ON
MB91F522KJDPMC1
OFF
ON
MB91F526KSDPMC1
None
ON
ON
MB91F526KHDPMC1
OFF
ON
MB91F525KSDPMC1
ON
ON
MB91F525KHDPMC1
OFF
ON
MB91F524KSDPMC1
ON
ON
MB91F524KHDPMC1
OFF
ON
MB91F523KSDPMC1
ON
ON
MB91F523KHDPMC1
OFF
ON
MB91F522KSDPMC1
ON
ON
MB91F522KHDPMC1
OFF
ON
MB91F526JWDPMC
Yes
ON
ON
LQM・120 pin,
Plastic
MB91F526JJDPMC
OFF
ON
MB91F525JWDPMC
ON
ON
MB91F525JJDPMC
OFF
ON
MB91F524JWDPMC
ON
ON
MB91F524JJDPMC
OFF
ON
MB91F523JWDPMC
ON
ON
MB91F523JJDPMC
OFF
ON
MB91F522JWDPMC
ON
ON
MB91F522JJDPMC
OFF
ON
MB91F526JSDPMC
None
ON
ON
MB91F526JHDPMC
OFF
ON
MB91F525JSDPMC
ON
ON
MB91F525JHDPMC
OFF
ON
MB91F524JSDPMC
ON
ON
MB91F524JHDPMC
OFF
ON
MB91F523JSDPMC
ON
ON
MB91F523JHDPMC
OFF
ON
MB91F522JSDPMC
ON
ON
MB91F522JHDPMC
OFF
ON
Document Number: 002-04662 Rev. *D Page 220 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526FWDPMC
Yes
ON
ON
LQI・100 pin,
Plastic
MB91F526FJDPMC
OFF
ON
MB91F525FWDPMC
ON
ON
MB91F525FJDPMC
OFF
ON
MB91F524FWDPMC
ON
ON
MB91F524FJDPMC
OFF
ON
MB91F523FWDPMC
ON
ON
MB91F523FJDPMC
OFF
ON
MB91F522FWDPMC
ON
ON
MB91F522FJDPMC
OFF
ON
MB91F526FSDPMC
None
ON
ON
MB91F526FHDPMC
OFF
ON
MB91F525FSDPMC
ON
ON
MB91F525FHDPMC
OFF
ON
MB91F524FSDPMC
ON
ON
MB91F524FHDPMC
OFF
ON
MB91F523FSDPMC
ON
ON
MB91F523FHDPMC
OFF
ON
MB91F522FSDPMC
ON
ON
MB91F522FHDPMC
OFF
ON
MB91F526DWDPMC
Yes
ON
ON
LQH・80 pin,
Plastic
MB91F526DJDPMC
OFF
ON
MB91F525DWDPMC
ON
ON
MB91F525DJDPMC
OFF
ON
MB91F524DWDPMC
ON
ON
MB91F524DJDPMC
OFF
ON
MB91F523DWDPMC
ON
ON
MB91F523DJDPMC
OFF
ON
MB91F522DWDPMC
ON
ON
MB91F522DJDPMC
OFF
ON
MB91F526DSDPMC
None
ON
ON
MB91F526DHDPMC
OFF
ON
MB91F525DSDPMC
ON
ON
MB91F525DHDPMC
OFF
ON
MB91F524DSDPMC
ON
ON
MB91F524DHDPMC
OFF
ON
MB91F523DSDPMC
ON
ON
MB91F523DHDPMC
OFF
ON
MB91F522DSDPMC
ON
ON
MB91F522DHDPMC
OFF
ON
Document Number: 002-04662 Rev. *D Page 221 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526BWDPMC1
Yes
ON
ON
LQD・64 pin,
Plastic
MB91F526BJDPMC1
OFF
ON
MB91F525BWDPMC1
ON
ON
MB91F525BJDPMC1
OFF
ON
MB91F524BWDPMC1
ON
ON
MB91F524BJDPMC1
OFF
ON
MB91F523BWDPMC1
ON
ON
MB91F523BJDPMC1
OFF
ON
MB91F522BWDPMC1
ON
ON
MB91F522BJDPMC1
OFF
ON
MB91F526BSDPMC1
None
ON
ON
MB91F526BHDPMC1
OFF
ON
MB91F525BSDPMC1
ON
ON
MB91F525BHDPMC1
OFF
ON
MB91F524BSDPMC1
ON
ON
MB91F524BHDPMC1
OFF
ON
MB91F523BSDPMC1
ON
ON
MB91F523BHDPMC1
OFF
ON
MB91F522BSDPMC1
ON
ON
MB91F522BHDPMC1
OFF
ON
*: For details of the package, see "■ PACKAGE DIMENSIONS ".
Document Number: 002-04662 Rev. *D Page 222 of 289
MB91520 Series
16. Ordering Information MB91F52xxxE
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526LWEPMC
Yes
ON
ON
LQP・176 pin,
Plastic
MB91F526LJEPMC
OFF
ON
MB91F525LWEPMC
ON
ON
MB91F525LJEPMC
OFF
ON
MB91F524LWEPMC
ON
ON
MB91F524LJEPMC
OFF
ON
MB91F523LWEPMC
ON
ON
MB91F523LJEPMC
OFF
ON
MB91F522LWEPMC
ON
ON
MB91F522LJEPMC
OFF
ON
MB91F526LSEPMC
None
ON
ON
MB91F526LHEPMC
OFF
ON
MB91F525LSEPMC
ON
ON
MB91F525LHEPMC
OFF
ON
MB91F524LSEPMC
ON
ON
MB91F524LHEPMC
OFF
ON
MB91F523LSEPMC
ON
ON
MB91F523LHEPMC
OFF
ON
MB91F522LSEPMC
ON
ON
MB91F522LHEPMC
OFF
ON
MB91F526KWEPMC
Yes
ON
ON
LQS・144 pin,
(Lead pitch 0.5mm)
Plastic
MB91F526KJEPMC
OFF
ON
MB91F525KWEPMC
ON
ON
MB91F525KJEPMC
OFF
ON
MB91F524KWEPMC
ON
ON
MB91F524KJEPMC
OFF
ON
MB91F523KWEPMC
ON
ON
MB91F523KJEPMC
OFF
ON
MB91F522KWEPMC
ON
ON
MB91F522KJEPMC
OFF
ON
MB91F526KSEPMC
None
ON
ON
MB91F526KHEPMC
OFF
ON
MB91F525KSEPMC
ON
ON
MB91F525KHEPMC
OFF
ON
MB91F524KSEPMC
ON
ON
MB91F524KHEPMC
OFF
ON
MB91F523KSEPMC
ON
ON
MB91F523KHEPMC
OFF
ON
MB91F522KSEPMC
ON
ON
MB91F522KHEPMC
OFF
ON
Document Number: 002-04662 Rev. *D Page 223 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526KWEPMC1
Yes
ON
ON
LQN・144 pin,
(LeaE pitch 0.4mm)
Plastic
MB91F526KJEPMC1
OFF
ON
MB91F525KWEPMC1
ON
ON
MB91F525KJEPMC1
OFF
ON
MB91F524KWEPMC1
ON
ON
MB91F524KJEPMC1
OFF
ON
MB91F523KWEPMC1
ON
ON
MB91F523KJEPMC1
OFF
ON
MB91F522KWEPMC1
ON
ON
MB91F522KJEPMC1
OFF
ON
MB91F526KSEPMC1
None
ON
ON
MB91F526KHEPMC1
OFF
ON
MB91F525KSEPMC1
ON
ON
MB91F525KHEPMC1
OFF
ON
MB91F524KSEPMC1
ON
ON
MB91F524KHEPMC1
OFF
ON
MB91F523KSEPMC1
ON
ON
MB91F523KHEPMC1
OFF
ON
MB91F522KSEPMC1
ON
ON
MB91F522KHEPMC1
OFF
ON
MB91F526JWEPMC
Yes
ON
ON
LQM・120 pin,
Plastic
MB91F526JJEPMC
OFF
ON
MB91F525JWEPMC
ON
ON
MB91F525JJEPMC
OFF
ON
MB91F524JWEPMC
ON
ON
MB91F524JJEPMC
OFF
ON
MB91F523JWEPMC
ON
ON
MB91F523JJEPMC
OFF
ON
MB91F522JWEPMC
ON
ON
MB91F522JJEPMC
OFF
ON
MB91F526JSEPMC
None
ON
ON
MB91F526JHEPMC
OFF
ON
MB91F525JSEPMC
ON
ON
MB91F525JHEPMC
OFF
ON
MB91F524JSEPMC
ON
ON
MB91F524JHEPMC
OFF
ON
MB91F523JSEPMC
ON
ON
MB91F523JHEPMC
OFF
ON
MB91F522JSEPMC
ON
ON
MB91F522JHEPMC
OFF
ON
Document Number: 002-04662 Rev. *D Page 224 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526FWEPMC
Yes
ON
ON
LQI・100 pin,
Plastic
MB91F526FJEPMC
OFF
ON
MB91F525FWEPMC
ON
ON
MB91F525FJEPMC
OFF
ON
MB91F524FWEPMC
ON
ON
MB91F524FJEPMC
OFF
ON
MB91F523FWEPMC
ON
ON
MB91F523FJEPMC
OFF
ON
MB91F522FWEPMC
ON
ON
MB91F522FJEPMC
OFF
ON
MB91F526FSEPMC
None
ON
ON
MB91F526FHEPMC
OFF
ON
MB91F525FSEPMC
ON
ON
MB91F525FHEPMC
OFF
ON
MB91F524FSEPMC
ON
ON
MB91F524FHEPMC
OFF
ON
MB91F523FSEPMC
ON
ON
MB91F523FHEPMC
OFF
ON
MB91F522FSEPMC
ON
ON
MB91F522FHEPMC
OFF
ON
MB91F526DWEPMC
Yes
ON
ON
LQH・80 pin,
Plastic
MB91F526DJEPMC
OFF
ON
MB91F525DWEPMC
ON
ON
MB91F525DJEPMC
OFF
ON
MB91F524DWEPMC
ON
ON
MB91F524DJEPMC
OFF
ON
MB91F523DWEPMC
ON
ON
MB91F523DJEPMC
OFF
ON
MB91F522DWEPMC
ON
ON
MB91F522DJEPMC
OFF
ON
MB91F526DSEPMC
None
ON
ON
MB91F526DHEPMC
OFF
ON
MB91F525DSEPMC
ON
ON
MB91F525DHEPMC
OFF
ON
MB91F524DSEPMC
ON
ON
MB91F524DHEPMC
OFF
ON
MB91F523DSEPMC
ON
ON
MB91F523DHEPMC
OFF
ON
MB91F522DSEPMC
ON
ON
MB91F522DHEPMC
OFF
ON
Document Number: 002-04662 Rev. *D Page 225 of 289
MB91520 Series
Part number
Sub clock
CSV Initial value
LVD Initial value
Package*
MB91F526BWEPMC1
Yes
ON
ON
LQE・64 pin,
Plastic
MB91F526BJEPMC1
OFF
ON
MB91F525BWEPMC1
ON
ON
MB91F525BJEPMC1
OFF
ON
MB91F524BWEPMC1
ON
ON
MB91F524BJEPMC1
OFF
ON
MB91F523BWEPMC1
ON
ON
MB91F523BJEPMC1
OFF
ON
MB91F522BWEPMC1
ON
ON
MB91F522BJEPMC1
OFF
ON
MB91F526BSEPMC1
None
ON
ON
MB91F526BHEPMC1
OFF
ON
MB91F525BSEPMC1
ON
ON
MB91F525BHEPMC1
OFF
ON
MB91F524BSEPMC1
ON
ON
MB91F524BHEPMC1
OFF
ON
MB91F523BSEPMC1
ON
ON
MB91F523BHEPMC1
OFF
ON
MB91F522BSEPMC1
ON
ON
MB91F522BHEPMC1
OFF
ON
*: For details of the package, see "■ PACKAGE DIMENSIONS ".
Document Number: 002-04662 Rev. *D Page 226 of 289
MB91520 Series
17. Package Dimensions
Document Number: 002-04662 Rev. *D Page 227 of 289
MB91520 Series
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MB91520 Series
Document Number: 002-04662 Rev. *D Page 229 of 289
MB91520 Series
Document Number: 002-04662 Rev. *D Page 230 of 289
MB91520 Series
Document Number: 002-04662 Rev. *D Page 231 of 289
MB91520 Series
Document Number: 002-04662 Rev. *D Page 232 of 289
MB91520 Series
Document Number: 002-04662 Rev. *D Page 233 of 289
MB91520 Series
18. Errata
This section describes the errata for the MB91520 Series. Details include errata trigger conditions, scope of impact, available
workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
Part Number
MB91F522B/D/F/J/K/L
MB91F523B/D/F/J/K/L
MB91F524B/D/F/J/K/L
MB91F525B/D/F/J/K/L
MB91F526B/D/F/J/K/L
MB91F522/3/4/5/6 Qualification Status
Product Status: Production
Errata Summary
The following table defines the errata applicability to available MB91520 Series devices.
Items Part Number Silicon
Revision
Fix Status
[1]. Power-on Conditions is not enough
in the Datasheet Specification
MB91F522B/D/F/J/K/L
MB91F523B/D/F/J/K/L
MB91F524B/D/F/J/K/L
MB91F525B/D/F/J/K/L
MB91F526B/D/F/J/K/L
B, C Will be fixed in production
silicon version D, E
[2]. Limitation for Watch mode (power
off) B, C, D, E -
1. Power-on Conditions is not enough in the Datasheet Specification
■ Problem Definition
If the Power-On-Reset and Internal Low Voltage Detection are not generated, some port functions will not be available.
■ Parameters Affected
tOFF for Power off time on Power-on Conditions
VCC Power ramp rate on Power-on Conditions
■ Trigger Condition
When the power supply voltage to the MCU has been turned off but has not reached 0 V when the power supply voltage
is turned on again, MCU does not generate an internal power-on-reset signal (Power-On reset or Internal LVD reset).
Then, some port functions will not be available.
If below condition (1) or (2) or (3) is satisfied, Power-On Reset (Initialization-Reset signal) is generated and no problem
occurs.
(1) The VCC voltage is less than 200 mV for 50 ms or longer (tOFF)
(2) VCC Power ramp rate less than 4 mV/µs (dV/dt) until a voltage level for a safe Power-On detection is reached
(3) C-pin voltage is below 60 mV when VCC is turned on again
Document Number: 002-04662 Rev. *D Page 234 of 289
MB91520 Series
■ Scope of Impact
For the affected parts, when the Power-On Reset and Internal Low Voltage Detection are not generated, the MCU may
set invalid package and sub clock option information. Therefore, the MCU may operate with an invalid pin configuration.
■ Workaround
For the affected parts, it is necessary to satisfy at least one of the Power-On Reset requirements for any Power-On event
as given below:
(1) The VCC voltage is less than 200 mV for 50 ms or longer (tOFF)
(2) VCC Power ramp rate is less than 4 mV/µs (dV/dt) until a voltage level for a safe Power-On detection is reached
(3) C-pin voltage is below 60 mV when VCC is turned on again
If the customer system does not satisfy the condition above-mentioned, Cypress will releases new version D, so Cypress
recommends the version D for MB91F52x. The new version prevents the limitation when an external reset signal is
asserted at pin RSTX anytime the supply voltage (VCC) is turned on.
■ Fix Status
Will be fixed in production silicon version D, E
2. Limitation for Watch mode (power off)
■ Problem Definition
If the below all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from
watch mode (power off).
■ Trigger Conditions
(1) Using the watch mode (power off)
(2) Interrupt levels that are used as sources for recovering from the watch mode (power off) are ‘16’ to ‘30’, or using
NMIX pin as source for recovering from the watch mode (power off)
(3) The sources for recovering from the watch mode (power off) are generated between PCLK 1 cycle and PMUCLK
3 cycles (*), after CPU state changes to the watch mode (power off)
(*): In case of PCLK = 0.5 MHz and PMUCLK = 32 kHz, it is approx. 2 µs to 100 µs
■ Scope of Impact
If the all trigger conditions (1) to (3) are satisfied, the below registers will be initialized after MCU recovers from watch
mode (power off).
WTCRH, WTCRM, WTCRL
CSELR.SCEN
CMONR.SCRDY
CCRTSELR.CST
CCRTSELR.CSC
Document Number: 002-04662 Rev. *D Page 235 of 289
MB91520 Series
■ Workaround
It is necessary to satisfy the below both conditions of (1) and (2).
(1) Interrupt levels that are used as sources for recovering from the watch mode (power off) are ‘31’, before CPU state
changes to the watch mode (power off)
(2) Don’t use NMIX pin as source for recovering from the watch mode (power off)
■ Fix Status
Will not be planned
Document Number: 002-04662 Rev. *D Page 236 of 289
MB91520 Series
19. Major Changes
Spansion Publication Number: MB91F526L_DS705-00011
Page Section Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
3 ■FEATURES
Corrected the following description.
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11
Automotive input
↓
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS
hysteresis input
33 to 36 ■I/O CIRCUIT TYPE
Corrected the following description to "Type F, G, I, J, K, M".
Schmitt input → CMOS hysteresis input
Corrected the following description to "Type D, E".
I
2
C Schmitt input → I
2
C hysteresis input
44 to 49 ■BLOCK DIAGRAM
Corrected the following description.
●MB91F522B, MB91F523B, MB91F524B, MB91F525B,
MB91F526B
●MB91F522D, MB91F523D, MB91F524D, MB91F525D,
MB91F526D
●MB91F522F, MB91F523F, MB91F524F, MB91F525F,
MB91F526F
●MB91F522J, MB91F523J, MB91F524J, MB91F525J,
MB91F526J
●MB91F522K, MB91F523K, MB91F524K, MB91F525K,
MB91F526K
●MB91F522L, MB91F523L, MB91F524L, MB91F525L,
MB91F526L
138 ■ELECTRICAL CHARACTERISTICS
2. Recommended operating conditions
Added the following description.
*1：When it is used outside recommended operation
guarantee range (range of the operation
guarantee),contact your sales representative. Moreover,
minimum value with an effective external low-voltage
detection reset becomes a voltage until generating
low-voltage detection reset
139,140 ■ELECTRICAL CHARACTERISTICS
3.DC characteristics
Corrected the value of "ICCT5 When using sub clock 32kHz
TA=+25°C
". Max 1420µA → Max 2000µA
139 ■ELECTRICAL CHARACTERISTICS
3.DC characteristics
Corrected the value of "Power supply voltage range".
(TA:-40°C to +105°C,Vcc=AVcc=2.7V to
5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to
+105°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V)
140,141 ■ELECTRICAL CHARACTERISTICS
3.DC characteristics
Corrected the value of "Power supply voltage range".
(TA:-40°C to +125°C,Vcc=AVcc=2.7V to
5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to
+125°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0
V)
141
■ELECTRICAL CHARACTERISTICS
3.DC characteristics
Corrected the value of " Pull-up resistance R
UP1
".
Vcc=3.3V±0.3V Min 49 Max 140 →Min 45 Max 140
Document Number: 002-04662 Rev. *D Page 237 of 289
MB91520 Series
Page Section Change Results
141 ■ELECTRICAL CHARACTERISTICS
3.DC characteristics
Corrected the following description.
Pull-up resistance RUP2
Port pin other than P035,041,093,122 → P073,074,076,077
141 ■ELECTRICAL CHARACTERISTICS
3.DC characteristics
Corrected the value of " Pull-up resistance R
UP2
".
VCC=5.0V±10% Min 25 Max 100 →Min 25 Max 60
VCC=3.3V±0.3V Min 49 Max 140 →Min 33 Max 90
141 ■ELECTRICAL CHARACTERISTICS
3.DC characteristics
Added the value of " Pull-up resistance RUP3".
Pin name : Port pin other than
P035,041,073,074,076,077,093,122
VCC=5.0V±10% Min 25 Max 100
VCC=3.3V±0.3V Min 45 Max 140
150,152,
154,156
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
(4-1-1),(4-1-4)SCK↓
⇒
SOT delay time t
SLOVI
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVI
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Value: Min -30 Max 30
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min -30 Max 30
Pin name: SCK3,SCK4
SOT3,SOT4
Value: Min -300 Max 300
150,152,
154,156
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
(4-1-1),(4-1-4)Valid SIN
⇒
SCK↑ setup time t
IVSHI
(4-1-2),(4-1-3)Valid SIN⇒SCK↓ setup time tIVSLI
Corrected the following description.
Pin name: SCK0 to SCK11 SIN0 to SIN11
Value: Min 34 Max -
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11 SIN0 to
SIN2,SIN5 to SIN11
Value: Min 34 Max -
Pin name: SCK3,SCK4,SIN3,SIN4
Value: Min 300 Max -
150,152,
154,156
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
(4-1-1),(4-1-4)SCK↓
⇒
SOT delay time t
SLOVE
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVE
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Value: Min - Max 33
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min - Max 33
Pin name: SCK3,SCK4 SOT3,SOT4
Value: Min - Max 300
Document Number: 002-04662 Rev. *D Page 238 of 289
MB91520 Series
Page Section Change Results
150,152,
154,156
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
(4-1-1),(4-1-2),(4-1-3),(4-1-4)SCK fall time tF
Corrected the following description.
Pin name: SCK0 to SCK2,SCK5 to SCK11
Value: Min - Max 5
Pin name: SCK3,SCK4
Value: Min - Max 250
↓
Pin name: SCK0 to SCK11
Value: Min - Max 5
158,161,
164,167
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
(4-1-5)SCS↓
⇒
SCK↓ setup time t
CSSI
(4-1-6)SCS↓⇒SCK↑ setup time tCSSI
(4-1-7)SCS↑⇒SCK↓ setup time tCSSI
(4-1-8)SCS↑⇒SCK↑ setup time tCSSI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to
SCS63,SCS70 to SCS73,SCS8 to SCS11
Value: Min tCSSU+0 Max tCSSU+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min tCSSU-50 Max tCSSU+0
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSSU-50
Max tCSSU+300
158,161,
164,167
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
(4-1-5)SCK↑
⇒
SCS↑hold time t
CSHI
(4-1-6)SCK↓⇒SCS↑hold time tCSHI
(4-1-7)SCK↑⇒SCS↓hold time tCSHI
(4-1-8)SCK↓⇒SCS↓hold time tCSHI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to
SCS63,SCS70 to SCS73,SCS8 to SCS11
Value: Min tCSHD-50 Max tCSHD+0
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min tCSHD-10 Max tCSHD+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSHD-300
Max tCSHD+50
Document Number: 002-04662 Rev. *D Page 239 of 289
MB91520 Series
Page Section Change Results
158,161,
164,167
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
(4-1-5),(4-1-6)SCS↓
⇒
SOT delay time t
DSE
(4-1-7),(4-1-8)SCS↑⇒SOT delay time tDSE
Corrected the following description.
Pin name: SCS1 to SCS3,SCS40 to SCS43,SCS50 to
SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to SCS11
SOT1 to SOT11
Value: Min - Max 40
↓
Pin name: SCS1,SCS2,SCS50 to SCS53,SCS60 to
SCS63,SCS70 to SCS73,
SCS8 to SCS11
SOT1,SOT2,SOT5 to SOT11
Value: Min - Max 40
Pin name: SCS3,SCS40 to SCS43
SOT3,SOT4
Value: Min -
Max 300
159,162,
165,168
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
(4-1-5)SCK↓⇒SCS↓ clock switch time tSCC
(4-1-6)SCK↑⇒SCS↓ clock switch time tSCC
(4-1-7)SCK↓⇒SCS↑ clock switch time tSCC
(4-1-8)SCK↑⇒SCS↑ clock switch time tSCC
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to
SCS63,SCS70 to SCS73,SCS8 to SCS11
Value: Min 3tCPP+0 Max 3tCPP+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,SCS8 to SCS11
Value: Min 3tCPP-10 Max 3tCPP+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min 3tCPP-300
Max 3tCPP+50
159,162,
165,168
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-5),(4-1-6),(4-1-7),(4-1-8)
Added the following description.
Regardless of the deselect time setting, once after the serial
chip select pin becomes inactive, it will take at least five
peripheral bus clock cycles to be active again
184
■ELECTRICAL CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter Electrical
Characteristics
Added the value of "Total error".
Total error value Min – Typ – Max ±12 LSB
184
■ELECTRICAL CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter Electrical
Characteristics
Corrected the value of "Zero transition voltage".
Min AVRL+0.5LSB-20mV Max AVRL+0.5LSB+20mV
↓
Min AVRL-11.5LSB Max AVRL+12.5LSB
184
■ELECTRICAL CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter Electrical
Characteristics
Corrected the value of "Full-scale transition voltage".
Min AVRH-1.5LSB-20mV Max AVRH-1.5LSB+20mV
↓
Min AVRH-13.5LSB Max AVRH+10.5LSB
Document Number: 002-04662 Rev. *D Page 240 of 289
MB91520 Series
Page Section Change Results
184
■ELECTRICAL CHARACTERISTICS
5.A/D Converter
(1) 12-bit A/D Converter Electrical
Characteristics
Added the following description.
Parameter : Power supply current IA AVCC*3
*3: The power supply current described only current value on
A/D converter. The total AVcc current value must be
calculated the power supply current for A/D converter and
D/A converter.
188
■ELECTRICAL CHARACTERISTICS
7.D/A Converter
Added the following description.
Parameter : Power supply current *1
*1: The power supply current described only current value on
D/A converter.The total Avcc current value must be calculated
the power supply current for D/A converter and A/D converter.
187 ■ELECTRICAL CHARACTERISTICS
6.Flash memory
Parameter: Erase cycle*2/Data retain time
Deleted the following description.
Remarks :
"Temperature at writing/erasing Tj<+105°C"
188 ■ELECTRICAL CHARACTERISTICS
7.D/A Converter
Corrected the following description.
Parameter : Power supply current
Symbol IA Pin name AVCC
Symbol IAH Pin name AVCC
↓
Symbol IA Pin name AVCC
Symbol IAH Pin name AVCC
190 ■EXAMPLE CHARACTERISTICS Corrected the following description.
Watch mode
192 ■ORDERING INFORMATION
Corrected the following description.
■ORDERING INFORMATION
↓
■ORDERING INFORMATION MB91F52xxxB*1
Package
↓
Package*
2
198 ■ORDERING INFORMATION
Added the following description.
*1: It is only supported for customers who have already
adopted it now. We do not recommend adopting new
products.
198 ■ORDERING INFORMATION
Corrected the following description.
For details of the package, see "■ PACKAGE DIMENSIONS
".
↓
*2: For details of the package, see "■ PACKAGE
DIMENSIONS ".
199 to
205
■ORDERING INFORMATION Added the following description.
■ORDERING INFORMATION MB91F52xxxC
-
-
Company name and layout design change
Document Number: 002-04662 Rev. *D Page 241 of 289
MB91520 Series
Page Section Change Results
Cypress Document Number: 002-04662
Rev *B
1 ■Features
Corrected the following description.
∙ Clock generation (equipped with SSCG function)
∙ Main oscillation (4MHz to 16MHz)
∙ Sub oscillation (32kHz to 100kHz) or none sub oscillation
∙ PLL multiplication rate : 1 to 20 times
↓
∙ Clock generation (equipped with SSCG function)
∙ Main oscillation (4MHz to 16MHz)
∙ Sub oscillation (32kHz) or no sub oscillation
∙ PLL multiplication rate : 1 to 20 times
∙ Equipped with a 100kHz CR oscillator
2 ■Features
Corrected the following description.
∙ Base timer : Max. 2 channels
∙16-bit timer
∙ Any of four PWM/PPG/PWC/reload timer functions can be
selected and used
∙ A 32-bit timer can be used in 2 channels of cascade mode
↓
∙ Base timer : Max. 2 channels
∙ 16-bit timer
∙ Any of four PWM/PPG/PWC/reload timer functions can be
selected and used
∙ As for the PWC function and the reload timer function, a
pair of 16-bit timers can be used as one 32-bit timer in the
cascaded mode
6 ■Product Lineup
Corrected the following description for Product lineup
comparison(64 pin).
Multi-Function
Serial Interface
8ch
↓
Multi-Function
Serial Interface
8ch*1
6 ■Product Lineup
Added the following sentences under Product lineup
comparison(64 pin)
*1: Only channel 5, channel 6 and channel 11 support the I2C
(standard mode).
7 ■Product Lineup
Corrected the following description for Product lineup
comparison(80 pin).
Multi-Function
Serial Interface
9ch
↓
Multi-Function
Serial Interface
9ch*1
7 ■Product Lineup
Added the following sentences under Product lineup
comparison(80 pin)
*1: Only channel 5, channel 6 and channel 11 support the I2C
(standard mode).
Document Number: 002-04662 Rev. *D Page 242 of 289
MB91520 Series
Page Section Change Results
8 ■Product Lineup
Corrected the following description for Product lineup
comparison(100 pin).
Multi-Function
Serial Interface
12ch
↓
Multi-Function
Serial Interface
12ch*1
8 ■Product Lineup
Added the following sentences under Product lineup
comparison(100 pin)
*1: Only channel 5, channel 6, channel 7, channel 8 and
channel 11 support the I
2
C (standard mode).
9 ■Product Lineup
Corrected the following description for Product lineup
comparison(120 pin).
Multi-Function
Serial Interface
12ch
↓
Multi-Function
Serial Interface
12ch*1
9 ■Product Lineup
Added the following sentences under Product lineup
comparison(120 pin)
*1: Only channel 3 and channel 4 support the I2C (high-speed
mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8 and
channel 11 support the I
2
C (standard mode).
10 ■Product Lineup
Corrected the following description for Product lineup
comparison(144 pin).
Multi-Function
Serial Interface
12ch
↓
Multi-Function
Serial Interface
12ch*1
10 ■Product Lineup
Added the following sentences under Product lineup
comparison(144 pin)
*1: Only channel 3 and channel 4 support the I2C (high-speed
mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8, channel
10 and channel 11 support the I
2
C (standard mode).
11 ■Product Lineup
Corrected the following description for Product lineup
comparison(176 pin).
Multi-Function
Serial Interface
12ch
↓
Multi-Function
Serial Interface
12ch*1
11 ■Product Lineup
Added the following sentences under Product lineup
comparison(176 pin)
*1: Only channel 3 and channel 4 support the I2C (high-speed
mode/standard mode).
Only channel 5, channel 6, channel 7, channel 8, channel
10 and channel 11 support the I
2
C (standard mode).
Document Number: 002-04662 Rev. *D Page 243 of 289
MB91520 Series
Page Section Change Results
13 ■Pin Assignment MB91F52xB
Signals indicated by the shading below deleted in Figure.
- Left side
↓
VSS 1
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1 2
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0 3
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1 4
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1 5
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2 6
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2 7
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 8
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0 9
P036/OCU7_1/TOT5_0/BIN0_0 10
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1 11
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0 12
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0 13
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2 14
P047/AN45/TRG8_0/TIN3_2/SOT0_1 15
P053/AN44/PPG35_0/INT14_1/SCK0_1 16
Document Number: 002-04662 Rev. *D Page 244 of 289
MB91520 Series
Page Section Change Results
13 ■Pin Assignment MB91F52xB
- Right side
↓
48 P122/SIN6_0/AN31/OCU8_0/INT9_1
47 P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
46 P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
45 P110/TX1(64)/SCS63_0/AN22
44 NM IX
43
P105/AN17/PPG13_0
42
P104/AN16/PPG12_0
41
P103/AN15/PPG11_0
40
P102/AN14/PPG10_0/INT10_0
39 AVCC0
38 AVRH0
37 AVS S 0/AVRL0
36 P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
35 P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
34 P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
33 VSS
Document Number: 002-04662 Rev. *D Page 245 of 289
MB91520 Series
Page Section Change Results
13 ■Pin Assignment MB91F52xB
- To p
↓
VCC
P011/WOT/INT3_1
P006/ADTG1_1/INT2_1/TX2(64)
P005/ADTG0_1/INT7_1/RX2(64)
C
VSS
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P126/SIN0_0/INT6_0
DEBUGIF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
13 ■Pin Assignment MB91F52xB
The following note added on the bottom left of Figure.
* In a single clock product, pin 56 and pin 57 are the
general-purpose ports.
Document Number: 002-04662 Rev. *D Page 246 of 289
MB91520 Series
Page Section Change Results
14 ■Pin Assignment MB91F52xD
Signals indicated by the shading below deleted in Figure.
- Left side
↓
VSS 1
P020/SIN3_1/TRG3_0/TIN0_2/RTO5_1 2
P024/SIN4_1/PPG24_0/TIN1_0/RTO4_1/INT15_0 3
P026/SCK4_1/PPG26_0/TIN3_0 4
P027/SCS40_1/PPG27_0/TOT0_0/RTO3_1 5
P031/SCS42_1/PPG29_0 6
P032/SCS43_1/PPG30_0/TOT3_0/RTO2_1 7
P033/PPG31_0/ICU3_3/TIN4_0/RTO1_1/SCK3_2 8
P034/OCU11_1/ICU2_3/TIN5_0/RTO0_1/SOT3_2 9
P151/OCU9_1/TRG7_0/ICU0_3/TIN7_0/ZIN0_2/DTTI_1 10
P035/OCU8_1/TOT4_0/AIN0_0/INT11_0 11
P036/OCU7_1/TOT5_0/BIN0_0 12
P040/PPG23_1/TOT7_0/AIN1_0/SIN0_1 13
P041/SIN9_0/ICU9_1/BIN1_0/INT12_0 14
P042/SOT9_0/AN47/ICU8_1/TRG0_1/ZIN1_0 15
P044/SCS9_0/ICU6_1/TRG2_1 16
P045/SCK9_0/AN46/ICU5_1/TRG3_1/TOT1_2 17
P047/AN45/TRG8_0/TIN3_2/SOT0_1 18
P053/AN44/PPG35_0/INT14_1/SCK0_1 19
VCC 20
Document Number: 002-04662 Rev. *D Page 247 of 289
MB91520 Series
Page Section Change Results
14 ■Pin Assignment MB91F52xD
- Bottom
↓
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/AN33/ICU3_2
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P087/DAO0/PPG7_0/INT8_0
VCC
Document Number: 002-04662 Rev. *D Page 248 of 289
MB91520 Series
Page Section Change Results
14 ■Pin Assignment MB91F52xD
- Right side
↓
60 VSS
59 P122/SIN6_0/AN31/OCU8_0/INT9_1
58 P116/SCK6_0/SCL6/AN28/PPG20_0/RTO4_0
57 P115/RX1_1/SOT6_0/SDA6/AN27/PPG19_0/RTO3_0/INT1_1
56 P114/SCS61_0/AN26/PPG18_0/RTO2_0
55 P110/TX1(64)/SCS63_0/AN22
54 NM IX
53 P107/AN19/PPG15_0
52
P105/AN17/PPG13_0
51
P104/AN16/PPG12_0
50
P103/AN15/PPG11_0
49
P102/AN14/PPG10_0/INT10_0
48
P100/AN12/PPG8_0
47 AVCC0
46 AVRH0
45 AVS S 0/AVRL0
44 P097/SCK11_0/SCL11/AN11/ICU5_0/PPG17_1
43 P096/RX0(128)/SOT11_0/SDA11/AN10/INT0_0
42 P093/TX0_1/SIN11_0/AN7/ICU4_2/PPG16_1/ICU3_0
41 VSS
Document Number: 002-04662 Rev. *D Page 249 of 289
MB91520 Series
Page Section Change Results
14 ■Pin Assignment MB91F52xD
- To p
↓
VCC
P011/WOT/SOT2_1/INT3_1
P006/SCS2_0/ADTG1_1/INT2_1/TX2(64)
P005/SCK2_0/ADTG0_1/INT7_1/RX2(64)
P003/SIN2_0/TIOB1_1/INT3_0
P001/TIOA1_1
C
VSS
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P127/SOT0_0
P126/SIN0_0/INT6_0
DEBUGIF
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
14 ■Pin Assignment MB91F52xD
The following note added on the bottom left of Figure.
* In a single clock product, pin 71 and pin 72 are the
general-purpose ports.
Document Number: 002-04662 Rev. *D Page 250 of 289
MB91520 Series
Page Section Change Results
15 ■Pin Assignment MB91F52xF
Signals indicated by the shading below deleted in Figure.
(Error)
- Bottom
↓
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
P055/SIN10_0/AN43/PPG37_0/TIN4_1
AVCC1
P057/SCK10_1/AN42/ICU8_0/TRG0_2/PPG1_1/ICU1_1/TIN6_1
AVRH1
AVSS1/AVRL1
P060/SCS10_0/PPG2_1/ICU2_1/TOT5_1/INT13_0
P061/SOT10_1/AN41/ICU6_0/PPG3_1/ICU3_1/TOT6_1/INT13_1
P062/SCS10_1/SCS40_0/AN40/PPG4_1/FRCK0_0/TOT7_1/ZIN1_1
P063/SCS41_0/AN39/PPG5_1/FRCK1_0/BIN1_1
P064/SCS42_0/AN38/FRCK2_0/AIN1_1/PPG43_1
P065/SCS43_0/FRCK3_0/ZIN0_1/PPG44_1
P066/SOT4_2/SCS3_0/AN37/FRCK4_0/BIN0_1
P067/AN36/FRCK5_0/AIN0_1
P070/ICU0_2
P071/SCK4_2/AN35/ICU1_2/MONCLK
P072/SIN4_0/AN34/ICU2_2/INT5_0
P073/AN33/ICU3_2
P152/SCS53_0
P153/SCK5_0/SCL5/AN32/FRCK1_1/INT4_1
P081/SOT5_0/SDA5/AN0/PPG1_0
P082/SIN5_0/AN1/PPG2_0
P086/DAO1/PPG6_0
P087/DAO0/PPG7_0/INT8_0
VCC
Document Number: 002-04662 Rev. *D Page 251 of 289
MB91520 Series
Page Section Change Results
15 ■Pin Assignment MB91F52xF
- To p
↓
VCC
P011/WOT/SOT2_1/
INT3_1
P006/SCS2_0/ADTG1_1/INT2_1
P005/SCK2_0/ADTG0_1/INT7_1
P003/SIN2_0/TIOB1_1/INT3_0
P001/SOT1_0/TIOA1_1
P000/SIN1_0/INT2_0
C
VSS
P144/SCK1_1
P134/RX2(64)/SCS1_1/ICU7_0/INT7_0
P133/TX2(64)
RSTX
X0A/P136
X1A/P135/DTTI_0
VSS
X1
X0
MD1
MD0
P130/SCK0_0
P127/SOT0_0
P126/SIN0_0/INT6_0
DEBUGIF
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
15 ■Pin Assignment MB91F52xF
The following note added on the bottom left of Figure.
* In a single clock product, pin 86 and pin 87 are the
general-purpose ports.
16 ■Pin Assignment MB91F52xJ
The following note added on the bottom left of Figure.
* In a single clock product, pin 102 and pin 103 are the
general-purpose ports.
17 ■Pin Assignment MB91F52xK
The following note added on the bottom left of Figure.
* In a single clock product, pin 121 and pin 122 are the
general-purpose ports.
18 ■Pin Assignment MB91F52xL
The following note added on the bottom left of Figure.
* In a single clock product, pin 149 and pin 150 are the
general-purpose ports.
19 to 35 ■PIN Description
A List of "Pin Description" modified.
I/O
Circuit
types
*1
Function*2
↓
I/O
Circuit
types
*8
Function*9
Document Number: 002-04662 Rev. *D Page 252 of 289
MB91520 Series
Page Section Change Results
19 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
- - - - 2 2
P015
D29
TRG0_0
- - - - 3 3
P016
D30
TRG1_0
- - - - - 4
P170
PPG36_1
- - - - 4 5
P017
D31
TRG2_0
- - - - - 6
P171
PPG37_1
2
2 2 2 5 7
P020
ASX
SIN3_1
TRG3_0
TIN0_2
RTO5_1
- - - 3 6 8
P021
CS0X
SOT3_1
TRG6_1
TRG4_0
- - - 4 7 9
P022
CS1X
SCK3_1
TRG7_1
TRG5_0
- - - 5 8 10
P023
RDX
SCS3_1
PPG32_0
TIN0_0
3 3 3 6 9 11
P024
WR0X
SIN4_1
PPG24_0
TIN1_0
RTO4_1
INT15_0
Document Number: 002-04662 Rev. *D Page 253 of 289
MB91520 Series
Page Section Change Results
19 ■PIN Description
(Continued)
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
- - - - 2 2
P015
D29
TRG0_0
- - - - 3 3
P016
D30
TRG1_0
- - - - - 4
P170
PPG36_1
- - - - 4 5
P017
D31
TRG2_0
- - - - - 6
P171
PPG37_1
2 *1 2 *1 2 *1 2 *1 5 7
P020
ASX *2, *3, *4, *5
SIN3_1
TRG3_0
TIN0_2
RTO5_1
- - - 3 *1 6 8
P021
CS0X *5
SOT3_1
TRG6_1
TRG4_0
- - - 4 *1 7 9
P022
CS1X *5
SCK3_1
TRG7_1
TRG5_0
- - - 5 *1 8 10
P023
RDX *5
SCS3_1
PPG32_0
TIN0_0
3 *1 3 *1 3 *1 6 *1 9 11
P024
WR0X *2, *3, *4,
*5
SIN4_1
PPG24_0
TIN1_0
RTO4_1
INT15_0
Document Number: 002-04662 Rev. *D Page 254 of 289
MB91520 Series
Page Section Change Results
20 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
- - 4 7 10 12
P025
WR1X
SOT4_1
PPG25_0
TIN2_0
- - - - - 13
P172
PPG38_1
- 4 5 8 11 14
P026
A00
SCK4_1
PPG26_0
TIN3_0
4 5 6 9 12 15
P027
A01
SCS40_1
PPG27_0
TOT0_0
RTO3_1
- - - - - 16
P173
PPG39_1
- - 7 10 13 17
P030
A02
SCS41_1
PPG28_0
TOT1_0
- 6 8 11 14 18
P031
A03
SCS42_1
PPG29_0
TOT2_0
5 7 9 12 15 19
P032
A04
SCS43_1
PPG30_0
TOT3_0
RTO2_1
6 8 10
13 16 20
P033
A05
PPG31_0
ICU3_3
TIN4_0
RTO1_1
SCK3_2
Document Number: 002-04662 Rev. *D Page 255 of 289
MB91520 Series
Page Section Change Results
20 ■PIN Description
(Continued)
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
- - 4 *1 7 *1 10 12
P025
WR1X *4, *5
SOT4_1
PPG25_0
TIN2_0
- - - - - 13
P172
PPG38_1
- 4 *1 5 *1 8 *1 11 14
P026
A00 *3, *4, *5
SCK4_1
PPG26_0
TIN3_0
4 *1 5 *1 6 *1 9 *1 12 15
P027
A01 *2, *3, *4, *5
SCS40_1
PPG27_0
TOT0_0
RTO3_1
- - - - - 16
P173
PPG39_1
- - 7 *1 10 *1 13 17
P030
A02 *4, *5
SCS41_1
PPG28_0
TOT1_0
- 6 *1 8 *1 11 *1 14 18
P031
A03 *3, *4, *5
SCS42_1
PPG29_0
TOT2_0 *3
5 *1 7 *1 9 *1 12 *1 15 19
P032
A04 *2, *3, *4, *5
SCS43_1
PPG30_0
TOT3_0
RTO2_1
6 *1 8 *1 10 *1 13 *1 16 20
P033
A05 *2, *3, *4, *5
PPG31_0
ICU3_3
TIN4_0
RTO1_1
SCK3_2
Document Number: 002-04662 Rev. *D Page 256 of 289
MB91520 Series
Page Section Change Results
21, 22 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
7 9 11
14 17 21
P034
A06
OCU11_1
ICU2_3
TIN5_0
RTO0_1
SOT3_2
8 10
13 16 19 23
P151
SCK8_0/
SCL8
OCU9_1
TRG7_0
ICU0_3
TIN7_0
ZIN0_2
DTTI_1
9 11 14
17 20 24
P035
A07
SIN8_0
OCU8_1
TOT4_0
AIN0_0
INT11_0
10 12
15
18 21 25
P036
A08
SCS8_0
OCU7_1
TOT5_0
BIN0_0
- - 16
19 22 26
P037
A09
OCU6_1
TOT6_0
ZIN0_0
- - - - - 27
P174
TRG8_1
Document Number: 002-04662 Rev. *D Page 257 of 289
MB91520 Series
Page Section Change Results
21, 22 ■PIN Description
(Continued)
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
7 *1 9 *1 11 *1 14 *1 17 21
P034
A06 *2, *3, *4, *5
OCU11_1
ICU2_3
TIN5_0
RTO0_1
SOT3_2
8 *1 10 *1 13 16 19 23
P151
SCK8_0/
SCL8
*2, *3
OCU9_1
TRG7_0
ICU0_3
TIN7_0
ZIN0_2
DTTI_1
9 *1 11 *1 14 *1 17 *1 20 24
P035
A07 *2, *3, *4, *5
SIN8_0 *2, *3
OCU8_1
TOT4_0
AIN0_0
INT11_0
10 *1 12 *1 15 *1 18 *1 21 25
P036
A08 *2, *3, *4, *5
SCS8_0 *2, *3
OCU7_1
TOT5_0
BIN0_0
- - 16 *1 19 *1 22 26
P037
A09 *4, *5
OCU6_1
TOT6_0
ZIN0_0
- - - - - 27
P174
TRG8_1
Document Number: 002-04662 Rev. *D Page 258 of 289
MB91520 Series
Page Section Change Results
22, 23 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
- - - - - 28
P175
TRG9_1
11 13
17
20 23 29
P040
A10
PPG23_1
TOT7_0
AIN1_0
SIN0_1
12 14
18
21 24 30
P041
A11
SIN9_0
ICU9_1
BIN1_0
INT12_0
13 15
19
22 25 31
P042
A12
SOT9_0
AN47
ICU8_1
TRG0_1
ZIN1_0
- - 20
23 26 32
P043
A13
ICU7_1
TRG1_1
- 16
21
24 27 33
P044
A14
SCS9_0
ICU6_1
TRG2_1
14 17
22
25 28 34
P045
A15
SCK9_0
AN46
ICU5_1
TRG3_1
TOT1_2
- - - 26 29 35
P046
A16
ICU4_1
TRG4_1
- - - - - 36
P176
TRG10_0
Document Number: 002-04662 Rev. *D Page 259 of 289
MB91520 Series
Page Section Change Results
22, 23 ■PIN Description
(Continued)
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
- - - - - 28
P175
TRG9_1
11 *1 13 *1 17 *1 20 *1 23 29
P040
A10 *2, *3, *4, *5
PPG23_1
TOT7_0
AIN1_0
SIN0_1
12 *1 14 *1 18 *1 21 *1 24 30
P041
A11 *2, *3, *4, *5
SIN9_0
ICU9_1
BIN1_0
INT12_0
13 *1 15 *1 19 *1 22 *1 25 31
P042
A12 *2, *3, *4, *5
SOT9_0
AN47
ICU8_1
TRG0_1
ZIN1_0
- - 20 *1 23 *1 26 32
P043
A13 *4, *5
ICU7_1
TRG1_1
- 16 *1 21 *1 24 *1 27 33
P044
A14 *3, *4, *5
SCS9_0
ICU6_1
TRG2_1
14 *1 17 *1 22 *1 25 *1 28 34
P045
A15 *2, *3, *4, *5
SCK9_0
AN46
ICU5_1
TRG3_1
TOT1_2
- - - 26 *1 29 35
P046
A16 *5
ICU4_1
TRG4_1
- - - - - 36
P176
TRG10_0
Document Number: 002-04662 Rev. *D Page 260 of 289
MB91520 Series
Page Section Change Results
23, 24 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
15 18
23
27 30 37
P047
A17
AN45
TRG8_0
TIN3_2
SOT0_1
- - - - - 38
P177
TRG11_0
- - - 28 31 39
P050
A18
TRG5_1
PPG33_0
- - - - 32 40
P051
A19
TRG9_0
- - - - 33 41
P052
A20
PPG34_0
INT14_0
16 19
24
29 34 42
P053
A21
AN44
PPG35_0
INT14_1
SCK0_1
- - - - 35 43
P054
SYSCLK
PPG36_0
17 22
27
32 38 46
P055
CS2X
SIN10_0
AN43
PPG37_0
TIN4_1
- - - 33 39 49
P056
CS3X
ICU9_0
PPG0_1
ICU0_1
TIN5_1
DTTI_2
Document Number: 002-04662 Rev. *D Page 261 of 289
MB91520 Series
Page Section Change Results
23, 24 ■PIN Description
(Continued)
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
15 *1 18 *1 23 *1 27 *1 30 37
P047
A17 *2, *3, *4, *5
AN45
TRG8_0
TIN3_2
SOT0_1
- - - - - 38
P177
TRG11_0
- - - 28 *1 31 39
P050
A18 *5
TRG5_1
PPG33_0
- - - - 32 40
P051
A19
TRG9_0
- - - - 33 41
P052
A20
PPG34_0
INT14_0
16 *1 19 *1 24 *1 29 *1 34 42
P053
A21 *2, *3, *4, *5
AN44
PPG35_0
INT14_1
SCK0_1
- - - - 35 43
P054
SYSCLK
PPG36_0
17 *1 22 *1 27 *1 32 *1 38 46
P055
CS2X *2, *3, *4, *5
SIN10_0
AN43
PPG37_0
TIN4_1
- - - 33 *1 39 49
P056
CS3X *5
ICU9_0
PPG0_1
ICU0_1
TIN5_1
DTTI_2
Document Number: 002-04662 Rev. *D Page 262 of 289
MB91520 Series
Page Section Change Results
24 ■PIN Description
A List of "Pin Description" modified.
(Error)
Function*2
General-purpose I/O port
External Bus chip select 2 output pin(0)
Multi-function serial ch.10 serial data input
pin(0)
ADC analog 43 input pin
PPG ch.37 output pin(0)
Reload timer ch.4 event input pin(1)
(Correct)
Function*9
General-purpose I/O port
External Bus chip select 2 output pin
Multi-function serial ch.10 serial data input
pin(0)
ADC analog 43 input pin
PPG ch.37 output pin(0)
Reload timer ch.4 event input pin(1)
Document Number: 002-04662 Rev. *D Page 263 of 289
MB91520 Series
Page Section Change Results
24 ■PIN Description
A List of "Pin Description" modified.
(Error)
Function*2
General-purpose I/O port
External Bus chip select 3 output pin(0)
Input capture ch.9 input pin(0)
PPG ch.0 output pin(1)
Input capture ch.0 input pin(1)
Reload timer ch.5 event input pin(1)
Waveform generator ch.0 to ch.5 input pin(2)
(Correct)
Function*9
General-purpose I/O port
External Bus chip select 3 output pin
Input capture ch.9 input pin(0)
PPG ch.0 output pin(1)
Input capture ch.0 input pin(1)
Reload timer ch.5 event input pin(1)
Waveform generator ch.0 to ch.5 input pin(2)
Document Number: 002-04662 Rev. *D Page 264 of 289
MB91520 Series
Page Section Change Results
25 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
19 24
29
35 41 51
P057
RDY
SCK10_1
AN42
ICU8_0
TRG0_2
PPG1_1
ICU1_1
TIN6_1
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
19 *1 24 *1 29 *1 35 *1 41 51
P057
RDY *2, *3, *4, *5
SCK10_1
AN42
ICU8_0
TRG0_2
PPG1_1
ICU1_1
TIN6_1
27 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
- 35
43
49 57 71
P073
SOT4_0/
SDA4
AN33
ICU3_2
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
- 35 *3 43 *4 49 57 71
P073
SOT4_0/
SDA4
*3, *4
AN33
ICU3_2
Document Number: 002-04662 Rev. *D Page 265 of 289
MB91520 Series
Page Section Change Results
29 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
34 42
52 62 77 96
P093
TX0_1
SIN11_0
AN7
ICU4_2
PPG16_1
ICU3_0
TOT2_1
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
34 *1 42 *1 52 62 77 96
P093
TX0_1
SIN11_0
AN7
ICU4_2
PPG16_1
ICU3_0
TOT2_1 *2, *3
Document Number: 002-04662 Rev. *D Page 266 of 289
MB91520 Series
Page Section Change Results
30 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
- 48
59 69 85 104
P100
SCK7_0/
SCL7
AN12
PPG8_0
40 49
61 71 87 106
P102
SIN7_0
AN14
PPG10_0
INT10_0
41 50
62 72 88 107
P103
SCS73_0
AN15
PPG11_0
42 51
63 73 89 108
P104
SCS72_0
AN16
PPG12_0
43 52
64 74 90 109
P105
SCS71_0
AN17
PPG13_0
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
- 48 *1 59 69 85 104
P100
SCK7_0/
SCL7
*3
AN12
PPG8_0
40 *1 49 *1 61 71 87 106
P102
SIN7_0 *2, *3
AN14
PPG10_0
INT10_0
41 *1 50 *1 62 72 88 107
P103
SCS73_0 *2, *3
AN15
PPG11_0
42 *1 51 *1 63 73 89 108
P104
SCS72_0 *2, *3
AN16
PPG12_0
43 *1 52 *1 64 74 90 109
P105
SCS71_0 *2, *3
AN17
PPG13_0
Document Number: 002-04662 Rev. *D Page 267 of 289
MB91520 Series
Page Section Change Results
33 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
- - 94
111
131 159
P000
D16
SIN1_0
TIOA0_1
INT2_0
- 75
95
112
132 160
P001
D17
SOT1_0
TIOA1_1
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
- - 94 *1 111 *1 131 159
P000
D16 *4, *5
SIN1_0
TIOA0_1 *4
INT2_0
- 75 *1 95 *1 112 *1 132 160
P001
D17 *3, *4, *5
SOT1_0 *3
TIOA1_1
Document Number: 002-04662 Rev. *D Page 268 of 289
MB91520 Series
Page Section Change Results
34, 35 ■PIN Description
A List of "Pin Description" modified.
(Error)
Pin no.
Pin
Name
64
80
100
120
144
176
- - - 113
133 161
P002
D18
SCK1_0
TIOB0_1
- 76
96
114
134 162
P003
D19
SIN2_0
TIOB1_1
INT3_0
- - - - 135 163
P004
D20
SOT2_0
- - - - - 164
P164
PPG32_1
61 77
97
115
136
165
P005
D21
SCK2_0
ADTG0_1
INT7_1
(RX2(64))
- - - - - 166
P165
PPG33_1
62 78
98
116
137
167
P006
D22
SCS2_0
ADTG1_1
INT2_1
(TX2(64))
- - - 117
138 168
P007
D23
- - - - - 169
P166
PPG34_1
- - - 118
139 170
P010
D24
63 79
99
119
140 171
P011
WOT
D25
SOT2_1
TIOA0_0
INT3_1
Document Number: 002-04662 Rev. *D Page 269 of 289
MB91520 Series
Page Section Change Results
34, 35 ■PIN Description
(Continued)
(Correct)
Pin no.
Pin
Name
64
80
100
120
144
176
- - - 113 *1 133 161
P002
D18 *5
SCK1_0
TIOB0_1
- 76 *1 96 *1 114 *1 134 162
P003
D19 *3, *4, *5
SIN2_0
TIOB1_1
INT3_0
- - - - 135 163
P004
D20
SOT2_0
- - - - - 164
P164
PPG32_1
61 *1 77 *1 97 *1 115 *1 136 *1
165 *1
P005
D21 *2, *3, *4, *5
SCK2_0 *2
ADTG0_1
INT7_1
RX2(64) *4, *5, *6,
*7
- - - - - 166
P165
PPG33_1
62 *1 78 *1 98 *1 116 *1 137 *1
167 *1
P006
D22 *2, *3, *4, *5
SCS2_0 *2
ADTG1_1
INT2_1
TX2(64) *4, *5, *6,
*7
- - - 117 *1 138 168
P007
D23 *5
- - - - - 169
P166
PPG34_1
- - - 118 *1 139 170
P010
D24 *5
63 *1 79 *1 99 *1 119 *1 140 171
P011
WOT
D25 *2, *3, *4, *5
SOT2_1 *2
TIOA0_0 *2, *3, *4
INT3_1
Document Number: 002-04662 Rev. *D Page 270 of 289
MB91520 Series
Page Section Change Results
34 ■PIN Description
A List of "Pin Description" modified.
(Error)
Function*2
General-purpose I/O port
External bus data bit21 I/O (0)
Multi-function serial ch.2 clock I/O (0)
A/D converter external trigger input 0 (1)
INT7 External interrupt input (1)
(CAN reception data 2 input
MB91F52xB ,MB91F52xD only)
General-purpose I/O port
External bus data bit22 I/O (0)
Serial chip select 2 I/O (0)
A/D converter external trigger input 1 (1)
INT2 External interrupt input (1)
(CAN transmission data 2 output
MB91F52xB ,MB91F52xD only)
(Correct)
Function*9
General-purpose I/O port
External bus data bit21 I/O (0)
Multi-function serial ch.2 clock I/O (0)
A/D converter external trigger input 0 (1)
INT7 External interrupt input (1)
CAN reception data 2 input
General-purpose I/O port
External bus data bit22 I/O (0)
Serial chip select 2 I/O (0)
A/D converter external trigger input 1 (1)
INT2 External interrupt input (1)
CAN transmission data 2 output
Document Number: 002-04662 Rev. *D Page 271 of 289
MB91520 Series
Page Section Change Results
36 ■PIN Description
The following sentences modified under the Table of Pin
description.
(Error)
*1: For the I/O circuit types, see "■I/O CIRCUIT TYPE".
*2: For switching, see "I/O Port" in HARDWARE MANUAL.
(Correct)
*1: There is a restriction of pin functions. See "Pin Name" of
this table.
*2: not supported in 64pin
*3: not supported in 80pin
*4: not supported in 100pin
*5: not supported in 120pin
*6: not supported in 144pin
*7: not supported in 176pin
*8: For the I/O circuit types, see "■I/O CIRCUIT TYPE".
*9: For switching, see "I/O Port" in HARDWARE MANUAL.
39 ■I/O Circuit Type
Remarks for Type I in "I/O Circuit Types" modified as follows:
(Error)
- 3V pad power supply (5V tolerant),
General-purpose I/O port
- Output 4mA
- CMOS hysteresis input
(Correct)
- General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
40 ■I/O Circuit Type
Remarks for Type J in "I/O Circuit Types" modified as follows:
(Error)
- 3V pad power supply (5V tolerant),
Analog input,General-purpose I/O port
- Output 4mA
- CMOS hysteresis input
(Correct)
- Analog input, General-purpose I/O port (5V tolerant)
- Output 4mA
- CMOS hysteresis input
Document Number: 002-04662 Rev. *D Page 272 of 289
MB91520 Series
Page Section Change Results
40 ■I/O Circuit Type
Remarks for Type L in "I/O Circuit Types" modified as follows:
(Error)
- Open-drain I/O
- Output 25mA (NOD)
- TTL input
(Correct)
- Open-drain I/O
- Output 25mA (Nch open-drain)
- TTL input
40 ■I/O Circuit Type
Remarks for Type M in "I/O Circuit Types" modified as
follows:
(Error)
- CMOS hysteresis input
- Pull-up resistor 50kΩ (5V cont)
(Correct)
- CMOS hysteresis input
- Pull-up resistor 50kΩ
121 ■Interrupt Vector Table
The following sentence deleted from Interrupt vector 64pins.
*5: It does not support the DMA transfer by the interrupt
because of the RAM ECC bit error.
124 ■Interrupt Vector Table
The interrupt factor in Interrupt vector 80pin modified as
follows:
(Error)
Base timer
1 IRQ0
61 3D ICR
45 308H
000F
FF08
H
45*5
Base timer
1 IRQ1
−
−
(Correct)
Base timer
1 IRQ0
61 3D ICR
45 308H
000F
FF08
H
45
Base timer
1 IRQ1
−
−
Document Number: 002-04662 Rev. *D Page 273 of 289
MB91520 Series
Page Section Change Results
125 ■Interrupt Vector Table
The following sentence deleted from Interrupt vector 80pins.
(Error)
*5: It does not support the DMA transfer by the interrupt
because of the RAM ECC bit error.
129 ■Interrupt Vector Table
The interrupt factor in Interrupt vector 100pin modified as
follows:
(Error)
Base timer 0
IRQ0
60 3
C
ICR
44 30CH
000F
FF0C
H
44
Base timer 0
IRQ1
(Correct)
−
60 3
C
ICR
44 30CH
000F
FF0C
H
44
−
129 ■Interrupt Vector Table
The interrupt factor in Interrupt vector 100pin modified as
follows:
(Error)
Base timer 1
IRQ0
61 3D ICR
45 308H 000F
FF08H
45
*5
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
61 3D ICR
45 308H
000F
FF08
H
45
Base timer 1
IRQ1
−
−
129 ■Interrupt Vector Table
The following sentence deleted from Interrupt vector 100pins.
(Error)
*5: It does not support the DMA transfer by the interrupt
because of the RAM ECC bit error.
Document Number: 002-04662 Rev. *D Page 274 of 289
MB91520 Series
Page Section Change Results
131 ■Interrupt Vector Table
"42" is deleted as shown below from the interrupt factor in
Interrupt vector 120pin.
(Error)
PPG2/3/12/13/22
/23/32/33/42/43
41 29 ICR
25
358
H
000F
FF58
H
25
*3
16-bit free-run
timer 2 (0
detection) /
(compare clear)
(Correct)
PPG2/3/12/13/22
/23/32/33/43
41 29 ICR
25
358
H
000F
FF58
H
25
*3
16-bit free-run
timer 2 (0
detection) /
(compare clear)
133 ■Interrupt Vector Table
The interrupt factor in Interrupt vector 120pin modified as
follows:
(Error)
Base timer 1
IRQ0
61 3D ICR
45
308
H
000F
FF08
H
45
*5
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
61 3D ICR
45
308
H
000F
FF08
H
45
Base timer 1
IRQ1
−
−
133 ■Interrupt Vector Table
The following sentence deleted from Interrupt vector 120pins.
(Error)
*5: It does not support the DMA transfer by the interrupt
because of the RAM ECC bit error.
Document Number: 002-04662 Rev. *D Page 275 of 289
MB91520 Series
Page Section Change Results
135 ■Interrupt Vector Table
"42" is deleted as shown below from the interrupt factor in
Interrupt vector 144pin.
(Error)
PPG2/3/12/13/22/
23/32/33/42/43
41 29 ICR
25
358
H
000F
FF58
H
25*
3
16-bit free-run
timer 2 (0
detection) /
(compare clear)
(Correct)
PPG2/3/12/13/22/
23/32/33/43
41 29 ICR
25
358
H
000F
FF58
H
25*
3
16-bit free-run
timer 2 (0
detection) /
(compare clear)
137 ■Interrupt Vector Table
The interrupt factor in Interrupt vector 144pin modified as
follows:
(Error)
Base timer 1
IRQ0
61 3D ICR
45
308
H
000F
FF08
H
45
*5
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
61 3D ICR
45
308
H
000F
FF08
H
45
Base timer 1
IRQ1
−
−
137 ■Interrupt Vector Table
The following sentence deleted from Interrupt vector 144pins.
(Error)
*5: It does not support the DMA transfer by the interrupt
because of the RAM ECC bit error.
Document Number: 002-04662 Rev. *D Page 276 of 289
MB91520 Series
Page Section Change Results
141 ■Interrupt Vector Table
The interrupt factor in Interrupt vector 176pin modified as
follows:
(Error)
Base timer 1
IRQ0
61 3D ICR
45
308
H
000F
FF08
H
45
*5
Base timer 1
IRQ1
−
−
(Correct)
Base timer 1
IRQ0
61 3D ICR
45
308
H
000F
FF08
H
45
Base timer 1
IRQ1
−
−
141 ■Interrupt Vector Table
The following sentence deleted from Interrupt vector 176pins.
(Error)
*5: It does not support the DMA transfer by the interrupt
because of the RAM ECC bit error.
142 ■Electrical Characteristics
1. Absolute Maximum Ratings
The remarks of "L" level average output current" and "H" level
average output current" modified as follows.
(Error)
Parameter Sym
bol
Rating
Unit Remarks
Min
Max
"L" level average
output current
*4
IOL AV1
-
4
mA
IOL AV2
-
12
mA
"H" level average
output current
*4
IOHAV1
-
-4
mA
IOHAV2
-
-12
mA
(Correct)
Parameter Sym
bol
Rating
Unit Remarks
Min
Max
"L" level average
output current
*4
IOL AV1
-
4
mA
*9
IOL AV2
-
12
mA
*10
"H" level average
output current
*4
IOHAV1
-
-4
mA
*9
IOHAV2
-
-12
mA
*10
Document Number: 002-04662 Rev. *D Page 277 of 289
MB91520 Series
Page Section Change Results
143 ■Electrical Characteristics
1. Absolute Maximum Ratings
The following note added.
(Correct)
*9: Corresponding pins: General-purpose ports other than
those of P103, P104, P105 and P106.
*10: Corresponding pins: General-purpose ports of P103,
P104, P105 and P106.
155
■Electrical Characteristics
AC Characteristics
(2) Reset Input
Added the At power-on
*2
condition to the remarks in Reset
input time.
156
■Electrical Characteristics
AC Characteristics
(3) Power-on Conditions
Deleted the Slope detection undetected specification.
Added the Power ramp rate and C pin voltage at Power-on.
*1, *2: Changed the sentence.
Added *3, *4, Note, Figure at the Power off time, Power ramp
rate, C pin voltage at Power-on.
6 to 11,
203 to
216
■Product lineup
■Ordering information Package description modified to JEDEC description.
47 ■During Power-on
The following sentence modified as fdeleted from Interrupt
(Error)
To prevent a malfunction of the voltage step-down circuit built
in the device, set the voltage rising time to have 50μs or
longer (between 0.2V and 2.7V) during power-on.
(Correct)
To prevent a malfunction of the voltage step-down circuit built
in the device, the voltage rising must be monotonic increasing
during power-on.
Power-on prohibits that the voltage goes up and down and
voltage rising stops temporarily.
49, 50 ■Block Diagram
The following Block diagram modified as follows:
●MB91F522B, MB91F523B, MB91F524B, MB91F525B,
MB91F526B
●MB91F522D, MB91F523D, MB91F524D, MB91F525D,
MB91F526D
(Error)
CAN (2ch).
(Correct)
CAN (3ch)
217 to
220 ■Ordering Information Added the following description.
■ORDERING INFORMATION MB91F52xxxD
221 to
227
■Package Dimensions Package Dimensions modified to JEDEC description.
Document Number: 002-04662 Rev. *D Page 278 of 289
MB91520 Series
Page Section Change Results
Rev *C
2 Features
Peripheral Functions
The following sentence modified in I2C as following:
(Error)
< I2C >
2 channels ch.3 , ch.4 Standard mode/high-speed mode
supported.
Standard mode (Max. 100kbps) / high-speed mode (Max.
400kbps) supported
(Correct)
< I2C >
2 channels ch.3 , ch.4 Standard mode/fast mode
supported.
Standard mode (Max. 100kbps) / fast mode (Max. 400kbps)
supported
5,6,7,8,9
,10 1. Product Lineup
The following *2 added as follows:
(Error)
Power supply
2.7 V to 5.5 V
(Correct)
Power supply
2.7 V to 5.5 V *2
5,6,7,8,9
,10 1. Product Lineup
The following sentence added as follows:
(Correct)
*2: Detection voltage of the external low voltage detection
reset (initial) is 2.8V±8% (2.576V to 3.024V).
This detection voltage (2.576V) is below the minimum
operation guarantee voltage (2.7V).
Between this detection voltage and the minimum operation
guarantee voltage, MCU functions are not guaranteed except
for the low voltage detector.
Note that although the detection level is below the minimum
operation guarantee voltage, the LVD reset factor flag is set
as the voltage drops below the detection level.
8, 9, 10, 1. Product Lineup
The following sentence modified in the bottom of Product
lineup comparison table as following:
(Error)
*1: Only channel 3 and channel 4 support the I2C
(high-speed mode/standard mode).
(Correct)
*1: Only channel 3 and channel 4 support the I2C (fast
mode/standard mode).
11
1. Product Lineup
Added silicon version E
Document Number: 002-04662 Rev. *D Page 279 of 289
MB91520 Series
Page Section Change Results
46 ■During Power-on
The following sentence modified as following:
(Error)
To prevent a malfunction of the voltage step-down circuit built
in the device, the voltage rising must be monotonic increasing
during power-on.
Power-on prohibits that the voltage goes up and down and
voltage rising stops temporarily.
(Correct)
To prevent a malfunction of the voltage step-down circuit built
in the device, the voltage rising must be monotonic during
power-on.
142,143 11. Electrical Characteristics
Recommended operating conditions
The following sentence modified as following:
(Error)
*1:
When it is used outside recommended operation guarantee
range (range of the operation guarantee), contact your
sales representative. Moreover, minimum value with an
effective external low-voltage detection reset
becomes a voltage until generating low-voltage detection
reset.
(Correct)
*1: When it is used outside recommended operation guarantee
range (range of the operation guarantee), contact your
sales representative.
Detection voltage of the external low voltage detection
reset (initial) is 2.8V±8% (2.576V to 3.024V).
This detection voltage (2.576V) is below the minimum
operation guarantee voltage (2.7V).
Between this detection voltage and the minimum operation
guarantee voltage,
MCU functions are not guaranteed except for the low
voltage detector.
Note that although the detection level is below the
minimum operation guarantee voltage,
the LVD reset factor flag is set as the voltage drops below
the detection level.
156, 157
11. Electrical Characteristics
AC Characteristics
Added (3-2) Power-on Conditions for MB91F52xxxE
Document Number: 002-04662 Rev. *D Page 280 of 289
MB91520 Series
Page Section Change Results
184
11. Electrical Characteristics
AC Characteristics
(4-4) I2C timing
The following sentence modified as following:
(Error)
High-speed
mode*
3
Unit Remarks
Min
Max
Notes: Only ch.3 and ch.4 are standard mode/high-speed
mode correspondence.
*3: A high-speed mode I2C bus device can be used
(Correct)
Fast mode*3
Unit Remarks
Min
Max
Notes: Only ch.3 and ch.4 are standard mode/fast mode
correspondence.
*3: A fast mode I
2
C bus device can be used
187
11. Electrical Characteristics
(8) Low voltage detection (External
low-voltage detection)
The following sentence modified in the Detection voltage as
following:
(Error)
Value
Unit Remarks
Min Typ Max
2.7
-
5.5
V
-8% 2.8 +8% V
When power-supply
voltage falls and
detection level is set
initially
(Correct)
Value
Unit Remarks
Min Typ Max
2.7
-
5.5
V
-8%
LVD5F
_SEL
[3:0]
+8% V
LVD5F_SEL[3:0] are
programmable. Refer
to the hardware
manual.
188
11. Electrical Characteristics
(9) Low voltage detection (RAM retention
low-voltage detection)
The following sentence modified as following:
(Error)
(9) Low voltage detection (Internal low-voltage detection)
(Correct)
(9) Low voltage detection (RAM retention low-voltage
detection)
Document Number: 002-04662 Rev. *D Page 281 of 289
MB91520 Series
Page Section Change Results
220 to
223
16. Ordering Information Added the following description.
■ORDERING INFORMATION MB91F52xxxE
Rev *D
1 Features
The following sentence should be modified as follows:
(Error)
Conversion time : 1μs
(Correct)
Conversion time : 1.4μs
5,6,7,8,9
,10 1. Product Lineup
The following sentence should be modified as follows:
(Error)
*2: Detection voltage of the external low voltage detection
reset (initial) is 2.8V±8% (2.576V to 3.024V). This detection
voltage (2.576V) is below the minimum operation guarantee
voltage (2.7V). Between this detection voltage and the
minimum operation guarantee voltage, MCU functions are not
guaranteed except for the low voltage detector. Note that
although the detection level is below the minimum operation
guarantee voltage, the LVD reset factor flag is set as the
voltage drops below the detection level.
(Correct)
*2: The initial detection voltage of the external low voltage
detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a reset
before voltage dips below minimum guaranteed operation
voltage, as these detection levels are below the minimum
guaranteed MCU operation voltage. Below the minimum
guaranteed MCU operation voltage, MCU operations are not
guaranteed with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 282 of 289
MB91520 Series
Page Section Change Results
142,143 11. Electrical Characteristics
Recommended operating conditions
The following sentence should be modified as follows:
(Error)
*1: When it is used outside recommended operation guarantee
range (range of the operation guarantee), contact your
sales representative.
Detection voltage of the external low voltage detection
reset (initial) is 2.8V±8% (2.576V to 3.024V). This
detection voltage (2.576V) is below the minimum
operation guarantee voltage (2.7V). Between this
detection voltage and the minimum operation guarantee
voltage, MCU functions are not guaranteed except for the
low voltage detector. Note that although the detection level
is below the minimum operation guarantee voltage, the
LVD reset factor flag is set as the voltage drops below the
detection level.
(Correct)
*1: When it is used outside recommended operation guarantee
range (range of the operation guarantee), contact your
sales representative.
The initial detection voltage of the external low voltage
detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
and internal LVD cannot be used to reliably generate a
reset before voltage dips below minimum guaranteed
operation voltage, as these detection levels are below the
minimum guaranteed MCU operation voltage. Below the
minimum guaranteed MCU operation voltage, MCU
operations are not guaranteed with the exception of LVD.
146 11. Electrical Characteristics
DC Characteristics
Pin name of RUP3 should be modified as follows:
(Error)
Port pin other than P035,041,093,122
(Correct)
Port pin other than P035,041,073,074,076,077,093,122
187
11. Electrical Characteristics
(8) Low voltage detection (External
low-voltage detection)
Note of Detection voltage should be added as follows:
(Correct)
Detection voltage *3
*3: The initial detection voltage of the external low voltage
detection is 2.8V±8% (2.576V to 3.024V). This LVD setting
cannot be used to reliably generate a reset before voltage
dips below minimum guaranteed MCU operation voltage, as
this detection level is below the minimum guaranteed MCU
operation voltage (2.7V). Below the minimum guaranteed
MCU operation voltage, MCU operations are not guaranteed
with the exception of LVD.
Document Number: 002-04662 Rev. *D Page 283 of 289
MB91520 Series
Page Section Change Results
188
11. Electrical Characteristics
(9) Low voltage detection (Internal
low-voltage detection)
The following sentence modified as following:
(Error)
(9) Low voltage detection (RAM retention low-voltage
detection)
(Correct)
(9) Low voltage detection (Internal low-voltage detection)
The following symbol should be modified as follows:
(Error)
*
(Correct)
*1
Note of Detection voltage should be added as follows:
(Correct)
Detection voltage *2
*2: The detection voltage of the internal low voltage detection
is 0.9V±0.1V. This LVD cannot be used to reliably generate a
reset before voltage dips below minimum guaranteed MCU
operation voltage, as this detection level is below the
minimum guaranteed MCU operation voltage. Below the
minimum guaranteed MCU operation voltage, MCU
operations are not guaranteed with the exception of LVD.
233 to
235 18. Errata Limitation for Watch mode (power off) should be added in
Errata.
Document History
Document Title: MB91520 Series 32-bit FR81S Microcontroller
Document Number: 002-04662
Revision
ECN Orig. of
Change
Submission
Date Description of Change
**
− − − Initial release
− − 2/20/2014
Features:
Corrected the following description.
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 Automotive input
↓
5V tolerant input: 4 channels ch.6, ch.8, ch.9, ch.11 CMOS hysteresis input
I/O CIRCUIT TYPE:
Corrected the following description to "Type F, G, I, J, K, M".
Schmitt input → CMOS hysteresis input
Document Number: 002-04662 Rev. *D Page 284 of 289
MB91520 Series
Revision
ECN Orig. of
Change
Submission
Date Description of Change
Corrected the following description to "Type D, E".
I2C Schmitt input → I2C hysteresis input
Block Diagram
Corrected the following description.
• MB91F522B, MB91F523B, MB91F524B, MB91F525B, MB91F526B
• MB91F522D, MB91F523D, MB91F524D, MB91F525D, MB91F526D
• MB91F522F, MB91F523F, MB91F524F, MB91F525F, MB91F526F
• MB91F522J, MB91F523J, MB91F524J, MB91F525J, MB91F526J
• MB91F522K, MB91F523K, MB91F524K, MB91F525K, MB91F526K
• MB91F522L, MB91F523L, MB91F524L, MB91F525L, MB91F526L
Electrical Characteristics
2. Recommended operating conditions:
*1
：
of the operation guarantee),contact your sales representative. Moreover,
minimum value with an effective external low-voltage detection reset
becomes a voltage until generating low-voltage detection reset
Electrical Characteristics
3.DC characteristics
Corrected the value of "ICCT5 When using sub clock 32kHz TA=+25°C
". Max 1420µA → Max 2000µA
Corrected the value of "Power supply voltage range".
(TA:-40°C to +105°C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to +105°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V)
Corrected the value of "Power supply voltage range".
(TA:-40°C to +125°C,Vcc=AVcc=2.7V to 5.5V,VSS=AVSS=0.0V)
↓
(TA:-40°C to +125°C,Vcc=AVcc=5.0V±10%/3.3V±0.3V,VSS=AVSS=0.0V)
Corrected the value of " Pull-up resistance RUP1".
Vcc=3.3V±0.3V Min 49 Max 140 →Min 45 Max 140
Corrected the following description.
Pull-up resistance RUP2
Port pin other than P035,041,093,122 → P073,074,076,077
Corrected the value of " Pull-up resistance RUP2".
VCC=5.0V±10% Min 25 Max 100 →Min 25 Max 60
VCC=3.3V±0.3V Min 49 Max 140 →Min 33 Max 90
Added the value of " Pull-up resistance RUP3".
Pin name : Port pin other than P035,041,073,074,076,077,093,122
VCC=5.0V±10% Min 25 Max 100
VCC=3.3V±0.3V Min 45 Max 140
Electrical Characteristics
4. AC characteristics
(4) Multi-function Serial
(4-1) CSIO timing
(4-1-1),(4-1-2),(4-1-3),(4-1-4)
(4-1-1),(4-1-4)SCK↓⇒SOT delay time tSLOVI
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVI
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Document Number: 002-04662 Rev. *D Page 285 of 289
MB91520 Series
Revision
ECN Orig. of
Change
Submission
Date Description of Change
Value: Min -30 Max 30
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min -30 Max 30
Pin name: SCK3,SCK4
SOT3,SOT4
Value: Min -300 Max 300
(4-1-1),(4-1-4)Valid SIN⇒SCK↑ setup time tIVSHI
(4-1-2),(4-1-3)Valid SIN⇒SCK↓ setup time tIVSLI
Corrected the following description.
Pin name: SCK0 to SCK11 SIN0 to SIN11
Value: Min 34 Max -
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11 SIN0 to SIN2,SIN5 to SIN11
Value: Min 34 Max -
Pin name: SCK3,SCK4,SIN3,SIN4
Value: Min 300 Max –
(4-1-1),(4-1-4)SCK↓⇒SOT delay time tSLOVE
(4-1-2),(4-1-3)SCK↑⇒SOT delay time tSHOVE
Corrected the following description.
Pin name: SCK0 to SCK11
SOT0 to SOT11
Value: Min - Max 33
↓
Pin name: SCK0 to SCK2,SCK5 to SCK11
SOT0 to SOT2,SOT5 to SOT11
Value: Min - Max 33
Pin name: SCK3,SCK4 SOT3,SOT4
Value: Min - Max 300
(4-1-1),(4-1-2),(4-1-3),(4-1-4)SCK fall time tF
Corrected the following description.
Pin name: SCK0 to SCK2,SCK5 to SCK11
Value: Min - Max 5
Pin name: SCK3,SCK4
Value: Min - Max 250
↓
Pin name: SCK0 to SCK11
Value: Min - Max 5
(4-1-5)SCS↓⇒SCK↓ setup time tCSSI
(4-1-6)SCS↓⇒SCK↑ setup time tCSSI
(4-1-7)SCS↑⇒SCK↓ setup time tCSSI
(4-1-8)SCS↑⇒SCK↑ setup time tCSSI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70
to SCS73,SCS8 to SCS11
Value: Min tCSSU+0 Max tCSSU+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to
SCS11
Value: Min tCSSU-50 Max tCSSU+0
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSSU-50 Max tCSSU+300
Document Number: 002-04662 Rev. *D Page 286 of 289
MB91520 Series
Revision
ECN Orig. of
Change
Submission
Date Description of Change
(4-1-5)SCK↑⇒SCS↑hold time tCSHI
(4-1-6)SCK↓⇒SCS↑hold time tCSHI
(4-1-7)SCK↑⇒SCS↓hold time tCSHI
(4-1-8)SCK↓⇒SCS↓hold time tCSHI
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60
to SCS63,SCS70
to SCS73,SCS8 to SCS11
Value: Min tCSHD-50 Max tCSHD+0
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to
SCS11
Value: Min tCSHD-10 Max tCSHD+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min tCSHD-300 Max tCSHD+50
(4-1-5),(4-1-6)SCS↓⇒SOT delay time tDSE
(4-1-7),(4-1-8)SCS↑⇒SOT delay time tDSE
Corrected the following description.
Pin name: SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to
SCS63,SCS70 to SCS73,SCS8 to SCS11
SOT1 to SOT11
Value: Min - Max 40
↓
Pin name: SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to
SCS73,
SCS8 to SCS11
SOT1,SOT2,SOT5 to SOT11
Value: Min - Max 40
Pin name: SCS3,SCS40 to SCS43
SOT3,SOT4
Value: Min - Max 300
(4-1-5)SCK↓⇒SCS↓ clock switch time tSCC
(4-1-6)SCK↑⇒SCS↓ clock switch time tSCC
(4-1-7)SCK↓⇒SCS↑ clock switch time tSCC
(4-1-8)SCK↑⇒SCS↑ clock switch time tSCC
Corrected the following description.
Pin name: SCK1 to SCK11
SCS1 to SCS3,SCS40 to SCS43,SCS50 to SCS53,SCS60 to SCS63,SCS70
to SCS73,SCS8 to SCS11
Value: Min 3tCPP+0 Max 3tCPP+50
↓
Pin name: SCK1,SCK2,SCK5 to SCK11
SCS1,SCS2,SCS50 to SCS53,SCS60 to SCS63,SCS70 to SCS73,SCS8 to
SCS11
Value: Min 3tCPP-10 Max 3tCPP+50
Pin name: SCK3,SCK4 SCS3,SCS40 to SCS43
Value: Min 3tCPP-300 Max 3tCPP+50
Added the following description.
Regardless of the deselect time setting, once after the serial chip select pin
becomes inactive, it will take at least five peripheral bus clock cycles to be
active again
Electrical Characteristics
5.A/D Converter
Document Number: 002-04662 Rev. *D Page 287 of 289
MB91520 Series
Revision
ECN Orig. of
Change
Submission
Date Description of Change
(1) 12-bit A/D Converter Electrical Characteristics:
Added the value of "Total error".
Total error value Min – Typ – Max ±12 LSB
Corrected the value of "Zero transition voltage".
Min AVRL+0.5LSB-20mV Max AVRL+0.5LSB+20mV
↓
Min AVRL-11.5LSB Max AVRL+12.5LSB
Corrected the value of "Full-scale transition voltage".
Min AVRH-1.5LSB-20mV Max AVRH-1.5LSB+20mV
↓
Min AVRH-13.5LSB Max AVRH+10.5LSB
Added the following description.
Parameter : Power supply current IA AVCC*3
*3: The power supply current described only current value on A/D converter.
The total AVcc current value must be calculated the power supply current for
A/D converter and D/A converter.
Electrical Characteristics
7.D/A Converter:
Added the following description.
Parameter : Power supply current *1
*1: The power supply current described only current value on D/A
converter.The total Avcc current value must be calculated the power supply
current for D/A converter and A/D converter.
Electrical Characteristics
6.Flash memory:
Parameter: Erase cycle*2/Data retain time
Deleted the following description.
Remarks :
"Temperature at writing/erasing Tj<+105°C"
Electrical Characteristics
7.D/A Converter:
Corrected the following description.
Parameter : Power supply current
Symbol IA Pin name AVCC
Symbol IAH Pin name AV CC
↓
Symbol IA Pin name AVCC
Symbol IAH Pin name AVCC
Example Characteristics
Corrected the following description.
Watch mode
Ordering Information
Corrected the following description.
• ORDERING INFORMATION
↓
• ORDERING INFORMATION MB91F52xxxB
*1
Document Number: 002-04662 Rev. *D Page 288 of 289
MB91520 Series
Revision
ECN Orig. of
Change
Submission
Date Description of Change
Package
↓
Package*2
Added the following description.
*1: It is only supported for customers who have already adopted it now. We
do not recommend adopting new products.
Corrected the following description.
For details of the package, see "■ PACKAGE DIMENSIONS ".
↓
*2: For details of the package, see "■ PACKAGE DIMENSIONS ".
Added the following description.
• ORDERING INFORMATION MB91F52xxxC
Company name and layout design change
*A 4999456 JHMU 11/13/2015
Updated to Cypress template.
Added the following note to the remarks of ""L" level average output
current" and ""H" level average output current" in “Absolute
Maximum Ratings” of “ELECTRICAL CHARACTERISTICS”.
*9: Corresponding pins: General-purpose ports other than those of P103,
P104, P105 and P106.
*10: Corresponding pins: General-purpose ports of P103, P104, P105 and
P106.
Added Errata section.
*B 5112138 KUME 01/28/2016 Fixed some clerical errors.
For details, please see the chapter 18. Major Changes.
*C 5196285 KUME 04/28/2016 For details, please see the chapter 19. Major Changes.
*D 5318862 KUME 06/23/2016 For details, please see the chapter 19. Major Changes.
Document Number: 002-04662 Rev. *D June 23, 2016 Page 289 of 289
MB91520 Series
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