CLC1200
Instrumentation Amplifier
© 2008-2014 Exar Corporation 1 / 15 exar.com/CLC1200
Rev 2E
FEATURES
±2.3V to ±18V supply voltage range
Gain range of 1 to 10,000
Gain set with one external resistor
±125μV maximum input offset voltage
0.1μV/°C input offset drift
700kHz bandwidth at G = 1
1.2V/μs slew rate
90dB minimum CMRR at G = 10
2.2mA maximum supply current
6.6nV/√Hz input voltage noise
70nV/√Hz output voltage noise
0.2μVpp input noise (0.1Hz to 10Hz)
DIP-8 or Pb-free SOIC-8
APPLICATIONS
Bridge amplier
Weigh scales
Thermocouple amplier
ECG and medical instrumentation
MRI (Magnetic Resonance Imaging)
Patient monitors
Transducer interface
Data acquisition systems
Strain gauge amplier
Industrial process controls
General Description
The CLC1200 is a low power, general purpose instrumentation amplier
with a gain range of 1 to 10,000. The CLC1200 is offered in 8-lead SOIC
or DIP packages and requires only one external gain setting resistor
making it smaller and easier to implement than discrete, 3-amp designs.
While consuming only 2.2mA of supply current, the CLC1200 offers a low
6.6nV/Hz input voltage noise and 0.2μVpp noise from 0.1Hz to 10Hz.
The CLC1200 offers a low input offset voltage of ±125μV that only varies
0.1μV/°C over it’s operating temperature range of -40°C to +85°C. The
CLC1200 also features 50ppm maximum nonlinearity. These features
make it well suited for use in data acquisition systems.
Typical Application
2
1
8
3
4
7
6
5
V
OUT
CLC1200
–Input
To Power
Supply Ground
Reference
+Input
+V
S
R
G
–V
S
Load
Thermocouple Amplier
Competitive Plot
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
0.0001 0.001 0.01 0.1 110
Normalized Gain (dB)
Frequency (MHz)
CLC1200
Competitor A
VOUT = 0.2Vpp
RL= 2kΩ
G = 1
VS= ±15V
Ordering Information - back page
© 2008-2014 Exar Corporation 2 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Absolute Maximum Ratings
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Supply Voltage ........................................................................±18V
Input Voltage Range ............................................................. ±VS V
Differential Input Voltage (G = 1 to 10) ..................................... 25V
Differential Input Voltage (G > 10) .............. ≤ 0.05 (RG + 800) +1 V
Load Resistance (min) ................................................................ 1Ω
Operating Conditions
Supply Voltage Range ....................... ±2.3V to ±18V (4.6V to 36V)
Gain Range .................................................................. 1 to 10,000
Operating Temperature Range .................................-40°C to 85°C
Junction Temperature ...........................................................150°C
Storage Temperature Range ...................................-65°C to 150°C
Lead Temperature (Soldering, 10s) ......................................260°C
Package Thermal Resistance
θJA (DIP-8) ........................................................................100°C/W
θJA (SOIC-8) .....................................................................150°C/W
Package thermal resistance (θJA), JEDEC standard, multi-layer
test boards, still air.
ESD Protection
SOIC-8 (HBM) ....................................................................... 1.5kV
ESD Rating for HBM (Human Body Model).
© 2008-2014 Exar Corporation 3 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Electrical Characteristics
TA = 25°C, VS = ±15V, RL = 2kΩ to GND; unless otherwise noted. Gain = 1 + (49.4k/RG); Total RTI Error = VOSI + (VOSO/G)
Symbol Parameter Conditions Min Ty p Max Units
Gain
Gain Range 1 10,000
Gain Error (1)
G = 1, VOUT = ±10V -0.1 0.1 %
G = 10, VOUT = ±10V -0.375 0.375 %
G = 100, VOUT = ±10V -0.375 0.375 %
G = 1,000, VOUT = ±10V -0.8 0.8 %
Gain Nonlinearity G = 1 - 100, VOUT = -10V to 10V, RL = 10kΩ 10 50 ppm
G = 1 - 100, VOUT = -10V to 10V, RL = 2kΩ 10 95 ppm
Gain vs. Temperature G = 1 <10 ppm/°C
G > 1 <-50 ppm/°C
Reference Gain Error(1) VS = ±16.5V -0.03 0.03 %
Voltage Offset
VOSI Input Offset Voltage VS = ±4.5V to ±16.5V -125 125 μV
Average Temperature Coefficient VS = ±4.5V to ±16.5V 0.1 μV/°C
VOSO Output Offset Voltage VS = ±4.5V to ±16.5V, G = 1 -1500 200 1500 μV
Average Temperature Coefficient VS = ±4.5V to ±16.5V 2.5 μV/°C
PSR Offset Referred to the Input vs. Supply
G = 1, VS = ±2.3V to ±18V 80 100 dB
G = 10, VS = ±2.3V to ±18V 95 120 dB
G = 100, VS = ±2.3V to ±18V 110 140 dB
G = 1000, VS = ±2.3V to ±18V 110 140 dB
Input Current
IBInput Bias Current VS = ±16.5V -2 0.5 2 nA
Average Temperature Coefficient VS = ±16.5V 3 pA/°C
IOS Input Offset Current VS = ±16.5V -1 1 nA
Input
Input Impedance Differential 10, 2 GΩ, pF
Common-Mode 10, 2 GΩ, pF
IVR Input Voltage Range (2) VS = ±4.5V, G = 1 -VS + 1.9 +VS - 1.2 V
VS = ±16.5V, G = 1 -VS + 1.9 +VS - 1.4 V
CMRR Common-Mode Rejection Ratio
G = 1, VS = ±16.5V 70 90 dB
G = 10, VS = ±16.5V 90 110 dB
G = 100, VS = ±16.5V 108 130 dB
G = 1000, VS = ±16.5V 108 130 dB
Output
VOUT Output Swing VS = ±2.3V to ±4.5V -VS + 1.1 +VS - 1.2 V
VS = ±18V, G = 1 -VS + 1.4 +VS - 1.2 V
ISC Short Circuit Current ±20 mA
Dynamic Performance
BW-3dB Small Signal -3dB Bandwidth
G = 1 700 kHz
G = 10 400 kHz
G = 100 100 kHz
G = 1000 12 kHz
SR Slew Rate G = 10, VS = ±15V 0.6 1. 2 V/μs
tSSettling Time to 0.01% 5V step, G = 1 to 100 13 μs
5V step, G = 1000 110 μs
© 2008-2014 Exar Corporation 4 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Electrical Characteristics continued
TA = 25°C, VS = ±15V, RL = 2kΩ to GND; unless otherwise noted. Gain = 1 + (49.4k/RG); Total RTI Error = VOSI + (VOSO/G)
Symbol Parameter Conditions Min Ty p Max Units
Noise
eni Input Voltage Noise 1kHz, G = 1000, VS = ±15V 6.6 13 nV/√Hz
eno Output Voltage Noise 1kHz, G = 1, VS = ±15V 70 100 nV/√Hz
enpp Peak-to-Peak Noise (RTI)
G = 1, 0.1Hz to 10Hz 5 μVpp
G = 10, 0.1Hz to 10Hz, VS = ±15V 0.8 μVpp
G = 100, 0.1Hz to 10Hz, VS = ±15V 0.2 0.4 μVpp
inCurrent Noise f = 1kHz 100 fA/√Hz
inpp Peak-to-Peak Current Noise 0.1Hz to 10Hz 10 pApp
Reference Input
RIN Input Resistance 20 kΩ
IIN Input Current VS = ±16.5V 50 60 μA
Voltage Range -VS + 1.6 +VS - 1.6 V
Gain to Output 1±0.0001
Power Supply
VSOperating Range ±2.3 ±18 V
ISSupply Current VS = ±16.5V 1. 3 2.2 mA
Notes:
1. Nominal reference voltage gain is 1.0
2. Input voltage range = CMV + (G VDIFF)/2
© 2008-2014 Exar Corporation 5 / 15 exar.com/CLC1200
Rev 2E
CLC1200
CLC1200 Pin Assignments
SOIC-8, DIP-8
Pin No. Pin Name Description
1, 8 RGRG sets gain
2 -IN Negative input
3 +IN Positive input
4 -VSNegative supply
5 REF Output is referred to the REF pin potential
6 OUT Output
7 +VSPositive supply
CLC1200 Pin Congurations
SOIC-8, DIP-8
-
+
1
2
3
4
RG
-IN1
+IN1
-Vs
RG
+Vs
OUT
REF
8
7
6
5
© 2008-2014 Exar Corporation 7 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Typical Performance Characteristics
TA = 25°C, VS = ±15V, RL = 2kΩ to GND; unless otherwise noted.
Large Signal Pulse Response (G = 1) Large Signal Settling Time (G = 1)
Input Voltage Range vs. VS Output Voltage Swing vs. RL
Gain vs. Frequency Output Voltage Swing vs. VS
-20
-10
0
10
20
30
40
50
60
70
0.0001 0.001 0.01 0.1 110
Gain (dB)
Frequency (MHz)
G = 1000
G= 100
G = 10
G = 1
-1.5
-1
-0.5
0
0.5
1
1.5
0 5 10 15 20
Output Voltage Swing (V)
Supply Voltage (+/-V)
G = 10
RL=2kΩ
RL=2kΩ
RL=10kΩ
RL=10kΩ
+V
S-
-
VS+
Referred to Supply Voltages
-2
-1
0
1
2
0 5 10 15 20
Input Voltage Swing (V)
Supply Voltage (+/-V)
G = 10
+V
S-
-
VS+
Referred to Supply Voltages
G = 10
+V
S-
-
VS+0
10
20
30
0.01 0.1 110
Output Voltage Swing (Vpp)
Load Resistance (kΩ)
-7.5
-5
-2.5
0
2.5
5
7.5
020 40 60 80 100
Output Voltage (V)
Time (us)
G = 1, RL=2K
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0 5 10 15 20 25 30 35 40 45
Output Settling (%)
Time (us)
G = 1, 5V Step
© 2008-2014 Exar Corporation 8 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Typical Performance Characteristics
TA = 25°C, VS = ±15V, RL = 2kΩ to GND; unless otherwise noted.
Large Signal Pulse Response (G = 1000) Large Signal Settling Time (G = 1000)
Large Signal Pulse Response (G = 100) Large Signal Settling Time (G = 100)
Large Signal Pulse Response (G = 10) Large Signal Settling Time (G = 10)
-7.5
-5
-2.5
0
2.5
5
7.5
020 40 60 80 100
Output Voltage (V)
Time (us)
G = 10, RL=2K
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0 5 10 15 20 25 30 35 40 45
Output Settling (%)
Time (us)
G = 10, 5V Step
-7.5
-5
-2.5
0
2.5
5
7.5
020 40 60 80 100
Output Voltage (V)
Time (us)
G= 100, RL=2K
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
0 5 10 15 20 25 30 35 40 45
Output Settling (%)
Time (us)
G = 100, 5V Step
-7.5
-5
-2.5
0
2.5
5
7.5
0200 400 600 800 1000
Output Voltage (V)
Time (us)
G = 1000, RL=2K
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
050 100 150 200 250 300 350 400 450
Output Settling (%)
Time (us)
G = 1000, 5V Step
© 2008-2014 Exar Corporation 9 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Typical Performance Characteristics
TA = 25°C, VS = ±15V, RL = 2kΩ to GND; unless otherwise noted.
Small Signal Pulse Response (G = 100) Small Signal Pulse Response (G = 1000)
Small Signal Pulse Response (G = 1) Small Signal Pulse Response (G = 10)
-0.1
-0.05
0
0.05
0.1
020 40 60 80 100
Output Voltage (V)
Time (us)
G = 1, RL=2K, CL=100pF
-0.1
-0.05
0
0.05
0.1
020 40 60 80 100
Output Voltage (V)
Time (us)
G = 10, RL=2K, CL=100pF
-0.1
-0.05
0
0.05
0.1
020 40 60 80 100
Output Voltage (V)
Time (us)
G = 100, RL=2K, CL=100pF
-0.1
-0.05
0
0.05
0.1
0100 200 300 400 500
Output Voltage (V)
Time (us)
G = 1000, RL=2K, CL=100pF
© 2008-2014 Exar Corporation 10 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Typical Competitive Comparison Plots
TA = 25°C, VS = ±15V, RL = 2kΩ, Exar evaluation board; unless otherwise noted.
Small Signal Pulse Response (G = 1) Small Signal Pulse Response (G = 10)
Frequency Response (G = 100) Frequency Response (G = 1000)
Frequency Response (G = 1) Frequency Response (G = 10)
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
0.0001 0.001 0.01 0.1 110
Normalized Gain (dB)
Frequency (MHz)
CLC1200
Competitor A
VOUT = 0.2Vpp
RL= 2kΩ
G = 1
VS= ±15V
-7
-6
-5
-4
-3
-2
-1
0
1
0.0001 0.001 0.01 0.1 110
Normalized Gain (dB)
Frequency (MHz)
Competitor A
CLC1200
VOUT = 0.2Vpp
RL= 2kΩ
G = 10
VS= ±15V
-7
-6
-5
-4
-3
-2
-1
0
1
0.0001 0.001 0.01 0.1 110
Normalized Gain (dB)
Frequency (MHz)
Competitor A
CLC1200
VOUT = 0.2Vpp
RL= 2kΩ
G = 100
VS= ±15V
-7
-6
-5
-4
-3
-2
-1
0
1
0.0001 0.001 0.01 0.1 110
Normalized Gain (dB)
Frequency (MHz)
Competitor A
CLC1200
VOUT = 0.2Vpp
RL= 2kΩ
G = 1,000
VS= ±15V
-0.050
-0.025
0.000
0.025
0.050
0.075
0.100
0.125
0.150
25 35 45 55 65 75
Output Amplitude (V)
Time (us)
Competitor A
CLC1200
VOUT = 0.1Vpp
CL= 100pF
-0.025
0.000
0.025
0.050
0.075
0.100
0.125
25 35 45 55 65 75
Output Amplitude (V)
Time (us)
Competitor A
CLC1200
VOUT = 0.1Vpp
CL= 100pF
© 2008-2014 Exar Corporation 11 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Application Information
Basic Information
The CLC1200 is a monolithic instrumentation amplier
based on the classic three op amp solution, refer to the
Functional Block Diagram shown in Figure 1. The CLC1200
produces a single-ended output referred to the REF pin
potential.
-IN
+IN
REF
OUT
–
+
–
+
+
–
RG
Figure 1: Functional Block Diagram
The internal resistors are trimmed which allows the gain to be
accurately adjusted with one external resistor RG.
G = + 1; RG =
49.4k
RG
49.4k
G - 1
RG also determines the transconductance of the preamp
stage. As RG is reduced for larger gains, the transconductance
increases to that of the input transistors. Producing the
following advantages:
Open-loop gain increases as the gain is increased, reducing
gain related errors
Gain-bandwidth increases as the gain is increased,
optimizing frequency response
Reduced input voltage noise which is determined by the
collector current and base resistance of the input devices
Gain Selection
The impedance between pins 1 and 8, RG, sets the gain
of the CLC1200. Table 1 shows the required standard table
values of RG for various calculated gains. For G = 1, RG = ∞.
1% RG (Ω) Caclulated
Gain 0.1% RG (Ω) Calculated
Gain
49.9k 1.990 49.3k 2.002
12.4k 4.984 12.4k 4.984
5.49k 9.998 5.49k 9.998
2.61k 19.93 2.61k 19.93
1.00k 50.40 1.01k 49.91
499 100.0 499 100.0
249 199.4 249 199.4
100 495.0 98.8 501.0
49.9 991.0 49.3 1,003.0
Table 1: Recommended RG Values
Follow these guidelines for improved performance:
To maintain gain accuracy, use 0.1% to 1% resistors
To minimize gain error, avoid high parasitic resistance in
series with RG
To minimize gain drift, use low TC resistors (<10ppm/°C)
Common Mode Rejection
The CLC1200 offers high CMRR. To achieve optimal CMRR
performance:
Connect the reference terminal (pin 5) to a low impedance
source
Minimize capacitive and resistive differences between the
inputs
In many applications, shielded cables are used to minimize
noise. Properly drive the shield for best CMRR performance
over frequency. Figures 1 and 2 show active data guards
that are congured to improve AC common-mode rejections.
the capacitances of input cable shields are “bootstrapped”
to minimize the capacitance mismatch between the inputs.
CLC1200
+
_
CLCxxx
+
_
+V
S
Output
R
G
/ 2
-V
S
REF
R
G
/ 2
+ Input
- Input
100
Figure 2: Common-mode Shield Driver
© 2008-2014 Exar Corporation 12 / 15 exar.com/CLC1200
Rev 2E
CLC1200
CLC1200
+
_
+
-
+V
S
Output
-V
S
REF
+ Input
- Input
100
+
-
RG
100 -VS
Figure 3: Differential Shield Driver
Pressure Measurement Applications
The CLC1200 is especially suitable for higher resistance
pressure sensors powered at lower voltages where small
size and low power become more signicant.
Figure 3 shows a 3kΩ pressure transducer bridge powered
from 5V. In such a circuit, the bridge consumes only 1.7mA.
Adding the CLC1200 and a buffered voltage divider allows
the signal to be conditioned for only 3.8mA of total supply
current.
Small size and low cost make the CLC1200 especially
attractive for voltage output pressure transducers. Since it
delivers low noise and drift, it will also serve applications such
as diagnostic noninvasive blood pressure measurement.
Medical ECG
The CLC1200 is perfect for ECG monitors because of its low
current noise. A typical application is shown in Figure 4. The
CLC1200’s low power, low supply voltage requirements,
and space-saving 8-lead SOIC package offerings make it
an excellent choice for battery-powered data recorders.
Furthermore, the low bias currents and low current noise,
coupled with the low voltage noise of the CLC1200, improve
the dynamic range for better performance.
The value of capacitor C1 is chosen to maintain stability
of the right leg drive loop. Proper safeguards, such as
isolation, must be added to this circuit to protect the patient
from possible harm.
CLC1200
+
_
Ref
499
G = 100
3k
5V
3k
3k3k
1.7mA
IN
AGND
Digital
Data
Output
CLCxxx
+
_
1.3mA
5V
5V 20k
10k
20k
0.1mA
REF 5V
Figure 4: Pressure Monitoring Circuits Operating on a Single 5V Supply
G = 7
CLC1200
0.03Hz
High-Pass
Filter
Output
1V/mV
+3V
–3V
R
G
8.25k
Ω
24.9k
Ω
24.9k
Ω
CLC1003
G = 143
C1
1M
Ω
R4
10k
Ω
R1 R3
R2
Output
Amplifier
Patient/Circuit
Protection/Isolation
3
7
4
5
6
8
1
2
Figure 5: Typical Circuit for ECG Monitor Applications
© 2008-2014 Exar Corporation 13 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Grounding
The output voltage of the CLC1200 is developed with
respect to the potential on the reference terminal (pin 8).
Simply tie the REF pin to the appropriate “local ground” to
resolve many grounding problems.
To isolate low level analog signals from a noisy digital
environment, many data acquisition components have
separate analog and digital ground pins. Use separate
ground lines (analog and digital) to minimize current ow
from sensitive areas to system ground. These ground
returns must be tied together at some point, usually best at
the ADC.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board # Products
CEB024 CLC1200 in SOIC-8
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 6-8. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplier is not
directly connected to the ground plane.
Figure 6. CEB024 Schematic
Figure 7. CEB024 Top View
Figure 8. CEB024 Bottom View
For Further Assistance:
Email: CustomerSupport@exar.com or HPATechSupport@exar.com
Exar Technical Documentation: http://www.exar.com/techdoc/
Exar Corporation Headquarters and Sales Offices
48760 Kato Road Tel.: +1 (510) 668-7000
Fremont, CA 94538 - USA Fax: +1 (510) 668-7001
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation
assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free
of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specic application. While the information
in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected
to cause failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
© 2008-2014 Exar Corporation 15 / 15 exar.com/CLC1200
Rev 2E
CLC1200
Ordering Information
Part Number Package Green Operating Temperature Range Packaging
CLC1200ISO8X SOIC-8 Ye s -40°C to +85°C Tape & Reel
CLC1200ISO8MTR SOIC-8 Ye s -40°C to +85°C Mini Tape & Reel
CLC1200ISO8EVB Evaluation Board N/A N/A N/A
CLC1200IDP8 DIP-8 Ye s -40°C to +85°C Rail
Moisture sensitivity level for all parts is MSL-1. Mini Tape and Reel contains 250 pieces.
Revision History
Revision Date Description
2E (ECN 1513-02) March 2015
Reformat into Exar data sheet template. Updated PODs and thermal resistance numbers. Updated
ordering information table to include MTR and EVB part numbers. Updated evaluation board top and
bottom views to Rev b. Added schematic used for evaluation boards.
