TECHNICAL DATA
KK74HC573A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
N SUFFIX
PLASTIC DIP
DW SUFFIX
SOIC
1
20
1
20
ORDERING INFORMATION
KK74HC573AN Plastic DIP
KK74HC573ADW SOIC
TA = -55° to 125° C for all packages
The KK74HC573A is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when LE is high. When LE goes low, data meeting the
setup and hold time becomes latched.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
1
2
3
5
4
6
7
8
9
10
VCC
20
18
17
16
15
14
19
11
12
13
GND
OE
LE
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LOGIC DIAGRAM
DATA
INPUTS NONINVERTING
OUTPUTS
OE
LE
D2
D6
D3
D7
D0
D4
Q5
Q1
Q7
Q3
Q4
Q0
D1
D5
Q6
Q2
1
11
4
8
5
9
2
6
14
18
12
16
15
19
3
7
13
17
PIN 20=VCC
PIN 10 = GND
FUNCTION TABLE
Inputs Output
OE LE D Q
L H H H
L H L L
L L X no change
H X X Z
H= high level
L = low level
X = don’t care
Z = high impedance
1
KK74HC573A
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±35 mA
ICC DC Supply Current, VCC and GND Pins ±75 mA
PDPower Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature, 1.5 mm from Case for 4 Seconds
(Plastic DIP or SOIC Package)
260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types -55 +125 °C
tr, tfInput Rise and Fall Time (Figure 1) VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC573A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
C
C
Guaranteed Limit
Symbol Parameter Test Conditions V
25 °C to
-55°C ≤85
°C ≤125
°C Unit
VIH Minimum High-Level
Input Voltage
VOUT ≥ VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low -Level
Input Voltage
VOUT⎢ ≤ 0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH Minimum High-Level
Output Voltage
VIN=VIH
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
IN=VIH
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL Maximum Low-Level
Output Voltage
VIN= VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN= VIL
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN Maximum Input
Leakage Current
VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
IOZ Maximum Three State
Leakage Current
Output in High-Impedance
State
VIN =VIH
VOUT= VCC or GND
6.0 ±0.5 ±5.0 ±10 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA
6.0 4.0 40 160
µA
3
KK74HC573A
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
V
CC Guaranteed Limit
Symbol Parameter V
25 °C to
-55°C ≤85°C ≤125°C Unit
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPLH, tPHL Maximum Propagation Delay, LE to Q
(Figures 2 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
tPLZ, tPHZ Maximum Propagation Delay, OE to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPZH, tPZL Maximum Propagation Delay, OE to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
CIN Maximum Input Capacitance - 10 10 10 pF
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State)
- 15 15 15 pF
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC
2f+ICCVCC
23 pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
V
CC Guaranteed Limit
Symbol Parameter V
25 °C to
-55°C
≤85°C ≤125°C Unit
tSU Minimum Setup Time, Input D to
Latch Enable
(Figure 4)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
ns
thMinimum Hold Time, Latch Enable
to Input D
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
twMinimum Pulse Width, Latch
Enable (Figure 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tr, tfMaximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
4
KK74HC573A
0 В
50%
50%
tt
PLH PHL
t
w
LE
Q
90%
90%
50%
50%
10%
10%
tt
t
tt
t
fr
PLH
TLH THL
PHL
V
CC
V
CC
0 В
D
Q
Figure 1. Switching Waveforms Figure 2. Switching Waveforms
50%
50%
t
V
V
CC
CC
0 В
0 В
t
su h
D
LE
tt
tt
PZH PHZ
PZL PLZ
V
V
CC
OH
0 В
50%
50%
50%
10%
90%
HIGH
IMPEDANCE
HIGH
IMPEDANCE
OE
Q
Q
V
OL
Figure 3. Switching Waveforms Figure 4. Switching Waveforms
* Includes all probe and jig capacitance * Includes all probe and jig capacitance
Figure 5. Test Circuit Figure 6. Test Circuit
DEVICE
UNDER
TEST
OUTPUT
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT 1 k
C
L
*
TEST POINT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND
when
testing t
PHZ
and t
PZH
EXPANDED LOGIC DIAGRAM
D0 D4D2 D6D1 D5D3 D7
DDDDDDDD
QQQQQQQQ
LE
LE
OE
LELE LELE LELE LE
Q0 Q4Q2 Q6
Q1 Q5Q3 Q7
5
KK74HC573A
N SUFFIX PLAST IC DI P
(MS - 001AD)
Symbol MIN MAX
A24.89 26.92
B6.1 7.11
C5.33
D0.36 0.56
F1.14 1.78
G
H
J0°10°
K2.92 3.81
NOTES: L7.62 8.26
1.
Dimensions “A”, “B” do not include mold flash or protrusions. M0.2 0.36
Maximum mold flas h or protrus ions 0.25 mm (0.010) per s ide. N0.38
D SUFFIX SOIC
(MS - 013AC)
Symbol MIN MAX
A12.6 13
B7.4 7.6
C2.35 2.65
D0.33 0.51
F0.4 1.27
G
H
NOTES: J0°8°
1.
Dimensions A and B do not include mold flash or protrusion. K0.1 0.3
2.
Maximum mold flash or protrusion 0.15 mm (0.006) per side M0.23 0.32
for A; for B ‑ 0.25 mm (0.010) per s ide. P10 10.65
R0.25 0.75
Dimension, mm
1.27
9.53
Dimension, mm
2.54
7.62
A
B
H
C
K
CM
JFM
P
G
D
R x 45
SEATING
PLANE
0.25 (0.010) M T
-T-
1
20
10
11
L
H
MJ
A
B
F
G
D
SEATING
PLANE
N
K
0.25 (0.010) M T
-T-
C
1
20
10
11
6
