RFG60P05E Data Sheet January 2002 60A, 50V, 0.030 Ohm, ESD Rated, P-Channel Power MOSFET Features * 60A, 50V This is a P-Channel power MOSFET manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. It was designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. This type can be operated directly from integrated circuits. Formerly developmental type TA09835. RFG60P05E PACKAGE TO-247 * Temperature Compensating PSPICE(R) Model * 2kV ESD Rated * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER * rDS(ON) = 0.030 BRAND Symbol RFG60P05E D NOTE: When ordering, use the entire part number. G S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) (c)2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B RFG60P05E Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Electrostatic Discharge Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD MIL-STD-883, Category B(2) Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg RFG60P05E -50 -50 20 60 Refer to Peak Current Curve 215 1.43 Refer to UIS Curve 2 UNITS V V V A -55 to 175 oC 300 260 oC oC W W/oC W/oC kV CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250A, VGS = 0V -50 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A -2 - -4 V IDSS VDS = -50V, VGS = 0V - - -1 A VDS = 0.8 x Rated BVDSS, TC = 150oC - - -25 A Zero Gate Voltage Drain Current Gate to Source Leakage Current VGS = 20V - - 100 nA ID = 60A, VGS = -10V (Figure 9) - - 0.030 VDD = -25V, ID = 30A, RL = 0.83, VGS = -10V, RGS = 2.5 (Figure 13) - - 125 ns - 20 - ns tr - 60 - ns td(OFF) - 65 - ns tF - 20 - ns t(OFF) - - 125 ns IGSS Drain to Source On Resistance (Note 2) rDS(ON) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Qg(TOT) VGS = 0V to -20V Gate Charge at 10V Qg(-10) VGS = 0V to -10V Threshold Gate Charge Qg(TH) VGS = 0V to -2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDD = -40V, ID = 60A, RL = 0.67 Ig(REF) = -4mA VDS = -25V, VGS = 0V, f = 1MHz (Figure 12) - - 450 nC - - 225 nC - - 15 nC - 7200 - pF - 1700 - pF - 325 - pF Thermal Resistance, Junction to Case RJC - - 0.70 oC/W Thermal Resistance, Junction to Ambient RJA - - 30 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage (Note 2) VSD ISD = -60A - - -1.75 V Diode Reverse Recovery Time tRR ISD = -60A, dISD/dt = 100A/s - - 200 ns NOTE: 2. Pulse test: pulse width 300s maximum, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). (c)2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B RFG60P05E Unless Otherwise Specified 1.2 -70 1.0 -60 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 0 -50 -40 -30 -20 -10 0 0 25 50 75 100 150 125 175 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZJC , NORMALIZED TRANSIENT THERMAL IMPEDANCE 2 1 0.5 0.2 0.1 PDM 0.1 0.05 t1 t2 0.02 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -500 -500 TC = 25oC, TJ = MAX RATED -100 100ms 1ms -10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -1 -1 10ms 100ms DC VDSS MAX = -50V -10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2002 Fairchild Semiconductor Corporation -100 IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A) VGS = -10V TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: 175 - T C I = I 25 --------------------- 150 -100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -50 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 FIGURE 5. PEAK CURRENT CAPABILITY RFG60P05E Rev. B RFG60P05E Typical Performance Curves Unless Otherwise Specified (Continued) -160 VGS = -8V VGS = -20V STARTING TJ = 25oC VGS = -7V -100 ID , DRAIN CURRENT (A) IAS , AVALANCHE CURRENT (A) -200 -120 STARTING TJ = 150oC If R = 0 tAV = (L) (IAS) / (1.3RATED BVDSS - VDD) If R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] -10 0.01 0.1 1 tAV , TIME IN AVALANCHE (ms) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = -10V -80 VGS = -6V -40 VGS = -4.5V VGS = -5V 0 10 0 -2 -4 -6 -8 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 7. SATURATION CHARACTERISTICS -160 VDD = -15V PULSE DURATIONM = 80s DUTY CYCLE = 0.5% MAX 2 -55oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE IDS(ON) , DRAIN TO SOURCE CURRENT (A) FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 175oC -120 25oC -80 -40 0 0 -2 -4 -6 -8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V, ID = 60A 1.5 1 0.5 0 -80 -10 -40 FIGURE 8. TRANSFER CHARACTERISTICS 0.5 0 120 160 200 ID = 250A 1 -40 80 2 VGS = VDS, ID = 250A 1.5 0 -80 40 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 2 0 TJ , JUNCTION TEMPERATURE (oC) VGS , GATE TO SOURCE VOLTAGE (V) 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation 1.5 1 0.5 0 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE RFG60P05E Rev. B RFG60P05E Typical Performance Curves VDS , DRAIN TO SOURCE VOLTAGE (V) 8000 C, CAPACITANCE (pF) CISS 6000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS 4000 COSS 2000 CRSS 0 -5 0 -10 -15 -20 -50 -37.5 -10 VDD = BVDSS VDD = BVDSS -7.5 RL = 0.83 IG(REF) = 4mA VGS = -10V -25 0.75 BVDSS -12.5 -5 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS -2.5 0 0 I G ( REF ) 20 ------------------------I G ( ACT ) -25 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V) Unless Otherwise Specified (Continued) t, TIME (s) I G ( REF ) 80 ------------------------I G ( ACT ) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN REQUIRED PEAK IAS - RG + 0V VGS VDD DUT VDD tP IAS IAS VDS tP 0.01 BVDSS FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) VDS RL tr 0 tf 10% 10% VGS VDD + VGS DUT RGS VDS VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 16. SWITCHING TIME TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation FIGURE 17. RESISTIVE SWITCHING WAVEFORMS RFG60P05E Rev. B RFG60P05E Test Circuits and Waveforms (Continued) VDS RL VDS Qg(TH) 0 VGS = -2V VGS VDD Qg(-10) + DUT VGS = -10V -VGS - VGS = -20V VDD Ig(REF) Qg(TOT) 0 IG(REF) FIGURE 18. GATE CHARGE TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation FIGURE 19. GATE CHARGE WAVEFORMS RFG60P05E Rev. B RFG60P05E PSPICE Electrical Model .SUBCKT RFG60P05E 2 1 3; REV 9/20/94 CA 12 8 1.01e-8 CB 15 14 1.05e-8 CIN 6 8 6.9e-9 ESG DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 6 DPLCAPMOD - DRAIN 2 5 + LDRAIN EBREAK DPLCAP 16 VTO GATE 1 LGATE RGATE 9 20 18 8 21 6 S1A MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 DBREAK CIN LSOURCE RSOURCE 13 CA 15 17 RBREAK S2B 18 RVTO CB + 6 EGS - 8 3 SOURCE 7 S2A 14 13 13 8 S1B 11 MOS1 8 12 DBODY MOS2 - RIN LDRAIN 2 5 1e-9 LGATE 1 9 7.9e-9 LSOURCE 3 7 4.18e-9 + 17 18 - + - EVTO IT 8 17 1 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 12.83e-3 RGATE 9 20 1.5 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 3.25e-3 RVTO 18 19 RVTOMOD 1 8 6 RDRAIN + EBREAK 5 11 17 18 -76.35 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTO 20 6 8 18 1 10 + EDS - IT 14 5 8 19 VBAT + S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 -0.83 .MODEL DBDMOD D (IS = 1.24e-12 RS = 4.72e-3 TRS1 = 1.43e-3 TRS2 = -4.91e-7 CJO = 6.98e-9 TT = 1.5e-7) .MODEL DBKMOD D (RS = 1.11e-1 TRS1 = 1.34e-3 TRS2 = 4.46e-12) .MODEL DPLCAPMOD D (CJO = 15e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -3.71 KP = 31.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.42e-4 TC2 = 0) .MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 7.69e-6) .MODEL RVTOMOD RES (TC1 = -3.39e-3 TC2 = 1.07e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.6 VOFF = 2.6) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.6 VOFF = 4.6) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.16 VOFF = -3.84) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.84 VOFF = 1.16) .ENDS For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. (c)2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET VCXTM STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4