©2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B
RFG60P05E
60A, 50V, 0.030 Ohm, ESD Rated,
P-Channel Power MOSFET
This is a P-Channel power MOSFET manufactured using the
MegaFET process. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. It was
designed for use in applications such as switching
regulators, switching converters, motor drivers, and relay
drivers. This type can be operated directly from integrated
circuits.
Formerly developmental type TA09835.
Features
• 60A, 50V
•r
DS(ON)
= 0.030
Ω
• Temperature Compensating PSPICE
®
Model
• 2kV ESD Rated
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175
o
C Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC STYLE TO-247
Ordering Information
PART NUMBER PACKAGE BRAND
RFG60P05E TO-247 RFG60P05E
NOTE: When ordering, use the entire part number.
D
G
S
DRAIN
(BOTTOM
SIDE METAL)
SOURCE
DRAIN
GATE
Data Sheet January 2002
©2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFG60P05E UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
-50 V
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
-50 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) (Figure 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
60
Refer to Peak Current Curve
A
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate above 25
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
215
1.43
W
W/
o
C
Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Refer to UIS Curve W/
o
C
Electrostatic Discharge Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
SD
MIL-STD-883, Category B(2)
2kV
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
J,
T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V -50 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 250
µ
A -2--4V
Zero Gate Voltage Drain Current I
DSS
V
DS
= -50V, V
GS
= 0V - - -1
µ
A
V
DS
= 0.8 x Rated BV
DSS
, T
C
= 150
o
C - - -25
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - -
±
100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 60A, V
GS
= -10V (Figure 9) - - 0.030
Ω
Turn-On Time t
(ON)
V
DD
= -25V, I
D
= 30A, R
L
= 0.83
Ω
,
V
GS
= -10V, R
GS
= 2.5
Ω
(Figure 13)
- - 125 ns
Turn-On Delay Time t
d(ON)
-20- ns
Rise Time t
r
-60- ns
Turn-Off Delay Time t
d(OFF)
-65- ns
Fall Time t
F
-20- ns
Turn-Off Time t
(OFF)
- - 125 ns
Total Gate Charge Q
g(TOT)
V
GS
= 0V to -20V V
DD
= -40V, I
D
= 60A,
R
L
= 0.67
Ω
I
g(REF)
= -4mA
- - 450 nC
Gate Charge at 10V Q
g(-10)
V
GS
= 0V to -10V - - 225 nC
Threshold Gate Charge Q
g(TH)
V
GS
= 0V to -2V - - 15 nC
Input Capacitance C
ISS
V
DS
= -25V, V
GS
= 0V, f = 1MHz
(Figure 12)
- 7200 - pF
Output Capacitance C
OSS
- 1700 - pF
Reverse Transfer Capacitance C
RSS
- 325 - pF
Thermal Resistance, Junction to Case R
θ
JC
- - 0.70
o
C/W
Thermal Resistance, Junction to Ambient R
θ
JA
--30
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage (Note 2) V
SD
I
SD
= -60A - - -1.75 V
Diode Reverse Recovery Time t
RR
I
SD
= -60A, dI
SD
/dt = 100A/
µ
s - - 200 ns
NOTE:
2. Pulse test: pulse width
≤
300
µ
s maximum, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
RFG60P05E
©2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 175
0.2
0.4
0.6
0.8
1.0
1.2
125 150
-50
-40
-30
-20
-10
0
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
-60
-70
2
1
0.1
0.01
10-5 10-4 10-3 10-2 10-1 100101
THERMAL IMPEDANCE
ZθJC, NORMALIZED TRANSIENT
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
0.5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
t, RECTANGULAR PULSE DURATION (s)
-500
-100
-10
-1-1 -10 -100
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
VDSS MAX = -50V
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
10ms
100ms
DC
100ms
TC = 25oC, TJ = MAX RATED
10-5 10-4 10-3 10-2 10-1 100101
-100
-500
t, PULSE WIDTH (s)
IDM, PEAK CURRENT (A)
-50
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
II25
175 TC
–
150
---------------------
=
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = -10V
TC = 25oC
RFG60P05E
©2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves Unless Otherwise Specified (Continued)
-200
-100
-10
0.01 0.1 1 10
tAV , TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
If R = 0
tAV = (L) (IAS) / (1.3RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
STARTING TJ = 150oC
STARTING TJ = 25oC
0
0-2 -4 -6 -8
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = -8V
VGS = -7V
VGS = -10V
-40
-80
-120
-160 VGS = -20V
VGS = -6V
VGS = -5V
VGS = -4.5V
PULSE DURATION = 80µs
TC = 25oC
DUTY CYCLE = 0.5% MAX
0 -2-4-6-8-10
VGS , GATE TO SOURCE VOLTAGE (V)
IDS(ON), DRAIN TO SOURCE CURRENT (A)
0
175oC
25oC
-40
-80
-160
-120
PULSE DURATIONM = 80µs
DUTY CYCLE = 0.5% MAX
-55oC
VDD = -15V
2
1.5
1
0.5
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
PULSE DURATION = 80µs
VGS = -10V, ID = 60A
ON RESISTANCE
DUTY CYCLE = 0.5% MAX
2
1.5
1
0.5
0
-80 -40 0 40 80 160120 200
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED GATE
VGS = VDS, ID = 250µA
2
1.5
1
0.5
0
-80 -40 0 40 80 120 160 200
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
ID = 250µA
RFG60P05E
©2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
CISS
COSS
CRSS
6000
4000
2000
00 -10 -15 -20 -25
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
8000
-5
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
-50
-37.5
-25
-12.5
0
-10
-7.5
-5
-2.5
0
VDD = BVDSS VDD = BVDSS
VDS , DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
20
IG REF()
IG ACT()
-------------------------t, TIME (µs) 80
IG REF()
IG ACT()
-------------------------
RL = 0.83Ω
IG(REF) = 4mA
VGS = -10V
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
tP
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
RFG60P05E
©2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
RL
VGS
+
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = -2V
Qg(-10)
VGS = -10V
Qg(TOT)
VGS = -20V
VDS
-VGS
IG(REF)
0
0
RFG60P05E
©2002 Fairchild Semiconductor Corporation RFG60P05E Rev. B
PSPICE Electrical Model
.SUBCKT RFG60P05E 2 1 3; REV 9/20/94
CA 12 8 1.01e-8
CB 15 14 1.05e-8
CIN 6 8 6.9e-9
DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD
EBREAK 5 11 17 18 -76.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 7.9e-9
LSOURCE 3 7 4.18e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 12.83e-3
RGATE 9 20 1.5
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.25e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 -0.83
.MODEL DBDMOD D (IS = 1.24e-12 RS = 4.72e-3 TRS1 = 1.43e-3 TRS2 = -4.91e-7 CJO = 6.98e-9 TT = 1.5e-7)
.MODEL DBKMOD D (RS = 1.11e-1 TRS1 = 1.34e-3 TRS2 = 4.46e-12)
.MODEL DPLCAPMOD D (CJO = 15e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD PMOS (VTO = -3.71 KP = 31.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 9.42e-4 TC2 = 0)
.MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 7.69e-6)
.MODEL RVTOMOD RES (TC1 = -3.39e-3 TC2 = 1.07e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.6 VOFF = 2.6)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.6 VOFF = 4.6)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.16 VOFF = -3.84)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.84 VOFF = 1.16)
.ENDS
For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature
Options; written by William J. Hepp and C. Frank Wheatley.
MOS1
10
DPLCAP
RDRAIN
DBREAK
LDRAIN
DRAIN
SOURCE
LSOURCE
DBODY
RBREAK
RVTO
VBAT
+
-
19
IT
RSOURCE
EBREAK
MOS2
EDSEGS
RIN CIN
VTO
ESG
S1A S2A
S2BS1B
CBCA
EVTO
RGATE
GATE
LGATE
5
2
1817
7
11
21
8
6
16
2091
12 15
14
13
13
8
14
13
+
-
+
-
+
-
+
-
+
-
+
-
3
8
6
17
18
5
8
6
8
18
8
RFG60P05E
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
Rev. H4
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
STAR*POWER is used under license
VCX™
